 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| mpc561/mpc563 reference manual additional devices supported: mpc562 mpc564 mpc561rm rev 1.2 08/2005
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 26668334 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the described product is a powerpc microprocessor. the powerpc name is a trademark of ibm corp. and used under license ? freescale semiconductor, inc. 2004, 2005. all rights reserved. mpc561rm rev 1.2 08/2005 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor iii paragraph number title page number about this book lxxvii audience ..................................................................................................................... l xxvii organization ................................................................................................................ lx xvii suggested reading ........................................................................................................ lxxx conventions and nome nclature .................................................................................... lxxx notational conventi ons ............................................................................................... lxxxi acronyms and abbrevia tions ..................................................................................... lxxxii references .................................................................................................................. lx xxiii chapter 1 overview 1.1 introducti on ............................................................................................................... ...... 1-1 1.2 block diag ram .............................................................................................................. .. 1-2 1.3 key features ............................................................................................................... .... 1-3 1.3.1 high-performance cpu system ................................................................................. 1-3 1.3.1.1 risc mcu central proce ssing unit (rcpu) ........................................................ 1-4 1.3.1.2 unified system interface unit (usiu) ................................................................... 1-4 1.3.1.3 burst buffer controller (bbc) module .................................................................. 1-4 1.3.1.4 flexible memory prot ection unit ........................................................................... 1-5 1.3.1.5 memory controll er ................................................................................................. 1-5 1.3.1.6 512-kbytes of cdr3 flas h eeprom memory (uc3f) ? mpc563/mpc564 only 1-5 1.3.1.7 32-kbyte static ram (calram) ........................................................................ 1-6 1.3.1.8 general purpose i/o s upport (gpio) ..................................................................... 1-6 1.3.2 nexus debug port (c lass 3) ........................................................................................ 1-6 1.3.3 integrated i/o sy stem ................................................................................................. 1-6 1.3.3.1 two time processor un its (tpu3) ........................................................................ 1-6 1.3.3.2 22-channel modular i/o sy stem (mios14) .......................................................... 1-6 1.3.3.3 two enhanced queued analog-to-digit al converter modules (qadc64e) ........ 1-7 1.3.3.4 three can 2.0b controller (toucan) modules .................................................. 1-7 1.3.3.5 queued serial multi-channel module (qsmcm) ................................................. 1-8 1.3.3.6 peripheral pin multiplexing (ppm) ........................................................................ 1-8 1.4 mpc561/mpc563 optional features ............................................................................. 1-9 1.5 comparison of mpc561/mp c563 and mpc555 ........................................................... 1-9 1.6 additional mpc561/mpc563 differences ................................................................... 1-10 1.7 sram keep-alive powe r behavior ............................................................................. 1-11 1.8 mpc561/mpc563 addr ess map .................................................................................. 1-11 contents mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor iv contents paragraph number title page number 1.9 supporting documentat ion list .................................................................................... 1-14 chapter 2 signal descriptions 2.1 signal groupings ........................................................................................................... .2-1 2.2 signal summary ............................................................................................................. .2-3 2.2.1 mpc561/mpc563 signal mu ltiplexing ................................................................... 2-20 2.2.2 readi port signal sharing ...................................................................................... 2-21 2.3 pad module configuration re gister (pdmcr) ............................................................ 2-22 2.4 pad module configuration re gister (pdmcr2) .......................................................... 2-23 2.5 mpc561/mpc563 development s upport signal sharing ............................................ 2-28 2.5.1 jtag mode select ion .............................................................................................. 2-29 2.5.2 bdm mode select ion ............................................................................................... 2-30 2.5.3 nexus mode sel ection .............................................................................................. 2-30 2.6 reset state ................................................................................................................ ..... 2-31 2.6.1 signal functionality configur ation out of reset ..................................................... 2-31 2.6.2 signal state duri ng reset ......................................................................................... 2-31 2.6.3 power-on reset and hard reset .............................................................................. 2-32 2.6.4 pull-up/pull-d own ................................................................................................... 2-32 2.6.4.1 pull-up/pull-down enable and disable fo r 5-v only and 2.6-v only signals .. 2-32 2.6.4.2 pull-down enable and disable for 5-v/2.6-v multiplexed signals .................... 2-32 2.6.4.3 special pull resistor disable cont rol functionality (sprds) ............................ 2-32 2.6.4.4 pull device select (pull_sel) .......................................................................... 2-33 2.6.5 signal reset st ates .................................................................................................... 2- 33 chapter 3 central processing unit 3.1 rcpu block diag ram ................................................ .................................................... 3-1 3.2 rcpu key features ........................................................................................................ 3- 3 3.3 instruction seque ncer ..................................................................................................... 3 -3 3.4 independent executio n units .......................................................................................... 3-4 3.4.1 branch processing un it (bpu) ................................................................................... 3-5 3.4.2 integer unit (iu) ........................................................................................................ .3-5 3.4.3 load/store unit (lsu) ............................................................................................... 3-6 3.4.4 floating-point unit (fpu) .......................................................................................... 3-6 3.5 levels of the powerpc isa architecture ....................................................................... 3-6 3.6 rcpu programming m odel ............................................................................................ 3-7 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor v contents paragraph number title page number 3.7 user instruction set architecture (uisa) register set ............................................................................................................... 3-1 2 3.7.1 general-purpose regist ers (gprs) ........................................................................... 3-12 3.7.2 floating-point regist ers (fprs) ............................................................................... 3-12 3.7.3 floating-point status and cont rol register (fpscr) .............................................. 3-13 3.7.4 condition register (cr) ........................................................................................... 3-16 3.7.4.1 condition register cr0 fi eld definiti on ............................................................. 3-17 3.7.4.2 condition register cr1 fi eld definiti on ............................................................. 3-17 3.7.4.3 condition register crn field ? compare instruction ....................................... 3-17 3.7.5 integer exception regi ster (xer) ............................................................................ 3-18 3.7.6 link register (lr) .................................................. .................................................. 3-1 9 3.7.7 count register (ctr) ............................................................................................... 3-19 3.8 vea register set ? time base (tb) .......................................................................... 3-20 3.9 oea register set .......................................................................................................... 3 -20 3.9.1 machine state regist er (msr) ................................................................................. 3-20 3.9.2 dae/source instruction servi ce register (dsisr) ................................................. 3-22 3.9.3 data address regist er (dar) .................................................................................. 3-23 3.9.4 time base facility (tb) ? oea ............................................................................. 3-23 3.9.5 decrementer regist er (dec) .................................................................................... 3-23 3.9.6 machine status save/restore register 0 (srr0) ..................................................... 3-23 3.9.7 machine status save/restore register 1 (srr1) ..................................................... 3-23 3.9.8 general sprs (spr g0?sprg3) .............................................................................. 3-24 3.9.9 processor version regi ster (pvr) ........................................................................... 3-25 3.9.10 implementation-speci fic sprs ................................................................................. 3-25 3.9.10.1 eie, eid, and nri special- purpose registers ..................................................... 3-25 3.9.10.2 floating-point exception caus e register (fpecr) ............................................. 3-26 3.9.10.3 additional implementation-sp ecific regist ers ..................................................... 3-27 3.10 instruction set ........................................................................................................... .... 3-27 3.10.1 instruction set summary .......................................................................................... 3-28 3.10.2 recommended simplified mnemonics ..................................................................... 3-33 3.10.3 calculating effectiv e addresses ............................................................................... 3-34 3.11 exception m odel ........................................................................................................... 3-34 3.11.1 exception cla sses ..................................................................................................... 3- 35 3.11.2 ordered excepti ons ................................................................................................... 3-3 5 3.11.3 unordered except ions ............................................. .................................................. 3-35 3.11.4 precise excepti ons .................................................................................................... 3- 36 3.11.5 exception vector table ............................................................................................ 3-36 3.12 instruction timing ........................................................................................................ 3-37 3.13 user instruction set arch itecture (uisa) .................................................................... 3-39 3.13.1 computation mo des .................................................................................................. 3-39 3.13.2 reserved fi elds ......................................................................................................... 3-39 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor vi contents paragraph number title page number 3.13.3 classes of instru ctions .............................................................................................. 3-4 0 3.13.4 exceptions .............................................................................................................. ... 3-40 3.13.5 branch processor ...................................................................................................... 3- 40 3.13.6 instruction fetching .................................................................................................. 3- 40 3.13.7 branch instruct ions ................................................................................................... 3- 40 3.13.7.1 invalid branch instru ction forms ......................................................................... 3-40 3.13.7.2 branch predic tion ................................................................................................. 3-40 3.13.8 fixed-point proc essor ............................................................................................... 3-41 3.13.8.1 fixed-point instru ctions ........................................................................................ 3-41 3.13.9 floating-point proc essor ........................................................................................... 3-41 3.13.9.1 general ............................................................................................................... ... 3-41 3.13.9.2 optional instruct ions .......................................... .................................................. 3-41 3.13.10 load/store proc essor .............................................. .................................................. 3-4 2 3.13.10.1 fixed-point load with update and st ore with update instructions ..................... 3-42 3.13.10.2 fixed-point load and store multiple instructions ............................................... 3-42 3.13.10.3 fixed-point load string instructions .................................................................... 3-42 3.13.10.4 storage synchronization instructions ................................................................... 3-42 3.13.10.5 floating-point load and store wi th update instru ctions .................................... 3-42 3.13.10.6 floating-point load sing le instructions ............................................................... 3-42 3.13.10.7 floating-point store singl e instructions ............................................................... 3-42 3.13.10.8 optional instruct ions .......................................... .................................................. 3-43 3.14 virtual environment architecture (vea) .................................................................... 3-43 3.14.1 atomic update pr imitives ........................................................................................ 3-43 3.14.2 effect of operand placem ent on performan ce ......................................................... 3-43 3.14.3 storage control inst ructions ..................................................................................... 3-43 3.14.4 instruction synchronize (i sync) instruction .............................................................. 3-43 3.14.5 enforce in-order execution of i/o (eieio) instruction ............................................. 3-44 3.14.6 time base ............................................................................................................... .. 3-44 3.15 operating environment arch itecture (oea) ................................................................ 3-44 3.15.1 branch processor registers ...................................................................................... 3-44 3.15.1.1 machine state regist er (msr) ............................................................................. 3-44 3.15.1.2 branch processors in structions ............................................................................. 3-44 3.15.2 fixed-point proc essor ............................................................................................... 3-44 3.15.2.1 special purpose re gisters ..................................................................................... 3-44 3.15.3 storage control inst ructions ..................................................................................... 3-45 3.15.4 exceptions .............................................................................................................. ... 3-45 3.15.4.1 system reset exception and nmi (0x0100) ........................................................ 3-45 3.15.4.2 machine check excep tion (0x0200) .................................................................... 3-46 3.15.4.3 data storage excep tion (0x0300) ......................................................................... 3-48 3.15.4.4 instruction storage ex ception (0x0400) ............................................................... 3-48 3.15.4.5 external interrupt (0x0500) .................................................................................. 3-48 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor vii contents paragraph number title page number 3.15.4.6 alignment excepti on (0x00600) .......................................................................... 3-49 3.15.4.7 program exception (0x0700) ................................................................................ 3-51 3.15.4.8 floating-point unavailabl e exception (0x0800) .................................................. 3-52 3.15.4.9 decrementer excepti on (0x0900) ......................................................................... 3-53 3.15.4.10 system call except ion (0x0c00) ......................................................................... 3-54 3.15.4.11 trace exception (0x0d00) ................................................................................... 3-54 3.15.4.12 floating-point assist ex ception (0x0e00) ........................................................... 3-55 3.15.4.13 implementation-dependent software emulation exception (0x1000) ................ 3-56 3.15.4.14 implementation-depende nt instruction protecti on exception (0x1300) .............. 3-57 3.15.4.15 implementation-specifi c data protection error exception (0x1400) .................. 3-58 3.15.4.16 implementation-dependent debug exceptions .................................................... 3-59 3.15.5 partially executed instructions ................................................................................. 3-60 3.15.6 timer facili ties ........................................................................................................ .3-61 3.15.7 optional facilities and instructions .......................................................................... 3-61 chapter 4 burst buffer controller 2 module 4.1 key features ............................................................................................................... .... 4-2 4.1.1 biu key featur es ....................................................................................................... 4- 2 4.1.2 impu key featur es .................................................................................................... 4-3 4.1.3 icdu key featur es .................................................................................................... 4-3 4.1.4 decram key feat ures ............................................................................................. 4-4 4.1.5 branch target buffer key features ............................................................................ 4-4 4.2 operation modes ............................................................................................................ .4-4 4.2.1 instruction fetch ........................................................................................................ .4-4 4.2.1.1 decompression of f mode ....................................................................................... 4-4 4.2.1.2 decompression on mode ....................................................................................... 4-5 4.2.2 burst operation of the bbc ........................................................................................ 4-5 4.2.3 access violation de tection ........................................................................................ 4-5 4.2.4 slave operation .......................................................................................................... .4-6 4.2.5 reset behavi or ........................................................................................................... .4-6 4.2.6 debug operation m ode .......................................... .................................................... 4-7 4.3 exception table relo cation (etr) ................................................................................. 4-7 4.3.1 etr operation ............................................................................................................ 4-8 4.3.2 enhanced external interrupt relocation (eei r) ...................................................... 4-10 4.4 decompressor ram (decram) functionality .......................................................... 4-12 4.4.1 general-purpose memory operation ........................................................................ 4-13 4.4.1.1 memory protection vi olations ............................................................................. 4-14 4.4.1.2 decram standby operat ion mode .................................................................... 4-14 4.5 branch target buffer .................................................................................................... 4-1 4 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor viii contents paragraph number title page number 4.5.1 btb operati on .......................................................................................................... 4- 14 4.5.1.1 btb invalidati on .................................................................................................. 4-16 4.5.1.2 btb enabling/disa bling ...................................................................................... 4-16 4.5.1.3 btb inhibit regi ons ............................................................................................. 4-16 4.6 bbc programming model ............................................................................................ 4-17 4.6.1 address ma p ............................................................................................................. 4 -17 4.6.1.1 bbc special purpose regi sters (sprs) ............................................................... 4-17 4.6.1.2 decram and dccr block ................................................................................ 4-18 4.6.2 bbc register desc riptions ....................................................................................... 4-19 4.6.2.1 bbc module configuration re gister (bbcmcr) ............................................... 4-19 4.6.2.2 region base address regist ers (mi_rba[0:3]) ................................................. 4-21 4.6.2.3 region attribute register s (mi_ra[0:3]) ............................................................ 4-22 4.6.2.4 global region attribute re gister (mi_gra) ...................................................... 4-23 4.6.2.5 external interrupt relocation table ba se address register (eibadr) .............. 4-25 4.6.3 decompressor class configur ation register s .......................................................... 4-25 chapter 5 unified system interface unit (usiu) overview 5.1 memory map and re gisters ............................................................................................ 5-2 5.1.1 usiu special-purpose registers ................................................................................ 5-6 chapter 6 system configuration and protection 6.1 system configuration and pr otection featur es .............................................................. 6-3 6.1.1 system configur ation ................................................................................................. 6-3 6.1.1.1 usiu pin multipl exing ........................................................................................... 6-4 6.1.1.2 arbitration s upport ................................................................................................. 6-4 6.1.2 external master modes ............................................................................................... 6-4 6.1.2.1 operation in external master modes ...................................................................... 6-5 6.1.2.2 address decoding for exte rnal accesses ............................................................... 6-6 6.1.3 usiu general-pur pose i/o ......................................................................................... 6-6 6.1.4 enhanced interrupt controller .................................................................................... 6-8 6.1.4.1 key features ........................................................................................................... 6-8 6.1.4.2 interrupt confi guration ........................................................................................... 6-8 6.1.4.3 regular interrupt controller operati on (mpc555/mpc556-com patible mode) 6-10 6.1.4.4 enhanced interrupt contro ller operati on ............................................................. 6-11 6.1.4.4.1 lower priority requ est masking ...................................................................... 6-14 6.1.4.4.2 backward compatibility with mpc555/m pc556 ............................................ 6-14 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor ix contents paragraph number title page number 6.1.4.5 interrupt overhead estimation for enhan ced interrupt controller mode ............ 6-16 6.1.5 hardware bus mo nitor ............................................................................................. 6-17 6.1.6 decrementer (d ec) .................................................................................................. 6-18 6.1.7 time base (t b) ........................................................................................................ 6-1 9 6.1.8 real-time clock (rtc) ........................................................................................... 6-19 6.1.9 periodic interrupt ti mer (pit) .................................................................................. 6-20 6.1.10 software watchdog ti mer (swt) ............................................................................ 6-21 6.1.11 freeze operation ....................................................................................................... 6 -23 6.1.12 low power stop op eration ....................................................................................... 6-23 6.2 memory map and register definitions ........................................................................ 6-23 6.2.1 memory map ............................................................................................................ 6-2 3 6.2.2 system configuration and pr otection regist ers ....................................................... 6-24 6.2.2.1 system configurati on registers ........................................................................... 6-24 6.2.2.1.1 siu module configuration register (siu mcr) .............................................. 6-25 6.2.2.1.2 internal memory map re gister (immr) .......................................................... 6-28 6.2.2.1.3 external master control register (emcr) ...................................................... 6-29 6.2.2.2 siu interrupt controll er registers ........................................................................ 6-31 6.2.2.2.1 siu interrupt pending regi ster (sipend) ....................................................... 6-32 6.2.2.2.2 siu interrupt pending regi ster 2 (sipend2) .................................................. 6-32 6.2.2.2.3 siu interrupt pending regi ster 3 (sipend3) .................................................. 6-33 6.2.2.2.4 siu interrupt mask regi ster (simask) .......................................................... 6-33 6.2.2.2.5 siu interrupt mask regist er 2 (simask2) .................................................... 6-34 6.2.2.2.6 siu interrupt mask regi ster 3 (simask3) ..................................................... 6-35 6.2.2.2.7 siu interrupt edge level register (si el) ....................................................... 6-35 6.2.2.2.8 siu interrupt vector re gister (sivec ) ........................................................... 6-35 6.2.2.2.9 interrupt in-service register s (sisr2 and sisr3) .......................................... 6-37 6.2.2.3 system protection registers ................................................................................. 6-37 6.2.2.3.1 system protection control register (sypcr) ................................................. 6-37 6.2.2.3.2 software service regi ster (swsr) .................................................................. 6-38 6.2.2.3.3 transfer error status re gister (tesr) ............................................................. 6-39 6.2.2.4 system timer re gisters ........................................................................................ 6-40 6.2.2.4.1 decrementer regist er (dec) ............................................................................ 6-40 6.2.2.4.2 time base sprs (tb) ....................................................................................... 6-40 6.2.2.4.3 time base reference register s (tbref0 and tbref1) ................................ 6-41 6.2.2.4.4 time base control and stat us register (tbscr) ............................................ 6-42 6.2.2.4.5 real-time clock status and c ontrol register (rtcsc) ................................. 6-42 6.2.2.4.6 real-time clock regi ster (rtc) ..................................................................... 6-43 6.2.2.4.7 real-time clock alarm re gister (rtcal) .................................................... 6-44 6.2.2.4.8 periodic interrupt status and control register (piscr) .................................. 6-44 6.2.2.4.9 periodic interrupt timer c ount register (pitc) .............................................. 6-45 6.2.2.4.10 periodic interrupt timer register (pitr) ........................................................ 6-45 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor x contents paragraph number title page number 6.2.2.5 general-purpose i/o registers ............................................................................. 6-46 6.2.2.5.1 sgpio data register 1 (sgpiodt1) ............................................................. 6-46 6.2.2.5.2 sgpio data register 2 (sgpiodt2) ............................................................. 6-47 6.2.2.5.3 sgpio control register (sgpiocr) .............................................................. 6-48 chapter 7 reset 7.1 reset operat ion ............................................................................................................ ... 7-1 7.1.1 power-on re set .......................................................................................................... 7 -1 7.1.2 hard reset ............................................................................................................... .... 7-2 7.1.3 soft reset ............................................................................................................... ..... 7-2 7.1.4 loss of pll lock ....................................................................................................... 7- 2 7.1.5 on-chip clock sw itch ............................................ .................................................... 7-3 7.1.6 software watchdog reset ........................................................................................... 7-3 7.1.7 checkstop reset .......................................................................................................... 7-3 7.1.8 debug port hard reset ............................................................................................... 7-3 7.1.9 debug port soft reset ................................................................................................. 7-3 7.1.10 jtag reset .............................................................................................................. ... 7-3 7.1.11 ilbc illegal bit ch ange ......................................... .................................................... 7-3 7.2 reset actions su mmary .................................................................................................. 7-3 7.3 data coherency duri ng reset ........................................................................................ 7-4 7.4 reset status regist er (rsr) ........................................................................................... 7-5 7.5 reset configur ation ........................................................................................................ 7-7 7.5.1 hard reset confi guration ........................................................................................... 7-7 7.5.2 hard reset configurati on word (rcw) .................................................................. 7-11 7.5.3 soft reset config uration .......................................................................................... 7-13 chapter 8 clocks and power control 8.1 system clock s ources .................................................................................................... 8-3 8.2 system pll ................................................................................................................. .... 8-3 8.2.1 frequency multipli cation ............................................................................................ 8-4 8.2.2 skew elimination ........................................................................................................ 8 -4 8.2.3 pre-divider .............................................................................................................. .... 8-4 8.2.4 pll block diag ram .................................................................................................... 8-4 8.2.5 pll pins ................................................................................................................. .... 8-5 8.3 system clock during pll loss of lock ........................................................................ 8-6 8.4 low-power divider ........................................................................................................ 8- 6 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xi contents paragraph number title page number 8.5 internal clock signals ..................................................................................................... 8-7 8.5.1 general system cl ocks ........................................... .................................................. 8-10 8.5.2 clock out (clk out) .............................................................................................. 8-13 8.5.3 engineering clock (engclk) ................................................................................ 8-14 8.6 clock source swit ching ................................................................................................ 8-14 8.7 low-power mode s ........................................................................................................ 8-16 8.7.1 entering a low-powe r mode .................................................................................... 8-16 8.7.2 power mode descri ptions ......................................................................................... 8-17 8.7.3 exiting from low-po wer modes .............................................................................. 8-17 8.7.3.1 exiting from normal -low mode .......................................................................... 8-18 8.7.3.2 exiting from doze mode ...................................................................................... 8-19 8.7.3.3 exiting from deep-s leep mode ............................................................................ 8-19 8.7.3.4 exiting from power- down mode ......................................................................... 8-19 8.7.3.5 low-power modes flow ...................................................................................... 8-19 8.8 basic power stru cture ................................................. .................................................. 8-2 1 8.8.1 general power supply definitions ........................................................................... 8-21 8.8.2 chip power structure ................................................................................................ 8-22 8.8.2.1 nvddl ................................................................................................................ 8- 22 8.8.2.2 qvddl ................................................................................................................ 8- 22 8.8.2.3 vdd .................................................................................................................... .. 8-22 8.8.2.4 vddsyn, vsssy n ............................................................................................ 8-22 8.8.2.5 kapwr ................................................................................................................ 8- 22 8.8.2.6 vdda, vssa ....................................................................................................... 8-22 8.8.2.7 vflash ............................................................................................................... 8- 22 8.8.2.8 vddf, vssf ........................................................................................................ 8-22 8.8.2.9 vddh ................................................................................................................... 8-23 8.8.2.10 iramstby .......................................................................................................... 8-23 8.8.2.11 vss ................................................................................................................... .... 8-23 8.8.3 keep-alive po wer ..................................................................................................... 8-24 8.8.3.1 keep-alive power c onfiguration ......................................................................... 8-24 8.8.3.2 keep-alive power register s lock mechanism .................................................... 8-25 8.9 iramstby supply failur e detection ......................................................................... 8-27 8.10 power-up/down se quencing ....................................................................................... 8-27 8.11 clocks unit program ming model ................................................................................. 8-29 8.11.1 system clock control re gister (sccr) ................................................................... 8-29 8.11.2 pll, low-power, and reset-cont rol register (plprcr) ...................................... 8-33 8.11.3 change of lock interrupt register (col ir) ............................................................ 8-36 8.11.4 iramstby control regist er (vsrmcr) .............................................................. 8-37 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xii contents paragraph number title page number chapter 9 external bus interface 9.1 features ................................................................................................................... ........ 9-1 9.2 bus transfer signals ....................................................................................................... 9-1 9.3 bus control si gnals ........................................................................................................ 9-2 9.4 bus interface signal de scriptions ................................................................................... 9-3 9.5 bus operati ons ............................................................................................................. ... 9-8 9.5.1 basic transfer pr otocol ... ........................................................................................... 9-8 9.5.2 single beat tr ansfer ................................................................................................... 9- 9 9.5.2.1 single beat read flow ........................................................................................... 9-9 9.5.2.2 single beat write flow ........................................................................................ 9-11 9.5.2.3 single beat flow with small port si ze ................................................................. 9-14 9.5.3 data bus pre-discha rge mode ................................................................................. 9-15 9.5.3.1 operating conditi ons ............................................................................................ 9-16 9.5.3.2 initialization se quence .......................................................................................... 9-16 9.5.4 burst transfer ........................................................................................................... 9-17 9.5.5 burst mechanis m ...................................................................................................... 9-18 9.5.6 alignment and packaging of transfers .................................................................... 9-29 9.5.7 arbitration ph ase ...................................................................................................... 9- 32 9.5.7.1 bus request .......................................................................................................... 9- 33 9.5.7.2 bus grant .............................................................................................................. 9-33 9.5.7.3 bus busy ............................................................................................................... 9-34 9.5.7.4 internal bus ar biter ............................................ .................................................. 9-35 9.5.8 address transfer phase signals ................................................................................ 9-37 9.5.8.1 transfer start ........................................................................................................ 9 -37 9.5.8.2 address bu s .......................................................................................................... 9- 37 9.5.8.3 read/write ............................................................................................................ 9 -37 9.5.8.4 burst indicat or ...................................................................................................... 9- 37 9.5.8.5 transfer size ......................................................................................................... 9 -38 9.5.8.6 address type s ...................................................................................................... 9-38 9.5.8.7 burst data in pr ogress . ......................................................................................... 9-40 9.5.9 termination signa ls .................................................................................................. 9-40 9.5.9.1 transfer acknowle dge .......................................................................................... 9-40 9.5.9.2 burst inhibit .......................................................................................................... 9-40 9.5.9.3 transfer error acknowledge ................................................................................ 9-40 9.5.9.4 termination signals protocol ............................................................................... 9-40 9.5.10 storage reserva tion ................................................ .................................................. 9-4 2 9.5.11 bus exception contro l cycles .................................................................................. 9-45 9.5.11.1 retrying a bus cycle .......................................... .................................................. 9-45 9.5.11.2 termination signals prot ocol summary ............................................................... 9-49 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xiii contents paragraph number title page number 9.5.12 bus operation in external master mode s ................................................................. 9-49 9.5.13 contention resolution on external bus .................................................................... 9-53 9.5.14 show cycle transa ctions . ......................................................................................... 9-55 chapter 10 memory controller 10.1 overview .................................................................................................................. ..... 10-1 10.2 memory controller architecture .................................................................................. 10-3 10.2.1 associated regi sters ................................................................................................. 10- 4 10.2.2 port size confi guration ... ......................................................................................... 10-4 10.2.3 write-protect conf iguration ..................................................................................... 10-5 10.2.4 address and address sp ace checking ...................................................................... 10-5 10.2.5 burst support ........................................................................................................... . 10-5 10.2.6 reduced data setup time ........................................................................................ 10-6 10.2.6.1 case 1: normal se tup time .................................................................................. 10-6 10.2.6.2 case 2: short se tup time ..................................................................................... 10-7 10.2.6.3 summary of short se tup time ............................................................................. 10-8 10.3 chip-select ti ming ..................................................................................................... 10- 10 10.3.1 memory devices interf ace example ...................................................................... 10-12 10.3.2 peripheral devices inte rface exampl e .................................................................... 10-13 10.3.3 relaxed timing examples ...................................................................................... 10-14 10.3.4 extended hold time on read accesses ................................................................. 10-18 10.3.5 summary of gpcm ti ming options ...................................................................... 10-22 10.4 write and byte enab le signals ................................................................................... 10-24 10.5 dual mapping of the internal flash eeprom array ................................................ 10-24 10.6 dual mapping of an extern al flash region ............................................................... 10-26 10.7 global (boot) chip-selec t operation ......................................................................... 10-27 10.8 memory controller extern al master support ............................................................. 10-28 10.9 programming model ................................................................................................... 10-31 10.9.1 general memory controller programming notes .................................................. 10-31 10.9.2 memory controller status registers (mstat) ..................................................... 10-32 10.9.3 memory controller base re gisters (br0?br3) .................................................... 10-32 10.9.4 memory controller option registers (or0 ?or3) ................................................ 10-34 10.9.5 dual-mapping base regi ster (dmbr) .................................................................. 10-36 10.9.6 dual-mapping option regi ster (dmor) ............................................................... 10-37 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xiv contents paragraph number title page number chapter 11 l-bus to u-bus interface (l2u) 11.1 general feat ures .......................................................................................................... . 11-1 11.2 data memory protection unit features ........................................................................ 11-1 11.3 l2u block diagram ...................................................................................................... 11- 2 11.4 modes of oper ation ..................................................................................................... 11- 3 11.4.1 normal mode ............................................................................................................ 1 1-3 11.4.2 reset operat ion ......................................................................................................... 11-4 11.4.3 peripheral mode ........................................................................................................ 1 1-4 11.4.4 factory test mode .................................................................................................... 11- 4 11.5 data memory prot ection ............................................. .................................................. 11-4 11.5.1 functional descri ption .............................................................................................. 11-5 11.5.2 associated regi sters ................................................................................................. 11- 6 11.5.3 l-bus memory access violations ............................................................................ 11-7 11.6 reservation s upport ...................................................................................................... 1 1-7 11.6.1 reservation prot ocol ................................................................................................. 11- 8 11.6.2 l2u reservation support ......................................................................................... 11-8 11.6.3 reserved location (bus) a nd possible actions ........................................................ 11-9 11.7 l-bus show cycle support .......................................................................................... 11-9 11.7.1 programming show cycles .................................................................................... 11-10 11.7.2 performance imp act ................................................................................................ 11-10 11.7.3 show cycle prot ocol .............................................. ................................................ 11-10 11.7.4 l-bus write show cycle flow ............................................................................... 11-10 11.7.5 l-bus read show cycle flow ................................................................................ 11-11 11.7.6 show cycle support guidelines ............................................................................. 11-11 11.8 l2u programming m odel ........................................................................................... 11-12 11.8.1 u-bus acce ss .......................................................................................................... 11 -13 11.8.2 transaction size ...................................................................................................... 11 -13 11.8.3 l2u module configuration re gister (l2u_mcr) ................................................ 11-13 11.8.4 region base address regist ers (l2u_rbax) ....................................................... 11-14 11.8.5 region attribute regist ers (l2u_rax) ................................................................. 11-15 11.8.6 global region attribute re gister (l2u_g ra) ...................................................... 11-16 chapter 12 u-bus to imb3 bus interface (uimb) 12.1 features .................................................................................................................. ....... 12-1 12.2 uimb block diag ram .................................................................................................. 12-2 12.3 clock modul e .............................................................................................................. . 12-2 12.4 interrupt oper ation ....................................................................................................... 12-3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xv contents paragraph number title page number 12.4.1 interrupt sources and le vels on imb3 ..................................................................... 12-3 12.4.2 imb3 interrupt mu ltiplexing .................................................................................... 12-4 12.4.3 ilbs sequencing ...................................................................................................... 12- 4 12.4.4 interrupt synchron izer .............................................................................................. 12-5 12.5 programming model ..................................................................................................... 12-6 12.5.1 uimb module configuration register (umc r) ..................................................... 12-7 12.5.2 test control register (utstcreg) ........................................................................ 12-8 12.5.3 pending interrupt request re gister (uipend) ........................................................ 12-8 chapter 13 qadc64e legacy mode operation 13.1 qadc64e block diagram ........................................................................................... 13-1 13.2 key features and quick re ference diagrams .............................................................. 13-2 13.2.1 features of the qadc64e le gacy mode operation ................................................ 13-2 13.2.2 memory map ............................................................................................................ 13 -3 13.2.3 legacy and enhanced mode s of operation .............................................................. 13-4 13.2.4 using the queue and result word table ................................................................. 13-5 13.2.5 external multip lexing ............................................................................................... 13-5 13.3 programming the qadc64e registers ........................................................................ 13-7 13.3.1 qadc64e module configurati on register (qadmcr) ........................................ 13-8 13.3.1.1 low power stop mode ......................................................................................... 13-9 13.3.1.2 freeze mode ......................................................................................................... 13 -9 13.3.1.3 switching between legacy and enha nced modes of operation ........................ 13-10 13.3.1.4 supervisor/unrestricted address spac e ............................................................. 13-10 13.3.2 qadc64e interrupt regist er (qadcint) ............................................................ 13-12 13.3.3 port data register (por tqa and portqb) ........................................................ 13-13 13.3.4 port data direction re gister (ddrqa) ................................................................. 13-14 13.3.5 control register 0 (qacr0) .................................................................................. 13-14 13.3.6 control register 1 (qacr1) .................................................................................. 13-15 13.3.7 control register 2 (qacr2) .................................................................................. 13-17 13.3.8 status registers (qasr0 and qasr1) .................................................................. 13-20 13.3.9 conversion command word table ........................................................................ 13-27 13.3.10 result word table .................................................................................................. 13-3 2 13.4 analog subsyste m ...................................................................................................... 13-3 4 13.4.1 analog-to-digital conver ter operation .................................................................. 13-34 13.4.1.1 conversion cycle times ..................................................................................... 13-35 13.4.1.2 amplifier bypass mode c onversion timing ..................................................... 13-35 13.4.2 channel decode and multiplexer ........................................................................... 13-36 13.4.3 sample buffer am plifier ........................................................................................ 13-36 13.4.4 digital-to-analog conver ter (dac) array ............................................................ 13-36 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xvi contents paragraph number title page number 13.4.5 comparator ............................................................................................................. 1 3-37 13.4.6 bias .................................................................................................................... ..... 13-37 13.4.7 successive approximati on register ...................................................................... 13-37 13.4.8 state machine ......................................................................................................... 13 -37 13.5 digital subsystem ....................................................................................................... 13 -37 13.5.1 queue priority ......................................................................................................... 1 3-38 13.5.2 paused sub-queu es ................................................................................................. 13-38 13.5.3 boundary conditi ons .............................................................................................. 13-40 13.5.4 scan modes ............................................................................................................. 1 3-41 13.5.4.1 disabled mode .................................................................................................... 13-41 13.5.4.2 reserved mode ................................................................................................... 13-41 13.5.4.3 single-scan m odes ............................................. ................................................ 13-42 13.5.4.3.1 software initiated si ngle-scan mode ............................................................. 13-42 13.5.4.3.2 external trigger singl e-scan mode ............................................................... 13-43 13.5.4.3.3 external gated singl e-scan mode ................................................................. 13-43 13.5.4.3.4 periodic/interval timer single-scan m ode .................................................... 13-44 13.5.4.4 continuous-scan modes ..................................................................................... 13-44 13.5.4.4.1 software initiated cont inuous-scan mode ..................................................... 13-45 13.5.4.4.2 external trigger cont inuous-scan mode ....................................................... 13-46 13.5.4.4.3 external gated conti nuous-scan mode ......................................................... 13-46 13.5.4.4.4 periodic/interval timer continuous-scan mode ............................................ 13-47 13.5.5 qadc64e clock (qclk) generation ................................................................... 13-47 13.5.6 periodic / interval timer .. ....................................................................................... 13-51 13.5.7 configuration and control usin g the imb3 interface ............................................ 13-51 13.5.7.1 qadc64e bus interf ace unit ............................................................................ 13-51 13.5.7.2 qadc64e bus ac cessing .................................................................................. 13-52 13.6 trigger and queue inter action examples ................................................................... 13-54 13.6.1 queue priority sc hemes .......................................... ................................................ 13-54 13.6.2 conversion timing schemes .................................................................................. 13-63 13.7 qadc64e integration requirements ......................................................................... 13-66 13.7.1 port digital input/out put signals ........................................................................... 13-66 13.7.2 external trigger i nput signals ................................................................................ 13-67 13.7.3 analog power signa ls ............................................................................................. 13-67 13.7.3.1 analog supply filtering and grounding ............................................................ 13-69 13.7.4 analog reference signals ....................................................................................... 13-71 13.7.5 analog input signa ls .............................................................................................. 13-71 13.7.5.1 analog input consid erations .............................................................................. 13-73 13.7.5.2 settling time for the ex ternal circui t ................................................................ 13-75 13.7.5.3 error resulting from leakage ............................................................................ 13-75 13.7.5.4 accommodating positive/negativ e stress conditions ....................................... 13-76 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xvii contents paragraph number title page number chapter 14 qadc64e enhanced mode operation 14.1 qadc64e block diagram ........................................................................................... 14-1 14.2 key features and quick re ference diagrams .............................................................. 14-2 14.2.1 features of the qadc64e enha nced mode operation ............................................ 14-2 14.2.2 memory map ............................................................................................................ 14 -3 14.2.3 legacy and enhanced mode s of operation .............................................................. 14-4 14.2.4 using the queue and result word table ................................................................. 14-5 14.2.5 external multip lexing ............................................................................................... 14-5 14.3 programming the qadc64e registers ........................................................................ 14-7 14.3.1 qadc64e module configurat ion register ........................................................... 14-8 14.3.1.1 low power stop mode ......................................................................................... 14-8 14.3.1.2 freeze mode ......................................................................................................... 14 -9 14.3.1.3 switching between legacy and enha nced modes of operation .......................... 14-9 14.3.1.4 supervisor/unrestricted address spac e ............................................................. 14-10 14.3.2 qadc64e interrupt register ................................................................................. 14-11 14.3.3 port data regi ster ................................................................................................... 14- 12 14.3.4 port data directio n register ................................................................................... 14-13 14.3.5 control register 0 ................................................................................................... 14- 14 14.3.6 control register 1 ................................................................................................... 14- 16 14.3.7 control register 2 ................................................................................................... 14- 18 14.3.8 status registers (qasr0 and qasr1) .................................................................. 14-22 14.3.9 conversion command word table ........................................................................ 14-28 14.3.10 result word table .................................................................................................. 14-3 4 14.3.10.1 analog subsys tem .............................................................................................. 14-36 14.3.11 analog-to-digital conver ter operation .................................................................. 14-36 14.3.11.1 conversion cycl e times ..................................................................................... 14-36 14.3.12 channel decode and multiplexer ........................................................................... 14-37 14.3.13 sample buffer am plifier ........................................................................................ 14-37 14.3.14 digital to analog convert er (dac) arra y ............................................................. 14-37 14.3.15 comparator ............................................................................................................. 14-38 14.3.16 bias ................................................................................................................... ...... 14-38 14.3.17 successive approximati on register ...................................................................... 14-38 14.3.18 state machine ......................................................................................................... 1 4-38 14.4 digital subsystem ....................................................................................................... 14 -38 14.4.1 queue priority ......................................................................................................... 1 4-39 14.4.2 sub-queues that ar e paused .................................................................................. 14-39 14.4.3 boundary conditi ons .............................................................................................. 14-41 14.4.4 scan modes ............................................................................................................. 1 4-42 14.4.4.1 disabled mode .................................................................................................... 14-42 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xviii contents paragraph number title page number 14.4.4.2 reserved mode ................................................................................................... 14-42 14.4.4.3 single-scan m odes ............................................. ................................................ 14-43 14.4.4.3.1 software initiated si ngle-scan mode ............................................................. 14-43 14.4.4.3.2 external trigger singl e-scan mode ............................................................... 14-44 14.4.4.3.3 external gated singl e-scan mode ................................................................. 14-44 14.4.4.3.4 periodic/interval timer single-scan m ode .................................................... 14-45 14.4.4.4 continuous-scan modes ..................................................................................... 14-45 14.4.4.4.1 software initiated cont inuous-scan mode ..................................................... 14-46 14.4.4.4.2 external trigger cont inuous-scan mode ....................................................... 14-47 14.4.4.4.3 external gated conti nuous-scan mode ......................................................... 14-47 14.4.4.4.4 periodic/interval timer continuous-scan mode ............................................ 14-48 14.4.5 qadc64e clock (qclk) generation ................................................................... 14-48 14.4.6 periodic/interval timer ........................................... ................................................ 14-50 14.4.7 configuration and control usin g the imb3 interface ............................................ 14-51 14.4.7.1 qadc64e bus interf ace unit ............................................................................ 14-51 14.4.7.2 qadc64e bus ac cessing .................................................................................. 14-51 14.5 trigger and queue inter action examples ................................................................... 14-53 14.5.1 queue priority sc hemes .......................................... ................................................ 14-53 14.5.2 conversion timing schemes .................................................................................. 14-62 14.6 qadc64e integration requirements ......................................................................... 14-65 14.6.1 port digital input/out put signals ........................................................................... 14-65 14.6.2 external trigger i nput signals ................................................................................ 14-66 14.6.3 analog power signa ls ............................................................................................. 14-66 14.6.3.1 analog supply filtering and grounding ............................................................ 14-67 14.6.4 analog reference signals ....................................................................................... 14-69 14.6.5 analog input signa ls .............................................................................................. 14-70 14.6.5.1 analog input consid erations .............................................................................. 14-71 14.6.5.2 settling time for the ex ternal circui t ................................................................ 14-73 14.6.5.3 error resulting from leakage ............................................................................ 14-73 14.6.5.4 accommodating positive/negativ e stress conditions ....................................... 14-74 chapter 15 queued serial mu lti-channel module 15.1 block diag ram ............................................................................................................. . 15-1 15.2 key features .............................................................................................................. ... 15-2 15.2.1 mpc561/mpc563 qsmcm details ........................................................................ 15-3 15.3 memory ma ps ............................................................................................................... 15-4 15.4 qsmcm global regi sters ............................................................................................ 15-6 15.4.1 low-power stop operation ...................................................................................... 15-6 15.4.2 freeze operation ....................................................................................................... 1 5-6 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xix contents paragraph number title page number 15.4.3 access protect ion ...................................................................................................... 1 5-6 15.4.4 qsmcm interrupt s ................................................................................................... 15-7 15.4.5 qspi interrupt ge neration ........................................................................................ 15-8 15.4.6 qsmcm configuration regi ster (qsmcmmcr) .................................................. 15-8 15.4.7 qsmcm test register (qtest) ............................................................................. 15-9 15.4.8 qsmcm interrupt level register s (qdsci_il, qs pi_il) ..................................... 15-9 15.5 qsmcm pin control registers .................................................................................. 15-10 15.5.1 port qs data regist er (portqs) .......................................................................... 15-11 15.5.2 portqs pin assignment regi ster (pqspar) ..................................................... 15-12 15.5.3 portqs data direction re gister (ddrqs) ......................................................... 15-13 15.6 queued serial peripheral interface ............................................................................. 15-14 15.6.1 qspi registers ....................................................................................................... 15 -16 15.6.1.1 qspi control register 0 (spcr0) ...................................................................... 15-17 15.6.1.2 qspi control register 1 (spcr1) ...................................................................... 15-19 15.6.1.3 qspi control register 2 (spcr2) ...................................................................... 15-20 15.6.1.4 qspi control register 3 (spcr3) ...................................................................... 15-20 15.6.1.5 qspi status regist er (spsr) .............................................................................. 15-21 15.6.2 qspi ram .............................................................................................................. 15 -22 15.6.2.1 receive ram ..................................................................................................... 15-23 15.6.2.2 transmit ram .................................................................................................... 15-23 15.6.2.3 command ram .................................................................................................. 15-23 15.6.3 qspi pins ............................................................................................................... . 15-24 15.6.4 qspi operation ....................................................................................................... 15- 25 15.6.4.1 enabling, disabling, and ha lting the spi ........................................................... 15-26 15.6.4.2 qspi interrupt s ................................................................................................... 15-2 6 15.6.4.3 qspi flow .......................................................................................................... 15- 27 15.6.5 master mode oper ation .......................................................................................... 15-34 15.6.5.1 clock phase and po larity .................................................................................... 15-35 15.6.5.2 baud rate select ion ............................................................................................ 15-35 15.6.5.3 delay before tran sfer ........................................................................................ 15-36 15.6.5.4 delay after tran sfer ........................................................................................... 15-36 15.6.5.5 transfer length .................................................................................................. 15-37 15.6.5.6 peripheral chip selects ....................................................................................... 15-37 15.6.5.7 optional enhanced periphera l chip selects ....................................................... 15-37 15.6.5.8 master wraparound mode .................................................................................. 15-38 15.6.6 slave mode ............................................................................................................. 1 5-39 15.6.6.1 description of slav e operation .......................................................................... 15-40 15.6.7 slave wraparound m ode ........................................ ................................................ 15-41 15.6.8 mode fault .............................................................................................................. 15-42 15.7 serial communicati on interface ................................................................................. 15-42 15.7.1 sci register s .......................................................................................................... 1 5-45 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xx contents paragraph number title page number 15.7.2 sci control register 0 (sccxr0) .......................................................................... 15-46 15.7.3 sci control register 1 (sccxr1) .......................................................................... 15-47 15.7.4 sci status register (scxsr) .................................................................................. 15-48 15.7.5 sci data register (scxdr) ................................................................................... 15-50 15.7.6 sci pins ................................................................................................................ .. 15-51 15.7.7 sci operati on ......................................................................................................... 15 -51 15.7.7.1 definition of te rms ............................................................................................ 15-51 15.7.7.2 serial formats ..................................................................................................... 15- 52 15.7.7.3 baud clock ......................................................................................................... 15- 52 15.7.7.4 parity checking .................................................................................................. 15-53 15.7.7.5 transmitter oper ation ......................................................................................... 15-54 15.7.7.6 receiver operat ion ............................................................................................. 15-55 15.7.7.7 receiver bit pro cessor ........................................................................................ 15-55 15.7.7.8 receiver functional operation ........................................................................... 15-57 15.7.7.9 idle-line detect ion ............................................................................................. 15-58 15.7.7.10 receiver wake- up .............................................................................................. 15-58 15.7.7.11 internal loop mode ............................................................................................ 15-59 15.8 sci queue operat ion .................................................................................................. 15-59 15.8.1 queue operation of sci1 for transmit and r eceive .............................................. 15-59 15.8.2 queued sci1 status and control registers ............................................................ 15-59 15.8.2.1 qsci1 control register (qsci1cr) .................................................................. 15-60 15.8.2.2 qsci1 status register (qsci1sr) .................................................................... 15-61 15.8.3 qsci1 transmitter bl ock diagram ........................................................................ 15-62 15.8.4 qsci1 additional transmit op eration featur es .................................................... 15-63 15.8.5 qsci1 transmit flow chart implementing the queue .......................................... 15-65 15.8.6 example qsci1 transmit fo r 17 data bytes ......................................................... 15-67 15.8.7 example sci transmit fo r 25 data bytes .............................................................. 15-68 15.8.8 qsci1 receiver block diagram ............................................................................. 15-70 15.8.9 qsci1 additional receive op eration featur es ...................................................... 15-70 15.8.10 qsci1 receive flow chart implementing the queue ............................................ 15-73 15.8.11 qsci1 receive queue software flow chart ......................................................... 15-74 15.8.12 example qsci1 receive operati on of 17 data fr ames ......................................... 15-75 chapter 16 can 2.0b controller module 16.1 features .................................................................................................................. ....... 16-1 16.2 external si gnals .......................................................................................................... .. 16-2 16.2.1 toucan signal sh aring ........................................................................................... 16-3 16.3 toucan architect ure ................................................................................................... 16-3 16.3.1 tx/rx message buffer structure .............................................................................. 16-4 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxi contents paragraph number title page number 16.3.1.1 common fields for extended and st andard format frames ................................ 16-4 16.3.1.2 fields for extended format frames ..................................................................... 16-6 16.3.1.3 fields for standard fo rmat frames ...................................................................... 16-6 16.3.1.4 serial message buffers ......................................................................................... 16-6 16.3.1.5 message buffer activation/de activation mechanism .......................................... 16-7 16.3.1.6 message buffer lock/releas e/busy mechanism ................................................. 16-7 16.3.2 receive mask regi sters ............................................................................................ 16-7 16.3.3 bit timing .............................................................................................................. ... 16-8 16.3.3.1 configuring the touc an bit timing ................................................................ 16-10 16.3.4 error counter s ......................................................................................................... 1 6-10 16.3.5 time stamp ............................................................................................................. 1 6-12 16.4 toucan operat ion ..................................................................................................... 16-12 16.4.1 toucan rese t ........................................................................................................ 16-1 2 16.4.2 toucan initiali zation ............................................ ................................................ 16-13 16.4.3 transmit process ..................................................................................................... 16- 13 16.4.3.1 transmit message buffer deactivati on .............................................................. 16-14 16.4.3.2 reception of transmit ted frames ....................................................................... 16-14 16.4.4 receive pro cess ...................................................................................................... 16- 14 16.4.4.1 receive message buffer deactivation ................................................................ 16-16 16.4.4.2 locking and releasing me ssage buffers ........................................................... 16-16 16.4.5 remote frames ....................................................................................................... 16-1 7 16.4.6 overload fram es ..................................................................................................... 16-1 7 16.5 special operating modes ............................................ ................................................ 16-17 16.5.1 debug mode ........................................................................................................... 16- 17 16.5.2 low-power stop m ode ........................................... ................................................ 16-18 16.5.3 auto power save mode .......................................... ................................................ 16-19 16.6 interrupts ................................................................................................................ ..... 16-20 16.7 programming model ................................................................................................... 16-21 16.7.1 toucan module configuration register (canmcr) ......................................... 16-25 16.7.2 toucan test configurat ion register .................................................................... 16-27 16.7.3 toucan interrupt configurati on register (canicr) .......................................... 16-27 16.7.4 control register 0 (canctrl0) ........................................................................... 16-27 16.7.5 control register 1 (canctrl1) ........................................................................... 16-28 16.7.6 prescaler divide regist er (presdiv) ................................................................... 16-29 16.7.7 control register 2 (canctrl2) ........................................................................... 16-30 16.7.8 free running timer (timer) ................................................................................ 16-31 16.7.9 receive global mask register s (rxgmskhi, rxgmsklo) ............................ 16-31 16.7.10 receive buffer 14 mask register s (rx14mskhi, rx14msklo) ...................... 16-32 16.7.11 receive buffer 15 mask register s (rx15mskhi, rx15msklo) ...................... 16-33 16.7.12 error and status regi ster (estat) ........................................................................ 16-33 16.7.13 interrupt mask regist er (imask) .......................................................................... 16-35 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxii contents paragraph number title page number 16.7.14 interrupt flag regist er (iflag) ............................................................................. 16-36 16.7.15 error counters (rxect r, txectr) .................................................................... 16-36 chapter 17 modular input/outpu t subsystem (mios14) 17.1 block diag ram ............................................................................................................. . 17-1 17.2 mios14 key feat ures .................................................................................................. 17-3 17.2.1 submodule numbering, naming, and addressing ................................................... 17-4 17.2.2 signal naming c onvention ....................................................................................... 17-5 17.3 mios14 configur ation ................................................................................................. 17-6 17.3.1 mios14 signa ls ........................................................................................................ 17 -9 17.3.2 mios14 bus syst em ................................................................................................ 17-9 17.3.3 read/write and c ontrol bus ................................................................................... 17-10 17.3.4 request bus ............................................................................................................ 1 7-10 17.3.5 counter bus set ...................................................................................................... 17- 10 17.4 mios14 programmi ng model .................................................................................... 17-10 17.4.1 bus error suppor t ................................................................................................... 17-1 0 17.4.2 wait stat es ............................................................................................................. . 17-11 17.5 mios14 i/o po rts ....................................................................................................... 17- 13 17.6 mios14 bus interface s ubmodule (mbism) ............................................................ 17-13 17.6.1 mios14 bus interface (mbi sm) registers ........................................................... 17-13 17.6.1.1 mios14 test and signal control register (mios14tpcr) ............................. 17-13 17.6.1.2 mios14 vector register (mios14vect) ........................................................ 17-14 17.6.1.3 mios14 module and version number register (mio s14vnr) ...................... 17-14 17.6.1.4 mios14 module configuration register (mios14mcr) ................................. 17-15 17.7 mios14 counter prescaler submodule (mcpsm) .................................................... 17-16 17.7.1 mcpsm features .................................................................................................... 17-16 17.7.1.1 mcpsm signal f unctions .................................................................................. 17-17 17.7.1.2 modular i/o bus (miob) interface .................................................................... 17-17 17.7.2 effect of reset on mcpsm ................................................................................. 17-17 17.7.3 mcpsm register s .................................................................................................. 17-17 17.7.3.1 mcpsm registers or ganization ........................................................................ 17-17 17.7.3.2 mcpsm status/control regi ster (mcpsmscr) .............................................. 17-18 17.8 mios14 modulus counter submodule (mmcsm ) ................................................... 17-19 17.8.1 mmcsm features .................................................................................................. 17-20 17.8.1.1 mmcsm signal func tions ................................................................................. 17-21 17.8.2 mmcsm prescale r ................................................................................................. 17-21 17.8.3 modular i/o bus (miob) interface ........................................................................ 17-21 17.8.4 effect of reset on mmcsm ................................................................................ 17-22 17.8.5 mmcsm register s ................................................................................................. 17-22 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxiii contents paragraph number title page number 17.8.5.1 mmcsm register or ganization ......................................................................... 17-22 17.8.5.2 mmcsm up-counter regist er (mmcsmcnt) ............................................... 17-23 17.8.5.3 mmcsm modulus latch regi ster (mmcsmml) ............................................ 17-24 17.8.5.4 mmcsm status/control register (mmcsmscrd) (duplicated) .................................................................................................... 17-24 17.8.5.5 mmcsm status/control regi ster (mmcsmscr) ............................................ 17-24 17.9 mios14 double action subm odule (mdasm) ........................................................ 17-26 17.9.1 mdasm features ................................................................................................... 17-27 17.9.1.1 mdasm signal functions ................................................................................. 17-28 17.9.2 mdasm descript ion .............................................................................................. 17-28 17.9.3 mdasm modes of op eration ................................................................................ 17-29 17.9.3.1 disable (dis) m ode ............................................................................................ 17-29 17.9.3.2 input pulse width measurem ent (ipwm) mode ................................................ 17-30 17.9.3.3 input period measuremen t (ipm) mode ............................................................. 17-31 17.9.3.4 input capture (ic) mode .................................................................................... 17-32 17.9.3.5 output compare (ocb a nd ocab) modes ....................................................... 17-33 17.9.3.5.1 single shot output pulse operation ............................................................... 17-34 17.9.3.5.2 single output comp are operati on ................................................................. 17-35 17.9.3.5.3 output port bit operation ............................................................................... 17-36 17.9.3.6 output pulse width modulat ion (opwm) mode .............................................. 17-36 17.9.4 modular i/o bus (miob) interface ........................................................................ 17-39 17.9.5 effect of reset on mdasm ................................................................................ 17-39 17.9.6 mdasm register s ................................................................................................. 17-39 17.9.6.1 mdasm registers or ganization ....................................................................... 17-39 17.9.6.2 mdasm data a (mdasmar ) register .......................................................... 17-41 17.9.6.3 mdasm data b (mdasmbr) register ........................................................... 17-42 17.9.6.4 mdasm status/control register (mdasmscrd) (duplicated) .................... 17-43 17.9.6.5 mdasm status/control regi ster (mdasmscr) ............................................ 17-43 17.10 mios14 pulse width modulati on submodule (mpwmsm) .................................... 17-46 17.10.1 mpwmsm termi nology ........................................................................................ 17-47 17.10.2 mpwmsm featur es ............................................................................................... 17-47 17.10.3 mpwmsm descript ion .......................................................................................... 17-48 17.10.3.1 clock selec tion ................................................................................................... 17- 49 17.10.3.2 counter .............................................................................................................. . 17-49 17.10.3.3 period regist er .................................................................................................... 17 -49 17.10.3.4 pulse width regi sters ......................................................................................... 17-50 17.10.3.5 duty cycles (0 % and 100%) .............................................................................. 17-51 17.10.3.6 pulse/frequency ra nge table ............................................................................ 17-52 17.10.3.7 mpwmsm status and contro l register (scr) ................................................. 17-53 17.10.3.8 mpwmsm interr upt .......................................................................................... 17-53 17.10.3.9 mpwmsm port f unctions ................................................................................. 17-54 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxiv contents paragraph number title page number 17.10.3.10 mpwmsm data c oherency ............................................................................... 17-54 17.10.4 modular input/output bus (m ios14) interface ..................................................... 17-54 17.10.5 effect of reset on mpwmsm ............................................................................ 17-54 17.10.6 mpwmsm regist ers .............................................................................................. 17-55 17.10.6.1 mpwmsm registers organization .................................................................... 17-55 17.10.6.2 mpwmsm period register (mpwmperr) ..................................................... 17-57 17.10.6.3 mpwmsm pulse width regi ster (mpwmpulr) ........................................... 17-57 17.10.6.4 mpwmsm counter regist er (mpwmcntr) .................................................. 17-58 17.10.6.5 mpwmsm status/control register (mpw mscr) ........................................... 17-58 17.11 mios14 16-bit parallel port i/o submodule (mpiosm) .......................................... 17-60 17.11.1 mpiosm featur es .................................................................................................. 17-61 17.11.2 mpiosm signal f unctions ..................................................................................... 17-61 17.11.3 mpiosm descript ion ............................................................................................. 17-61 17.11.3.1 mpiosm port function ...................................................................................... 17-61 17.11.3.2 non-bonded mpiosm pads .............................................................................. 17-61 17.11.4 modular i/o bus (miob) interface ........................................................................ 17-62 17.11.5 effect of reset on mpiosm ............................................................................... 17-62 17.11.6 mpiosm testi ng .................................................................................................... 17-62 17.11.7 mpiosm regist ers ................................................................................................. 17-62 17.11.8 mpiosm register or ganization ............................................................................ 17-62 17.11.8.1 mpiosm data register (mpiosmdr) ............................................................. 17-62 17.11.8.2 mpiosm data direction re gister (mpiosmddr) .......................................... 17-63 17.12 mios14 interr upts ...................................................................................................... 17 -63 17.12.1 mios14 interrupt structure .................................................................................... 17-63 17.12.2 mios14 interrupt request submodule (mirsm) ................................................. 17-64 17.12.3 mirsm0 interrupt registers .................................................................................. 17-65 17.12.3.1 interrupt status regist er (mios14sr0 ) ............................................................. 17-65 17.12.3.2 interrupt enable regist er (mios14er0) ........................................................... 17-66 17.12.3.3 interrupt request pending re gister (mios14rpr0) ......................................... 17-66 17.12.4 mirsm1 interrupt registers .................................................................................. 17-67 17.12.4.1 interrupt status regist er (mios14sr1 ) ............................................................. 17-67 17.12.4.2 interrupt enable regist er (mios14er1) ........................................................... 17-68 17.12.4.3 interrupt request pending re gister (mios14rpr1) ......................................... 17-68 17.12.5 interrupt control section (ics) .............................................................................. 17-69 17.12.6 mbism interrupt registers .................................................................................... 17-69 17.12.6.1 mios14 interrupt level register 0 (m ios14lvl0) ........................................ 17-69 17.12.6.2 mios14 interrupt level register 1 (m ios14lvl1) ........................................ 17-70 17.13 mios14 function ex amples ...................................................................................... 17-70 17.13.1 mios14 input double edge pu lse width measurement ........................................ 17-70 17.13.2 mios14 input double edge period measurem ent ................................................. 17-71 17.13.3 mios14 double edge single ou tput pulse generation ......................................... 17-72 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxv contents paragraph number title page number 17.13.4 mios14 output pulse width modulation with mdasm ...................................... 17-73 17.13.5 mios14 input pulse accumulation ........................................................................ 17-74 chapter 18 peripheral pin multiplexing (ppm) module 18.1 key features .............................................................................................................. ... 18-1 18.2 programming model ..................................................................................................... 18-2 18.3 functional descri ption .................................................................................................. 18 -3 18.3.1 ppm parallel-to-serial comm unication protoc ol ..................................................... 18-3 18.3.1.1 internal multiplexing ............................................................................................ 18-4 18.3.1.2 ppm clocks .......................................................................................................... 18 -5 18.3.1.3 ppm control sett ings ........................................................................................... 18-7 18.3.2 ppm signal short f unctionality ............................................................................... 18-9 18.3.2.1 toucan shortin g ................................................................................................. 18-9 18.3.2.2 tpu shorting ........................................................................................................ 18 -9 18.3.2.3 etrig1 and etrig 2 ........................................................................................... 18-9 18.3.2.4 t2clk ................................................................................................................ 1 8-10 18.3.3 ppm module pad conf iguration ............................................................................. 18-10 18.4 ppm regist ers ............................................................................................................. 18-10 18.4.1 module configuration regi ster (ppmmcr) .......................................................... 18-10 18.4.1.1 entering stop mo de ............................................................................................ 18-11 18.4.2 ppm control register (ppmpcr) .......................................................................... 18-12 18.4.3 transmit configuration registers (t x_config_1 and tx_config_2) ........... 18-15 18.4.4 receive configuration registers (r x_config_1 and rx_c onfig_2) ............ 18-16 18.4.5 receive data register (rx_data) ...................................................................... 18-17 18.4.6 receive shift register (rx_shifter) ................................................................. 18-18 18.4.7 transmit data register (tx_data) ..................................................................... 18-18 18.4.8 general-purpose data out (gpdo) ....................................................................... 18-18 18.4.9 general-purpose data in (gpdi) ............................................................................ 18-19 18.4.10 short register (s hort_reg) .............................................................................. 18-19 18.4.11 short channels register (short_ch_reg) ...................................................... 18-22 18.4.12 scale transmit clock regist er (scale_tclk_reg) ........................................ 18-24 chapter 19 time processor unit 3 19.1 overview .................................................................................................................. ..... 19-2 19.2 tpu3 compone nts ........................................................................................................ 19- 2 19.2.1 time bases .............................................................................................................. .. 19-2 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxvi contents paragraph number title page number 19.2.2 timer channe ls ......................................................................................................... 1 9-2 19.2.3 scheduler ............................................................................................................... ... 19-2 19.2.4 microengine ............................................................................................................. . 19-3 19.2.5 host interface .......................................................................................................... .. 19-3 19.2.6 parameter ra m ........................................................................................................ 19- 3 19.3 tpu operation ............................................................................................................. . 19-3 19.3.1 event timing ............................................................................................................ 19-3 19.3.2 channel orthogonali ty .............................................................................................. 19-4 19.3.3 interchannel comm unication .................................................................................... 19-4 19.3.4 programmable channel se rvice priority .................................................................. 19-4 19.3.5 coherency ............................................................................................................... .. 19-4 19.3.6 emulation s upport .................................................................................................... 19- 4 19.3.7 tpu3 interrupts ........................................................................................................ 1 9-5 19.3.8 prescaler control for tcr1 ...................................................................................... 19-5 19.3.9 prescaler control for tcr2 ...................................................................................... 19-7 19.4 programming model ..................................................................................................... 19-8 19.4.1 tpu module configuration regi ster (tpumcr) ................................................. 19-11 19.4.2 development support control register (dsc r) .................................................... 19-12 19.4.3 development support status register (dssr) ...................................................... 19-13 19.4.4 tpu3 interrupt configuratio n register (tic r) ..................................................... 19-14 19.4.5 channel interrupt enable register (cier) ............................................................. 19-15 19.4.6 channel function select re gisters (cfsrn) .......................................................... 19-15 19.4.7 host sequence regist ers (hsqrn) ........................................................................ 19-16 19.4.8 host service request regi sters (hsrrn) ............................................................. 19-17 19.4.9 channel priority regi sters (cprx) ......................................................................... 19-18 19.4.10 channel interrupt status register (cis r) .............................................................. 19-19 19.4.11 tpu3 module configuration re gister 2 (tpu mcr2) ........................................... 19-19 19.4.12 tpu module configuration re gister 3 (tpumcr3) ............................................. 19-21 19.4.13 siu test register (siutst) ................................................................................... 19-22 19.4.14 factory test regi sters ............................................................................................ 19-22 19.4.15 tpu3 parameter ram ............................................................................................ 19-23 19.5 time functions ........................................................................................................... 1 9-23 chapter 20 dual-port tpu3 ram (dptram) 20.1 features .................................................................................................................. ....... 20-1 20.2 dptram configuration block diagram ..................................................................... 20-2 20.3 programming model ..................................................................................................... 20-2 20.3.1 dptram module configuration register (dptmcr) ......................................... 20-3 20.3.2 dptram test register (dpttcr) ......................................................................... 20-4 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxvii contents paragraph number title page number 20.3.3 ram base address regist er (rambar) ............................................................... 20-4 20.3.4 misr high (misrh) and misr low registers (misrl) ...................................... 20-5 20.3.5 misc counter (m iscnt) ........................................................................................ 20-6 20.4 dptram operat ion ..................................................................................................... 20-6 20.4.1 normal operat ion ..................................................................................................... 20- 6 20.4.2 standby opera tion .................................................................................................... 20- 6 20.4.3 reset operat ion ......................................................................................................... 20-7 20.4.4 stop operat ion .......................................................................................................... 20-7 20.4.5 freeze operation ....................................................................................................... 2 0-7 20.4.6 tpu3 emulation mode operation ............................................................................ 20-7 20.5 multiple input signature ca lculator (misc) ................................................................ 20-8 chapter 21 cdr3 flash (uc3f) eeprom 21.0.1 features of the cdr3 flash eeprom (uc3f) ....................................................... 21-3 21.1 uc3f inte rface ............................................................................................................ . 21-4 21.1.1 external inte rface ...................................................................................................... 21-4 21.2 programming model ..................................................................................................... 21-5 21.2.1 uc3f eeprom control registers .......................................................................... 21-5 21.2.1.1 register addres sing .............................................................................................. 21-5 21.2.1.2 uc3f eeprom configuration register (uc3fmcr) ....................................... 21-5 21.2.1.3 uc3f eeprom extended configurati on register (uc3fmcre) ..................... 21-8 21.2.1.4 uc3f eeprom high voltage contro l register (uc3fctl) .......................... 21-11 21.2.2 uc3f eeprom array addressing ........................................................................ 21-15 21.2.3 uc3f eeprom shadow row ............................................................................... 21-15 21.2.3.1 reset configuration word (uc3fcfig) ........................................................... 21-16 21.2.4 uc3f eeprom 512-kbyte arra y configurati on .................................................. 21-19 21.3 uc3f operat ion .......................................................................................................... 21 -19 21.3.1 reset ................................................................................................................... ..... 21-19 21.3.2 register read and wr ite operation ........................................................................ 21-20 21.3.3 array read oper ation ............................................................................................. 21-20 21.3.3.1 array on-page read operation .......................................................................... 21-21 21.3.4 shadow row select r ead operation ...................................................................... 21-21 21.3.5 array program/erase interloc k write operation .................................................... 21-21 21.3.6 high voltage operations ........................................................................................ 21-21 21.3.6.1 overview of program/era se operation .............................................................. 21-21 21.3.7 programmi ng .......................................................................................................... 21- 21 21.3.7.1 program sequenc e .............................................................................................. 21-22 21.3.7.2 program shadow in formation ............................................................................. 21-24 21.3.7.3 program suspe nd ................................................................................................ 21-25 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxviii contents paragraph number title page number 21.3.8 erasing ................................................................................................................. ... 21-25 21.3.8.1 erase sequen ce ................................................................................................... 21-26 21.3.8.2 erasing shadow information words .................................................................. 21-28 21.3.8.3 erase suspe nd ..................................................................................................... 21-2 8 21.3.9 stop operat ion ........................................................................................................ 21 -28 21.3.10 disabled ............................................................................................................... ... 21-29 21.3.11 censored accesses and non- censored acce sses ................................................... 21-29 21.3.11.1 setting and cleari ng censor ............................................................................... 21-31 21.3.11.2 setting cens or ..................................................................................................... 21 -32 21.3.11.3 clearing cens or .................................................................................................. 21-3 2 21.3.11.4 switching the uc3f eep rom censorship ...................................................... 21-33 21.3.12 background debug mode or freeze operation ...................................................... 21-34 chapter 22 calram operation 22.1 features .................................................................................................................. ....... 22-1 22.2 calram block di agram .......................................... .................................................. 22-2 22.3 calram memory map .............................................................................................. 22-2 22.4 modes of oper ation ...................................................................................................... 22 -4 22.4.1 reset ................................................................................................................... ....... 22-5 22.4.2 one-cycle m ode ....................................................................................................... 22- 5 22.4.2.1 calram access/privileg e violations ................................................................ 22-5 22.4.3 two-cycle mode ...................................................................................................... 22-5 22.4.4 standby operation/keep -alive power .................................................................... 22-5 22.4.5 stop operat ion .......................................................................................................... 22-6 22.4.6 overlay mode op eration ......................................................................................... 22-6 22.4.6.1 overlay mode conf iguration ................................................................................ 22-6 22.4.6.2 priority of overla y regions ................................................................................ 22-11 22.4.6.3 normal (non-overlay) access to overlay regions ........................................... 22-12 22.4.6.4 calibration write cy cle flow ............................................................................. 22-12 22.5 programming model ................................................................................................... 22-12 22.5.1 calram module configuration register (crammcr) .................................... 22-13 22.5.2 calram region base address registers (cram_rbax) ................................ 22-15 22.5.3 calram overlay configuration register (cram_ovlcr) ............................. 22-17 22.5.4 calram ownership trace re gister (cram_otr) ........................................... 22-17 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxix contents paragraph number title page number chapter 23 development support 23.1 program flow tr acking .............................................. .................................................. 23-1 23.1.1 program trace cy cle ................................................................................................ 23-2 23.1.1.1 instruction queue status pins ? vf [0:2] ........................................................... 23-2 23.1.1.2 history buffer flushes stat us pins? vfls [0:1] ............................................... 23-3 23.1.1.3 queue flush information special case ................................................................ 23-4 23.1.2 program trace when in debug mode ....................................................................... 23-4 23.1.3 sequential instructions marked as indirect branch .................................................. 23-4 23.1.4 external hard ware .................................................................................................... 23- 4 23.1.4.1 synchronizing the trace window to the cpu internal events ............................ 23-5 23.1.4.2 detecting the trace window start address ......................................................... 23-6 23.1.4.3 detecting the assertion/ne gation of vsync ...................................................... 23-6 23.1.4.4 detecting the trace win dow end address .......................................................... 23-6 23.1.4.5 compress .............................................................................................................. 23-7 23.1.5 instruction fetch show cycle control ...................................................................... 23-7 23.2 watchpoints and brea kpoints support ......................................................................... 23-7 23.2.1 internal watchpoints a nd breakpoints ...................................................................... 23-9 23.2.1.1 restrictions ......................................................................................................... 2 3-11 23.2.1.2 byte and half-word wo rking modes ................................................................ 23-11 23.2.1.3 examples ............................................................................................................. 2 3-12 23.2.1.4 context dependent filter .................................................................................... 23-13 23.2.1.5 ignore first ma tch .............................................................................................. 23-14 23.2.1.6 generating six compare types .......................................................................... 23-14 23.2.2 instruction s upport ................................................................................................. 23-1 4 23.2.2.1 load/store support ............................................................................................. 23-16 23.2.3 watchpoint count ers .............................................................................................. 23-19 23.2.3.1 trap enable programming .................................................................................. 23-19 23.3 development system interface ................................................................................... 23-19 23.3.1 debug mode suppor t .............................................................................................. 23-21 23.3.1.1 debug mode enable vs. de bug mode disable .................................................. 23-23 23.3.1.2 entering debug m ode ......................................................................................... 23-24 23.3.1.3 check stop state and debug mode .................................................................... 23-26 23.3.1.4 saving machine state upon entering debug mode ........................................... 23-27 23.3.1.5 running in debug mode .................................................................................... 23-27 23.3.1.6 exiting debug m ode ........................................................................................... 23-28 23.4 development po rt ....................................................................................................... 23- 28 23.4.1 development port pins ........................................... ................................................ 23-28 23.4.2 development serial clock ...................................................................................... 23-29 23.4.3 development serial data in .................................................................................... 23-29 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxx contents paragraph number title page number 23.4.4 development serial data out ................................................................................. 23-29 23.4.5 freeze signal ........................................................................................................... 23-29 23.4.5.1 sgpio6/frz/ptr signal ................................................................................... 23-30 23.4.5.2 iwp[0:1]/vfls[0:1] signals .............................................................................. 23-30 23.4.5.3 vfls[0:1]/mpio32b[3:4] signals ................................................................... 23-30 23.4.6 development port registers ................................................................................... 23-30 23.4.6.1 development port shif t register ........................................................................ 23-30 23.4.6.2 trap enable contro l register ............................................................................. 23-30 23.4.6.3 development port regi sters decode .................................................................. 23-31 23.4.6.4 development port serial communicati ons ? clock mode selection ............... 23-31 23.4.6.5 development port serial communicat ions ? trap enable mode .................... 23-33 23.4.6.6 serial data into development po rt ? trap enable mode ................................. 23-33 23.4.6.7 serial data out of development port ? trap enable mode ............................. 23-34 23.4.6.8 development port serial comm unications ? debug mode ............................. 23-35 23.4.6.9 serial data into deve lopment port ..................................................................... 23-35 23.4.6.10 serial data out of de velopment port ................................................................. 23-36 23.4.6.11 fast download pr ocedure ................................................................................... 23-37 23.5 software monitor de bugger support ......................................................................... 23-38 23.5.1 freeze indication ..................................................................................................... 23 -38 23.6 development support registers ................................................................................. 23-39 23.6.1 register prot ection .................................................................................................. 23- 40 23.6.2 comparator a?d value registers (cmpa?cmpd) .............................................. 23-41 23.6.3 exception cause regi ster (ecr) ............................................................................ 23-41 23.6.4 debug enable regist er (der) ................................................................................ 23-43 23.6.5 breakpoint counter a value an d control register ................................................ 23-45 23.6.6 breakpoint counter b value a nd control register ................................................ 23-46 23.6.7 comparator e?f value registers (cmpe?cmpf) ................................................ 23-46 23.6.8 comparator g?h value registers (cmpg?cmph) .............................................. 23-47 23.6.9 l-bus support control register 1 .......................................................................... 23-47 23.6.10 l-bus support control register 2 .......................................................................... 23-48 23.6.11 i-bus support control regi ster (ictrl) ............................................................... 23-51 23.6.12 breakpoint address regi ster (bar) ...................................................................... 23-53 23.6.13 development port data re gister (dpdr) .............................................................. 23-53 chapter 24 readi module 24.1 features summary ........................................................................................................ 24 -1 24.1.1 functional block diagram ........................................................................................ 24-2 24.2 modes of oper ation ...................................................................................................... 24 -3 24.2.1 reset configur ation .................................................................................................. 24- 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxi contents paragraph number title page number 24.2.2 security ................................................................................................................ ..... 24-4 24.2.3 normal .................................................................................................................. .... 24-4 24.2.4 disabled ................................................................................................................ .... 24-4 24.3 parametric s ............................................................................................................... ..... 24-4 24.4 messages .................................................................................................................. ..... 24-4 24.5 terms and defini tions .................................................................................................. 24- 6 24.6 programming model ..................................................................................................... 24-8 24.6.1 register map ............................................................................................................ . 24-8 24.6.1.1 user-mapped regist er (otr) .............................................................................. 24-8 24.6.1.2 tool-mapped regi sters ........................................................................................ 24-9 24.6.1.3 device id register (did) ..................................................................................... 24-9 24.6.1.4 development control re gister (dc) .................................................................. 24-10 24.6.1.5 mode control regist er (mc) .............................................................................. 24-11 24.6.1.6 user base address re gister (uba) ................................................................... 24-12 24.6.1.7 read/write access regi ster (rwa) .................................................................. 24-13 24.6.1.8 upload/download informati on register (udi) .................................................. 24-15 24.6.1.9 data trace attributes 1 and 2 registers (dta1 a nd dta2) ............................. 24-17 24.6.2 accessing memory-mapped locations via the auxiliary po rt ............................................................................................... 24-18 24.6.3 accessing readi tool mapped regist ers via the auxiliary port ........................ 24-19 24.6.4 partial register updates ... ....................................................................................... 24-19 24.6.5 programming consid erations ................................................................................. 24-20 24.6.5.1 program trace guid elines .................................................................................. 24-20 24.6.5.2 compressed code mode guidelines .................................................................. 24-20 24.7 signal interface .......................................................................................................... . 24-20 24.7.1 functional descri ption ............................................................................................ 24-21 24.7.1.1 signals implemen ted .......................................... ................................................ 24-21 24.7.2 functional block diagram ...................................................................................... 24-22 24.7.3 message priori ty ..................................................................................................... 24- 22 24.7.4 signal protoc ol ........................................................................................................ 2 4-23 24.7.5 messages ................................................................................................................ . 24-24 24.7.5.1 message format s ................................................................................................ 24-28 24.7.5.2 rules of messa ges .............................................................................................. 24-31 24.7.5.3 branch trace messag e examples ....................................................................... 24-32 24.7.5.3.1 example of indirect branch message ............................................................. 24-32 24.7.5.3.2 example of direct br anch message ............................................................... 24-33 24.7.5.4 non-temporal ordering of transmitted messages ............................................ 24-33 24.7.6 readi reset confi guration ................................................................................... 24-34 24.7.7 readi signals ....................................................................................................... 24-3 6 24.7.7.1 reset configuration fo r debug mode ................................................................ 24-36 24.7.7.2 reset configuration for non-debug mode ........................................................ 24-37 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxii contents paragraph number title page number 24.7.7.3 secure mode ....................................................................................................... 24-3 7 24.7.7.4 disabled mode .................................................................................................... 24-37 24.7.7.5 guidelines for transmitti ng input message s ...................................................... 24-37 24.8 program trace ............................................................................................................ 24-38 24.8.1 branch trace mess aging ........................................................................................ 24-38 24.8.1.1 rcpu instructions that ca use btm messag es .................................................. 24-38 24.8.2 btm message form ats ........................................................................................... 24-38 24.8.2.1 direct branch messages ..................................................................................... 24-38 24.8.2.2 indirect branch messages ................................................................................... 24-39 24.8.2.3 correction messa ges ........................................................................................... 24-40 24.8.2.4 synchronization me ssages .................................................................................. 24-42 24.8.2.4.1 direct branch synchr onization message ....................................................... 24-44 24.8.2.4.2 indirect branch synchr onization message ..................................................... 24-44 24.8.2.4.3 direct branch sync hronization message with compressed code ................ 24-44 24.8.2.4.4 indirect branch synchronization me ssage with compressed code ............... 24-45 24.8.2.4.5 resource full message ................................................................................... 24-45 24.8.2.5 error message s ................................................................................................... 24-46 24.8.2.6 relative addres sing ............................................................................................ 24-46 24.8.3 queue overflow program tr ace error message .................................................... 24-47 24.8.4 branch trace messag e operation ........................................................................... 24-47 24.8.4.1 btm capture and encodi ng algorithm ............................................................. 24-47 24.8.4.2 instruction fetch snooping ................................................................................. 24-48 24.8.4.3 instruction executi on tracking .......................................................................... 24-48 24.8.4.4 instruction flus h cases ....................................................................................... 24-48 24.8.5 branch trace messag e queueing ........................................................................... 24-48 24.8.6 btm timing diagrams .......................................................................................... 24-49 24.8.7 program trace guid elines ...................................................................................... 24-51 24.9 data trace ............................................................................................................... ... 24-52 24.9.1 data trace for the load/s tore bus (l-bus) ............................................................ 24-52 24.9.2 data trace message formats .................................................................................. 24-52 24.9.2.1 data write mess age ............................................................................................ 24-52 24.9.2.2 data read messa ge ............................................. ................................................ 24-53 24.9.2.3 data trace synchroniza tion messages ............................................................... 24-53 24.9.2.4 data write synchronizat ion message ................................................................ 24-54 24.9.2.5 data read synchroniza tion messaging .............................................................. 24-54 24.9.2.6 relative addres sing ............................................................................................ 24-54 24.9.3 queue overflow data tra ce error message ........................................................... 24-54 24.9.4 data trace oper ation .............................................................................................. 24-54 24.9.5 data trace window ing ........................................................................................... 24-56 24.9.6 special l-bus ca ses ............................................................................................... 24-56 24.9.7 data trace queu ing ................................................................................................ 24-56 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxiii contents paragraph number title page number 24.9.8 throughput and late ncy ......................................... ................................................ 24-57 24.9.8.1 assumptions for throug hput analysis ............................................................... 24-57 24.9.8.2 throughput calcula tions .................................................................................... 24-57 24.9.9 data timing diag rams ............................................................................................ 24-57 24.10 read/write ac cess ...................................................................................................... 24 -59 24.10.1 functional descri ption ............................................................................................ 24-59 24.10.2 write operation to memory-mapped locations and spr registers ..................... 24-61 24.10.2.1 single write op eration ....................................................................................... 24-61 24.10.2.2 block write oper ation ........................................................................................ 24-62 24.10.3 read operation to memory-mapped locations and spr registers ...................... 24-63 24.10.3.1 single read op eration . ....................................................................................... 24-63 24.10.3.2 block read oper ation ......................................................................................... 24-64 24.10.4 read/write access to intern al readi registers ................................................... 24-64 24.10.4.1 write operat ion .................................................................................................. 24-6 4 24.10.4.2 read operat ion ................................................................................................... 24-6 5 24.10.5 error handling ........................................................................................................ 2 4-65 24.10.5.1 access alignm ent ............................................................................................... 24-65 24.10.5.2 l-bus address error ........................................................................................... 24-65 24.10.5.3 l-bus data er ror ................................................................................................ 24-65 24.10.6 exception sequenc es .............................................................................................. 24-66 24.10.7 secure mode ........................................................................................................... 2 4-66 24.10.8 error messages ....................................................................................................... 24 -66 24.10.8.1 read/write acces s error .................................................................................... 24-66 24.10.8.2 invalid mess age .................................................................................................. 24-6 7 24.10.8.3 invalid access opcode ....................................................................................... 24-67 24.10.9 faster read/write accesses with default attributes ............................................. 24-67 24.10.10 throughput and late ncy ......................................... ................................................ 24-68 24.10.10.1 assumptions for throug hput analysis ............................................................... 24-68 24.11 read/write timing diagrams ..................................................................................... 24-69 24.12 watchpoint s upport ................................................................................................... 24- 72 24.12.1 watchpoint messa ging ........................................................................................... 24-72 24.12.1.1 watchpoint sour ce field .................................................................................... 24-73 24.12.2 watchpoint overrun er ror message ....................................................................... 24-73 24.12.3 synchronizati on ...................................................................................................... 24 -74 24.12.4 watchpoint timing di agrams ................................................................................ 24-74 24.13 ownership trace ........................................................................................................ 2 4-74 24.13.1 ownership trace messaging .................................................................................. 24-75 24.13.2 queue overflow ownership trace error message ................................................. 24-75 24.13.2.1 otm flow .......................................................................................................... 24- 75 24.13.2.2 otm queuei ng ................................................................................................... 24-76 24.13.3 otm timing diagrams .......................................................................................... 24-76 mpc561/mpc563 reference manual, rev. 1.2 xxxiv freescale semiconductor contents paragraph number title page number 24.14 rcpu development access ...................................................................................... 24-76 24.14.1 rcpu development access messaging ................................................................. 24-77 24.14.1.1 dsdi messag e .................................................................................................... 24-77 24.14.1.2 dsdo message .................................................................................................. 24-78 24.14.1.3 bdm status me ssage ......................................... ................................................ 24-78 24.14.1.4 error message (inva lid message) ....................................................................... 24-79 24.14.2 rcpu development access operation .................................................................. 24-79 24.14.2.1 enabling rcpu development a ccess via readi signals ............................... 24-80 24.14.2.2 entering background debug mode (bdm) via readi signals ...................... 24-80 24.14.2.3 non-debug mode access of rc pu development access ................................ 24-80 24.14.2.4 rcpu development access flow diagram ....................................................... 24-81 24.14.3 throughput ............................................................................................................. . 24-82 24.14.4 development access timi ng diagrams ................................................................. 24-82 24.15 power manageme nt ................................................................................................... 24-86 24.15.1 functional descri ption ............................................................................................ 24-86 24.15.2 low power mode s .................................................................................................. 24-86 chapter 25 ieee 1149.1-compliant interface (jtag) 25.1 ieee 1149.1 test acce ss port ...................................................................................... 25-1 25.1.1 overview ................................................................................................................ ... 25-2 25.1.2 entering jtag mo de ................................................................................................ 25-3 25.1.2.1 tap controll er ..................................................................................................... 25- 4 25.1.2.2 boundary scan register ....................................................................................... 25-4 25.1.3 instruction register ................................................................................................. 25- 30 25.1.3.1 extest ............................................................................................................. 25- 31 25.1.3.2 sample/preload ......................................................................................... 25-31 25.1.3.3 bypass ............................................................................................................. 25- 31 25.1.3.4 clamp ............................................................................................................... 25 -32 25.1.4 hi-z .................................................................................................................... .... 25-32 25.2 mpc561/mpc563 restri ctions .................................................................................. 25-32 25.2.1 non-scan chain op eration ..................................................................................... 25-32 25.2.2 bsdl descrip tion ................................................................................................... 25-33 appendix a mpc562/mpc564 compression features a.1 icdu key feat ures ..................................................... ................................................... a-1 a.2 class-based compression mode l main principles......................................................... a-1 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxv contents paragraph number title page number a.2.1 compression model features ..................................................................................... a-1 a.2.2 model limitat ions....................................................................................................... a- 2 a.2.3 instruction class-based compression algor ithm....................................................... a-2 a.2.4 compressed address generati on with direct branches............................................. a-4 a.2.5 compressed address genera tion?indirect branches ............................................... a-6 a.2.6 compressed address ge neration?exceptions .......................................................... a-6 a.2.7 class code compression algorithm rule s ................................................................ a-7 a.2.8 bypass field comp ression rules ............................................................................... a-7 a.2.8.1 branch right segmen t compression #1................................................................. a-7 a.2.8.2 branch right segmen t compression #2................................................................. a-8 a.2.8.3 right segment zero lengt h compression bypass................................................. a-8 a.2.9 instruction class structur es and program ming .......................................................... a-8 a.2.9.1 global bypa ss......................................................................................................... a- 8 a.2.9.2 single segment full comp ression ? class_1 ..................................................... a-9 a.2.9.3 twin segment full compression ? class_2 ....................................................... a-9 a.2.9.4 left segment compression and ri ght segment bypass ? class_3................. a-10 a.2.9.5 left segment bypass and right segment compression?class_4..................a-11 a.2.10 instruction layout progr amming summary ..............................................................a-11 a.2.11 compression pr ocess .................................................................................................a-11 a.2.12 decompressi on.......................................................................................................... a- 12 a.2.13 compression environmen t initializatio n .................................................................. a-13 a.2.14 compression/non-compre ssion mode swit ch ........................................................ a-14 a.2.14.1 compression definition fo r exception ha ndlers ................................................. a-14 a.2.14.2 running mixed code............................................................................................ a-14 a.3 operation modes........................................................................................................... a- 14 a.3.1 instruction fetch ....................................................................................................... a- 14 a.3.1.1 decompression off mode..................................................................................... a-15 a.3.1.2 decompression on mode ..................................................................................... a-15 a.3.1.2.1 show cycles in deco mpression on mode ....................................................... a-15 a.3.2 vocabulary table stor age operation ........................................................................ a-16 a.3.3 readi compress ion ................................................................................................ a-16 a.3.3.1 i-bus support control re gister (ictrl) ............................................................. a-16 a.4 decompressor class configurati on registers (dccr0-15) ........................................ a-18 mpc561/mpc563 reference manual, rev. 1.2 xxxvi freescale semiconductor contents paragraph number title page number appendix b internal memory map appendix c clock and boar d guidelines c.1 mpc56x device power distribution ...............................................................................c-2 c.2 crystal oscillator exte rnal components .........................................................................c-4 c.2.1 kapwr filteri ng ........................................................................................................c-5 c.2.2 pll external co mponents...........................................................................................c-5 c.2.3 pll off-chip cap acitor cxfc...................................................................................c-6 c.3 pll and clock oscillator external components layout requirements .........................c-7 c.3.1 traces and plac ement ..................................................................................................c-7 c.3.2 grounding/guardi ng....................................................................................................c-7 c.3.3 iramstby regulator circuit....................................................................................c-7 appendix d tpu3 rom functions d.1 overview.................................................................................................................... ..... d-1 d.2 programmable time accu mulator (pta) ....................................................................... d-3 d.3 queued output match tpu3 function (qom) .............................................................. d-5 d.4 table stepper moto r (tsm).. .......................................................................................... d-7 d.5 frequency measurem ent (fqm) .................................................................................. d-10 d.6 universal asynchronous receiv er/transmitter (uart).............................................. d-12 d.7 new input capture/transi tion counter (n itc)............................................................ d-15 d.8 multiphase motor comm utation (comm) .................................................................. d-17 d.9 hall effect decode (halld) ...................................................................................... d-20 d.10 multichannel pulse-width modulation (mcp wm) ..................................................... d-22 d.11 multi tpu (mul ti) ..................................................................................................... d-30 d.12 fast quadrature decode tpu3 function (fqd) .......................................................... d-35 d.13 period/pulse-width accu mulator (ppwa)................................................................... d-38 d.14 id tpu3 functi on (id)................................................ ................................................. d-40 d.15 output compar e (oc) .................................................................................................. d-42 d.16 pulse-width modulat ion (pwm).................................................................................. d-44 d.17 discrete input/out put (dio)......................................................................................... d-46 d.18 synchronized pulse-width modulation (spw m)......................................................... d-48 d.19 read/write timers and pin tpu3 function (rwtpin) .............................................. d-51 d.20 serial input/output port (siop) ................................................................................... d-53 d.20.1 parameters............................................................................................................... .. d-53 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxvii contents paragraph number title page number d.20.1.1 chan_contro l .............................................................................................. d-56 d.20.1.2 bit_d .................................................................................................................. .d-56 d.20.1.3 half_perio d ................................................................................................... d-56 d.20.1.4 bit_count ........................................................................................................ d-56 d.20.1.5 xfer_size .......................................................................................................... d-56 d.20.1.6 siop_data ......................................................................................................... d-57 d.20.2 host rcpu initialization of the siop function....................................................... d-57 d.20.3 siop function pe rformance ..................................................................................... d-57 d.20.3.1 xfer_size greate r than 16 .............................................................................. d-58 d.20.3.2 data positi oning.................................................................................................... d-5 8 d.20.3.3 data timi ng .......................................................................................................... d- 58 appendix e memory access timing appendix f electrical characteristics f.1 package ..................................................................................................................... ....... f-2 f.2 emi characte ristics ......................................................................................................... f-2 f.2.1 reference docu ments .............................................. .................................................... f-2 f.2.2 definitions and acronyms ........................................................................................... f-3 f.2.3 emi testing speci fications.......................................................................................... f-3 f.3 thermal characte ristics ........ ........................................................................................... f- 3 f.3.1 thermal refere nces ..................................................................................................... f-5 f.4 esd protec tion .............................................................................................................. .. f-6 f.5 dc electrical char acteristics........................................................................................... f-7 f.6 oscillator and pll electri cal characterist ics................................................................ f-11 f.7 flash electrical ch aracteristics...................................................................................... f-12 f.8 power-up/down sequencing......................................................................................... f-13 f.8.1 power-up/down option a ........................................................................................ f-13 f.8.2 power-up/down option b ........................................................................................ f-15 f.9 issues regarding po wer sequence ................................................................................ f-17 f.9.1 application of pore set or hreset ..................................................................... f-17 f.9.2 keep-alive ram....................................................................................................... f-18 f.10 ac timing .................................................................................................................. ... f-18 f.10.1 debug port timing .................................................................................................... f-43 f.11 readi electrical ch aracteristics .................................................................................. f-45 f.12 reset ti ming............................................................................................................... f-47 f.13 ieee 1149.1 electrical ch aracteristics.......................................................................... f-50 mpc561/mpc563 reference manual, rev. 1.2 xxxviii freescale semiconductor contents paragraph number title page number f.14 qadc64e electrical ch aracteristics............................................................................. f-54 f.15 qsmcm electrical ch aracteristics ............................................................................... f-56 f.16 gpio electrical ch aracteristic s ..................................................................................... f-60 f.17 tpu3 electrical char acteristics..................................................................................... f-61 f.18 toucan electrical characteristics................................................................................ f-62 f.19 ppm timing charact eristics .......................................................................................... f-62 f.20 mios timing charac teristics ........................................................................................ f-64 f.20.1 mpwmsm timing char acteristics ........................................................................... f-64 f.20.2 mmcsm timing charac teristics .............................................................................. f-67 f.20.3 mdasm timing char acteristics............................................................................... f-69 f.21 mpiosm timing char acteristics .................................................................................. f-71 f.22 pin summary ............................................................................................................... .. f-73 f.22.1 package diag rams...................................................................................................... f-8 3 f.22.1.1 mpc561/mpc563 ba ll map ................................................................................. f-86 appendix g 66-mhz electrical characteristics g.1 66-mhz feature li mitations .......................................................................................... g-1 g.2 package ..................................................................................................................... ...... g-3 g.3 emi characteri stics .............. .......................................................................................... g -3 g.3.1 reference docu ments .............................................. ................................................... g-3 g.3.2 definitions and acronyms .......................................................................................... g-3 g.3.3 emi testing speci fications......................................................................................... g-3 g.4 thermal characte ristics ........ .......................................................................................... g-3 g.4.1 thermal refere nces .................................................................................................... g-6 g.5 esd protec tion .............................................................................................................. .g-6 g.6 dc electrical char acteristics.......................................................................................... g-7 g.7 oscillator and pll electri cal characterist ics............................................................... g-10 g.8 flash electrical ch aracteristics......................................................................................g-11 g.9 power-up/down sequencing........................................................................................ g-12 g.9.1 power-up/down option a ....................................................................................... g-13 g.9.2 power-up/down option b ....................................................................................... g-15 g.10 issues regarding po wer sequence ............................................................................... g-17 g.10.1 application of pore set or hreset .................................................................... g-17 g.10.2 keep-alive ram...................................................................................................... g-18 g.11 ac timing .................................................................................................................. .. g-18 g.11.1 debug port timing ................................................................................................... g-41 g.12 readi electrical ch aracteristics ................................................................................. g-43 g.13 reset timin g.............................................................................................................. g -44 g.14 ieee 1149.1 electrical ch aracteristic s......................................................................... g-47 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xxxix contents paragraph number title page number g.15 qadc64e electrical ch aracteristic s............................................................................ g-50 g.16 qsmcm electrical ch aracteristics .............................................................................. g-52 g.17 gpio electrical ch aracteristic s .................................................................................... g-56 g.18 tpu3 electrical char acteristics.................................................................................... g-57 g.19 toucan electrical characteristics............................................................................... g-58 g.20 ppm timing charact eristics . ........................................................................................ g-58 g.21 mios timing charac teristics ....................................................................................... g-59 g.21.1 mpwmsm timing char acteristics .......................................................................... g-60 g.21.2 mmcsm timing charac teristics ............................................................................. g-62 g.21.3 mdasm timing char acteristics.............................................................................. g-64 g.22 mpiosm timing char acteristics ................................................................................. g-67 g.23 pin summary ............................................................................................................... .g-68 g.23.1 package diag rams..................................................................................................... g-78 g.23.1.1 mpc561/mpc563 ba ll map ................................................................................ g-81 mpc561/mpc563 reference manual, rev. 1.2 xl freescale semiconductor contents paragraph number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xli figure number title page number 1-1 mpc561/mpc563 bloc k diagram ........................................................................................... 1-3 1-2 recommended connection diag ram for iramstby........................................................... 1-11 1-3 mpc561/mpc563 memo ry map .. ......................................................................................... 1-12 1-4 mpc561/mpc563 internal memory map .............................................................................. 1-14 2-1 mpc561/mpc563 signa l groupings ....................................................................................... 2-2 2-2 pads module configuration register (pdmcr) .................................................................... 2-22 2-3 pads module configuration re gister 2 (pdmcr2) ............................................................... 2-23 2-4 debug mode selecti on (jtag) ..... ......................................................................................... 2-3 0 2-5 debug mode selecti on (bdm)............................................................................................... 2-3 0 2-6 debug mode selecti on (nexus) .............................................................................................. 2- 31 3-1 rcpu block di agram .......................................................................................................... .... 3-2 3-2 sequencer da ta path ......................................................................................................... ........ 3-4 3-3 rcpu programmi ng model ..................................................................................................... 3-8 3-4 general-purpose regi sters (gprs)......................................................................................... 3-1 2 3-5 floating-point regi sters (fprs) ............................................................................................. 3-13 3-6 floating-point status and c ontrol register (fpscr)............................................................. 3-14 3-7 condition register (cr) ..................................................................................................... .... 3-16 3-8 integer exception re gister (xer) .......................................................................................... 3- 18 3-9 link register (lr).......................................................................................................... ........ 3-19 3-10 count register (ctr) ....................................................................................................... ...... 3-19 3-11 machine state regi ster (msr) ............................................................................................... 3-20 3-12 dae/source instruc tion service register (dsisr) ............................................................... 3-22 3-13 data address regi ster (dar ) ................................................................................................ 3-23 3-14 machine status save/restore register 0 (srr0) ................................................................... 3-23 3-15 machine status save/restore register 1 (srr1) ................................................................... 3-24 3-16 sprg0?sprg3 ? general speci al-purpose regist ers 0?3 .................................................. 3-24 3-17 processor version re gister (pvr) ......................................................................................... 3- 25 3-18 floating-point exception caus e register (fpecr) ............................................................... 3-26 3-19 basic instructi on pipeline ................................................................................................. ...... 3-38 4-1 bbc module block diagram ................................................................................................... 4 -2 4-2 exception table entr ies mapping ............................................................................................ 4 -8 4-3 external interrupt vectors splitting........................................................................................ 4-12 4-4 decram interfaces bl ock diagram ..................................................................................... 4-13 4-5 btb block diagram ........................................................................................................... .... 4-16 4-6 mpc561/mpc563 memo ry map .. ......................................................................................... 4-17 4-7 bbc module configuration register (bbc mcr)................................................................. 4-19 4-8 region base address regist er (mi_rba[0: 3]) ..................................................................... 4-21 4-9 region attribute register (mi_ra0[0:3]) ............................................................................. 4-22 4-10 global region attribute register (mi_ gra) ........................................................................ 4-23 figures mpc561/mpc563 reference manual, rev. 1.2 xlii freescale semiconductor figures figure number title page number 4-11 external interrupt relocation table base address regist er (eibadr)................................ 4-25 5-1 usiu block diagram.......................................................................................................... ...... 5-2 6-1 system configuration and protection logi c............................................................................. 6-3 6-2 circuit paths of reading a nd writing to sgpio ...................................................................... 6-7 6-3 mpc561/mpc563 interrupt structure...................................................................................... 6-9 6-4 lower priority request mask ing?one bit diag ram ............................................................ 6-14 6-5 mpc561/mpc563 interrupt contro ller block diagram ........................................................ 6-15 6-6 typical interrupt ha ndler routine.......................................................................................... 6 -17 6-7 rtc block diagram ........................................................................................................... .... 6-20 6-8 pit block diagram ........................................................................................................... ...... 6-21 6-9 swt state di agram ........................................................................................................... ..... 6-22 6-10 swt block di agram .......................................................................................................... .... 6-23 6-11 mpc561/mpc563 memo ry map .. ......................................................................................... 6-24 6-12 siu module configuration register (siu mcr).................................................................... 6-25 6-13 internal memory mapping register (imm r)......................................................................... 6-28 6-14 external master contro l register (emcr) ............................................................................ 6-30 6-15 siu interrupt pending re gister (sipend) ............................................................................. 6-32 6-16 siu interrupt pending regi ster 2 (sipend2) ........................................................................ 6-32 6-17 siu interrupt pending regi ster 3 (sipend3) ........................................................................ 6-33 6-18 siu interrupt mask re gister (simask) ................................................................................ 6-34 6-19 siu interrupt mask regi ster 2 (simask2) ........................................................................... 6-34 6-20 siu interrupt mask regi ster 3 (simask3) ........................................................................... 6-35 6-21 siu interrupt edge leve l register (siel) ............................................................................. 6-35 6-22 siu interrupt vector re gister (sivec ).................................................................................. 6-36 6-23 example of sivec register usage for interrupt table handling ......................................... 6-36 6-24 interrupt in-service regi ster 2 (sisr2) ................................................................................. 6-3 7 6-25 interrupt in-service regi ster 3 (sisr3) ................................................................................. 6-3 7 6-26 system protection contro l register (sypcr) ....................................................................... 6-38 6-27 software service re gister (swsr) ........................................................................................ 6-3 9 6-28 transfer error status register (tes r) ................................................................................... 6-3 9 6-29 decrementer regi ster (dec)................................................................................................. .6-40 6-30 time base (read ing) (tb) ................................................................................................... .. 6-41 6-31 time base (wri ting) (tb) ................................................................................................... ... 6-41 6-32 time base reference re gister 0 (tbr ef0)........................................................................... 6-41 6-33 time base reference re gister 1 (tbr ef1)........................................................................... 6-41 6-34 time base control and stat us register (tbscr).................................................................. 6-42 6-35 real-time clock status and c ontrol register (r tcsc) ....................................................... 6-43 6-36 real-time clock regi ster (rtc) . .......................................................................................... 6- 43 6-37 real-time clock alarm re gister (rtcal) .......................................................................... 6-44 6-38 periodic interrupt status and c ontrol register (piscr) ........................................................ 6-44 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xliii figures figure number title page number 6-39 periodic interrupt time r count (pitc) .................................................................................. 6-45 6-40 periodic interrupt timer register (pitr)............................................................................... 6-45 6-41 sgpio data register 1 (sgpiodt1) .................................................................................... 6-46 6-42 sgpio data register 2 (sgpiodt2) .................................................................................... 6-47 6-43 sgpio control regist er (sgpiocr)..................................................................................... 6-48 7-1 reset status regi ster (rsr) ................................................................................................. .... 7-5 7-2 reset configurati on basic scheme........................................................................................... 7 -8 7-3 reset configuration sampling scheme for ?short? poreset assertion, li mp mode disa bled ............................................................... 7-9 7-4 reset configuration timing for ?short? po reset assertion, limp mode enabled............. 7-9 7-5 reset configuration timing for ?long? po reset assertion, limp mode disabled.......... 7-10 7-6 reset configuration sampli ng timing requirements............................................................ 7-10 7-7 reset configuration word (rcw) ......................................................................................... 7-11 8-1 clock unit bloc k diagram .................................................................................................... ... 8-2 8-2 main system oscillator cr ystal configurat ion ........................................................................ 8-3 8-3 system pll bloc k diagram .................................................................................................... .8-5 8-4 mpc561/mpc563 clocks ........................................................................................................ 8-8 8-5 general system cl ocks sele ct ................................................................................................ 8-11 8-6 divided system clocks timing diagram ............................................................................... 8-12 8-7 clocks timing for dfnh = 1 (or dfnl = 0) ....................................................................... 8-13 8-8 clock source switchi ng flow chart ...................................................................................... 8-15 8-9 low-power modes fl ow diagram ......................................................................................... 8-20 8-10 iramstby regulator circuit ............................................................................................... 8- 23 8-11 basic power supply configuration......................................................................................... 8- 24 8-12 external power s upply scheme.............................................................................................. 8 -25 8-13 keep-alive register ke y state diagram................................................................................ 8-27 8-14 no standby, no kapwr, all sy stem power-on/off ........................................................... 8-28 8-15 standby and kapwr, othe r power-on/off .......................................................................... 8-29 8-16 system clock and reset cont rol register (sccr) ................................................................ 8-30 8-17 pll, low-power, and reset-co ntrol register (plprcr) .................................................... 8-34 8-18 change of lock interrupt register (col ir).......................................................................... 8-36 8-19 iramstby control regi ster (vsrmcr) ............................................................................ 8-37 9-1 input sample window ......................................................................................................... ..... 9-2 9-2 mpc561/mpc563 bus signals ................................................................................................ 9-3 9-3 basic transfer protocol ..................................................................................................... ....... 9-8 9-4 basic flow diagram of a si ngle beat read cycle ................................................................... 9-9 9-5 single beat read cycle ? basi c timing ? zero wait states.................................................. 9-10 9-6 single beat read cycle ? basi c timing ? one wait state .................................................... 9-11 9-7 basic flow diagram of a si ngle beat write cycle ................................................................ 9-12 9-8 single beat basic write cycle ti ming ? zero wait states .................................................... 9-13 mpc561/mpc563 reference manual, rev. 1.2 xliv freescale semiconductor figures figure number title page number 9-9 single beat basic write cycle timing ? one wait state ...................................................... 9-14 9-10 single beat 32-bit data write cy cle timing ? 16-bit port size ......................................... 9-15 9-11 read followed by write when pre-discharg e mode is enabled, and ehtr is set .............. 9-17 9-12 basic flow diagram of a burst-read cycle......................................................................... 9-21 9-13 burst-read cycle ? 32-bit port size ? zero wait state......................................................... 9-21 9-14 burst-read cycle ? 32-bit port size ? one wait state.......................................................... 9-22 9-15 burst-read cycle ? 32-bit port size ? wait states betw een beats ....................................... 9-23 9-16 burst-read cycle ? 16-bit port size ...................................................................................... 9- 24 9-17 basic flow diagram of a burst-write cycle.......................................................................... 9-26 9-18 burst-write cycle, 32-bit port size, zero wait states (only for external master memory controller service support)........................................... 9-26 9-19 burst-inhibit read cy cle, 32-bit port size (emulated burst)................................................ 9-27 9-20 non-wrap burst with three beats ......................................................................................... 9-2 8 9-21 non-wrap burst with one data beat ..................................................................................... 9-29 9-22 internal operand representation ............................................................................................ 9-30 9-23 interface to different po rt size devices................................................................................ 9-3 1 9-24 bus arbitration flowchart .................................................................................................. .... 9-33 9-25 master signals basi c connection . .......................................................................................... 9 -34 9-26 bus arbitration ti ming diagram............................................................................................ 9 -35 9-27 internal bus arbitrati on state machine .................................................................................. 9-3 6 9-28 termination signals protoc ol basic connect ion .................................................................... 9-41 9-29 termination signals protoc ol timing diagram...................................................................... 9-41 9-30 reservation on local bus ................................................................................................... .... 9-43 9-31 reservation on multi-leve l bus hierarchy ............................................................................. 9-44 9-32 retry transfer timing ? internal arbi ter ............................................................................... 9-46 9-33 retry transfer timing ? external arbiter .............................................................................. 9-47 9-34 retry on burs t cycle....................................................................................................... ........ 9-48 9-35 basic flow of an external master read access ..................................................................... 9-50 9-36 basic flow of an external master write access .................................................................... 9-51 9-37 peripheral mode: external master reads from mpc561/mp c563 (two wait states) ......... 9-52 9-38 peripheral mode: external ma ster writes to mpc561/mpc563 (two wait states)............ 9-53 9-39 flow of retry of external master read access ..................................................................... 9-54 9-40 retry of external master a ccess (internal arbiter)................................................................ 9-55 9-41 instruction show cy cle transaction....................................................................................... 9- 57 9-42 data show cycle transaction................................................................................................ .9-58 10-1 memory controller function within the usiu....................................................................... 10-1 10-2 memory controller bl ock diagram........................................................................................ 10-2 10-3 mpc561/mpc563 simple syst em configuration .................................................................. 10-3 10-4 bank base address and match structur e ............................................................................... 10-4 10-5 a 4-2-2-2 burst read cycle (one wait state between bursts) ............................................. 10-9 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xlv figures figure number title page number 10-6 4 beat burst read with short se tup time (zero wait state) ............................................... 10-10 10-7 gpcm?memory devices interface ...................................................................................... 10-12 10-8 memory devices interface basic timing (acs = 00, trlx = 0)....................................... 10-13 10-9 peripheral device s interface ............................................................................................... .. 10-13 10-10 peripheral devices basic timi ng (acs = 11, trlx = 0) ................................................... 10-14 10-11 relaxed timing ? read access (acs = 11, scy = 1, trlx = 1).................................... 10-15 10-12 relaxed timing ? write access (acs = 10, scy = 0, csnt = 0, trlx = 1) ................ 10-16 10-13 relaxed timing ? write access (acs = 11, scy = 0, csnt = 1, trlx = 1) ................ 10-17 10-14 relaxed timing ? write access (acs = 00, scy = 0, csnt = 1, trlx = 1.................. 10-18 10-15 consecutive accesses (write after read, ehtr = 0) ......................................................... 10-19 10-16 consecutive accesses (write after read, ehtr = 1) ......................................................... 10-20 10-17 consecutive accesses (read after read from differen t banks, ehtr = 1) .......................................................... 10-21 10-18 consecutive accesses (read after r ead from same bank, ehtr = 1).............................. 10-22 10-19 aliasing phenomenon illustratio n ........................................................................................ 10 -26 10-20 synchronous external master configuration for gp cm-handled memory devices .......................................................... 10-29 10-21 synchronous external master basi c access (gpcm controlled)........................................ 10-30 10-22 memory controller status register (mstat) ..................................................................... 10-32 10-23 memory controller base re gisters 0?3 (br 0?br3) ........................................................... 10-32 10-24 memory controller option re gisters 1?3 (or0?or3) ....................................................... 10-34 10-25 dual-mapping base re gister (dmbr) ................................................................................ 10-36 10-26 dual-mapping option re gister (dmor)............................................................................. 10-37 11-1 l2u bus interface block diagram ......................................................................................... 11- 3 11-2 dmpu basic functiona l diagram .......................................................................................... 11-5 11-3 region base addre ss example............................................................................................... 1 1-7 11-4 l2u module configuration register (l2u_mcr) .............................................................. 11-14 11-5 l2u region x base address register (l2u_r bax) ........................................................... 11-14 11-6 l2u region x attribute re gister (l2u_rax) .................................................................... 11-15 11-7 l2u global region attribute register (l2u_gra) ........................................................... 11-16 12-1 uimb interface module block diagram................................................................................ 12-2 12-2 imb3 clock ? full-spe ed imb3 bus ..................................................................................... 12-3 12-3 imb3 clock ? half-spe ed imb3 bus .................................................................................... 12-3 12-4 interrupt synchroni zer signal flow........................................................................................ 1 2-4 12-5 time-multiplexing protoc ol for irq signals ......................................................................... 12-5 12-6 interrupt synchronizer block diagram................................................................................... 12-6 12-7 uimb module conf iguration register (umcr) ................................................................... 12-7 12-8 pending interrupt request register (uipend)...................................................................... 12-9 13-1 qadc64e block diagram ..................................................................................................... 1 3-1 13-2 qadc64e conversion qu eue operation............................................................................... 13-5 mpc561/mpc563 reference manual, rev. 1.2 xlvi freescale semiconductor figures figure number title page number 13-3 example of external multiplexi ng ......................................................................................... 13 -6 13-4 module configuration regi ster (qadcmcr) ...................................................................... 13-8 13-5 qadc interrupt regist er (qadcint) ................................................................................ 13-12 13-6 interrupt levels on irq with ilbs ...................................................................................... 13-1 3 13-7 port x data register (portq a and portqb).................................................................. 13-13 13-8 port a data direction register (ddrqa) .......................................................................... 13-14 13-9 control register 0 (qacr0) ................................................................................................ 1 3-15 13-10 control register 1 (qacr1) ............................................................................................... 13-16 13-11 control register 2 (qacr2) ................................................................................................ 13-18 13-12 status register 0 (qasr0) ................................................................................................. .. 13-21 13-13 qadc64e queue status transition ..................................................................................... 13-26 13-14 status register 1 (qasr1) ................................................................................................. .. 13-27 13-15 qadc64e conversion qu eue operation............................................................................. 13-28 13-16 conversion command word table (ccw) ......................................................................... 13-30 13-17 right justified, unsigned resu lt format (rjurr).............................................................. 13-33 13-18 left justified, signed resu lt format (ljsrr) ..................................................................... 13-33 13-19 left justified, unsigned resu lt register (l jurr) .............................................................. 13-33 13-20 qadc64e analog subsyste m block diagra m .................................................................... 13-34 13-21 conversion timing ......................................................................................................... ...... 13-35 13-22 bypass mode convers ion timing . ....................................................................................... 13-36 13-23 qadc64e queue operati on with pause.............................................................................. 13-39 13-24 qadc64e clock subsys tem functions ............................................................................... 13-48 13-25 qadc64e clock programma bility examples ..................................................................... 13-50 13-26 bus cycle accesses ........................................................................................................ ...... 13-53 13-27 ccw priority situation 1.................................................................................................. .... 13-56 13-28 ccw priority situation 2.................................................................................................. .... 13-56 13-29 ccw priority situation 3.................................................................................................. .... 13-57 13-30 ccw priority situation 4.................................................................................................. .... 13-57 13-31 ccw priority situation 5.................................................................................................. .... 13-58 13-32 ccw priority situation 6.................................................................................................. .... 13-58 13-33 ccw priority situation 7.................................................................................................. .... 13-59 13-34 ccw priority situation 8.................................................................................................. .... 13-59 13-35 ccw priority situation 9.................................................................................................. .... 13-60 13-36 ccw priority situation 10................................................................................................. ... 13-60 13-37 ccw priority situation 11................................................................................................. ... 13-61 13-38 ccw freeze situ ation 12 ................................................................................................... .. 13-61 13-39 ccw freeze situ ation 13 ................................................................................................... .. 13-62 13-40 ccw freeze situ ation 14 ................................................................................................... .. 13-62 13-41 ccw freeze situ ation 15 ................................................................................................... .. 13-62 13-42 ccw freeze situ ation 16 ................................................................................................... .. 13-62 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xlvii figures figure number title page number 13-43 ccw freeze situ ation 17 ................................................................................................... .. 13-63 13-44 ccw freeze situ ation 18 ................................................................................................... .. 13-63 13-45 ccw freeze situ ation 19 ................................................................................................... .. 13-63 13-46 external trigger mode (positiv e edge) timing with pause................................................. 13-64 13-47 gated mode, single-s can timing . ....................................................................................... 13-6 5 13-48 gated mode, continuous scan timing................................................................................. 13-66 13-49 equivalent analog input circui try ....................................................................................... 13 -68 13-50 errors resulting from clippi ng ............................................................................................ 13-69 13-51 star-ground at the point of power supply or igin ................................................................ 13-71 13-52 electrical model of an a/d input si gnal .............................................................................. 13-72 13-53 external multiplexing of analog signal sources ................................................................. 13-74 13-54 input signal subjected to negative stress ............................................................................ 13-76 13-55 input signal subjected to positive stress ............................................................................. 13-7 7 14-1 qadc64e block diagram ..................................................................................................... 1 4-1 14-2 ccw queue and result ta ble block diagram ...................................................................... 14-5 14-3 example of external multiplexi ng ......................................................................................... 14 -6 14-4 module configuration regi ster (qadcmcr) ...................................................................... 14-8 14-5 qadc interrupt regist er (qadcint) ................................................................................ 14-12 14-6 interrupt levels on irq with ilbs ...................................................................................... 14-1 2 14-7 port a data register (portqa), po rt b data register (portqb)................................... 14-13 14-8 port x data direction register (ddrqa and ddrqb) ...................................................... 14-14 14-9 control register 0 (qacr0) ................................................................................................ 1 4-14 14-10 control register 1 (qacr1) ............................................................................................... 14-16 14-11 control register 2 (qacr2) ................................................................................................ 14-18 14-12 status register 0 (qasr0) ................................................................................................. .. 14-22 14-13 queue status transition ................................................................................................... ..... 14-27 14-14 status register 1 (qasr1) ................................................................................................. .. 14-28 14-15 qadc64e conversion qu eue operation............................................................................. 14-29 14-16 conversion command word table (ccw) ......................................................................... 14-31 14-17 right justified, unsigned resu lt format (rjurr).............................................................. 14-35 14-18 left justified, signed resu lt format (ljsrr) ..................................................................... 14-35 14-19 left justified, unsigned resu lt register (l jurr) .............................................................. 14-35 14-20 qadc64e analog subsyste m block diagra m .................................................................... 14-36 14-21 conversion timing ......................................................................................................... ...... 14-37 14-22 qadc64e queue operati on with pause ............................................................................. 14-40 14-23 qadc64e clock subsys tem functions ............................................................................... 14-49 14-24 bus cycle accesses ........................................................................................................ ...... 14-52 14-25 ccw priority situation 1.................................................................................................. .... 14-55 14-26 ccw priority situation 2.................................................................................................. .... 14-55 14-27 ccw priority situation 3.................................................................................................. .... 14-56 mpc561/mpc563 reference manual, rev. 1.2 xlviii freescale semiconductor figures figure number title page number 14-28 ccw priority situation 4.................................................................................................. .... 14-56 14-29 ccw priority situation 5.................................................................................................. .... 14-57 14-30 ccw priority situation 6.................................................................................................. .... 14-57 14-31 ccw priority situation 7.................................................................................................. .... 14-58 14-32 ccw priority situation 8.................................................................................................. .... 14-58 14-33 ccw priority situation 9.................................................................................................. .... 14-59 14-34 ccw priority situation 10................................................................................................. ... 14-59 14-35 ccw priority situation 11................................................................................................. ... 14-60 14-36 ccw freeze situ ation 12 ................................................................................................... .. 14-60 14-37 ccw freeze situ ation 13 ................................................................................................... .. 14-61 14-38 ccw freeze situ ation 14 ................................................................................................... .. 14-61 14-39 ccw freeze situ ation 15 ................................................................................................... .. 14-61 14-40 ccw freeze situ ation 16 ................................................................................................... .. 14-61 14-41 ccw freeze situ ation 17 ................................................................................................... .. 14-62 14-42 ccw freeze situ ation 18 ................................................................................................... .. 14-62 14-43 ccw freeze situ ation 19 ................................................................................................... .. 14-62 14-44 external trigger mode (positiv e edge) timing with pause................................................. 14-63 14-45 gated mode, single-s can timing . ....................................................................................... 14-6 4 14-46 gated mode, continuous scan timing................................................................................. 14-65 14-47 equivalent analog input circui try ....................................................................................... 14 -66 14-48 errors resulting from clippi ng ............................................................................................ 14-67 14-49 star-ground at the point of power supply or igin ................................................................ 14-69 14-50 electrical model of an a/d input si gnal .............................................................................. 14-71 14-51 external multiplexing of analog signal sources ................................................................. 14-72 14-52 input signal subjected to negative stress ............................................................................ 14-74 14-53 input signal subjected to positive stress ............................................................................. 14-7 5 15-1 qsmcm block diagram ........................................................................................................ 15-2 15-2 qsmcm interrupt levels ..................................................................................................... .. 15-7 15-3 interrupt hardware block diagram ........................................................................................ 15- 8 15-4 qsmcm configuration regi ster (qsmcmmcr) ................................................................ 15-8 15-5 qsm2 dual sci interrupt leve l register (qds ci_il) ......................................................... 15-9 15-6 qspi_il ? qspi interrupt level register .......................................................................... 15-10 15-7 portqs ? port qs da ta register ..................................................................................... 15-12 15-8 portqs pin assignment re gister (pqspar).................................................................... 15-13 15-9 portqs data direction re gister (ddrqs) ....................................................................... 15-14 15-10 qspi block diagram ........................................................................................................ .... 15-15 15-11 qspi control regist er 0 (spcr0)........................................................................................ 15- 17 15-12 spcr1 ? qspi contro l register ........................................................................................ 15-19 15-13 spcr2 ? qspi contro l register 2 ..................................................................................... 15-20 15-14 spcr3 ? qspi contro l register 3 ..................................................................................... 15-21 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor xlix figures figure number title page number 15-15 qspi status regi ster (spsr)............................................................................................... . 15-21 15-16 qspi ram.................................................................................................................. .......... 15-23 15-17 cr[0:f] ? command ra m 0x30 51c0, 0x30 51df.......................................................... 15-24 15-18 flowchart of qspi initia lization operat ion.......................................................................... 15-28 15-19 flowchart of qspi master operation (part 1) ...................................................................... 15-29 15-20 flowchart of qspi master operation (par t 2) ...................................................................... 15-30 15-21 flowchart of qspi master operation (par t 3) ...................................................................... 15-31 15-22 flowchart of qspi slave operation (part 1) ........................................................................ 15-32 15-23 flowchart of qspi slave operation (part 2) ........................................................................ 15-33 15-24 sci transmitter bl ock diagram ........................................................................................... 15 -43 15-25 sci receiver bloc k diagram ............................................................................................... 1 5-44 15-26 sccxr0 ? sci contro l register 0 ..................................................................................... 15-46 15-27 sci control regist er 1 (sccxr1)........................................................................................ 15- 47 15-28 scix status regi ster (scxsr).............................................................................................. 15-49 15-29 sci data regist er (scxdr) ................................................................................................. 15-51 15-30 start search example...................................................................................................... ...... 15-57 15-31 qsci1 control regist er (qsci1cr).................................................................................... 15-60 15-32 qsci1 status regist er (qsci1sr )....................................................................................... 15-6 1 15-33 queue transmitter bloc k enhancements ............................................................................. 15-63 15-34 queue transm it flow ....................................................................................................... .... 15-66 15-35 queue transmit so ftware flow ............................................................................................ 15 -66 15-36 queue transmit example for 17 data by tes ........................................................................ 15-67 15-37 queue transmit example for 25 data fr ames ..................................................................... 15-69 15-38 queue receiver bloc k enhancements .................................................................................. 15-70 15-39 queue receive flow ........................................................................................................ ..... 15-73 15-40 queue receive soft ware flow ............................................................................................. 15 -74 15-41 queue receive example fo r 17 data bytes.......................................................................... 15-75 16-1 toucan block diagram ....................................................................................................... . 16-1 16-2 typical can ne twork........................................................................................................ .... 16-3 16-3 extended id message bu ffer structure .................................................................................. 16-4 16-4 standard id message bu ffer structur e ................................................................................... 16-4 16-5 relationship between system cl ock and can bit segments ................................................ 16-9 16-6 can controller st ate diagram............................................................................................. 16 -12 16-7 interrupt levels on irq with ilbs ...................................................................................... 16-2 1 16-8 toucan message buffer memory map .............................................................................. 16-24 16-9 toucan module configuration register (can mcr) ....................................................... 16-25 16-10 toucan interrupt configurat ion register (canicr) ........................................................ 16-27 16-11 control register 0 (canctrl0)......................................................................................... 16-2 7 16-12 control register 1 (canctrl1)......................................................................................... 16-2 8 16-13 prescaler divide register................................................................................................. ..... 16-29 mpc561/mpc563 reference manual, rev. 1.2 l freescale semiconductor figures figure number title page number 16-14 control register 2 (canctrl2)......................................................................................... 16-3 0 16-15 free running timer regi ster (timer ) ............................................................................... 16-31 16-16 receive global mask register: hi gh (rxgmskhi), low (rxgmsklo) ....................... 16-31 16-17 receive buffer 14 mask registers: hi gh (rx14mskhi), low (rx14msklo)............... 16-32 16-18 receive buffer 15 mask registers: hi gh (rx15mskhi), low (rx15msklo)............... 16-33 16-19 error and status re gister (estat) ...................................................................................... 16- 33 16-20 interrupt mask regi ster (imask)........................................................................................ 16- 35 16-21 interrupt flag regi ster (iflag)........................................................................................... 16-36 16-22 receive error counter (rxectr), transmit error counter (txectr)............................ 16-36 17-1 mpc561/mpc563 mios14 bl ock diagram .......................................................................... 17-2 17-2 mios14 memory map ......................................................................................................... 1 7-13 17-3 mbism regi sters ............................................................................................................ ..... 17-13 17-4 test and signal control regi ster (mios14tpcr) .............................................................. 17-14 17-5 vector register (m ios14vect) .. ....................................................................................... 17-14 17-6 mios14 module/version number register (mios14vnr)............................................... 17-14 17-7 module configuration regi ster (mios14m cr).................................................................. 17-15 17-8 mcpsm block di agram....................................................................................................... 1 7-16 17-9 mcpsm status/control regi ster (mcpsmscr) ................................................................ 17-18 17-10 mmcsm block di agram ..................................................................................................... 17 -20 17-11 mmcsm modulus up -counter............................................................................................ 17-20 17-12 mmcsm up-counter regi ster (mmcsmcn t) ................................................................. 17-23 17-13 mmcsm modulus latch regi ster (mmcsmml) .............................................................. 17-24 17-14 mmcsm status/control regi ster (mmcsmscr).............................................................. 17-24 17-15 mdasm block di agram...................................................................................................... 1 7-27 17-16 input pulse width meas urement exampl e ........................................................................... 17-31 17-17 input period measurem ent example..................................................................................... 17-32 17-18 mdasm input captur e example ......................................................................................... 17-33 17-19 single shot output pulse example ....................................................................................... 17- 35 17-20 single shot output tr ansition exampl e ............................................................................... 17-36 17-21 mdasm output pulse width modulation exam ple............................................................ 17-37 17-22 mdasm data a regist er (mdasmar) ............................................................................ 17-41 17-23 mdasm datab regist er (mdasmbr).............................................................................. 17-42 17-24 mdasm status/control regi ster (mdasmscr )............................................................... 17-44 17-25 mpwmsm block di agram .................................................. ................................................ 17-4 7 17-26 mpwmsm period regist er (mpwmper r) ....................................................................... 17-57 17-27 mpwmsm pulse width regi ster (mpwmpulr).............................................................. 17-58 17-28 mpwmsm counter regist er (mpwmcnt r) .................................................................... 17-58 17-29 mpwmsm status/control re gister (mpwms cr)............................................................. 17-58 17-30 mpiosm 1-bit bloc k diagram ..... ....................................................................................... 17-6 0 17-31 mpiosm ? register organization ..................................................................................... 17-62 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor li figures figure number title page number 17-32 mpiosm data regist er (mpiosmdr)............................................................................... 17-62 17-33 mpiosm data direction re gister (mpiosmd dr)............................................................ 17-63 17-34 mios14 interrupt structure................................................................................................ .. 17-64 17-35 interrupt status regist er (mios14sr0 )............................................................................... 17-66 17-36 interrupt enable regist er (mios14er0) ............................................................................. 17-66 17-37 interrupt request pending re gister (mios14r pr0) ........................................................... 17-67 17-38 interrupt status regist er (mios14sr1 )............................................................................... 17-67 17-39 interrupt enable regist er (mios14er1) ............................................................................. 17-68 17-40 interrupt request pending re gister (mios14r pr1) ........................................................... 17-68 17-41 mios14 interrupt level register 0 (m ios14lvl0)........................................................... 17-69 17-42 mios14 interrupt level register 1 (m ios14lvl1)........................................................... 17-70 17-43 mios14 example: double captur e pulse width meas urement .......................................... 17-71 17-44 mios14 example: double capt ure period measur ement ................................................... 17-72 17-45 mios14 example: double e dge output compare .............................................................. 17-73 17-46 mios14 example: pulse wi dth modulation ou tput............................................................ 17-74 18-1 n-signal i/o compared with ppm i/o................................................................................... 18-2 18-2 block diagram of ppm module ............................................................................................. 18- 4 18-3 internal multiplexer mechanis m for transmit data............................................................... 18-5 18-4 internal multiplexer mechanism for received data .............................................................. 18-5 18-5 ppm clocks and seri al data signals ...................................................................................... 18- 6 18-6 one transmit and receive cycle in spi mode ...................................................................... 18-7 18-7 examples of several tclk fre quencies and sample rates ................................................. 18-8 18-8 module configuration re gister (ppmmcr)........................................................................ 18-10 18-9 ppm control register (ppmpcr). ....................................................................................... 18-12 18-10 set enrx while entx = 1................................................................................................. 18 -14 18-11 set entx while enrx = 1.................................................................................................. 1 8-14 18-12 spi transfer format with cp = 0 ......................................................................................... 18 -15 18-13 spi transfer format with cp = 1 ......................................................................................... 18 -15 18-14 transmit configuration regi ster 1 (tx_conf ig_1) ......................................................... 18-16 18-15 transmit configuration regi ster 2 (tx_conf ig_2) ......................................................... 18-16 18-16 receive configur ation register 1 (r x_config_1)........................................................... 18-16 18-17 receive configur ation register 2 (r x_config_2)........................................................... 18-17 18-18 receive data regist er (rx_data ) .................................................................................... 18-18 18-19 receive shifter regist er (rx_shifter) ............................................................................ 18-18 18-20 transmit data regist er (tx_data) ................................................................................... 18-18 18-21 general purpose data ou t register (gpdo) ....................................................................... 18-19 18-22 general purpose data in register (g pdi)............................................................................ 18-19 18-23 short register (s hort_reg)............................................................................................. 18- 19 18-24 example of toucan internal short with sh_tcan = 0b110............................................ 18-21 18-25 short between tp u channels .............................................................................................. 18 -22 mpc561/mpc563 reference manual, rev. 1.2 lii freescale semiconductor figures figure number title page number 18-26 short channels register (short_ch_reg) ..................................................................... 18-23 18-27 scale transmit clock regist er (scale_tclk_r eg)....................................................... 18-24 19-1 tpu3 block di agram ......................................................................................................... .... 19-1 19-2 tpu3 interrupt levels ...................................................................................................... ...... 19-5 19-3 tcr1 prescaler control ..................................................................................................... ..... 19-7 19-4 tcr2 prescaler control ..................................................................................................... ..... 19-8 19-5 tpumcr ? tpu module confi guration register ............................................................. 19-11 19-6 dscr ? development support control register ............................................................... 19-12 19-7 dssr ? development support status regist er .................................................................. 19-14 19-8 ticr ? tpu3 interrupt conf iguration regi ster ................................................................. 19-14 19-9 cier ? channel interrupt enable register......................................................................... 19-15 19-10 cfsr0 ? channel function se lect register 0 .................................................................... 19-16 19-11 cfsr1 ? channel function se lect register 1 .................................................................... 19-16 19-12 cfsr2 ? channel function se lect register 2 .................................................................... 19-16 19-13 cfsr3 ? channel function se lect register 3 .................................................................... 19-16 19-14 hsqr0 ? host sequenc e register 0................................................................................... 19-17 19-15 hsqr1 ? host sequenc e register 1................................................................................... 19-17 19-16 hsrr0 ? host service re quest register 0 ........................................................................ 19-17 19-17 hsrr1 ? host service re quest register 1 ........................................................................ 19-17 19-18 cpr0 ? channel prior ity register 0 ................................................................................... 19-18 19-19 cpr1 ? channel prior ity register 1 ................................................................................... 19-18 19-20 cisr ? channel interrupt status regi ster .......................................................................... 19-19 19-21 tpumcr2 ? tpu module confi guration register 2 ........................................................ 19-19 19-22 tpumcr3 ? tpu module confi guration register 3 ........................................................ 19-21 19-23 siutst ? siu test register .............................................................................................. 19 -22 20-1 dptram confi guration ....................................................................................................... . 20-2 20-2 dptram memory map......................................................................................................... 2 0-3 20-3 dpt module configuration register (dpt mcr).................................................................. 20-3 20-4 ram array base address register (rambar)................................................................... 20-5 20-5 multiple input signature re gister high (misrh) ................................................................. 20-5 20-6 multiple input signature re gister low (mis rl) .................................................................. 20-6 20-7 misc counter (miscnt) ...................................................................................................... 20-6 21-1 block diagram for a 512 kbyte uc3f module confi guration .............................................. 21-2 21-2 uc3f eeprom configuration re gister (uc3fmcr) ......................................................... 21-5 21-3 uc3fmcre? uc3f eeprom extende d configuration register ..................................... 21-9 21-4 uc3f eeprom high voltage cont rol register (uc3fctl) ............................................ 21-11 21-5 pegood valid time .......................................................................................................... . 21-14 21-6 shadow inform ation ......................................................................................................... .... 21-16 21-7 hard reset configuration word (uc3fcfi g) .................................................................... 21-16 21-8 512-kbyte array conf iguration ............................................................................................ 21 -19 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor liii figures figure number title page number 21-9 program state diagram...................................................................................................... ... 21-23 21-10 erase state diagram ....................................................................................................... ....... 21-27 21-11 censorship states and transiti ons ........................................................................................ 2 1-33 22-1 system block diagram ....................................................................................................... .... 22-2 22-2 mpc561/mpc563 memory map with calram address ranges ...................................... 22-3 22-3 standby power supply configurat ion for calram array .................................................. 22-4 22-4 calram array ............................................................................................................... ...... 22-7 22-5 calram module overlay map of flash (clps = 0) .......................................................... 22-8 22-6 calram address map (clps = 0) ..................................................................................... 22-9 22-7 calram module overlay map of flash (clps = 1) ........................................................ 22-10 22-8 calram address map (clps = 1) ................................................................................... 22-11 22-9 calram module configuration register (crammcr).................................................. 22-13 22-10 calram region base addres s register (cram_rbax) ................................................ 22-16 22-11 calram overlay configuratio n register (cram_ovlcr)........................................... 22-17 22-12 calram ownership trace re gister (cram_otr) ......................................................... 22-18 23-1 watchpoint and breakpoint s upport in the cpu.................................................................... 23-9 23-2 partially supported watchpoint /breakpoint example.......................................................... 23-13 23-3 instruction support gene ral structure .................................................................................. 23-1 5 23-4 load/store support gene ral structure.................................................................................. 23-18 23-5 functional diagram of mpc561/mp c563 debug mode support ....................................... 23-21 23-6 debug mode logic ........................................................................................................... .... 23-23 23-7 bdm mode se lection ......................................................................................................... .. 23-24 23-8 debug mode reset co nfiguration ........................................................................................ 23-25 23-9 asynchronous clock serial communications ...................................................................... 23-32 23-10 synchronous self clock se rial communicat ion .................................................................. 23-32 23-11 enabling clock mode fo llowing reset................................................................................ 23-33 23-12 download procedure code example .................................................................................... 23-37 23-13 slow download pro cedure loop ... ....................................................................................... 23-3 8 23-14 fast download pr ocedure loop ........................................................................................... 23- 38 23-15 comparator a?d value regi ster (cmpa?cmpd).............................................................. 23-41 23-16 exception cause regi ster (ecr).......................................................................................... 23 -42 23-17 debug enable regist er (der) .............................................................................................. 2 3-43 23-18 breakpoint counter a value and c ontrol register (counta)......................................... 23-45 23-19 breakpoint counter b value and control register (countb) .......................................... 23-46 23-20 comparator e?f value re gisters (cmpe?cmpf) .............................................................. 23-46 23-21 comparator g?h value regi sters (cmpg?cmph)............................................................ 23-47 23-22 l-bus support control re gister 1 (lctrl) ........................................................................ 23-47 23-23 l-bus support control re gister 2 (lctrl2) ...................................................................... 23-48 23-24 i-bus support control re gister (ictrl ) ............................................................................. 23-51 23-25 breakpoint address re gister (bar ) .................................................................................... 23-53 mpc561/mpc563 reference manual, rev. 1.2 liv freescale semiconductor figures figure number title page number 23-26 development port data register (dpdr) ............................................................................ 23-53 24-1 readi functional bl ock diagram......................................................................................... 24-3 24-2 readi ownership trace re gister (otr).............................................................................. 24-9 24-3 readi device id register .................................................................................................. 2 4-10 24-4 readi development contro l (dc) register ....................................................................... 24-10 24-5 readi mode control (mc) register .................................................................................. 24-12 24-6 readi user base a ddress regist er .................................................................................... 24-13 24-7 readi read/write access register .................................................................................... 24-14 24-8 readi upload/download in formation regi ster ................................................................. 24-16 24-9 rwd field conf iguration .................................................................................................... 24-17 24-10 readi data trace attr ibutes 1 register (dta1) readi data trace attributes 2 register (d ta2) ............................................................... 24-17 24-11 functional diagram of si gnal interfac e................................................................................ 24-2 2 24-12 auxiliary signal packet stru cture for program trace indirect branch message ................................................................................................................. ... 24-23 24-13 msei/mseo tr ansfers....................................................................................................... .. 24-24 24-14 transmission sequence of messages.................................................................................... 24-32 24-15 readi module enabled...................................................................................................... . 24-34 24-16 enabling program trace out of system reset ..................................................................... 24-36 24-17 readi mode se lection ...................................................................................................... .. 24-36 24-18 readi module disabled ..................................................................................................... . 24-37 24-19 direct branch me ssage format ............................................................................................ 24 -38 24-20 indirect branch me ssage format .......................................................................................... 24 -39 24-21 indirect branch message form at with compressed code.................................................... 24-39 24-22 bit pointer format with compressed code .......................................................................... 24-39 24-23 program trace correcti on message format ......................................................................... 24-42 24-24 direct branch sync hronization message form at (ptsm = 0)............................................. 24-44 24-25 direct branch sync hronization message form at (ptsm = 1)............................................. 24-44 24-26 indirect branch s ynchronization message format (ptsm = 0) .......................................... 24-44 24-27 indirect branch s ynchronization message format (ptsm = 1) .......................................... 24-44 24-28 direct branch s ynchronization message format with compressed code (ptsm = 0)................................................................................................................ .. 24-45 24-29 direct branch s ynchronization message format with compressed code (ptsm = 1)................................................................................................................ .. 24-45 24-30 indirect branch synchronizati on message format with compressed code (ptsm - 0)................................................................................................................ ... 24-45 24-31 indirect branch synchronizati on message format with compressed code (ptsm = 1)................................................................................................................ .. 24-45 24-32 program trace full message format.................................................................................... 24-46 24-33 relative address generati on and re-creation ..................................................................... 24-47 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lv figures figure number title page number 24-34 error message (queue overflow) format ............................................................................ 24-47 24-35 direct branch message ..................................................................................................... .... 24-49 24-36 indirect bran ch message ................................................................................................... ... 24-49 24-37 indirect branch message wi th compressed code ................................................................ 24-49 24-38 program trace correct ion message ..................................................................................... 24-50 24-39 error message (program/data/ ownership trace overrun).................................................. 24-50 24-40 direct branch synchr onization messa ge.............................................................................. 24-50 24-41 indirect branch synchr onization message ........................................................................... 24-51 24-42 direct branch synchronization message with compressed code ......................................................................................................... 24 -51 24-43 indirect branch sync hronization message with compressed code ..................................... 24-51 24-44 data write mess age format ................................................................................................. 24-52 24-45 data read messa ge format .................................................................................................. 24-53 24-46 data write synchronizati on message format ...................................................................... 24-54 24-47 data read synchronizati on message format ....................................................................... 24-54 24-48 error message (queue overflow) format ............................................................................ 24-54 24-49 data trace flow diagram fo r non-pipelined access .......................................................... 24-55 24-50 date write message........................................................................................................ ...... 24-57 24-51 data read message......................................................................................................... ...... 24-58 24-52 data write synchroni zation message................................................................................... 24-58 24-53 data read synchroni zation message ................................................................................... 24-58 24-54 error message (program/data/ ownership trace overrun).................................................. 24-59 24-55 target ready message...................................................................................................... .... 24-59 24-56 read register message ..................................................................................................... .... 24-59 24-57 write register message .................................................................................................... .... 24-60 24-58 read/write respons e message............................................................................................. 24 -60 24-59 read/write access fl ow diagram ....................................................................................... 24-61 24-60 error message (read/write access error) format............................................................... 24-67 24-61 error message (invalid message) form at ............................................................................ 24-67 24-62 error message (invalid a ccess opcode) format.................................................................. 24-67 24-63 block write access ........................................................................................................ ...... 24-69 24-64 block read access ......................................................................................................... ...... 24-70 24-65 device ready for upload/dow nload request me ssage....................................................... 24-70 24-66 upload request message.................................................................................................... .. 24-71 24-67 download request message ................................................................................................. 2 4-71 24-68 upload/download info rmation message.............................................................................. 24-72 24-69 error message (invalid access opcode) .............................................................................. 24-72 24-70 watchpoint message format ................................................................................................ 2 4-73 24-71 error message (watchpoint overrun) format...................................................................... 24-73 24-72 watchpoint message........................................................................................................ ..... 24-74 mpc561/mpc563 reference manual, rev. 1.2 lvi freescale semiconductor figures figure number title page number 24-73 error message (watc hpoint overrun) .................................................................................. 24-74 24-74 ownership trace me ssage format ....................................................................................... 24-75 24-75 error message format ...................................................................................................... .... 24-75 24-76 ownership tra ce message................................................................................................... . 24-76 24-77 error message (program/data/ ownership trace overrun).................................................. 24-76 24-78 rcpu development access multiplexing between readi and bdm signals .................. 24-77 24-79 dsdi messag e format....................................................................................................... ... 24-78 24-80 dsdo message format ....................................................................................................... . 24-78 24-81 bdm status messa ge format ............................................................................................... 24 -79 24-82 error message (invalid message) form at ............................................................................ 24-79 24-83 rcpu development access flow diagram ......................................................................... 24-81 24-84 rcpu development access timing diagram ? debug mode entry out-of-reset........... 24-83 24-85 transmission sequence of ds dx data messages ................................................................ 24-83 24-86 error message (inva lid message) . ........................................................................................ 24 -85 24-87 dsdi data message (assert no n-maskable brea kpoint) .................................................... 24-85 24-88 dsdi data message (cpu instruction ? rfi) ...................................................................... 24-85 24-89 dsdo data message (c pu data out) ................................................................................. 24-86 25-1 pin requiremen t on jtag.................................................................................................... .. 25-1 25-2 test logic bloc k diagram................................................................................................... ... 25-3 25-3 jtag mode se lection ........................................................................................................ .... 25-3 25-4 tap controller st ate machin e ............................................................................................... 25-4 25-5 bypass re gister............................................................................................................ ......... 25-31 a-1 instruction compression alternatives ..................................................................................... a-3 a-2 addressing instructions with compressed address ................................................................ a-4 a-3 compressed target address gene ration by direct branches.................................................. a-5 a-4 branch right segment compression #1 .................................................................................. a-7 a-5 branch right segment compression #2 .................................................................................. a-8 a-6 global bypass inst ruction layout ........................................................................................... a -8 a-7 class_1 instruction layout .................................................................................................. a-9 a-8 class_2 instruction layout .................................................................................................. a-9 a-9 class_3 instruction layout ................................................................................................ a- 10 a-10 class_4 instruction layout ................................................................................................ a -11 a-11 code compressi on process................................................................................................... .a-12 a-12 code decompressi on process ................................................................................................ a -13 a-13 i-bus support control re gister (ictrl ) .............................................................................. a-16 a-14 decompressor class confi guration registers1 (dccr x ) ..................................................... a-19 c-1 mpc561/mpc563 power distribu tion diagram ? 2.6 v .......................................................c-3 c-2 power distribution diagram ? 5 v and analog .....................................................................c-3 c-3 crystal oscillat or circuit .................................................................................................. ........c-4 c-4 rc filter ex ample ........................................................................................................... .........c-5 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lvii figures figure number title page number c-5 bypass capacitors exampl e (alternative) ................................................................................c-5 c-6 rc filter ex ample ........................................................................................................... .........c-6 c-7 lc filter example (alternative )............................................................................................. ..c-6 c-8 pll off-chip capaci tor example ............................................................................................c- 7 c-9 iramstby regulator circuit .................................................................................................c -8 d-1 tpu3 memory map............................................................................................................. .... d-1 d-2 pta parame ters .............................................................................................................. ......... d-4 d-3 qom parameters .............................................................................................................. ....... d-6 d-4 tsm parameters ? ma ster mode ........................................................................................... d-8 d-5 tsm parameters ? slave mode ... .......................................................................................... d-9 d-6 fqm parameters .............................................................................................................. ...... d-11 d-7 uart transmitter pa rameters ...... ........................................................................................ d-1 3 d-8 uart receiver parameters................................................................................................... d -14 d-9 nitc parameters ............................................................................................................. ...... d-16 d-10 comm parameters ............................................................................................................ .... d-18 d-10 comm parameters (c ontinued)..... ........................................................................................ d-2 0 d-11 halld parameters ........................................................................................................... .... d-21 d-12 mcpwm parameters ? master mode ................................................................................. d-23 d-13 mcpwm parameters ? slav e edge-aligned mode ............................................................ d-24 d-14 mcpwm parameters ? slave ch a n on-inverted center-aligned mode.......................... d-26 d-15 mcpwm parameters ? slave ch b n on-inverted center-aligned mode .......................... d-27 d-16 mcpwm parameters ? slave ch a inverted center-a ligned mode .................................. d-28 d-17 mcpwm parameters ? slave ch b inverted center-a ligned mode .................................. d-29 d-18 multi parameters ? frinc ...... ........................................................................................ d-31 d-19 multi parameters ? fredec........................................................................................... d-32 d-20 multi parameters ? speed.............................................................................................. d-33 d-21 multi parameters ? pwm_in .......................................................................................... d-34 d-22 fqd parameters ? pr imary channel ................................................................................... d-36 d-23 fqd parameters ? sec ondary channel ............................................................................... d-37 d-24 ppwa parameters............................................................................................................ ...... d-39 d-25 id parameters .............................................................................................................. .......... d-41 d-26 oc parameters .............................................................................................................. ......... d-43 d-27 pwm parameters ............................................................................................................. ...... d-45 d-28 dio parameters............................................................................................................. ......... d-47 d-29 spwm parame ters ............................................................................................................ ..... d-49 d-30 rwtpin para meters .......................................................................................................... ... d-52 d-31 two possible siop c onfigurations ....................................................................................... d-53 d-32 siop parameters ............................................................................................................ ........ d-55 d-33 siop function data transition example .............................................................................. d-59 f-1 option a power-up sequence wi thout keep-alive supply.................................................. f-14 mpc561/mpc563 reference manual, rev. 1.2 lviii freescale semiconductor figures figure number title page number f-2 option a power-up sequence wi th keep-alive s upply....................................................... f-14 f-3 option a power-down sequence wi thout keep-alive supply............................................. f-15 f-4 option a power-down sequence with keep-alive supply.................................................. f-15 f-5 option b power-up sequence wi thout keep-alive supply.................................................. f-16 f-6 option b power-up sequence wi th keep-alive s upply ....................................................... f-16 f-7 option b power-down sequence wi thout keep-alive supply ............................................. f-17 f-8 option b power-down sequence with keep-alive supply ................................................... f-17 f-9 generic timing examples ..................................................................................................... .f-19 f-10 clkout pin timing .......................................................................................................... ... f-27 f-11 synchronous output si gnals timing ...................................................................................... f-28 f-12 predischarge timing ........................................................................................................ ....... f-29 f-13 synchronous active pull-up and open drain outputs signals timing ......................................................................................................... .f-30 f-14 synchronous input si gnals timing......................................................................................... f- 31 f-15 input data timing in normal case ........................................................................................ f-3 2 f-16 external bus read timing (gpcm controlled ? acs = ?00?).............................................. f-33 f-17 external bus read timing (gpcm contro lled ? trlx = ?0? acs = ?10?).......................... f-34 f-18 external bus read timing (gpcm contro lled ? trlx = ?0? acs = ?11?).......................... f-35 f-19 external bus read timing (gpcm controll ed ? trlx = ?1?, acs = ?10?, acs = ?11?).... f-36 f-20 address show cycle bus timing .. ......................................................................................... f-3 6 f-21 address and data show cycle bus timi ng............................................................................ f-37 f-22 external bus write timing (gpcm contro lled ? trlx = ?0?, csnt = ?0?) ....................... f-38 f-23 external bus write timing (gpcm cont rolled ? trlx = ?0?, csnt = ?1?) ....................... f-39 f-24 external bus write timing (gpcm cont rolled ? trlx = ?1?, csnt = ?1?) ....................... f-40 f-25 external master read from in ternal registers timing.......................................................... f-41 f-26 external master write to in ternal registers timing ............................................................. f-42 f-27 interrupt detection ti ming for external edge sensitive lines .............................................. f-43 f-28 debug port clock i nput timing ............................................................................................. f -44 f-29 debug port timings......................................................................................................... ....... f-44 f-30 auxiliary port data i nput timing diag ram............................................................................ f-45 f-31 auxiliary port data out put timing diagram ......................................................................... f-46 f-32 enable auxiliar y from rsti................................................................................................. .f-46 f-33 disable auxiliar y from rsti................................................................................................ .f-46 f-34 reset timing ? configurati on from data bus........................................................................ f-48 f-35 reset timing ? data bus weak drive during configuration................................................ f-49 f-36 reset timing ? debug port configuration ............................................................................. f-50 f-37 jtag test clock i nput timing .............................................................................................. f -51 f-38 jtag test access port timing diagram ............................................................................... f-52 f-39 boundary scan (jtag) timing diagram............................................................................... f-53 f-40 qspi timing ? master , cpha = 0 ......................................................................................... f-58 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lix figures figure number title page number f-41 qspi timing ? master , cpha = 1 ......................................................................................... f-58 f-42 qspi timing ? slave, cpha = 0 ........................................................................................... f-5 9 f-43 qspi timing ? slave, cpha = 1 ........................................................................................... f-5 9 f-44 tpu3 timing ................................................................................................................ .......... f-61 f-45 ppm_tclk ti ming ............................................................................................................ ... f-63 f-46 ppm data transfer ti ming (spi mode)................................................................................. f-63 f-47 mcpsm enable to vs_pclk pulse timing diagram .......................................................... f-64 f-48 mpwmsm minimum output puls e example timing diagram............................................ f-65 f-49 mcpsm enable to mpwmo output pi n rising edge timing diagram .............................. f-66 f-50 mpwmsm enable to mpwmo output pin rising edge timing diagram ......................... f-66 f-51 mpwmsm interrupt flag to mpwmo output pin falling edge timing diagram.............. f-66 f-52 mmcsm minimum input pin (either lo ad or clock) timi ng diagram .............................. f-67 f-53 mmcsm clock pin to counter bu s increment timing diagram ........................................ f-68 f-54 mmcsm load pin to counter bu s reload timing diagram............................................... f-68 f-55 mmcsm counter bus reload to interr upt flag setting timing diagram........................... f-68 f-56 mmcsm prescaler clock se lect to counter bus increm ent timing diagram .................... f-69 f-57 mdasm minimum input pi n timing diagram..................................................................... f-70 f-58 mdasm input pin to counter bu s capture timing diagram.............................................. f-70 f-59 mdasm input pin to mdasm inte rrupt flag timing diagram .......................................... f-70 f-60 mdasm minimum output pulse width timing diagram.................................................... f-71 f-61 counter bus to mdasm output pin change timing diagram............................................. f-71 f-62 counter bus to mdasm interrupt flag setting timing diagram ......................................... f-71 f-63 mpiosm input pin to mpiosm_dr (d ata register) timing diagram ............................... f-72 f-64 mpc561/mpc563 package f ootprint (1 of 2) ....................................................................... f-84 f-65 mpc561/mpc563 package f ootprint (2 of 2) ....................................................................... f-85 f-66 mpc561/mpc563 ba ll map .................................................................................................. f-8 6 f-67 mpc561/mpc563 ball map (black and white, page 1) ....................................................... f-87 f-68 mpc561/mpc563 ball map (black and white, page 2) ....................................................... f-88 f-69 mpc561/mpc563 ball map (black and white, page 3) ....................................................... f-89 f-70 mpc561/mpc563 ball map (black and white, page 4) ....................................................... f-90 g-1 option a power-up sequence wi thout keep-alive supply................................................. g-13 g-2 option a power-up sequence wi th keep-alive s upply...................................................... g-14 g-3 option a power-down sequence wi thout keep-alive supply............................................ g-14 g-4 option a power-down sequence with keep-alive supply................................................. g-15 g-5 option b power-up sequence wi thout keep-alive supply................................................. g-16 g-6 option b power-up sequence wi th keep-alive s upply ...................................................... g-16 g-7 option b power-down sequence wi thout keep-alive supply ............................................ g-17 g-8 option b power-down sequence with keep-alive supply .................................................. g-17 g-9 generic timing examples ..................................................................................................... g-19 g-10 clkout pin timing .......................................................................................................... .. g-25 mpc561/mpc563 reference manual, rev. 1.2 lx freescale semiconductor figures figure number title page number g-11 synchronous output si gnals timing ..................................................................................... g-26 g-12 synchronous active pull-up and open drain outputs signals timing .............................. g-27 g-13 synchronous input si gnals timing ........................................................................................ g-2 8 g-14 input data timing in normal case ....................................................................................... g-29 g-15 external bus read timing (gpcm controlled ? acs = ?00?)............................................. g-30 g-16 external bus read timing (gpcm contro lled ? trlx = ?0? acs = ?10?)......................... g-31 g-17 external bus read timing (gpcm contro lled ? trlx = ?0? acs = ?11?)......................... g-32 g-18 external bus read timing (gpcm controll ed ? trlx = ?1?, acs = ?10?, acs = ?11?)... g-33 g-19 address show cycle bus timing .. ........................................................................................ g-34 g-20 address and data show cycle bus timi ng........................................................................... g-35 g-21 external bus write timing (gpcm contro lled ? trlx = ?0?, csnt = ?0?) ...................... g-36 g-22 external bus write timing (gpcm cont rolled ? trlx = ?0?, csnt = ?1?) ...................... g-37 g-23 external bus write timing (gpcm cont rolled ? trlx = ?1?, csnt = ?1?) ...................... g-38 g-24 external master read from in ternal registers timing......................................................... g-39 g-25 external master write to in ternal registers timing ............................................................ g-40 g-26 interrupt detection ti ming for external edge sensitive lines ............................................. g-41 g-27 debug port clock i nput timing ............................................................................................ g- 42 g-28 debug port timings......................................................................................................... ...... g-42 g-29 auxiliary port data i nput timing diag ram........................................................................... g-43 g-30 auxiliary port data out put timing diagram ........................................................................ g-43 g-31 enable auxiliar y from rsti................................................................................................. g-44 g-32 disable auxiliar y from rsti................................................................................................ g-44 g-33 reset timing ? configurati on from data bus....................................................................... g-45 g-34 reset timing ? data bus weak drive during configuration............................................... g-46 g-35 reset timing ? debug port configuration ............................................................................ g-47 g-36 jtag test clock i nput timing ............................................................................................. g- 48 g-37 jtag test access port timing diagram .............................................................................. g-48 g-38 boundary scan (jtag) timing diagram.............................................................................. g-49 g-39 qspi timing ? master, cpha = 0 ........................................................................................ g-54 g-40 qspi timing ? master, cpha = 1 ........................................................................................ g-54 g-41 qspi timing ? slave, cpha = 0 .......................................................................................... g-55 g-42 qspi timing ? slave, cpha = 1 .......................................................................................... g-55 g-43 tpu3 timing ................................................................................................................ ......... g-57 g-44 ppm_tclk ti ming ............................................................................................................ .. g-59 g-45 ppm data transfer ti ming (spi mode)................................................................................ g-59 g-46 mcpsm enable to vs_pclk pulse timing diagram ......................................................... g-60 g-47 mpwmsm minimum output puls e example timing diagram........................................... g-61 g-48 mcpsm enable to mpwmo output pi n rising edge timing diagram ............................. g-61 g-49 mpwmsm enable to mpwmo output pin rising edge timing diagram ....................... g-62 g-50 mpwmsm interrupt flag to mpwmo output pin falling edge timing diagram............. g-62 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxi figures figure number title page number g-51 mmcsm minimum input pin (either lo ad or clock) timing diagram.............................. g-63 g-52 mmcsm clock pin to counter bu s increment timing diagram......................................... g-63 g-53 mmcsm load pin to counter bu s reload timing diagram ............................................... g-64 g-54 mmcsm counter bus reload to interr upt flag setting ti ming diagram ........................... g-64 g-55 mmcsm prescaler clock select to count er bus increment timing diagram..................... g-64 g-56 mdasm minimum input pi n timing diagram.................................................................... g-65 g-57 mdasm input pin to counter bu s capture timing diagram............................................. g-66 g-58 mdasm input pin to mdasm inte rrupt flag timing diagram ......................................... g-66 g-59 mdasm minimum output pulse width timing diagram................................................... g-66 g-60 counter bus to mdasm output pin change timing diagram............................................ g-66 g-61 counter bus to mdasm interrupt flag setting timing diagram ........................................ g-67 g-62 mpiosm input pin to mpiosm_dr (d ata register) timing diagram .............................. g-67 g-63 mpc561/mpc563 package f ootprint (1 of 2) ...................................................................... g-79 g-64 mpc561/mpc563 package f ootprint (2 of 2) ...................................................................... g-80 g-65 mpc561/mpc563 ba ll map ................................................................................................. g-81 g-66 mpc561/mpc563 ball map (black and white, page 1) ...................................................... g-82 g-67 mpc561/mpc563 ball map (black and white, page 2) ...................................................... g-83 g-68 mpc561/mpc563 ball map (black and white, page 3) ...................................................... g-84 g-69 mpc561/mpc563 ball map (black and white, page 4) ...................................................... g-85 mpc561/mpc563 reference manual, rev. 1.2 lxii freescale semiconductor figures figure number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxiii table number title page number i notational convent ions ..................................................................................................... 1-l xxxii ii acronyms and abbreviate d terms .................................................................................... 1-lxxxii 1-1 mpc56x family features ...................................................................................................... ... 1-1 1-2 differences between mpc 555 and mpc561/mp c563............................................................ 1-9 2-1 mpc561/mpc563 signal descriptions .................................................................................... 2-3 2-2 mpc561/mpc563 signa l sharing.......................................................................................... 2-20 2-3 reduced and full port mode pads.......................................................................................... 2-2 1 2-4 full port only mode pads .................................................................................................... .. 2-21 2-5 pdmcr field de scriptions .................................................................................................... 2-22 2-6 pdmcr2 field de scription.................................................................................................... 2-24 2-7 tcnc pad functi onalities .................................................................................................... .. 2-25 2-8 ppmpad pad functi onalities........ ......................................................................................... 2 -25 2-9 enhanced pcs f unctionality ................................................................................................. 2-25 2-10 enhanced pcs 4 & 5 pad function ........................................................................................ 2-26 2-11 enhanced pcs 6 & 7 pad function ........................................................................................ 2-28 2-12 mpc561/mpc563 development su pport shared signals ..................................................... 2-28 2-13 mpc561/mpc563 mode selection opti ons.......................................................................... 2-29 2-14 mpc561/mpc563 signal reset state .................................................................................... 2-34 3-1 rcpu execution units ........................................................................................................ ..... 3-4 3-2 supervisor-lev el sprs ....................................................................................................... ...... 3-9 3-3 development s upport sprs.................................................................................................... 3-11 3-4 fpscr bit cate gories ........................................................................................................ .... 3-13 3-5 fpscr bit desc riptions ...................................................................................................... ... 3-14 3-6 floating-point result flags in fpscr ................................................................................... 3-16 3-7 bit settings for cr0 field of cr............................................................................................ 3-17 3-8 bit settings for cr1 field of cr............................................................................................ 3-17 3-9 crn field bit settings for compare instructions ................................................................... 3-18 3-10 integer exception register bit descriptions .......................................................................... 3-18 3-11 machine state register bit descriptio ns ................................................................................ 3-20 3-12 floating-point excepti on mode bits ...................................................................................... 3-2 2 3-13 uses of spr g0?sprg3 ........................................................................................................ .3-24 3-14 processor version register bit descriptions.......................................................................... 3-25 3-15 eie, eid, and nr i registers ............................................................................................... 3 -25 3-16 fpecr bit desc riptions ..................................................................................................... .... 3-26 3-17 instruction se t summary .................................................................................................... .... 3-28 3-18 rcpu exception classes ..................................................................................................... ... 3-35 3-19 exception vector offset tabl e ............................................................................................. .3-36 3-20 instruction latency and blockage .......................................................................................... 3 -39 3-21 floating-point exception mode encoding ............................................................................. 3-44 tables tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 lxiv freescale semiconductor 3-22 settings caused by reset .................................................................................................. ..... 3-45 3-23 register settings fo llowing an nmi ....................................................................................... 3- 45 3-24 machine check exception processor actions ........................................................................ 3-47 3-25 register settings following a machine check exception ...................................................... 3-47 3-26 register settings follow ing external interrupt ...................................................................... 3-49 3-27 register settings for alignment exception ........................................................................... 3-50 3-28 register settings follow ing program exception.................................................................... 3-52 3-29 register settings following a floa ting-point unavailable exception ................................... 3-52 3-30 register settings following a decrementer exception ......................................................... 3-53 3-31 register settings following a system call ex ception ........................................................... 3-54 3-32 register settings follow ing a trace exception....................................................................... 3-55 3-33 register settings following floa ting-point assist exceptions ............................................... 3-55 3-34 register settings following a software emulation exception................................................ 3-56 3-35 register settings following an instruction protecti on exception ........................................... 3-57 3-36 register settings fo llowing a data protection error exception ............................................ 3-59 3-37 register setti ngs following a debug ex ception .................................................................... 3-60 3-38 register settings for da ta breakpoint match ......................................................................... 3-60 4-1 exception addres ses mapping ................................................................................................. 4-9 4-2 exception relocation page offset .......................................................................................... 4- 10 4-3 bbc sprs.................................................................................................................... ........... 4-17 4-4 bbcmcr field desc riptions ................................................................................................ 4- 19 4-5 mi_rba[0:3] registers bit descriptions.............................................................................. 4-21 4-6 mi_ra[0:3] registers bit descriptio ns ................................................................................ 4-22 4-7 region size programming possible values............................................................................ 4-23 4-8 mi_gra field de scriptions.................................................................................................. 4-24 4-9 eibadr external interrupt relocation table base address re gister bit descriptions ...... 4-25 5-1 usiu addres s map............................................................................................................ ....... 5-3 5-2 usiu special-purpos e register s .............................................................................................. 5-7 5-3 hex address format for spr cycles ....................................................................................... 5-7 6-1 usiu pin multiplex ing control............................................................................................... .6-4 6-2 sgpio confi guration ......................................................................................................... ...... 6-7 6-3 priority of interrupt sources ?regular operat ion.................................................................. 6-10 6-4 priority of interrupt sources ?enhanced operation .............................................................. 6-12 6-5 interrupt latency estimation for three t ypical cases ........................................................... 6-16 6-6 decrementer time-o ut periods .............................................................................................. 6- 18 6-7 siumcr bit desc riptions .................................................................................................... .6-25 6-8 debug pins conf iguration .................................................................................................... .. 6-27 6-9 general pins c onfiguratio n .................................................................................................. .. 6-27 6-10 single-chip select field pin configuration ........................................................................... 6-27 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxv 6-11 multi-level reservation cont rol pin configur ation .............................................................. 6-28 6-12 immr bit de scriptions ..................................................................................................... .... 6-29 6-13 emcr bit desc riptions ..................................................................................................... .... 6-30 6-14 siu interrupt controller ? bit acronym defi nitions.............................................................. 6-31 6-15 sypcr bit de scriptions.................................................................................................... .... 6-38 6-16 swsr bit de scriptions ..................................................................................................... .... 6-39 6-17 tesr bit desc riptions..................................................................................................... ...... 6-39 6-18 tbscr bit de scriptions.................................................................................................... .... 6-42 6-19 rtcsc bit de scriptions.................................................................................................... .... 6-43 6-20 piscr bit de scriptions .................................................................................................... ..... 6-44 6-21 pitc bit de scriptions ..................................................................................................... ....... 6-45 6-22 pit bit descriptions ...................................................................................................... ........ 6-45 6-23 sgpiodt1 bit descriptions ................................................................................................. 6-46 6-24 sgpiodt2 bit descriptions ................................................................................................. 6-47 6-25 sgpiocr bit de scriptions .................................................................................................. .6-48 6-26 data directi on control..................................................................................................... ....... 6-48 7-1 reset action taken for ea ch reset cause ............................................................................... 7-4 7-2 reset configuration word and data corruption/coherency.................................................... 7-4 7-3 reset status register bit descriptions ..................................................................................... 7 -5 7-4 reset configurat ion options ................................................................................................. ... 7-7 7-5 rcw bit desc riptions ........................................................................................................ .... 7-11 8-1 reset clocks source configuration .......................................................................................... 8 -9 8-2 tmbclk divi sions ............................................................................................................ ... 8-10 8-3 status of cloc k source...................................................................................................... ...... 8-16 8-4 power mode control bit settings .......................................................................................... 8- 17 8-5 power mode de scriptions .................................................................................................... .. 8-17 8-6 power mode wake-u p operation ......................................................................................... 8-18 8-7 power suppl ies .............................................................................................................. ......... 8-21 8-8 kapwr registers and key register s.................................................................................... 8-26 8-9 sccr bit desc riptions ....................................................................................................... .... 8-30 8-10 com and cqds bits functionality ....................................................................................... 8-33 8-11 plprcr bit de scriptions ................................................................................................... .. 8-34 8-12 colir bit de scriptions .................................................................................................... .... 8-36 8-13 vsrmcr bit de scriptions ................................................................................................... .8-37 9-1 mpc561/mpc563 biu signals................................................................................................ 9-4 9-2 data bus requirements fo r read cycles............................................................................... 9-31 9-3 data bus contents fo r write cycles....................................................................................... 9-3 2 9-4 priority between internal and extern al masters over external bus ....................................... 9-36 9-5 4 word burst lengt h and order ............................................................................................. 9- 38 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 lxvi freescale semiconductor 9-6 burst/tsize encoding ....................................................................................................... 9 -38 9-7 address type pins ........................................................................................................... ....... 9-39 9-8 address types de finition .................................................................................................... ... 9-39 9-9 termination signals protocol ................................................................................................ .9-49 10-1 timing requirements for reduced setup time ..................................................................... 10-6 10-2 timing attributes summary ................................................................................................. 1 0-11 10-3 programming rules for timing strobes ............................................................................... 10-22 10-4 write enable/byte enable signals function ........................................................................ 10-24 10-5 boot bank fields values after hard reset .......................................................................... 10-28 10-6 memory controller a ddress map.. ....................................................................................... 10-31 10-7 mstat bit desc riptions.................................................................................................... . 10-32 10-8 br0?br3 bit de scriptions .................................................................................................. 10-33 10-9 brx[v] reset value ........................................................................................................ .... 10-34 10-10 or0?or3 bit de scriptions ................................................................................................. 10-35 10-11 dmbr bit desc riptions..................................................................................................... ... 10-36 10-12 dmor bit desc riptions ..................................................................................................... .. 10-38 11-1 dmpu regist ers ............................................................................................................. ........ 11-6 11-2 reservation s noop support .................................................................................................. .. 11-9 11-3 l2u_mcr lshow modes ................................................................................................. 11-10 11-4 l2u show cycle s upport chart .... ....................................................................................... 11-1 2 11-5 l2u (ppc) regist er decode................................................................................................. 1 1-12 11-6 hex address for spr cycles ............................................................................................... 11 -13 11-7 l2u_mcr bit desc riptions ................................................................................................ 11 -14 11-8 l2u_rbax bit de scriptions............................................................................................... 11 -15 11-9 l2u_rax bit desc riptions ................................................................................................. 1 1-15 11-10 l2u_gra bit de scriptions................................................................................................. 11-16 12-1 stop and hspeed bit functionality.................................................................................... 12-2 12-2 bus cycles and system clock cycles .................................................................................... 12-3 12-3 ilbs signal func tionality .................................................................................................. .... 12-5 12-4 irqmux functi onality ....................................................................................................... ... 12-5 12-5 uimb interface re gister map ................................................................................................ 12-6 12-6 umcr bit desc riptions...................................................................................................... .... 12-8 12-7 uipend bit desc riptions.................................................................................................... ... 12-9 13-1 qadc64e_a addr ess map ................................................................................................... 13- 3 13-2 qadc64e_b addr ess map.................................................................................................... 13 -4 13-3 multiplexed analog input channels....................................................................................... 13- 7 13-4 analog input channels ...................................................................................................... ..... 13-7 13-5 qadcmcr bit desc riptions ................................................................................................. 13 -8 13-6 qadc64e bus error response..... ....................................................................................... 13-11 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxvii 13-7 qadcint bit desc riptions ................................................................................................. 13 -12 13-8 portqa, portqb bit descriptions .................................................................................. 13-14 13-9 qacr0 bit desc riptions ..................................................................................................... . 13-15 13-10 qacr1 bit desc riptions .................................................................................................... .. 13-16 13-11 queue 1 operat ing modes ................................................................................................... . 13-16 13-12 qacr2 bit desc riptions .................................................................................................... .. 13-18 13-13 queue 2 operat ing modes ................................................................................................... . 13-19 13-14 qasr0 bit desc riptions.................................................................................................... ... 13-21 13-15 pause response............................................................................................................ ......... 13-25 13-16 queue status .............................................................................................................. ........... 13-25 13-17 qasr1 bit desc riptions.................................................................................................... ... 13-27 13-18 ccw bit desc riptions ...................................................................................................... .... 13-30 13-19 non-multiplexed channel assign ments and signal designations....................................... 13-31 13-20 multiplexed channel assignments and signal designations ............................................... 13-32 13-21 qadc64e clock progr ammability ...................................................................................... 13-50 13-22 trigger events............................................................................................................ ........... 13-54 13-23 status bits ............................................................................................................... .............. 13-55 13-24 external circuit settling time to 1/2 lsb (10-bit conversions) ....................................... 13-75 13-25 error resulting from input leakage (io ff)......................................................................... 13-76 14-1 qadc64e_a addr ess map ................................................................................................... 14- 3 14-2 qadc64e_b addr ess map.................................................................................................... 14 -4 14-3 multiplexed analog input channels....................................................................................... 14- 6 14-4 analog input channels ...................................................................................................... ..... 14-7 14-5 qadcmcr bit desc riptions ................................................................................................. 14 -8 14-6 qadc64e bus error response..... ....................................................................................... 14-11 14-7 qadcint bit desc riptions ................................................................................................. 14 -12 14-8 portqa, portqb bit descriptions .................................................................................. 14-13 14-9 qacr0 bit desc riptions ..................................................................................................... . 14-15 14-10 prescaler f sysclk divide-by values.................................................................................... 14-15 14-11 qacr1 bit desc riptions .................................................................................................... .. 14-17 14-12 queue 1 operat ing modes ................................................................................................... . 14-17 14-13 qacr2 bit desc riptions .................................................................................................... .. 14-19 14-14 queue 2 operat ing modes ................................................................................................... . 14-20 14-15 qasr0 bit desc riptions.................................................................................................... ... 14-22 14-16 pause response............................................................................................................ ......... 14-26 14-17 queue status .............................................................................................................. ........... 14-26 14-18 qasr1 bit desc riptions.................................................................................................... ... 14-28 14-19 ccw bit desc riptions ...................................................................................................... .... 14-31 14-20 qadc64e_a multiplexed channel assi gnments and signal designations ....................... 14-32 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 lxviii freescale semiconductor 14-21 qadc64e_b multiplexed channel assi gnments and signal designations........................ 14-33 14-22 qadc64e clock progr ammability ...................................................................................... 14-50 14-23 trigger events............................................................................................................ ........... 14-53 14-24 status bits ............................................................................................................... .............. 14-54 14-25 external circuit sett ling time to 1/2 lsb (10- bit conversions) ........................................ 14-73 14-26 error resulting from input leakage (ioff)........................................................................ 14-74 15-1 qsmcm register map ......................................................................................................... .. 15-4 15-2 qsmcm global registers..................................................................................................... . 15-6 15-3 interrupt levels........................................................................................................... ............ 15-7 15-4 qsmcmmcr bit desc riptions..... ......................................................................................... 15-9 15-5 qdsci_il bit de scriptions.................................................................................................. .. 15-9 15-6 qspi_il bit descriptions ................................................................................................... .. 15-10 15-7 qsmcm pin control registers ..... ....................................................................................... 15-1 0 15-8 effect of ddrqs on qspi pin function.............................................................................. 15-11 15-9 qsmcm pin f unctions ........................................................................................................ 15-12 15-10 pqspar bit de scriptions ................................................................................................... . 15-13 15-11 ddrqs bit desc riptions .................................................................................................... .. 15-14 15-12 qspi regist er map ......................................................................................................... ...... 15-16 15-13 spcr0 bit de scriptions................................................................................................... .... 15-18 15-14 bits per transfer ......................................................................................................... .......... 15-18 15-15 spcr1 bit desc riptions.................................................................................................... .... 15-19 15-16 spcr2 bit de scriptions................................................................................................... .... 15-20 15-17 spcr3 bit de scriptions................................................................................................... .... 15-21 15-18 spsr bit desc riptions .................................................................................................... ..... 15-22 15-19 command ram bit de scriptions. ....................................................................................... 15-24 15-20 qspi pin f unctions........................ ................................................................................ ....... 15-25 15-21 example sck frequencies with a 40-mhz imb3 clock..................................................... 15-35 15-22 pcs enhanced f unctionality ................................................................................................ 15-37 15-23 sci regi sters ............................................................................................................. ........... 15-45 15-24 sccxr0 bit de scriptions ................................................................................................... .. 15-46 15-25 sccxr1 bit de scriptions .................................................................................................. .. 15-47 15-26 scxsr bit de scriptions................................................................................................... .... 15-49 15-27 scxdr bit de scriptions ................................................................................................... ... 15-51 15-28 sci pin f unctions ......................................................................................................... ........ 15-51 15-29 serial frame formats...................................................................................................... ...... 15-52 15-30 examples of scix baud rates.............................................................................................. 1 5-53 15-31 effect of parity check ing on data si ze ................................................................................ 15-5 3 15-32 qsci1cr bit de scriptions .................................................................................................. . 15-60 15-33 qsci1sr bit de scriptions .................................................................................................. . 15-61 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxix 16-1 common extended/standard format frames ........................................................................ 16-4 16-2 message buffer codes fo r receive buff ers............................................................................ 16-5 16-3 message buffer codes fo r transmit buff ers .......................................................................... 16-5 16-4 extended format frames ..................................................................................................... ... 16-6 16-5 standard format frames ..................................................................................................... .... 16-6 16-6 receive mask regist er bit values ......................................................................................... 16 -8 16-7 mask examples for normal /extended messages .................................................................. 16-8 16-8 example system clock, can bit ra te, and s-clock fr equencies ........................................ 16-9 16-9 interrupt levels........................................................................................................... .......... 16-20 16-10 toucan regist er map ....................................................................................................... .. 16-21 16-11 canmcr bit desc riptions .................................................................................................. 1 6-25 16-12 canicr bit de scriptions .................................................................................................. . 16-27 16-13 canctrl0 bit de scriptions............................................................................................... 16 -28 16-14 rx mode[1:0] conf iguration .............................................................................................. 16 -28 16-15 transmit signal c onfiguration ............................................................................................. 16-28 16-16 canctrl1 bit de scriptions............................................................................................... 16 -29 16-17 presdiv bit de scriptions................................................................................................. . 16-30 16-18 canctrl2 bit de scriptions.............................................................................................. 16 -30 16-19 timer bit desc riptions .................................................................................................... ... 16-31 16-20 rxgmskhi, rxgmsklo bi t descriptions...................................................................... 16-32 16-21 rx14mskhi, rx14msklo fi eld descriptions ................................................................ 16-32 16-22 rx15mskhi, rx15msklo fi eld descriptions ................................................................ 16-33 16-23 estat bit de scriptions ................................................................................................... ... 16-34 16-24 transmit bit error status ................................................................................................. ..... 16-35 16-25 fault confinement state encoding ....................................................................................... 16- 35 16-26 imask bit desc riptions .................................................................................................... .. 16-36 16-27 iflag bit de scriptions ................................................................................................... .... 16-36 16-28 rxectr, txectr bi t descriptions ................................................................................. 16-36 17-1 mios14 configuration description ....................................................................................... 17-6 17-2 mios14 i/o ports ........................................................................................................... ...... 17-13 17-3 mios14tpcr bit desc riptions .... ....................................................................................... 17-14 17-4 mios14vnr bit desc riptions ...... ....................................................................................... 17-1 5 17-5 mios14mcr bit desc riptions ............................................................................................ 17-15 17-6 mcpsm register a ddress map .... ....................................................................................... 17-17 17-7 mcpsmscr bit descri ptions ............................................................................................ 17-18 17-8 clock prescale r setting .................................................................................................... ..... 17-18 17-9 mmcsm addres s map ........................................................................................................ 17 -22 17-10 mmcsmcnt bit desc riptions..... ....................................................................................... 17-23 17-11 mmcsmml bit desc riptions....... ....................................................................................... 17-2 4 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 lxx freescale semiconductor 17-12 mmcsmscr bit desc riptions ..... ....................................................................................... 17-25 17-13 mmcsmcnt edge se nsitivity............................................................................................ 17-25 17-14 mmcsmcnt clock signal ................................................................................................. 17-2 5 17-15 prescaler values......................................................................................................... .......... 17-26 17-16 mdasm modes of op eration .............................................................................................. 17-2 9 17-17 mdasm pwm example output frequencies/resolutions at f sys = 40 mhz.................... 17-38 17-18 mdasm addres s map ......................................................................................................... 17-39 17-19 mdasmar bit desc riptions............................................................................................... 17- 42 17-20 mdasmbr bit desc riptions ............................................................................................... 17- 43 17-21 mdasmscr bit desc riptions............................................................................................. 17-4 4 17-22 mdasm mode selects........................................................................................................ . 17-45 17-23 mdasm counter bus selection ... ....................................................................................... 17-46 17-24 pwm pulse/frequency ranges (in hz) us ing /1 or /256 option (40 mhz) ........................ 17-52 17-25 mpwmsm addre ss map ..................................................................................................... 17- 55 17-26 mpwmperr bit desc riptions ..... ....................................................................................... 17-57 17-27 mpwmpulr bit desc riptions ..... ....................................................................................... 17-58 17-28 mpwmcntr bit desc riptions..... ....................................................................................... 17-58 17-29 mpwmscr bit desc riptions............................................................................................... 17- 59 17-30 pwmsm output signal pola rity selectio n .......................................................................... 17-59 17-31 prescaler values.......................................................................................................... .......... 17-60 17-32 mpiosm i/o signal function .............................................................................................. 17 -61 17-33 mpiosmdr bit de scriptions .............................................................................................. 17- 63 17-34 mpiosmddr bit desc riptions .... ....................................................................................... 17-63 17-35 mios14sr0 bit de scription ................................................................................................ 1 7-66 17-36 mios14er0 bit de scriptions .............................................................................................. 17 -66 17-37 mios14pr0 bit de scriptions .............................................................................................. 17 -67 17-38 mios14sr1 bit de scriptions .............................................................................................. 17 -67 17-39 mios14er1 bit de scriptions .............................................................................................. 17 -68 17-40 mios14rpr1 bit de scriptions............................................................................................ 17- 68 17-41 mbism interrupt regist ers address map............................................................................ 17-69 17-42 mios14lvl0 bit de scriptions............................................................................................ 17- 70 17-43 mios14lvl1 bit de scriptions............................................................................................ 17- 70 18-1 ppm memory map ............................................................................................................. .... 18-2 18-2 ppmmcr bit desc riptions .................................................................................................. 18 -11 18-3 ppmpcr bit desc riptions.................................................................................................... 18-12 18-4 samp[0:2] bit settings ..................................................................................................... ... 18-13 18-5 ppmpcr[cm] and ppmpcr[str] bit operation.............................................................. 18-15 18-6 configuration register (tx a nd rx) channel se ttings ....................................................... 18-17 18-7 short_reg bit desc riptions ............................................................................................ 18-20 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxi 18-8 short_reg[sh_tcan] bit settings ............................................................................... 18-20 18-9 short_reg[sh_tpu] bit settings .................................................................................. 18-21 18-10 short_ch_reg bit descriptions..................................................................................... 18-23 18-11 examples of the sh ort_ch bits ....................................................................................... 18-23 18-12 scale_tclk fre quencies ................................................................................................. 18- 24 18-13 scale_tclk_reg bit descriptions ................................................................................ 18-24 19-1 tpu memory map............................................................................................................. ..... 19-1 19-2 enhanced tcr1 prescale r divide valu es .............................................................................. 19-6 19-3 tcr1 prescale r values ...................................................................................................... ..... 19-6 19-4 tcr2 counter cl ock source .................................................................................................. 19-7 19-5 tcr2 prescaler control ..................................................................................................... ..... 19-8 19-6 tpu3 register map .......................................................................................................... ...... 19-8 19-7 tpumcr bit desc ription .................................................................................................... 1 9-11 19-8 dscr bit desc riptions ...................................................................................................... ... 19-12 19-9 dssr bit desc riptions ...................................................................................................... ... 19-14 19-10 ticr bit desc ription...................................................................................................... ...... 19-15 19-11 cier bit desc riptions ..................................................................................................... ..... 19-15 19-12 cfsr n bit descriptions........................................................................................................ 19-16 19-13 hsqr n bit descripti ons....................................................................................................... 19-17 19-14 hssrn bit desc riptions .................................................................................................... ... 19-18 19-15 cpr n bit descriptio n ........................................................................................................... 19-1 8 19-16 channel priorities ........................................................................................................ ......... 19-18 19-17 cisr bit desc riptions ..................................................................................................... ..... 19-19 19-18 tpumcr2 bit desc riptions ................................................................................................. 1 9-19 19-19 entry table ba nk location................................................................................................. .. 19-20 19-20 system clock frequency/minimum guaranteed detect ed pulse......................................... 19-20 19-21 tpumcr3 bit desc riptions ................................................................................................. 1 9-21 19-22 siutst bit de scriptions ................................................................................................... ... 19-22 19-23 registers used for fa ctory test only .................................................................................. 19-2 2 19-24 parameter ram addre ss offset map .................................................................................. 19-23 20-1 dptram regist er map ........................................................................................................ . 20-3 20-2 dptmcr bit se ttings ........................................................................................................ .... 20-4 20-3 rambar bit settings .................. ...................................................................................... ... 20-5 21-1 uc3f external inte rface signa ls ............................................................................................ 21-4 21-2 uc3f register progr amming model ...................................................................................... 21-5 21-3 uc3fmcr bit de scriptions ................................................................................................... 21-6 21-4 uc3fmcre bit desc riptions ................................................................................................ 21 -9 21-5 uc3fctl bit desc riptions .................................................................................................. 2 1-11 21-6 rcw bit desc riptions ....................................................................................................... ... 21-17 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxii 21-7 program interlock stat e descriptions ................................................................................... 21-2 3 21-8 erase interlock stat e descriptions ........................................................................................ 2 1-27 21-9 censorship states .......................................................................................................... ........ 21-30 21-10 censorship modes and ce nsorship status ............................................................................ 21-31 22-1 priorities of ov erlay regions .............................................................................................. . 22-12 22-2 calram control re gisters ................................................................................................ 22- 13 22-3 crammcr bit desc riptions............................................................................................... 22-1 4 22-4 crammcr privilege bit assignment for 8-kbyte array blocks ...................................... 22-15 22-5 cram_rbax bit desc riptions .... ....................................................................................... 22-16 22-6 rgn_size encoding .......................................................................................................... . 22-16 22-7 cramovlcr bit desc riptions ... ....................................................................................... 22-17 23-1 vf pins instruct ion encodings .............................................................................................. . 23-3 23-2 vf pins queue flush encodings ............................................................................................ 23 -3 23-3 vfls pin en codings ......................................................................................................... ..... 23-4 23-4 detecting the trace bu ffer start point ................................................................................... 23 -6 23-5 fetch show cycl es contro l .................................................................................................. .. 23-7 23-6 instruction watchpoints pr ogramming options ................................................................... 23-15 23-7 load/store data events ..................................................................................................... ... 23-16 23-8 load/store watchpoints pr ogramming opti ons................................................................... 23-17 23-9 check stop state a nd debug mode ...................................................................................... 23-27 23-10 trap enable data shifted into de velopment port shif t register ......................................... 23-34 23-11 debug port command shifted into de velopment port shif t register ................................. 23-34 23-12 status / data shifted out of de velopment port shift register............................................. 23-35 23-13 debug instructions / data shifted into development port shift register ............................ 23-36 23-14 development support pr ogramming mode l......................................................................... 23-39 23-15 development support registers read access prot ection .................................................... 23-40 23-16 development support registers write access prot ection ................................................... 23-41 23-17 cmpa-cmpd bit desc riptions .... ....................................................................................... 23-41 23-18 ecr bit desc riptions...................................................................................................... ...... 23-42 23-19 der bit desc riptions ...................................................................................................... ..... 23-43 23-20 breakpoint counter a value and control register (counta).......................................... 23-45 23-21 breakpoint counter b value and control register (countb) ......................................... 23-46 23-22 cmpe?cmpf bit desc riptions..... ....................................................................................... 23-4 6 23-23 cmpg-cmph bit desc riptions .... ....................................................................................... 23-47 23-24 lctrl1 bit de scriptions................................................................................................... .. 23-47 23-25 lctrl2 bit de scriptions................................................................................................... .. 23-49 23-26 ictrl bit desc riptions.................................................................................................... .... 23-51 23-27 isct_ser bit de scriptions ................................................................................................. 23-52 23-28 bar bit desc riptions ...................................................................................................... ..... 23-53 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxiii 24-1 public messages............................................................................................................ .......... 24-5 24-2 vendor-defined messages.................................................................................................... .. 24-5 24-3 terms and de finitions ...................................................................................................... ...... 24-6 24-4 otr bit desc riptions ....................................................................................................... ...... 24-9 24-5 tool-mapped regi ster space................................................................................................. . 24-9 24-6 did bit desc riptions ....................................................................................................... ..... 24-10 24-7 dc bit descri ptions........................................................................................................ ...... 24-11 24-8 rcpu development access modes ..................................................................................... 24-11 24-9 mc bit descri ptions ........................................................................................................ ..... 24-12 24-10 uba bit desc riptions ...................................................................................................... ..... 24-13 24-11 rwa read/write access bit descriptions .......................................................................... 24-14 24-12 udi bit desc riptions ...................................................................................................... ...... 24-16 24-13 read access status ........................................................................................................ ....... 24-16 24-14 write access status ....................................................................................................... ....... 24-16 24-15 dta 1 and 2 bit de scriptions ........................................................................................... 24- 17 24-16 data trace values......................................................................................................... ........ 24-18 24-17 description of re adi signals ............................................................................................. 2 4-21 24-18 msei/mseo pr otocol ........................................................................................................ .. 24-23 24-19 public message s supported ................................................................................................. . 24-24 24-20 error message codes ....................................................................................................... ..... 24-27 24-21 vendor-defined messa ges supported .................................................................................. 24-27 24-22 message field sizes , ............................................................................................................. 24-29 24-23 indirect bran ch message ................................................................................................... ... 24-33 24-24 direct branch message ..................................................................................................... .... 24-33 24-25 readi reset configur ation options ................................................................................... 24-34 24-26 bit pointer format ........................................................................................................ ........ 24-39 24-27 program trace correction due to a mispredicted branch ................................................... 24-40 24-28 program trace correction du e to an exception................................................................... 24-41 24-29 resource codes............................................................................................................ ......... 24-46 24-30 special l-bus ca se handling ............................................................................................... 24-56 24-31 throughput comparison for fpm and rpm mdo/mdi configurations ............................ 24-68 24-32 watchpoint source......................................................................................................... ....... 24-73 24-33 development port acces s: dsdi field ................................................................................ 24-84 24-34 development port acces s: dsdo field............................................................................... 24-84 24-35 power management mech anism overview .......................................................................... 24-86 25-1 mpc561 boundary scan bi t definition ................................................................................. 25-5 25-2 mpc563 boundary scan bi t definition ............................................................................... 25-17 25-3 instruction d ecoding....................................................................................................... ...... 25-30 a-1 ictrl bit desc riptions...................................................................................................... ... a-17 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxiv a-2 isct_ser bit desc riptions .................................................................................................. a -18 a-3 dccr0-dccr15 field descriptions .................................................................................... a-20 a-4 instruction layout encoding ................................................................................................. a-21 b-1 spr (special pur pose register s) ............................................................................................. .b-2 b-2 uc3f flash array............................................................................................................ .........b-4 b-3 decram sram array........................................................................................................... b-4 b-4 bbc (burst buffer co ntroller module)....................................................................................b-4 b-5 usiu (unified system interface unit) .....................................................................................b-5 b-6 cdr3 flash control regist ers eeprom (uc3f)...................................................................b-9 b-7 dptram control re gisters...................................................................................................b -10 b-8 dptram memory arrays ................................................... ..................................................b-1 0 b-9 time processor unit 3 a a nd b (tpu3 a and b) ..................................................................b-10 b-10 qadc64e a and b (queued anal og-to-digital converter)..................................................b-14 b-11 qsmcm (queued serial mu lti-channel m odule) .................................................................b-16 b-12 peripheral pin multiple xing (ppm) module...........................................................................b-17 b-13 mios14 (modular input/o utput subsystem) .........................................................................b-18 b-14 toucan a, b and c (can 2.0b controller) ........................................................................b-26 b-15 uimb (u-bus to imb bus interface).....................................................................................b-31 b-16 calram control registers ..................................................................................................b -31 b-17 calram array ............................................................................................................... ......b-32 b-18 readi module re gisters ..................................................................................................... ..b-32 c-1 external components value for di fferent crystals (q1) ........................................................c-4 c-2 iramstby regulator opera ting specificati ons ....................................................................c-8 d-1 bank 0 and bank 1 functions ................................................................................................. .d-2 d-2 qom bit en coding ............................................................................................................ ...... d-5 d-3 siop function valid chan_ control options ..................................................................... d-56 d-4 siop state timing ......................... .................................................................................. ...... d-58 e-1 memory access times using different buse s.........................................................................e-1 e-2 instruction timing examples for different bu ses....................................................................e-2 f-1 absolute maximum ratings (vss = 0v) ................................................................................. f-1 f-2 thermal charac teristics ..................................................................................................... ....... f-3 f-3 esd protec tion .............................................................................................................. ........... f-6 f-4 dc electrical char acteristics ............................................................................................... ..... f-7 f-5 oscillator and pll.......................................................................................................... ........ f-11 f-6 array program and erase characteristics ............................................................................... f-12 f-7 censor cell program and er ase characteris tics................................................................. f-12 f-8 flash modul e life........................................................................................................... ........ f-12 f-9 power supply pi n groups..................................................................................................... .. f-13 f-10 bus operati on timing ....................................................................................................... ..... f-20 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxv f-12 debug port timing .......................................................................................................... ....... f-43 f-11 interrupt timing........................................................................................................... ........... f-43 f-13 readi ac electrical characteristics..................................................................................... f-4 5 f-14 reset ti ming ............................................................................................................... ........ f-47 f-15 jtag timing ................................................................................................................ .......... f-50 f-16 qadc64e conversion ch aracteristics .................................................................................. f-54 f-17 qspi timing ................................................................................................................ ........... f-56 f-18 qsci timing................................................................................................................ ........... f-57 f-19 gpio timing ................................................................................................................ .......... f-60 f-20 tpu3 timing ................................................................................................................ .......... f-61 f-21 toucan ti ming.............................................................................................................. ....... f-62 f-22 ppm timing................................................................................................................. ........... f-62 f-23 mcpsm timing char acteristics............................................................................................. f- 64 f-24 mpwmsm timing char acteristics ........................................................................................ f-64 f-25 mmcsm timing charac teristics .. ......................................................................................... f-67 f-26 mdasm timing charact eristics............................................................................................ f-6 9 f-27 mpiosm timing charac teristics .. ......................................................................................... f-7 1 f-28 mpc561/mpc563 signal name s and pin names .................................................................. f-73 g-1 absolute maximum ratings (vss = 0v) ................................................................................ g-1 g-2 thermal charac teristics ..................................................................................................... ...... g-3 g-3 esd protec tion .............................................................................................................. .......... g-6 g-4 dc electrical char acteristics ............................................................................................... .... g-7 g-5 oscillator and pll.......................................................................................................... ....... g-10 g-6 array program and erase characteristics .............................................................................. g-11 g-7 censor cell program and er ase characteris tics................................................................ g-11 g-8 flash modul e life........................................................................................................... ....... g-12 g-9 power supply pi n groups..................................................................................................... .g-12 g-10 bus operati on timing ....................................................................................................... .... g-20 g-11 interrupt timing........................................................................................................... .......... g-40 g-12 debug port timing .......................................................................................................... ...... g-41 g-13 readi ac electrical characteristic s.................................................................................... g-43 g-14 reset ti ming ............................................................................................................... ....... g-44 g-15 jtag timing ................................................................................................................ ......... g-47 g-16 qadc64e conversion ch aracteristics ................................................................................. g-50 g-17 qspi timing ................................................................................................................ .......... g-52 g-18 qsci timing................................................................................................................ .......... g-53 g-19 gpio timing ................................................................................................................ ......... g-56 g-20 tpu3 timing ................................................................................................................ ......... g-57 g-21 toucan timing.............................................................................................................. ...... g-58 tables table number title page number mpc561/mpc563 reference manual, rev. 1.2 lxxvi freescale semiconductor g-22 ppm timing................................................................................................................. .......... g-58 g-23 mcpsm timing charact eristics............................................................................................ g-6 0 g-24 mpwmsm timing characteristics ....................................................................................... g-60 g-25 mmcsm timing charac teristics .. ........................................................................................ g-62 g-26 mdasm timing charact eristics... ........................................................................................ g-64 g-27 mpiosm timing charac teristics .. ........................................................................................ g-67 g-28 mpc561/mpc563 signal name s and pin names ................................................................. g-68 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxvii about this book this manual describes the capabilities, operati on, and function of the freescale mpc561/mpc563 microcontrollers. the documentation follows the modul ar construction of the devices in the mpc500 family product line. each microcontroller in the mpc500 family has a comprehensive reference manual that provides sufficient information for normal ope ration of the device. the reference manual is supplemented by module-specific re ference manuals that provide de tailed informat ion about module operation and applications. where info rmation in this manual varies from information in other references, this manual takes precedence. refer to suggested reading for further information. unless otherwise noted, references to the mpc561 and mpc563 also apply to their code compressed counterparts, the mpc562 and mpc564, respective ly. any functional differences between the mpc561/mpc563 and mpc562/mpc564 are noted. mpc562/mpc564-specific information is located in appendix a, ?mpc562/mpc564 compression features .? audience this manual is intended for system software and hardware developers and applications programmers who want to develop products for the mpc561/mpc563. it is assumed that the reader understands operating systems and microprocessor and microcontroller system design. organization following is a summary and br ief description of the major sections of this manual: ? chapter 1, ?overview ,? provides an overview of the mpc 561/mpc563 microcont roller, including a block diagram showing the major modular com ponents, a features lis t, and a summary of differences between the mpc561/mpc563 and the mpc555. ? chapter 2, ?signal descriptions ,? describes the mpc561/mpc563 microcontroller?s external signals. ? chapter 3, ?central processing unit ,? describes the risc processo r (rcpu) used in the mpc500 family of microcontrollers. ? chapter 4, ?burst buffer controller 2 module ,? describes the three main functional parts: the bus interface unit (biu), the instru ction memory protection unit (imp u), and the instruction code decompressor unit (icdu). ? chapter 5, ?unified system in terface unit (usiu) overview .? the unified system interface unit (usiu) of the mpc561/mpc563 consists of seve ral functional modules that control system start-up, system initia lization and operation, system protect ion, and the external system bus. ? chapter 6, ?system configuration and protection .? the mpc561/mpc563 incorporates many system functions that norm ally must be provided in external circuits. in a ddition, it is designed to mpc561/mpc563 reference manual, rev. 1.2 lxxviii freescale semiconductor provide maximum system safeguard s against hardware and software faults. this chapter provides a detailed explanation of this functionality. ? chapter 7, ?reset .? this section describes the mpc561/ mpc563 reset sources, operation, control, and status. ? chapter 8, ?clocks and power control ,? describes the main timing a nd power control reference for the mpc561/mpc563. ? chapter 9, ?external bus interface ,? describes the functionality of the mpc561/mpc563 external bus. ? chapter 10, ?memory controller ,? generates interface signals to support a glueless interface to external memory and peripheral devices. ? chapter 11, ?l-bus to u-bus interface (l2u) ,? describes the interface between the load/store bus (l-bus) and the unified bus (u-bus). the l2u mo dule includes the data memory protection unit (dmpu), which provides protecti on for data memory accesses. ? chapter 12, ?u-bus to imb3 bus interface (uimb) .? the u-bus to imb3 bus interface (uimb) structure is used to connect the cpu internal uni fied bus (u-bus) to the intermodule bus 3 (imb3). it controls bus communication be tween the u-bus and the imb3. ? chapter 13, ?qadc64e legacy mode operation .? the two queued analog- to-digital converter (qadc) modules on mpc561/mpc563 devices are 10-bit, unipolar, successive approximation converters. the modules can be c onfigured to operate in one of two modes, legacy mode (mpc555 compatible) and enhanced mode. this chapter desc ribes how the modules op erate in legacy mode, which is the default mode of operation. ? chapter 14, ?qadc64e enhanced mode operation .? the two queued analog- to-digital converter (qadc) modules on the mpc561/mp c563 devices are 10 -bit, unipolar, succe ssive approximation converters. the modules can be configured to ope rate in one of two modes, legacy mode (for mpc555 compatibility) and enhanced mode. this chapter describes how the module operates in enhanced mode. ? chapter 15, ?queued serial multi-channel module .? the mpc561/mpc563 contains one queued serial multi-channel module (q smcm) which provides three seri al communication interfaces: the queued serial peripheral interface (qspi) and two serial communi cations interfaces (sci/uart). this chapter describes th e functionality of each. ? chapter 16, ?can 2.0b controller module ,? describes the three c an 2.0b controller modules (toucan) implemented on the mpc561/mpc563. e ach toucan is a communication controller that implements the controlle r area network (can) protocol, an asynchronous communications protocol used in automotive and industrial control systems. it is a high spee d (one mbit/sec), short distance, priority based protocol that can run over a va riety of mediums. ? chapter 17, ?modular input/output subsystem (mios14) .? the modular i/o system (mios) consists of a library of flexible i/o and timer functions including i/o port, counters, input capture, output compare, pulse and period measurement, and pwm. becaus e the mios14 is composed of submodules, it is easily configurable for different kinds of applications. ? chapter 18, ?peripheral pin multiplexing (ppm) module .? the ppm functions as a parallel-to-serial communications module that reduces the number of signals required to connect mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxix the mpc561/mpc563 to an external device; and s horts internal signals to increase access to multiple functions multiplexe d on the same external signal. ? chapter 19, ?time processor unit 3 ,? describes an enhanced vers ion of the original tpu, an intelligent, semi-autonomous microcontro ller designed for timing control. ? chapter 20, ?dual-port tpu3 ram (dptram) .? the dual-port ram (dptram) module consists of a control register block and an 8-kbyte array of static ram that can be used either as microcode storage for the tpu3 or as gene ral-purpose memory. the mpc561/mpc563 has one dptram module that serves two tpu3 modules. ? chapter 21, ?cdr3 flash (uc3f) eeprom .? the mpc563 u-bus cdr3 (uc3f) eeprom module is designed for use in embe dded microcontroller applications targeted for high-speed read performance and high-densit y byte count requirements. ? chapter 22, ?calram operation .? this module provides the mpc561/mpc563 with a general purpose memory that may be read from or written to as either bytes, half-words, or words. in addition to this, a portion of th e calram, called the overlay regi on, can be used for calibration (i.e., overlaying portions of the u-bus fl ash with a portion of the calram array). ? chapter 23, ?development support ,? covers program flow tracking support, breakpoint/watchpoint support, de velopment system interface s upport (debug mode) and software monitor debugger support. these features allow efficiency in debugging systems based on the mpc561/mpc563. ? chapter 24, ?readi module .? the readi module provides deve lopment support capabilities for mcus in single chip mode, without requiring addr ess and data signals for internal visibility. ? chapter 25, ?ieee 1149.1-compliant interface (jtag) ,? describes mpc561/mpc563 compatibility with the ieee 1149.1 standard test access port and boundary scan architecture as well as any potential incompatibility issues. ? appendix a, ?mpc562/mpc564 compression features ,? includes information about code compression features of the mpc562/mpc564. ? appendix b, ?internal memory map ,? provides memory maps fo r the mpc561/mpc563 modules. ? appendix c, ?clock and board guidelines .? the mpc561/mpc563 built-in pll, oscillator, and other analog and sensitive circuits require that the board desi gn follow special layout guidelines to ensure proper operation of the chip clocks. this appendix describes how the clock supplies and external components should be connected in a system. ? appendix d, ?tpu3 rom functions ,? provides a brief descript ion of the pre-programmed functions in the tpu3. ? appendix e, ?memory access timing ,? lists memory access timings for internal and external memory combinations. ? appendix f, ?electrical characteristics ,? contains detailed inform ation on power considerations, dc/ac electrical character istics, and ac timing characteristi cs of the mpc561/mpc563 at the default 40 mhz and optional 56 mhz operating frequencies. ? appendix g, ?66-mhz elect rical characteristics ,? contains detailed information on power considerations, dc/ac electric al characteristics, and ac ti ming characteristics of the mpc561/mpc563 at the optional operating frequency of 66 mhz. this document also includes a regi ster index and comprehensive index. mpc561/mpc563 reference manual, rev. 1.2 lxxx freescale semiconductor suggested reading this section lists additional reading that provides bac kground for the information in this manual as well as general information about the powerpc ? architecture. also listed are doc uments that further complement this manual by providing in-depth functi onal descriptions of certain modules: ? qsm (queued serial module) reference manual (qsmrm/ad) ? tpu (time processor unit) documentati on (tpulitpak/d, including the tpurm/ad) ? rcpu (risc central processor unit) reference manual (rcpurm/ad) ? nexus standard specification rev 1.0 (ieee-isto 5001-1999) available at: http://www.nexus5001.org/ ? jtag ieee 1149.1 specification the following general documentatio n, available through morgan-kaufm ann publishers, 340 pine street, sixth floor, san francisco, ca, provides useful information a bout the powerpc architecture: ? the powerpc architecture: a specification for a new family of risc processors , second edition, by international business machines, inc. freescale documentation is availabl e from the sources listed on the b ack cover of this manual. a brief summary of available docum entation is listed below: ? programming environments manual for 32-bit impl ementations of the po werpc architecture (mpcfpe32b/ad)?describes resources de fined by the powerpc architecture. ? reference manuals?these books provide detail s about individual imple mentations and are intended for use with the programming environments manual. ? addenda/errata to reference manuals?because so me processors have follow-on parts, an addendum is provided that descri bes the additional features and functionality changes and are intended for use with the corresponding reference manuals. ? product briefs?each device has a product brief that provides an overview of its features. this document is roughly the equivalent to the overvie w chapter (chapter 1) of an implementation?s reference manual. ? the programmer?s reference guide for the powerpc architecture (mpcprg/d)?this concise reference includes the register su mmary, exception vectors, and th e powerpc isa instruction set. ? application notes?these short documents address specific design issues us eful to programmers and engineers working with freescale processors. additional literature is published as new processors become av ailable. for a current list of documentation, refer to http://www.motorola.com/semiconductors . conventions and nomenclature this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e zero, it is said to be clea red; when it ta kes a value of one, it is said to be set. mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxxi active_high names for signals that are active hi gh are shown in uppercase text. signals that are active high are referred to as asserted wh en they are high and negated when they are low. active_low names for signals that are active low are shown in uppercase text with an overbar. active-low signals are referred to as as serted (active) when they are low and negated when they are high. 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number italics italics indicate variable command parameters. book titles in text are also set in italics. reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, crammcr [dis] identifies the array disable bit (dis) within the calram m odule configuration register. a range of bits or signals is referred to by mnemonic a nd the numbers that define the range. for example, data[24:31] form the least significant byte of the data bus. x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an undefined numerical value ? not logical operator & and logical operator | or logical operator logic level one is the voltage that corresponds to boolean true (1) state. logic level zero is the voltage that corresponds to boolean false (0) state. to set a bit or bits means to establ ish logic level one on the bit or bits. to clear a bit or bits means to establ ish logic level zero on the bit or bits. lsb means least signifi cant bit or bits. msb means most significant bit or bits. asserted means that a signal is in active logic state. an activ e low signal changes from logic level one to logic level zero when assert ed, and an active high signal changes from logic level zero to logic level one. negated means that an asserted signal change s logic state. an active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. notational conventions table i contains notational c onventions that are used in this document. mpc561/mpc563 reference manual, rev. 1.2 lxxxii freescale semiconductor acronyms and abbreviations table ii contains acronyms and abbreviations that are used in this document. table i. notational conventions symbol function + addition ? subtraction (two?s complement) or negation * multiplication / division > greater < less = equal equal or greater equal or less not equal and | inclusive or (or) exclusive or (eor) not complementation : concatenation ? transferred ? exchanges sign bit; also used to show tolerance ? sign extension table ii. acronyms and abbreviated terms term meaning alu arithmetic logic unit bist built-in self test biu bus interface unit bpu branch processing unit bsdl boundary-scan description language cmos complementary metal-oxide semiconductor ea effective address ear external access register fifo first-in-first-out fpr floating-point register fpscr floating-point status and control register mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor lxxxiii references the sematech official dictionary and the reference guide to letter sy mbols for semiconductor devices by the jedec council/electronics i ndustries association are recommende d as references for terminology and symbology. fpu floating-point unit gpr general-purpose register iabr instruction address breakpoint register ieee institute for electrical and electronics engineers iu integer unit jtag joint test action group lifo last-in-first-out lr link register lsb least-significant bit lsu load/store unit msb most-significant bit msr machine state register nan not a number no-op no operation oea operating environment architecture pll phase-locked loop por power-on reset pvr processor version register risc reduced instruction set computing spr special-purpose register srr0 machine status save/restore register 0 srr1 machine status save/restore register 1 tb time base facility tbl time base lower register tbu time base upper register tlb translation lookaside buffer ttl transistor-to-transistor logic uimm unsigned immediate value uisa user instruction set architecture vea virtual environment architecture xer register used for indicating conditions such as carries and overflows for integer operations table ii. acronyms and a bbreviated terms (continued) term meaning mpc561/mpc563 reference manual, rev. 1.2 lxxxiv freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-1 chapter 1 overview this chapter provides an overview of the mpc561/ mpc563 microcontrollers, including a block diagram showing the major modular components and sections th at list the major features , and differences between the mpc561/mpc563 and the mpc555. the mpc5 61, mpc562, mpc563, and mpc564 devices are members of the freescale mpc500 risc microcontroller family. the parts herein will be referred to only as mpc561/mpc563 unless specific pa rts need to be referenced. 1.1 introduction the mpc561/mpc563 devices offe r the following features: ? powerpc isa-compliant 32-bit si ngle issue risc processor (rcpu) ? 64-bit floating-point unit (fpu) ? unified system integration unit (u siu) with a flexible memory controller and enhanced interrupt controller (eic) ? 512-kbytes of flash eeprom memory (available on the mpc563 only) ? typical endurance of 100,000 write/erase cycles @ 25oc ? typical data retenti on of 100 years @ 25oc ? 32-kbytes of static ram in one calram module, configured as ? 28-kbyte normal access only array ? 4-kbyte normal access or overlay a ccess array (eight 512-byte regions) ? two time processing units (tpu3) with one 8-kbyte dual port tpu ram (dptram) ? one 22-timer channel modul ar i/o system (mios14) ? three toucan modules (toucan) ? two enhanced queued analog systems (qadc64e) ? one queued serial multi-channel module (qsmcm), which contains one queued seri al peripheral interface (qspi) and two serial controller interfaces (sci/uart) ? one peripheral pin multiplexing module ( ppm) with a parallel to serial driver table 1-1. mpc56x family features device flash code compression mpc561 none not supported mpc562 none supported mpc563 512-kbytes flash not supported mpc564 512-kbytes flash supported overview mpc561/mpc563 reference manual, rev. 1.2 1-2 freescale semiconductor ? debug features: ? nexus debug port (class 3) ? background debug mode (bdm) ? ieee 1194.1-compliant interface (jtag) for boundary scan ? plastic ball grid array (pbga) packaging ? 388 ball pbga ? 27 mm x 27 mm body size ? 1.0 mm ball pitch ? default 40-, and optional 56-, and 66-mhz operation ? -40c?125c ? independent power supplies ? 5-v i/o (5.0 0.25 v) ? 2.6 0.1-v external bus with a 5-v tolerant i/o system ? 2.6 0.1-v internal logic ? <150 a on-chip voltage shunt regul ator for ram standby operation 1.2 block diagram figure 1-1 is a block diagram of the mpc561/mpc563. overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-3 figure 1-1. mpc561/mpc563 block diagram 1.3 key features the mpc561/mpc563 key features are e xplained in the following sections. 1.3.1 high-performance cpu system ? fully static design ? four major power saving modes ? on, doze, sleep, deep-sleep, and power-down e-bus l-bus u-bus imb3 usiu buffer burst l2u uimb qsmcm mios14 dptram 8-kbyte readi qadc64e jtag tpu3 qadc64e tpu3 32-kbyte calram 28-kbyte (no overlay) 4-kbyte overlay to u can to u can ppm sram to u can controller 512 kbytes flash rcpu mpc563 only overview mpc561/mpc563 reference manual, rev. 1.2 1-4 freescale semiconductor 1.3.1.1 risc mcu central processing unit (rcpu) ?powerpc ? -compliant 32-bit single issue core ? precise exception model ? 64-bit floating point unit (fpu) ? code compression suppor ted on mpc562/mpc564 ? reduces usage of internal/external flash memory (up to 50% for code) on the mpc564 ? reduces code size up to 50% ? extensive system development support ? on-chip watchpoints and breakpoints ? program flow tracking capability 1.3.1.2 unified system interface unit (usiu) ? system configuration a nd protection features: ? periodic-interrupt timer ? bus monitor ? software watchdog timer ? real-time clock (rtc) ? ppc decrementer ?time base ? clock synthesizer ? power management ? reset controller ? external bus interface that tole rates 5-v inputs, provides 2.6-v out puts, and supports multi-master designs ? enhanced interrupt controller that supports up to eight external and 40 internal interrupts, simplifies the interrupt structure, and decreases interrupt processing time ? usiu supports dual mapping to map part of one internal/external memory to another external memory ? external bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per memory cycle 1.3.1.3 burst buffer controller (bbc) module ? support for enhanced interrupt controller (eic) ? support for enhanced exception table relocation feature ? branch target buffer ? contains 2 kbytes of decompression ram (d ecram) for code compression. this ram may also be used as general-purpose ram when the code compression feature is not used. overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-5 1.3.1.4 flexible memory protection unit ? flexible memory protection units (mpu) in bbc and l2u ? default attributes available in one global entry ? attribute support for speculative accesses ? up to eight memory regions are supported, four for data and four for instructions 1.3.1.5 memory controller ? four flexible chip selects via memory controller ? 32-bit address and data buses ? 4-kbyte to one 16-mbyte (data) or 4- gbyte (instruction) region size support ? supports enhanced external burst ? up to eight-beat transfer bursts, two-clock minimum bus transactions ? use with sram, eprom, flash and other peripherals ? byte selects or write enables ? 32-bit address fully decodes internal a ddress space (4 gbytes) with bit masks ? four regions 1.3.1.6 512-kbytes of cdr3 flash eeprom memory (uc3f) ? mpc563/mpc564 only ? one 512-kbyte module ? page read mode (2/1/1/1 clock read access time) ? byte, half-word or word programmable. ? block (64 kbytes) erasable ? external 4.75- to 5.25-v vflash power supply for program, erase, and read operations ? security modes for software protection ? typical endurance of 100,000 writ e/erase cycles @ 25oc ? typical data retenti on of 100 years @ 25oc overview mpc561/mpc563 reference manual, rev. 1.2 1-6 freescale semiconductor 1.3.1.7 32-kbyte static ram (calram) ? composed of one 32-kbyte calram module ? 28-kbyte static ram ? 4-kbyte calibration (overlay) ra m feature that allows calibra tion of flash-based constants ? eight 512-byte overlay regions ? one clock fast accesses ? two clock cycle access option for power saving ? standby power supply (irams tby) for data retention 1.3.1.8 general purpose i/o support (gpio) ? 24 address signals and 32 data signals can be used for general-purpose i/o in single-chip mode ? 16 gpio in mios14 ? many peripheral signals can be used as gpio when not used as primary functions ? 5-v outputs with slew rate control 1.3.2 nexus debug port (class 3) ? compliant with class 3 of the ieee-isto 5001-1999 ? program trace via branch trace messaging (btm) ? data trace via data write messaging (dwm) and data read messaging (drm) ? ownership trace via ownership trace messaging (otm) ? run-time access to on-chip memory map and sp ecial-purpose registers (sprs) via the readi read/write access protocol ? watchpoint messaging via the auxiliary port ? 9 or 16 full-duplex auxiliary pin inte rface for medium and high visibility throughput ? all features configurable and co ntrollable via the auxiliary port ? supports the rcpu debug mode via the auxiliary port 1.3.3 integrated i/o system 1.3.3.1 two time processor units (tpu3) ? true 5 v i/o ? two time processing units (t pu3) with 16 channels each ? each tpu3 is a micro-coded timer subsystem ? 8 kbytes of dual port tpu ram (dptram) sh ared by two tpu3 modules for tpu micro-code 1.3.3.2 22-channel modular i/o system (mios14) ? six modulus counter sub-modules (mcsm) ? 10 double-action s ub-modules (dasm) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-7 ? 12 dedicated pwm sub-modules (pwmsm) ? one mios14 16-bit parallel port i/o sub-modules (mpiosm) 1.3.3.3 two enhanced queued an alog-to-digital converter modules (qadc64e) ? two queued analog-to-digital converter m odules (qadc64e_a, qadc64e _b) providing a total of 32 analog channels ? 16 analog input channels on each qadc 64e module using internal multiplexing ? directly supports up to four external multiplexers ? up to 41 total input channels on the two qadc64e modules with external multiplexing ? software configurable to operate in e nhanced or legacy (mpc555 compatible) mode ? unused analog channels can be us ed as digital input/output signals ? gpio on all channels in enhanced mode ? 10-bit a/d converter with internal sample/hold ? minimum conversion time of 7 s (with typical qclk frequency, 2 mhz) a nd +/- 2 bits accuracy ? two conversion command queues of variable length ? automated queue modes initiated by: ? external edge trigger ? software command ? periodic/interval timer within the qadc64e module, that can be assigned to both queue 1 and 2 ? external gated trigger (queue 1 only) ? 64 result registers ? output data is right- or le ft-justified, signed or unsigned. ? alternate reference input (altref), with c ontrol in the conversion command word (ccw) 1.3.3.4 three can 2.0b c ontroller (toucan) modules ? three toucan modules (touc an_a, toucan_b, toucan_c) ? each toucan provides the following features: ? 16 message buffers, programmable i/o modes ? maskable interrupts ? independent of the transmission medium (external transceiver is assumed) ? open network architecture , multi-master concept ? high immunity to emi ? short latency time for high-priority messages ? low-power sleep mode, with pr ogrammable wake-up on bus activity ? toucan_c pins are shared with mios14 gpio or qsmcm overview mpc561/mpc563 reference manual, rev. 1.2 1-8 freescale semiconductor 1.3.3.5 queued serial mult i-channel module (qsmcm) ? one queued serial module with one queued spi and two scis (qsmcm) ? qsmcm matches full mp c555 qsmcm functionality ? queued spi ? provides full-duplex communi cation port for peripheral e xpansion or inter-processor communication ? up to 32 preprogrammed tr ansfers, reducing overhead ? synchronous serial interface with baud rate of up to system clock / 4 ? four programmable peri pheral-selects signals: ? supports up to 16 devices with external decoding ? supports up to eight devices with internal decoding ? special wrap-around mode allows continuous sa mpling of a serial peripheral for efficient interfacing to serial analog- to-digital (a/d) converters ?sci ? uart mode provides nrz format a nd half- or full-duplex interface ? 16 register receive buffers and 16 re gister transmit buffers on one sci ? advanced error detection and optiona l parity generation and detection ? word-length programmable as eight or nine bits ? separate transmitter and receiver enab le bits, and double buffering of data ? wake-up functions allow the cpu to run uninterrupted until either a true idle line is detected, or a new address byte is received 1.3.3.6 peripheral pin multiplexing (ppm) ? synchronous serial interface between the microprocessor and an external device ? four internal parallel data source s can be multiplexed through the ppm ? tpu3_a: 16 channels ? tpu3_b: 16 channels ? mios14: 12 pwm channels, four mda channels ? internal gpio: 16 general-purpose inputs, 16 general-purpose outputs ? software configurable stream size ? software configurable clock (tclk) based on system clock ? software selectable clock m odes (spi mode and tdm mode) ? software selectable operation modes ? continuous mode ? start-transmit-receive (str) mode ? software configurable internal modules interconnect (shorting) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-9 1.4 mpc561/mpc563 optional features the following features of the mpc561/mpc563 are opt ional features and may not appear in certain configurations: ? 56- or 66-mhz operati on (40 mhz is default) ? code compression (availab le on mpc562 and mpc564 only) ? 512 kbytes flash (available on mpc563 and mpc564 only) 1.5 comparison of mpc561/mpc563 and mpc555 in table 1-2 , the mpc555 is used as a baseline to compare the high level differences from an early device offering in the mpc500 family to the mpc561/mpc563. table 1-2. differences between mpc555 and mpc561/mpc563 module mpc555 mpc561/mpc563 cpu core identical bbc basic enhanced code compression (classes scheme with 2 kbytes decram) code compression is available only on mpc562/mpc564. l2u identical sram 26 kbytes 32 kbytes calibration sram with overlay features flash 448-kbyte cmf (2 modules, 256-kbyte and 192-kbyte) 512-kbyte uc3f (1 module) on mpc563 only. no flash on mpc561 usiu basic enhanced interrupt controller jtag selectable by rcw selectable at poreset readi none new module (class 3 nexus ieee-isto 5001-1999) uimb identical qadc64e (2) (2) enhanced qsmcm (1) identical (1) mios mios1 mios14 4 extra pwmsm 4 extra mcsm overview mpc561/mpc563 reference manual, rev. 1.2 1-10 freescale semiconductor 1.6 additional mpc561/mpc563 differences ? the mpc561/mpc563 devices are very similar to the mpc555 with the following differences: ? up to 66 mhz operating frequency (refer to the applicable elec trical characteristics document for more information.) ? cdr3 technology ? two power supplies: 5.0-v i/o, 2.6-v ex ternal bus signals, 2.6-v internal logic ? new modules: readi, calram, ppm ? extra toucan module, additional 6 kbytes of sram on l-bus (32 kbytes total) with calram overlay features, extra 2 k bytes of dptram (8 kbytes total) ? qadc64e ? gpo on all channel signals in addition to gpi functions ? toucan, tpu3, qsmcm, uimb, core, l2u ? no changes ? bbc2 ? enhanced interrupt controller support ? enhanced exception relocation table ? branch target buffer ? 2 kbytes of decompression ram for code compression. this may also be used as general-purpose ram while not used for code compression. ? calram (with overlay features) ? new module ? overlay features allow calibra tion of flash-based constants ? uc3f (u-bus cdr3 flash module) on mpc563/mpc564 only ? 512 kbytes of non-volatile memory (nvm) ? designed for use in embedded microcontroller (mcu) applications targeted for high speed read performance and high de nsity byte count requirements ?readi ? new module ?usiu ? enhanced interrupt controller ? engclk default frequency toucan (2) identical (3) tpu3 (2) identical (2) dptram (6 kbytes) identical (8 kbytes) ppm ? new module table 1-2. differences between mpc555 and mpc561/mpc563 (continued) module mpc555 mpc561/mpc563 overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-11 ? readi support ? reduced data setup time ? enhanced external burst support ?mios14 ? four additional pwm channels ? four additional mcsm timers ?dptram (8 kbytes) ? no functional changes ? ppm (peripheral pin multiplexing) ? new module ? four-to-one multiplexing ? parallel-to-serial driver (spi and tdm) 1.7 sram keep-alive power behavior the iramstby pin provides keep-ali ve power to ram when the main power supply is shut down. the iramstby pin can be powered directly from a batter y using an internal shunt regulator or via a small battery for standby use. see figure 1-2 . figure 1-2. recommended connection diagram for iramstby while power is off, the iramst by supply powers the following: ? 32-kbyte calram ? 8-kbyte dptram module ? 2-kbyte bbc decram module note iramstby must always be supplied with at least 50 a for correct operation. 1.8 mpc561/mpc563 address map the internal memory map is organize d as a single 4-mbyte bl ock. the user can assign this block to one of eight locations by programming a regi ster in the usiu (immr[isb]). th e eight possible locations are the to iramstby pad r c to battery overview mpc561/mpc563 reference manual, rev. 1.2 1-12 freescale semiconductor first eight 4-mbyte memory blocks st arting with address 0x0000 0000 (refer to figure 1-3 ). the programmability of the internal memory map locati on allows the user to implement a multiple-chip system. figure 1-3. mpc561/mpc563 memory map the internal memory space is divided into the following sections. refer to figure 1-4 . ? flash memory (512-kbytes) ? calram static ram memory (32-kbytes) ? control registers and imb3 modules (64 kbytes) ? bbc control registers (16-kbytes) ? usiu and flash control registers (16-kbytes) ? uimb interface and imb3 modules (32-kbytes) ? calram/readi control registers (256-bytes) 0x0000 0000 0xffff ffff 0x0100 0000 0x00ff ffff 0x01ff ffff 0x00c0 0000 0x00bf ffff 0x0080 0000 0x007f ffff 0x0040 0000 0x003f ffff 0x01c0 0000 0x01bf ffff 0x0140 0000 0x013f ffff 0x0180 0000 0x017f ffff internal 4-mbyte memory block (can reside in one of eight locations) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 1-13 4-kbyte overlay section 0x30 7fff 0x2f ffff 0x30 0000 0x00 0000 0x38 0000 0x38 3fff 0x3f ffff 0x2f c000 0x2f bfff 0x30 8000 0x37 ffff 0x38 4000 0x07 ffff 0x3f 7fff 0x3f 8000 0x08 0000 0x38 00ff 0x38 0100 0x2f 8000 0x2f 7fff uc3f flash* 512 kbytes reserved for flash 2,605 kbytes bbc decram 2 kbytes usiu & flash control 16 kbytes uimb i/f & imb modules 32 kbytes reserved for imb 480 kbytes calram/ readi control 256 bytes reserved (l-bus control) 16 kbytes reserved (l-bus mem) 464 kbytes calram 32 kbytes 0x3f f000 0x30 0000 0x30 7fff dptram (8 kbytes) qsmcm (1 kbyte) mios14 (4 kbytes) toucan_a (1 kbyte) toucan_b (1 kbyte) uimb registers (128 bytes) tpu3_a (1 kbyte) tpu3_b (1 kbyte) qadc64e_a (1 kbyte) qadc64e_b (1 kbyte) dptram control (32 bytes) usiu control registers 0x2f c000 0x30 7900 0x30 7000 0x30 6000 0x30 5400 0x30 5000 0x30 4c00 0x30 4800 0x30 4400 0x30 4000 0x30 2000 0x30 7400 reserved (8160 bytes) reserved (2 kbytes) reserved (896 bytes) 0x30 7800 0x2f c800 0x30 7f80 toucan_c (1 kbyte) 0x30 5c00 ppm (64 bytes) 0x30 5c80 reserved (960 bytes) 0x30 0020 uc3f control registers* 0x2f 8800 reserved for bbc 0x2f a000 bbc control reserved 0x2fc80b note: flash is available only on the mpc563/mpc564. overview mpc561/mpc563 reference manual, rev. 1.2 1-14 freescale semiconductor figure 1-4. mpc561/mpc563 internal memory map 1.9 supporting documentation list this list contains references to curr ently available and planned documentation. ? mpc555 user?s manual (mpc555um/ad) ? rcpu reference manual (rcpurm/ad) ? nexus standard specificatio n (non-freescale documen t) available at: ht tp://www.nexus5001.org/ ? ieee 1149.1 specification (non-freescale document) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-1 chapter 2 signal descriptions this chapter describes the mpc561/mp c563 microcontroller?s external si gnals. it contains a description of individual signals, show s their behavior, shows whether the signal is an input or an output, and indicates signal multiplexing. note a bar over a signal name indicates that the signal is active-low?for example, ta (transfer acknowledge) . active-low signals are referred to as asserted (active) when they are low and negated when th ey are high. signals that are not active-low, such as addr[8:31] (address bus signals) and data[0:31] (data bus signals ) are referred to as assert ed when they are high and negated when they are low. refer to appendix f, ?electrical characteristics ,? and appendix g, ?66-mhz elect rical characteristics ,? for detailed electrical information for each signal. 2.1 signal groupings figure 2-1 illustrates the external signals of the mpc561/mpc563 groupe d by functional module. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-2 freescale semiconductor figure 2-1. mpc561/mpc563 signal groupings mpc561/563 24 32 2 1 1 1 1 1 1 1 1 1 cs [0:3] we [0:3] / be [0:3] / at[0:3] a_anw / a_pqb0 / a_an0 a_anx/ a_pqb1 / a_an1 4 4 1 1 a_anz / a_pqb3 / a_an3 a_pqb[4:7] / a_an[48:51] a_ma[0:2] / a_pqa[0:2] / a_an[52:54] 1 1 4 3 a_pqa[3:7] / a_an[55:59] 5 vrh 1 1 1 1 1 1 1 1 1 1 1 1 1 1 mdo4 / sgpioc0 / irq0 1 rsv / sgpioc1 / irq1 cr / sgpioc2 / mts / irq2 kr / retry / sgpioc3 / irq3 1 1 1 1 modck[2:3] / irq [6:7] modck1 / spgioc5 / irq5 2 1 frz / ptr / sgpioc6 lwp0 / irqout / sgpioc7 1 1 vf0 / lwp1 / bg vf1 / iwp2 / br 1 1 vf2 / iwp3 / bb vfls[0:1] / iwp[0:1] 1 2 1 1 1 1 3 1 1 1 1 1 1 3 1 hreset poreset / trst sreset a_any/ a_pqb2 / a_an2 pcs[6:7] / etrig[1:2] 2 1 1 system control 3 pins 1 altref vdda vssa qgpio[1:3] / pcs[1:3] qgpio5 / mosi qgpio6 / sck qgpo1 / txd1 c_cnrx0 / qgpi2 / rxd2 vrl mpio32b[7:9] / mpwm[5,20:21] mpio32b10 / ppm_tsync mpio32b5 / mdo5 bus interface 67 pins 1 1 1 5 3 5 1 1 1 jtag/bdm/readi 5 pins 1 1 1 mpwm0 / mdi1 mpwm[17:19] / mdo[3, 6:7] tck / dsck / mcki tdi / dsdi / mdi0 tdo / dsdo / mdo0 tms / evti jcomp / rsti sgpioa[8:31] / addr[8:31] sgpiod[0:31] / data[0:31] tsiz[0:1] wr / rd burst bdip ta tea oe texp / rstconf sts / bi ts interrupt development xtal extal xfc pull_sel clkout extclk engclk / buclk vddsyn vsssyn clocks and a_cntx0 a_cnrx0 b_cntx0 b_cnrx0 toucan epee b0epee vflash vddf vssf 1 1 uc3f flash eeprom 1 iramstby qadc64e_a qsmcm 11 pins 16 1 a_tpuch[0:15] 16 1 b_tpuch[0:15] b_t2clk / pcs4 mios14 tpu3 a and b chip selects write enable at2 / sgpioc4 / irq4 1 ss / qgpio0 / pcs0 controller 8 pins and debug 7 pins pll 8 pins 4 pins 4 pins 4 pins (plus 2 pins 5 pins mpio32b6 / mpwm4 / mdo6 qvddl nvddl vdd vss kapwr vddh global power supply 1 34 pins note: in cases where one multiplexed signal b_anw / b_pqb0 / b_an0 b_anx/ b_pqb1 / b_an1 1 1 b_anz / b_pqb3 / b_an3 b_pqb[4:7] / b_an[48:51] b_ma[0:2] / b_pqa[0:2] / b_an[52:54] 1 1 4 3 b_pqa[3:7] / b_an[55:59] 5 b_any/ b_pqb2 / b_an2 and qadc64e_b 1 mpwm1 / mdo2 1 mpwm2 / ppm_tx1 1 mpwm3 / ppm_rx1 1 mpwm16 1 mpio32b11 / c_cnrx0 1 mpio32b12 / c_cntx0 1 mpio32b13 / ppm_tclk 1 mpio32b14 / ppm_rx0 mpio32b15 / ppm_tx0 1 39 pins qgpio4 / miso 1 c_cntx0 /qgpo2 / txd2 1 qgpi1 / rxd1 34 pins 1 1 1 mpio32b2 / msei / vf2 mpio32b3 / mseo / vfls0 mpio32b0 / mdo1 / vf0 mpio32b1 / mcko / vf1 1 mpio32b4 / vfls1 1 mda[11:15] mda[27:31] configuration 1 pin a_t2clk / pcs5 multiplexed with mios and qsmcm) 1 the mpc561 has no flash eeprom is an input and another is an output, together they are shown as i/o. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-3 2.2 signal summary table 2-1 describes individual mpc561/mpc563 signals, grouped by functional module. table 2-1. mpc561/mpc563 signal descriptions signal name no. of signals type function after reset 1 description bus interface addr[8:31] / sgpioa[8:31] 24 i/o controlled by rcw[sc]. see ta b l e 6 - 1 0 . address bus [8:31]. specifies the physical address of the bus transaction. the address is driven onto the bus and kept valid until a transfer acknowledge is received from the slave. addr8 is the msb for this bus. i/o port sgpioa[8:31]. allows the signals to be used as general-purpose inputs/outputs. data[0:31] / sgpiod[0:31] 32 i/o controlled by rcw[sc]. see ta b l e 6 - 1 0 . data bus [0:31]. provides the general-purpose data path between the mpc561/mpc563 and all other devices. although the data path is a maximum of 32 bits wide, it can be sized to support 8-, 16-, or 32-bit transfers. data0 is the msb of the data bus. i/o port sgpiod[0:31]. allows the signals to be used as general-purpose inputs/outputs. tsiz[0:1] 2 i/o tsiz[0:1] transfer size [0:1]. indicates the size of the requested data transfer in the current bus cycle. rd/wr 1i/ord/wr read/write. indicates the direction of the data transfer for a transaction. a logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. burst 1 i/o burst burst indicator. driven by the bus master to indicate that the currently initiated tr ansaction is a burst. bdip 1 i/o bdip burst data in progress. indicate s to the slave that there is a data beat following the current data beat. ts 1i/ots transfer start. indicates th e start of a bus cycle that transfers data to/from a slave device. this signal is driven by the master only when it has gained ownership of the bus. every master should negate this signal before relinquishing the bus. this is an active-low signal and needs an external pull-up resistor to ensure proper operation and meet signal timing specifications. ta 1i/ota transfer acknowledge. this line indicates that the slave device addressed in the current transaction has accepted the data transferred by the master (write) or has driven the data bus with valid data (read). the slave device negates the ta signal after the end of the transaction. the slave device will then immediately three-state the ta signal to prevent contention on the line in case a new transfer that addresses another slave device(s) is initiated. this signal is an active-low signal and needs an external pull-up resistor to ensure proper operation and conform to signal timing specifications. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-4 freescale semiconductor tea 1i/otea transfer error acknowledge. this signal indicates that a bus error occurred in the current transaction. the mpc561/mpc563 asserts this signal when the bus monitor does not detect a bus cycle te rmination within 2040 clock cycles. the assertion of tea causes the termination of the current bus cycle, regardless of the state of ta . an external pull-up device is required to negate tea quickly, before a second error is detected. that is, the signal must be pulled up wi thin one clock cycle of the time it was three-stated by the mpc561/mpc563. oe 1ooe output enable. this output lin e is asserted when a read access is initiated by the mpc561/mpc563 to an external slave controlled by the memory controller?s gpcm. rstconf / texp 1 i rstconf until reset negates. reset configuration. this input line is sampled by the mpc561/mpc563 during the assertion of the hreset signal in order to sample the reset configuration. if the line is asserted, the configuration mode is sampled from the external data bus. when this line is negated, the configuration mode adopted by the mpc561/mpc563 is either the internal default or read from the internal flash (mpc563 only). o timer expired. this output line reflects the status of plprcr[texps] in the usiu. this bit indicates an expired timer value. bi / sts 1 i/o controlled by rcw[dbgc]. see ta b l e 6 - 8 . burst inhibit. this bidirectional, active-low, three-state signal indicates that the slave device addressed in the current burst transaction is not able to support burst transfers. when the mpc561/mpc563 drives out the signal for a specific transaction, it asserts or negates bi according to the value specified in the appropriate control registers. the signal is negated after the end of the transaction and then is immediately three-stated. this is an active-low signal and needs an external pull-up resistor to ensure proper operation and signal timing specifications. o special transfer start. this output signal is driven by the mpc561/mpc563 to indicate the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-5 interrupt controller irq0 / sgpioc0 / mdo4 1 i mdo4 if the nexus (readi) port is enabled, irq0 otherwise. see section 2.5 . interrupt request 0. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. irq0 is a non-maskable interrupt (nmi). i/o port sgpioc0. allows the signal to be used as a general-purpose input/output. o readi message data out. message data out (mdo4) are output signals used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight signals are implemented. irq1 / rsv / sgpioc1 1 i irq 1 interrupt request 1. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. o reservation. this signal is used, together with the address bus, to indicate that the internal core initiated a transfer as a result of a stwcx or a lwarx instruction. i/o port sgpioc1. allows the signal to be used as a general-purpose input/output. irq2 / cr / sgpioc2 / mts 2 1 i irq2 interrupt request 2. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. i cancel reservation. instructs the mpc561/mpc563 to clear its reservation because some other master has touched its reserved space. an external bus snooper asserts this signal. i/o port sgpioc2. allows the signal to be used as a general-purpose input/output. o memory transfer start. this is the transfer start signal from the mpc561?s memory contro ller that allows external memory access by an external bus master. irq3 / kr / retry / sgpioc3 1 i irq3 interrupt request 3. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. i/o kill reservation. in case of a bus cycle initiated by a stwcx instruction issued by the rcpu core to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. i/o retry. indicates to a master that the cycle is terminated but should be repeated. as an input, it is driven by the external slave to retry a cycle. i/o port sgpioc3. allows the signal to be used as a general-purpose input/output. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-6 freescale semiconductor irq4 / at2 / sgpioc4 1 i irq4 interrupt request 4. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. o address type 2. a bit from the address type bus which indicates one of the 16 ?address types? to which the address applies. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) is asserted. i/o port sgpioc4. allows the signal to be used as a general-purpose input/output. irq5 / modck1 / spgioc5 1 i modck1 until reset negates, then irq5 interrupt request 5. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. i mode clock 1. sampled at the negation of poreset /trst in order to configure the phase-locked loop (pll)/clock mode of operation. i/o port sgpioc5. allows the signal to be used as a general-purpose input/output. irq [6:7] / modck[2:3] 2 i modck[2:3] until reset negates, then irq[6:7] interrupt request [6:7]. one of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the rcpu. i mode clock [2:3]. sampled at the negation of poreset /trst in order to configure the pll/clock mode of operation. cs [0:3] 4 o cs [0:3] chip select [0:3]. these output signals enable peripheral or memory devices at programmed addresses if defined appropriately in the memory controller. cs0 or cs3 can be configured to be the global chip select for the boot device. we [0:3] / be [0:3] / at[0:3] 4 o controlled by rcw[atwc]. see ta b l e 6 - 8 . write enable[0:3]/byte enable[0:3]. this output signal is asserted when a write access to an external slave controlled by the memory controller is initiated by the mpc561/mpc563. it can be optional ly asserted on all read and write accesses. see webs bit definition in table 10-8 . we n/be n are asserted when data lanes shown below contain valid data to be stored by the slave device. ? we0 /be0 is asserted if the data lane data[0:7] contains valid data to be stored by the slave device. we1 /be1 is asserted if the data lane data[8:15] contains valid data to be stored by the slave device. we2 /be2 is asserted if the data lane data[16:23] contains valid data to be stored by the slave device. we3 /be3 is asserted if the data lane data[24:31] contains valid data to be stored by the slave device. o address type [0:3]. indicates one of the 16 address types to which the address applies. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) is asserted. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-7 system control poreset / trst 1 i poreset / trst power-on reset. this signal should be activated as a result of a voltage failure on the keep-alive power supply. the signal has a glitch detector to ensure that low spikes of less than 20 ns are rejected . the internal poreset / trst signal is asserted only if poreset / trst is asserted for more than 100 ns. see chapter 7, ?reset ,? for more details on timing. i test reset. this input provides asynchronous reset to the test logic (jtag). hreset 1 i/o hreset hard reset. the reset controlle r can detect an external assertion of hreset only if it occurs while the mpc561/mpc563 is not asserting reset. after negation of hreset or sreset is detected, a 16- cycle period is taken before testing the presence of an external reset. the internal hreset signal is considered asserted only when assertion lasts for more than 100 ns. to meet external timing requirements, an external pull-up device is required to negate hreset . see chapter 7, ?reset ,? for more details on timing. sreset 1 i/o sreset soft reset. the reset controller can detect an external assertion of sreset only if it occurs while the mpc561/mpc563 is not asserting reset. after negation of hreset or sreset is detected, a 16- cycle period is taken before testing the presence of an external soft reset. to meet external timing requirements, an external pull-up device is required to negate sreset . see chapter 7, ?reset ,? for more details on timing. development and debug sgpioc6 / frz / ptr 1 i/o ptr port sgpioc6. allows the signals to be used as general-purpose inputs/outputs. o freeze. indicates that the rcpu is in debug stopped mode. o program trace. indicates an instruction fetch is taking place (for program flow tracking). sgpioc7 / irqout / lwp0 1 i/o lwp0 port sgpioc7. allows the signal to be used as general-purpose inputs/outputs. o interrupt out. indicates that an interrupt has been requested to all external devices. o load/store watchpoint 0. this output signal reports the detection of a data watchpoint in the program flow executed by the rcpu. see chapter 23, ?development support ,? fo r more details. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-8 freescale semiconductor bg / vf0 / lwp1 1 i/o controlled by rcw[dbgc]. see ta b l e 6 - 8 . bus grant. indicates ex ternal bus status. bg is asserted low when the external bus arbiter grants ownership of the external bus to a specific master. this is an active-low signal and needs an external pull-up resistor to ensure proper operation and meet signal timing specifications. o visible instruction queue flush status 0. this output signal together with vf1 and vf2 is output by the mpc561/mpc563 when program instruction flow tracking is required. vfs report the number of instructions flushed from the instruction queue in the internal core. see chapter 23, ?development support ,? for more details. o load/store watchpoint 1. this output signal reports the detection of a data watchpoint in the program flow executed by the rcpu. br / vf1 / iwp2 1 i/o controlled by rcw[dbgc]. see ta b l e 6 - 8 . bus request. indicates that the external bus has been requested for external cycle. this is an active-low signal and needs an external pull-up resistor to ensure proper operation and meet signal timing specifications. o visible instruction queue flush status 1. this output signal together with vf0 and vf2 is output by the mpc561/mpc563 when program instruction flow tracking is required. vfs report the number of instructions flushed from the instruction queue in the internal core. see chapter 23, ?development support ,? for more details. o instruction watchpoint 2. th is output signal reports the detection of an instruction watc hpoint in the program flow executed by the rcpu. bb / vf2 / iwp3 1 i/o controlled by rcw[dbgc]. see ta b l e 6 - 8 bus busy. indicates that the master is using the external bus. bb is an active-low signal and needs an external pull-up resistor to ensure proper operation and signal timing specifications. o visible instruction queue flush status 2. this output signal together with vf0 and vf1 is output by the mpc561/mpc563 when a program instructions flow tracking is required. vfs report the number of instructions flushed from the instruction queue in the internal core. o instruction watchpoint 3. this output signal reports the detection of an instruction watc hpoint in the program flow executed by the internal core. iwp[0:1] / vfls[0:1] 2 o controlled by rcw[dbgc]. see ta b l e 6 - 8 . instruction watchpoint [0:1]. these output signals report the detection of an instruction watc hpoint in the program flow executed by the rcpu. o visible history buffer flush status [0:1]. these signals are output by the mpc561/mpc563 to enable program instruction flow tracking. they report the number of instructions flushed from the history buffer in the rcpu. see chapter 23, ?development support ,? for details. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-9 jtag/bdm/readi tms / evti 1 i tms unless the nexus (readi) port is enabled, then evti . see section 2.5 . test mode select. this input controls test mode operations for on-board test logic (jtag). i evti . event in (evti ) is level sensitive when configured for breakpoint generation, otherw ise it is edge sensitive. tdi / dsdi / mdi0 1 i dsdi unless the nexus (readi) port (mdi0) or jtag mode (tdi) is enabled. see section 2.5 . test data in. this input is used for serial test instructions and test data for on-board test logic (jtag). i development serial data input. this input signal is the data in for the debug port interface. see chapter 23, ?development support ,? for details. i message data in. mdi0 is a nexus input signal used for downloading configuration information, writes to user resources, and so forth. internal latching of mdi occurs on the rising edge of mcki. tck / dsck / mcki 1 i dsck unless the nexus (readi) port (mcki) or jtag mode (tck) is enabled. see section 2.5 . test clock. this input provides a clock for on-board test logic (jtag). i development serial clock. this input signal is the clock for the debug port interface. see chapter 23, ?development support ,? for details. i message clock in. this input line is the input clock to the readi module for the nexus message clock input. tdo / dsdo / mdo0 1 o dsdo unless the nexus (readi) port (mdo0) or jtag mode (tdo) is enabled. see section 2.5 . test data out. this output is us ed for serial test instructions and test data for on-board test logic (jtag). o development serial data output. this output signal is the data-out line of the debug port interface. see chapter 23, ?development support ,? for details. o readi message data out. message data out: mdo0 is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. jcomp / rsti 1isee section 2.5 . jtag compliancy. this sign al enables the ieee1149.1 jtag compliant circuitry in the mpc561/mpc563. 0jtag disabled 1 jtag enabled irsti . reset input for the nexus port. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-10 freescale semiconductor clocks and pll xtal 1 o xtal xtal. this output signal is one of the connections to an external crystal for the internal oscillator circuitry. extal 1 i extal extal. this signal is one of the connections to an external crystal for the internal oscillator circuitry. if extal is unused, it must be grounded. xfc 1 i xfc external filter capacitance. this input signal is the connection for an external capacitor filter for the pll circuitry. clkout 1 o clkout clock out. this output signal is the clock system frequency. the clkout drive strength can be configured to full strength, half strength, quarte r strength, or disabled. the drive strength is configured us ing the com[0:1] bits and cqds bits in the sccr register in the usiu. extclk 1 i extclk extclk. this is the external frequency source for the mpc561/mpc563. if extclk is unused, it must be grounded. engclk / buclk 1 o engclk (2.6 v) engclk. this is the engineering clock output. drive voltage can be configured to 2.6 v, 5 v (with slew-rate control), or disabled. the drive voltage is configured using the eeclk[0:1] bits in the sccr register in the siu. o buclk. when the mpc561/mpc563 is in limp mode, it is operating from a less precise on-chip ring oscillator to allow the system to continue mini mum functionality until the system clock is fixed. this backup clock can be seen externally if selected by the values of the eeclk[0:1] bits in the sccr register in the usiu. vddsyn 1 i vddsyn vddsyn. this is the power supply of the pll circuitry. vsssyn 1 i vsssyn vsssyn. this is the ground reference of the pll circuitry. configuration pull_sel 3 1 i pull_sel pull select. pull_sel determines whether the pull devices on the mios and tpu signals are pull-ups or pull-downs. when pull-ups are selected, the pull-ups are to 5.0 v except the following mios signals will be pulled to 2.6v: vf[0:2]/mpio32b[0:2], vfls[0:1]/mpio32b[3:4], and mdo[7:4]/mpio32b[7:10]. when th is pin is low, pull-downs are selected. toucan a_cntx0 1 o a_cntx0 toucan_a transmit data. this signal is the serial data output. a_cnrx0 1 i a_cnrx0 toucan_a receive data. this signal is the serial data input. b_cntx0 1 o b_cntx0 toucan_b transmit data. this signal is the serial data output. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-11 b_cnrx0 1 i b_cnrx0 toucan_b receive data. this signal is the serial data input. uc3f flash 4 epee 4 1i epee epee. this external program/ erase enable control signal externally controls the program or erase operations. when held low, program or erase o perations on the entire internal flash module are disabled. available in the mpc563 only. this signal is not connected on the mpc561. b0epee 4 1i b0epee b0epee. this control signal externally controls the program or erase operations on block 0 of the internal flash. when held low, program or erase operations on block 0 only are disabled. available in the mpc563 only. this signal is not connected on the mpc561. vflash 4 1i vflash vflash. flash supply voltage (5-v supply) used during all operations of the uc3f. available in the mpc563 only. this signal is not connected on the mpc561. vddf 4 1i vddf vddf. flash core voltage input (2.6-v supply). available in the mpc563 only. this signal should be connected to vdd, preferably directly to a 2.6v plane on the circuit board. this signal is not connected on the mpc561. vssf 4 1i vssf vssf. flash core ground refe rence. available in the mpc563 only. this signal is not connected on the mpc561. qadc64e_a and qadc64e_b etrig[1:2] / pcs[ 6:7] 2 i etrig[1:2] etrig[1:2]. thes e are the external trigger inputs to the qadc64e_a and qadc64e_b modules. etrig1 can be configured to be used by both qadc64e_a and qadc64e_b. likewise, etrig2 can be used by both qadc64e_b and qadc64e_a. the trigger input signals are associated with the scan queues. o pcs[6:7]. this signals provide qspi peripheral chip select when the enhanced pcs mode is selected. a_an0 / a_anw / a_pqb0 1 i a_an0 analog channel 0. internally multiplexed input-only analog channel. passed on as a separ ate signal to the qadc64e. i multiplexed analog input (a_anw). externally multiplexed analog input. i/o 5 port a_pqb0. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. a_an1 / a_anx/ a_pqb1 1 i a_an1 analog channel 1. internally multiplexed input-only analog channel. passed on as a separ ate signal to the qadc64e. i multiplexed analog input (a_anx). externally multiplexed analog input. i/o 5 port a_pqb1. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-12 freescale semiconductor a_an2 / a_any/ a_pqb2 1 i a_an2 analog channel 2. internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. i multiplexed analog input (a_any). externally multiplexed analog input. i/o 5 port a_pqb2. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. a_an3 / a_anz / a_pqb3 1 i a_an3 analog input 3. internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. i multiplexed analog input (a_anz). externally multiplexed analog input. i/o 5 port a_pqb 3. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. a_an[48:51] / a_pqb[4:7] 4 i an[48:51] analog input [48:51]. analog input channel. the input is passed on as a separate signal to the qadc64e. i/o 5 port a_pqb[4:7]. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. a_an[52:54] / a_ma[0:2] / a_pqa[0:2] 3 i a_an[52:54] analog input [52:54]. input-only. these inputs are passed on as separate signals to the qadc64e. i multiplexed address [0:2] for qadc64e module a. provides a three-bit multiplexed address output to the external multiplexer chip to allow select ion of one of the eight inputs. i/o port a_pqa[0:2]. this is a bidirectional general-purpose i/o. a_an[55:59] / a_pqa[3:7] 5 i a_an[55:59] analog input [55:59]. input-only. these inputs are passed on as separate signals to the qadc64e. i/o port a_pqa[3:7]. this is a bidirectional general-purpose i/o. b_an0 / b_anw / b_pqb0 1 i b_an0 analog channel 0. internally multiplexed input-only analog channel. passed on as a separ ate signal to the qadc64e. i multiplexed analog input (b_anw). externally multiplexed analog input. i/o port b_pqb0. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-13 b_an1 / b_anx/ b_pqb1 1 i b_an1 analog channel 1. internally multiplexed input-only analog channel. passed on as a separ ate signal to the qadc64e. i multiplexed analog input (b_anx). externally multiplexed analog input. i/o port b_pqb1. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. b_an2 / b_any/ b_pqb2 1 i b_an2 analog channel 2. internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. i multiplexed analog input (b_any). externally multiplexed analog input. i/o port b_pqb2. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. b_an3 / b_anz / b_pqb3 1 i b_an3 analog input 3. internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. i multiplexed analog input (b_anz). externally multiplexed analog input. i/o port b_pqb3. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. b_an[48:51] / b_pqb[4:7] 4 i b_an[48:51] analog input [48:51]. analog input channel. the input is passed on as a separate signal to the qadc64e. i/o port b_pqb[4:7]. this is a bidirectional general-purpose i/o if the qadc64e is configured in enhanced mode, otherwise it is an input only. b_an[52:54] / b_ma[0:2] / b_pqa[0:2] 3 i b_an[52:54] analog input [52:54]. these inputs are passed on as separate signals to the qadc64e. i multiplexed address [0:2] for qadc64e module a. provides a three-bit multiplexed address output to the external multiplexer chip to allow select ion of one of the eight inputs. i/o port b_pqa[0:2]. this is a bidirectional general-purpose i/o. b_an[55:59] / b_pqa[3:7] 5 i b_an[55:59] analog input [55:59]. t hese inputs are passed on as separate signals to the qadc64e. i/o port b_pqa[3:7]. this is a bidirectional general-purpose i/o. vrh 1 i vrh vrh. input signal for high reference voltage for the qadc64e_a and qadc64e_b modules. vrl 1 i vrl vrl. input signal for low reference voltage for the qadc64e_a and qadc64e_b modules. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-14 freescale semiconductor altref 1 i altref altref. input signal for alternate reference voltage for the qadc64e_a and qadc64e_b modules. vdda 1 i vdda vdda. power supply input to analog subsystems of the qadc64e_a and qadc64e_b modules. vssa 1 i vssa vssa. ground level for anal og subsystems of the qadc64e_a and qadc64e_b modules. qsmcm pcs0 / ss / qgpio0 1 i/o qgpio0 pcs0. this signal provides qspi peripheral chip select 0 for the qsmcm module. i/o ss . assertion of this bidirectional signal places the qspi in slave mode. i/o port qgpio0. when this signal is not needed for a qspi application it can be conf igured as a general-purpose input/output. pcs[1:3] / qgpio[1:3] 3 i/o qgpio[1:3] pcs[1:3]. these signals provide qspi peripheral chip selects for the qsmcm module. i/o port qgpio[1:3]. when these signals are not needed for qspi applications they can be configured as general-purpose input/outputs. miso / qgpio4 1 i/o qgpio4 master-in slave-out (miso). this bidirectional signal is the serial data input to the qspi in master mode, and serial data output from the qspi in slave mode. i/o port qgpio4. when this signal is not needed for a qspi application it can be conf igured as a general-purpose input/output. mosi / qgpio5 1 i/o qgpio5 master-out slave-in (mosi). this bidirectional signal is the serial data output from the qs pi in master mode and serial data input to the qspi in slave mode. i/o port qgpio5. when this signal is not needed for a qspi application it can be conf igured as a general-purpose input/output. sck / qgpio6 1 i/o qgpio6 sck. this bidirectional signal is the clock from the qspi in master mode or is the clock to the qspi in slave mode. i/o port qgpio6 for the qsmcm module. when this signal is not needed for a qspi application it can be configured as a general-purpose input/output. when the qspi is enabled for serial transmitting, the signal cannot function as a gpio. txd1 / qgpo1 1 o qgpo1 transmit data 1. this is the se rial data output from the sci1. o port qgpo 1. when these signals are not needed for sci applications, they can be configured as general-purpose outputs. when the transmit enable bit in the sci control register is set to a logic 1, these signals cannot function as general-purpose outputs. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-15 txd2 / qgpo2 / c_cntx0 6 1 o qgpo2 transmit data 2. this is the serial data output from the sci2 o port qgpo 2. when this signal is not needed for sci applications it can be configured as general-purpose output. when the transmit enable bit in the sci control register is set to a logic 1, this signal cannot function as a general-purpose output. o toucan transmit data. this signal is the serial data output for the toucan_c module. rxd1 / qgpi1 1 i qgpi1 receive data 1. this input signal is the serial data input to the sci. i port qgpi 1. when this signal is not needed for sci applications, it can be configured as a general-purpose input. when the receive enable bit in the sci control register is set to a logic 1, this signal cannot function as a general-purpose input. rxd2 / qgpi2 / c_cnrx0 6 1 i qgpi2 receive data 2. this input signal provides serial data input to the sci2. i port qgpi 2. when this signal is not needed for sci applications it can be conf igured as a general-purpose input. when the receive enable bit in the sci control register is set to a logic 1, this signal cannot function as a general-purpose input. i toucan receive data. this is the serial data input signal for the toucan_c module. mios14 mda[11:15, 27:31] 10 i/o mda[11:15, 27:31] double action. these 10 signals provide paths for two 16-bit input captures and two 16-bit output compares. clock and load inputs: mda11 can provide clock in puts to the modulus counter submodule, mmcsm6 mda12 can provide load inputs to the modulus counter submodule, mmcsm6 mda13 can provide clock inputs to mmcsm22 mda14 can provide load inputs to mmcsm22 mda27 can provide clock inputs to mmcsm23 mda28 can provide load inputs to mmcsm23 mda30 can provide clock inputs to mmcsm7 mda31 can provide load inputs to mmcsm7 mpwm0 / mdi1 1 i/o mpwm0 unless the nexus (readi) port is enabled, then mdi1. see section 2.5 . pulse width modulation 0. this signal provides variable pulse width outputs at a wide range of frequencies. i message data in. mdi1 is a nexus input signal used for downloading configuration information, writes to user resources, etc. internal latching of mdi will occur on rising edge of mcki. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-16 freescale semiconductor mpwm1 / mdo2 1 i/o mpwm1 unless the nexus (readi) port is enabled, then mdo2. see section 2.5 . pulse width modulation 1. this signal provides a variable pulse width output signal at a wide range of frequencies. o readi message data out. message data out (mdo2) is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on the rising edge of mcko. eight mdo signals are implemented. mpwm2 / ppm_tx1 1 i/o mpwm2 pulse width modulation 2. this signal provides a variable pulse width output signal at a wide range of frequencies. o ppmtx1. transmit data from ppm channel number 1. mpwm3 / ppm_rx1 1 i/o mpwm3 pulse width modulation 3. this signal provides a variable pulse width output signal at a wide range of frequencies. i ppmrx1. receive data to the ppm channel number 1. mpwm16 1 i/o mpwm16 pulse width modulation 16. this signal provides a variable pulse width output at a wide range of frequencies. clock input: mpwm16 can provide a clock input to modulus clock submodule, mmcsm8 mpwm17 / mdo3 1 i/o mpwm17 unless the nexus (readi) port is enabled. see section 2.5 . pulse width modulation 17. this signal provides variable pulse width outputs at a wide range of frequencies. load input: pwm17 can provid e a load input to modulus clock submodule, mmcsm8 o readi message data out. message data out (mdo3) is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. mpwm[18:19] / mdo[6:7] 2 i/o mpwm[18:19] pulse width modulation [18:19]. these signals provide variable pulse width output signals at a wide range of frequencies. clock and load input: mpwm18 can provide clock inputs to modulus counter submodule mmcsm24 mpwm19 can provide load inputs to modulus counter submodule mmcsm24 o readi message data out. me ssage data out (mdo[6:7]) are output signals used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-17 mpio32b0 / vf0 / mdo1 1 i/o mpio32b0 unless the nexus (readi) port is enabled, then mdo1. see section 2.5 . mios14 gpio 0. allows the signals to be used as general-purpose inputs/outputs. o visible instruction queue flus h status 0. these signals output by the mpc561/mpc563 when program instruction flow tracking is required. vf reports the number of instructions flushed from the instruction queue in the internal core. vf signals are also multiplexed with the development and debug signals vf0 / lwp1 / bg , vf1 / iwp2 / br , and vf2 / iwp3 / bb . o readi message data out. message data out (mdo1) is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. mpio32b1 / vf1 / mcko 1 i/o mpio32b1 unless the nexus (readi) port is enabled, then mcko. see section 2.5 . mios14 gpio 1. allows the signals to be used as general-purpose inputs/outputs. o visible instruction queue flus h status 1. these signals output by the mpc561/mpc563 when program instruction flow tracking is required. vf reports the number of instructions flushed from the instruction queue in the internal core. vf signals are also multiplexed with the development and debug signals vf0 / lwp1 / bg , vf1 / iwp2 / br , and vf2 / iwp3 / bb . o mcko. message clock-out (mcko) is a free-running output clock to development tools for timing of mdo and mseo signal functions. mcko is the same as the mpc561/mpc563 system clock. mpio32b2 / vf2 / msei 1 i/o mpio32b2 unless the nexus (readi) port is enabled, then msei . see section 2.5 . mios14 gpio 2. allows the signals to be used as general-purpose inputs/outputs. o visible instruction queue flus h status 2. these signals output by the mpc561/mpc563 when program instruction flow tracking is required. vf reports the number of instructions flushed from the instruction queue in the internal core. vf signals are also multiplexed with the development and debug signals vf0 / lwp1 / bg , vf1 / iwp2 / br , and vf2 / iwp3 / bb . i msei . message start/end input. the msei input is a nexus input signal that indicates when a message on the mdi signals has started, when a variable length packet has ended, and when the message has ended. internal latching of msei occurs on rising edge of mcki. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-18 freescale semiconductor mpio32b3 / vfls0 / mseo 2 i/o mpio32b3 unless the nexus (readi) port is enabled. see section 2.5 . mios14 gpio 3. allows the signal to be used as a general-purpose input/output. o visible history buffer flush status 0. this signal is output by the mpc561/mpc563 to allow program instruction flow tracking. it reports the number of instructions flushed from the history buffer in the rcpu. see chapter 23, ?development support ,? for details. o mseo . message start/end out (mseo ) is an output signal which indicates when a message on the mdo signals has started, when a variable length packet has ended, and when the message has ended. external latching of mseo occurs on rising edge of mcko. mpio32b4 / vfls1 1 i/o mpio32b4 mios14 gpio 4. allows the signal to be used as a general-purpose input/output. o visible history buffer flush status 1. this signal is output by the mpc561/mpc563 to allow program instruction flow tracking. it reports the number of instructions flushed from the history buffer in the rcpu. see chapter 23, ?development support ,? for details. mpio32b5 / mdo5 1 i/o mpio32b5 unless the nexus (readi) port is enabled, then mdo5. see section 2.5 . mios14 gpio 5. allows the signal to be used as a general-purpose input/output. o readi message data out. message data out (mdo5) is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. mpio32b6 / mpwm4 / mdo6 1 i/o mpio32b6 unless the nexus (readi) port is enabled, then mdo6. see section 2.5 . mios14 gpio 6. allows the signal to be used as general-purpose input/output. i/o pulse width modulation 4. these signals provide variable pulse width outputs at a wide range of frequencies. o readi message data out. message data out (mdo6) is an output signal used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on rising edge of mcko. eight mdo signals are implemented. mpio32b[7:9] / mpwm[5, 20:21] 3 i/o mpio32b[7:9] mios14 gpio[7:9]. allows these signals to be used as general-purpose input/outputs. i/o pulse width modulation [5, 20:21]. these signals provide variable pulse width outputs at a wide range of frequencies. mpio32b10 / ppm_tsync 1 i/o mpio32b10 mios14 gpio 10. this function allows the signals to be used as general-purpose inputs/outputs. o ppm_tsync. synchronizes t he data between the ppm and peripheral devices. mpio32b11 / c_cnrx0 6 1 i/o mpio32b11 mios14 gpio 11. this function allows the signals to be used as general-purpose inputs/outputs. i toucan_c receive data. this is the serial data input signal for the toucan_c module. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-19 mpio32b12 / c_cntx0 6 1 i/o mpio32b12 mios14 gpio 12. this function allows the signals to be used as general-purpose inputs/outputs. o toucan_c transmit data. this is the serial data output signal for the toucan_c module. mpio32b13 / ppm_tclk 1 i/o mpio32b13 mios14 gpio 13. this function allows the signals to be used as general-purpose inputs/outputs. o ppm_tclk. ppm bus clock mpio32b14 / ppm_rx0 1 i/o mpio32b14 mios14 gpio 14. this function allows the signals to be used as general-purpose inputs/outputs. i ppm_rx0. receive data to the ppm channel number 0. mpio32b15 / ppm_tx0 1 i/o mpio32b15 mios14 gpio 15. this function allows the signals to be used as general-purpose inputs/outputs. o ppm_tx0. transmit data from ppm channel number 0. tpu a_tpuch[0:15] 16 i/o a_tpuch[0:15] provides tpu module a with 16 input/output programmable timed events. a_t2clk / pcs5 1 i/o a_t2clk this signal is used to clock or gate the timer count register 2 (tcr2) within the tpu module a. this signal is an output-only in special test mode. o pcs5. this signal provides qspi peripheral chip select when the enhanced pcs mode is selected. b_tpuch[0:15] 16 i/o b_tpuch[0:15] provides tpu module b with 16 input/output programmable timed events. b_t2clk / pcs4 1 i/o b_t2clk this signal is used to clock or gate the timer count register 2 (tcr2) within the tpu module b. this signal is an output-only in special test mode. o pcs4. this signal provides qspi peripheral chip select when the enhanced pcs mode is selected. global power nvddl 1 i nvddl nvddl. noisy 2.6-v voltage supply input. this signal supplies the final output stage of the 2.6-v pad output drivers. the nvddl and qvddl supplies should be connected to the same power supply in a user's system. qvddl 1 i qvddl qvddl. quiet 2.6-v voltage supply input. this signal supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-v pad output drivers. the nvddl and qvddl supplies should be connected to the same power supply in a user's system. vddh 1 i vddh vddh. 5-v voltage supply input. vdd 1 i vdd vdd. 2.6-v voltage supply input for internal logic. kapwr 1 i kapwr keep-alive power. 2.6-v voltage supply input for the oscillator and keep-alive registers. table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-20 freescale semiconductor 2.2.1 mpc561/mpc563 signal multiplexing table 2-2 describes the signal multiplexing that oc curs between differen t modules of the mpc561/mpc563. most of the signal functions are controlled by the pdmcr2 register. vss 1 i vss vss. zero supply/ground level for internal logic/external bus. iramstby 1 i iramstby sram keep-alive power. this is an input current source for an internal regulator that supplies voltage to all sram modules in standby mode. this pad connects through a voltage regulator and a voltage switch to the following modules: calram (32-kbyte sram), dptram (8-kbyte sram), bbc decram (2-kbyte vocabulary sram). 1 this is the function after poreset /trst and hreset . 2 this signal also included the mdo5 function on the k27s mask set of the mpc561. 3 this signal was eck on k27s mask set of mpc561. 4 only the mcp563/mpc564 have flash memory. 5 the input only applies in legacy mode. 6 c_cntx0 and c_cnrx0 can be shared eith er with the mios14 gpio pins (mpio 32b12, mpio32b11) or with the qsmcm sc12 pins (txd2 / qgpo2, rxd2 / qgpi2). the selection is made by the tcnc bits in the pdmcr2 register. refer to section 2.4, ?pad module configuration register (pdmcr2) .? table 2-2. mpc561/mpc563 signal sharing signal name module sharing c_cntx0/mpio32b12, c_cnrx0/mpio32b11 toucan shared with mios14 gpio txd2/qgpo2/c_cntx0 rxd2/qgpi2/c_cnrx0 toucan shared with qsmcm sci2 mpio32b5/mdo5 readi submodule shared with mios14 gpio mpio32b6/mpwm4, mpio32b7/mpwm5, mpio32b8/mpwm20, mpio32b9/mpwm21 mios14 pwm submodule shared with mios14 gpio vf0/mpio32b0/mdo1, vf1/mpio32b1/mcko, vf2/mpio32b2/msei, vfls0/mpio32b3/mseo debug pins shared with mios14 gpio and readi mpio32b13/ppm_tclk mpio32b14/ppm_rx0 mpio32b15/ppm_tx0 ppm submodule shared with mios14 gpio mpwm2/ppm_tx1 mpwm3/ppm_rx1 ppm submodule shared with mios14 pwm submodule table 2-1. mpc561/mpc563 signal descriptions (continued) signal name no. of signals type function after reset 1 description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-21 2.2.2 readi port signal sharing table 2-3 and table 2-4 show the signal functionality of the re adi signals when the nexus port is in reduced port mode and full port mode. . mpwm0/mdi1, mpwm1/mdo2, mpwm17/mdo3, mpwm[18:19]/mdo[6:7] readi submodule shared with mios14 pwm submodule b_t2clk/pcs4 a_t2clk/pcs5 tpu3 modules shared with qsmcm module. etrig1/pcs6 etrig2/pcs7 qadc64e modules shared with qsmcm module. table 2-3. reduced and full port mode pads pad name functionality in reduced port mode functionality when not in reduced port mode tdi/dsdi/mdi0 1 1 tdi in jtag mode, dsdi in bdm mode. mdi0 tdi/dsdi tdo/dsdo/mdo0 mdo0 tdo/dsdo 2 2 tdo in jtag mode, dsdo in bdm mode. vf0/mpio32b0/mdo1 m do1 vf0/mpio32b0 3 3 selected by the vf bit in the mios14tpcr. vf1/mpio32b1/mcko mcko vf1/mpio32b1 3 vf2/mpio32b2/msei msei vf2/mpio32b2 3 vfls0/mpio32b3/mseo mseo vfls0/mpio32b3 4 4 selected by the vfls bit in the mios14tpcr. table 2-4. full port only mode pads pad name functionality in full port mode functionality when not in full port mode mpwm0/mdi1 mdi1 mpwm0 mpwm1/mdo2 mdo2 mpwm1 mpwm17/mdo3 mdo3 mpwm17 irq0 /sgpioc0/mdo4 mdo4 irq0 /sgpioc0 mpio32b5/mdo5 mdo5 mpio32b5 mpio32b6 / mpwm4 / mdo6 mdo6 1 1 the mdo6 bit in the pdmcr2 register determines where the mdo6 signal is available. mpio32b6/mpwm4 mpwm18/mdo6 mdo6 1 mpwm18 mpwm19/mdo7 mdo7 mpwm19 table 2-2. mpc561/mpc563 signal sharing (continued) signal name module sharing signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-22 freescale semiconductor 2.3 pad module configurat ion register (pdmcr) bits in the pdmcr (which resi des in the siu memory map) c ontrol the slew rate and weak pull-up/pull-down charac teristics of some signals; refer to appendix f, ?electrical characteristics .? the poreset /trst signal resets all the pdmcr bits asynchronously. table 2-5 contains bit descriptions for the pdmcr. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field slrc prds sprds t2clk_pu pull_dis ? hreset 0000_0000_0000_0000 addr 0x2f c03c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? hreset 0000_0000_0000_0000 figure 2-2. pads module configuration register (pdmcr) table 2-5. pdmcr field descriptions bits name description 0:5 slrc[0:5] slrc0 controls the slew rate of signals on the following modules: tpu3, qadc64e, sgpioa, sgpiod, sgpioc. for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled slrc1 controls the slew rate of signals on the following modules: qspi, toucan_a, toucan_b. for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled slrc2 controls the slew rate of signals on the qsci in qsmcm . for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled slrc3 controls the slew rate of signal s on the following modules: mios14 except mpwm2/ppm_tx1 and mpwm3 signal. for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled slrc4 controls the slew rate of the mios14 mpwm2 signal. for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled slrc5 controls the slew rate of the mios14 mpwm3 signal. for the slew rate refer to appendix f, ?electrical characteristics .? 0 slew rate controlled 1 not slew rate controlled signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-23 2.4 pad module configurat ion register (pdmcr2) the pdmcr2 controls alternate func tionality of signals shared between different modules, as well as the pre-discharge circuitr y to allow 5v friendliness on the data bus. 6 prds disables weak pull-up/pull down devices enabled at the assertion of poreset /trst or hreset . signals affected by the prds bit include the following: all sgpio signals all tpu3 signals 0 enable weak pull-up/pull down devices on pads controlled by this signal. 1 disable weak pull-up/pull down devices on pads controlled by this signal. refer to ta b l e 2 - 1 4 for more information on prds. 7 sprds disables weak pull-up/pull down devices enabled at the assertion of poreset /trst or hreset . signals affected by the sprds bit include the following: bdip , ta , ts , tea , rd/wr , br , bg , bb , tsiz, bi /sts , burst , tdi, tms, jcomp, tck. 0 enable weak pull-up/pull down devices on pads controlled by this signal. 1 disable weak pull-up/pull down devices on pads controlled by this signal. refer to ta b l e 2 - 1 4 for more information on sprds. 8 t2clk_pu controls the pull-up on the tpu t2clk signals. 0 pull-ups are enabled if the t2clk signals are defined as inputs 1 pull-ups are disabled on the t2clk signals 9:14 pull_dis disables weak pul l up-or-down devices enabled at the assertion of poreset /trst or hreset . signals affected by these bits include the following: pull_dis0 (bit 9): all mios14 input signals pull_dis1 (bit 10): all qsmcm input signals pull_dis2 (bit 11): all qadc64e input signals, except etrig1 and etrig2 pull_dis3 (bit 12): all toucan input signals pull_dis4 (bit 13): reserved pull_dis5 (bit 14): etrig1 and etrig2 1 0 enable weak pull-up/pull-down devices on pads controlled by this signal. 1 disable weak pull-up/pull-down devices on pads controlled by this signal. 15-31 ? reserved 1 this bit was reserved on the k27s mask set of mpc561. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field predis_ en ? tcnc mpi7 mpi8 mpi9 ? ppmpad ? hreset 0000_0000_0000_0000 addr 0x2f c038 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ppmv ? mdo6 mpi6 ? pc sv pcs 4en pcs 5en pcs 6en pcs 7en ? hreset 0000_0000_0000_0000 figure 2-3. pads module configuration register 2 (pdmcr2) table 2-5. pdmcr field descriptions (continued) bits name description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-24 freescale semiconductor table 2-6. pdmcr2 field description bits name description 0predis_ en enable for the pre-discharge circuit to allow 5 volt external devices on the external data bus. 0 bus pre-discharge disabled 1 bus pre-discharge enabled note: this bit is reserved in 66-mhz implementations. 1:3 ? reserved 4:5 tcnc controls the function on the following pads: txd2/qgpo2/c_cntx0, rxd2/qgpi2/c_cnrx0, mpio32b11/c_cnrx0, mpio32b12/c_cntx0. refer to ta bl e 2 - 7 . 6 mpi7 controls the pad mpio32b7/mpwm5. 0 mpio32b7 function will be selected. 1 mpwm5 function will be selected. 7 mpi8 controls the pad mpio32b8/mpwm20. 0 mpio32b8 function will be selected. 1 mpwm20 function will be selected. 8 mpi9 controls the pad mpio32b9/mpwm21. 0 mpio32b9 function will be selected. 1 mpwm21 function will be selected. 11:13 ppmpad control the ppm module pads: mpio32b14/ppm_rx0, mpio32b15/ppm_tx0, mpwm2/ppm_tx1, mpwm3/ppm_rx1, mpio32 b10/ppm_tsync, mpio32b13/ppm_tclk. refer to ta bl e 2 - 8 . 14:15 ? reserved 16 ppmv selects the voltage of the ppm pads. 0 the voltage will be 2.6 v. 1 the voltage will be 5 v. 17:19 ? reserved 20 mdo6 selects the functionality of mdo6 0 the pad mpio32b6/mpwm4/mdo6 will function as mdo6, and the pad mpwm18/mdo6 will function as mpwm18. 1 the pad mpwm18/mdo6 will function as md o6, and the pad mpio32b 6/mpwm4/mdo6 will function according to mpi6 bit. this selection is enabled only if full port mode is implemented in the readi module, if full port mode is not selected then mpwm18/mdo6 will function as mpwm18, and mpio32b6/mpwm4/mdo6 will functi on according to mpi6 bit. note: it is recommended to use mpio32b6/mpwm4/mdo6 for the nexus port as mdo6 is enabled from reset. 21 mpi6 controls the pad mpio32b6/mpwm4/mdo6. 0 mpio32b6 function will be selected. 1 mpwm4 function will be selected. this bit will be disabled if full port mode is enabled in the readi module, and mdo6 bit is logic ?0?. 22:24 ? reserved 25 pcsv selects the polarity of qsmcm module qspi pcs signals in the pcs expanded mode. 0 selects active high. 1 selects active low. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-25 26 pcs4en 1 controls the pad b_t2clk/pcs4. 0 b_t2clk function will be selected. 1 pcs4 function will be selected. 27 pcs5en controls th e pad a_t2clk/pcs5. 0 a_t2clk function will be selected. 1 pcs5 function will be selected. 28 pcs6en controls the pad etrig1/pcs6. 0 etrig1 function will be selected. 1 pcs6 function will be selected. 29 pcs7en controls the pad etrig2/pcs7. 0 etrig2 function will be selected. 1 pcs7 function will be selected. 30:31 ? reserved 1 refer to ta b l e 2 - 9 for information regarding enhanced pcs functionality. table 2-7. tcnc pad functionalities tcnc values txd2/qgpo2/ c_cntx0 rxd2/qgpi2/ c_cnrx0 mpio32b11/ c_cnrx0 mpio32b12/ c_cntx0 00 txd2/qgpo2 rxd2/qgpi2 mpio32b11 mpio32b12 x1 txd2/qgpo2 rxd2/qgpi2 c_cnrx0 c_cntx0 10 c_cntx0 c_cnrx0 mpio32b11 mpio32b12 table 2-8. ppmpad pad functionalities ppmpad values mpio32b14/ ppm_rx0 mpio32b15/ ppm_tx0 mpwm3/ ppm_rx1 mpwm2/ ppm_tx1 mpio32b10/ ppm_tsync mpio32b1/ ppm_tclk x00 mpio32b14 mpio32b15 mpwm3 mpwm2 mpio32b10 mpio32b13 001 mpio32b14 ppm_tx0 mpwm3 mpwm2 ppm_tsync ppm_tclk 010 ppm_rx0 mpio32b15 mpwm3 mpwm2 ppm_tsync ppm_tclk 011 ppm_rx0 ppm_tx0 mpwm3 mpwm2 ppm_tsync ppm_tclk 101 mpio32b14 ppm_tx0 mpwm3 p pm_tx1 ppm_tsync ppm_tclk 110 ppm_rx0 mpio32b15 ppm_rx1 mpwm2 ppm_tsync ppm_tclk 111 ppm_rx0 ppm_tx0 ppm_rx1 ppm_tx1 ppm_tsync ppm_tclk table 2-9. enhanced pcs functionality pcs_in[3:0] pcs_out[7:0] if pc sv = 0 pcs_out[7:0] if pcsv = 1 0000 00000001 11111110 0001 00000010 11111101 table 2-6. pdmcr2 field description (continued) bits name description signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-26 freescale semiconductor note pcs_in[3:0] are driven from the qsmcm module. pcs_out[7:0] values are driven by the corresponding pcs[7:0] pads. if all of the pcs enable bits pcs4en, pcs5en, pcs6en and pcs7en bits are zero, pcs[3:0] will be driven directly by the qsmcm module. if one or more of these enable bits is set, the enhanced pcs function is selected, and the enabled pads drive pcs_out[7:0] value, as shown in table 2-9 . table 2-10 details the functionality of the a_t2clk/pc s5 and b_t2clk/pcs4 pads dependent on the values of pdmcr2[pcs5en], pdm cr2[pcs4en] and short_reg [sh_ t2clk]. also shown in this table is the internal connection of the tpu signals when the enhanced chip select function is used. 0010 00000100 11111011 0011 00001000 11110111 0100 00010000 11101111 0101 00100000 11011111 0110 01000000 10111111 0111 10000000 01111111 1000 00000000 11111111 1001 reserved reserved 1010 1011 1100 1101 1110 1111 table 2-10. enhanced pcs 4 & 5 pad function pdmcr2 [pcs5en] pdmcr2 [pcs4en] short_reg [sh_t2clk] a_t2clk/pcs5 pad function b_t2clk/pcs4 pad function a_t2clk internal tpu_a connection b_t2clk internal tpu_b connection 0 0 0 a_t2clk b_t2clk a_t2clk/pcs5 pad b_t2clk/pcs4 pad 0 0 1 a_t2clk b_t2clk a_t2clk/pcs5 pad a_t2clk/pcs5 pad 0 1 0 a_t2clk pcs4 a_t2clk/pcs5 pad b_t2clk signal driven hi internally table 2-9. enhanced pcs functionality (continued) pcs_in[3:0] pcs_out[7:0] if pc sv = 0 pcs_out[7:0] if pcsv = 1 signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-27 table 2-11 details the functionality of the etrig1/pcs6 and etrig2/pcs7 pads dependent on the values of pdmcr2[pcs6en], pdmcr2[pcs7en], shor t_reg [sh_et1] and short_reg [sh_et2]. also shown in this table is the internal connection of the etrig signals when the enhanced chip select function is used. 0 1 1 a_t2clk pcs4 a_t2clk/pcs5 pad a_t2clk/pcs5 pad 1 0 0 pcs5 b_t2clk a_t2clk signal driven hi internally b_t2clk/pcs4 pad 1 0 1 pcs5 b_t2clk a_t2clk signal driven hi internally b_t2clk signal driven hi internally by connection to a_t2clk 1 1 0 pcs5 pcs4 a_t2clk signal driven hi internally b_t2clk signal driven hi internally 1 1 1 pcs5 pcs4 a_t2clk signal driven hi internally b_t2clk signal driven hi internally by connection to a_t2clk 1. if pcs4/5en = 1 then a/b_t2clk into the module is pulled up internally (enabling div/8 clock, in gate mode). 2. if only pcs4en=1, then a_t2clk can be driven into b_t2clk if ppm_s hort[sh_t2clk] is set. 3. if only pcs5en=1 then a_t2clk will be pulled up, if ppm_short[sh_t2clk] is set, then, b_t2clk will be high regardless of pin state. all of this is regardless of the pull up/down state. note: the ppm shorting function has higher priority logic. if shorting is selected, then a_t2clk b_t2clk. if a_t2clk is selected as pcs then both a_t2clk and b_t2clk will be high regardless of b_t2clk/pcs4 pad state. table 2-10. enhanced pcs 4 & 5 pad function pdmcr2 [pcs5en] pdmcr2 [pcs4en] short_reg [sh_t2clk] a_t2clk/pcs5 pad function b_t2clk/pcs4 pad function a_t2clk internal tpu_a connection b_t2clk internal tpu_b connection signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-28 freescale semiconductor 2.5 mpc561/mpc563 developmen t support signal sharing on the mpc561/mpc563, the jtag, bd m, and readi (nexus interface) si gnals are all shared. only one set of signals can be active at a time. table 2-12 shows the shared functions in the different modes. table 2-11. enhanced pcs 6 & 7 pad function pdmcr2 [pcs6en] pdmcr2 [pcs7en] pull_ dis5 short_ reg [sh_et1] short_ reg [sh_et2] etrig1/pcs6 pad function etrig2/pcs7 pad function pad pull-up etrig 1 internal connection etrig2 internal connection 0 0 0 0 0 etrig1 etrig2 enabled etrig1 etrig2 0 0 0 1 1 etrig1 etrig2 enabled a_tpuch15 b_tpuch15 0 0 1 0 0 etrig1 etrig2 disabled etrig1 etrig2 0 0 1 1 1 etrig1 etrig2 disabled a_tpuch15 b_tpuch15 0 1 0 0 0 etrig1 pcs7 enabled etrig1 pcs7 0 1 0 1 1 etrig1 pcs7 enabled a_tpuch15 b_tpuch15 0 1 1 0 0 etrig1 pcs7 disabled etrig1 pcs7 0 1 1 1 1 etrig1 pcs7 disabled a_tpuch15 b_tpuch15 10000pcs6etrig2enabled pcs6 etrig2 1 0 0 1 1 pcs6 etrig2 enabled a_tpuch15 b_tpuch15 1 0 1 0 0 pcs6 etrig2 disabled pcs6 etrig2 1 0 1 1 1 pcs6 etrig2 disabled a_tpuch15 b_tpuch15 1 1 0 0 0 pcs6 pcs7 enabled pcs6 pcs7 1 1 0 1 1 pcs6 pcs7 enabled a_tpuch15 b_tpuch15 1 1 1 0 0 pcs6 pcs7 disabled pcs6 pcs7 1 1 1 1 1 pcs6 pcs7 disabled a_tpuch15 b_tpuch15 table 2-12. mpc561/mpc563 development support shared signals signal 1 1 only one set of signals are enabled at a time. direction jtag bdm readi jcomp/rsti input jcomp 0 rsti tck/dsck/mcki input tck dsck mcki tdi/dsdi/mdi0 input tdi dsdi mdi0 tdo/dsdo/mdo0 output tdo dsdo mdo0 tms/evti input tms ? evti signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-29 2.5.1 jtag mode selection the mpc561/mpc563 has five jtag sign als. the test data input (tdi) and test data output (tdo) scan ports are used to scan instructions as well as data into the various s can registers for jtag operations. the scan operation is controlled by the te st access port (tap) controller, which in turn is controlled by the test mode select (tms) input sequence. th e scan data is latched at the ri sing edge of the test clock (tck). on the mpc561/mpc563, jtag is used for boundary scan only. there is no access to internal mpc561/mpc563 circuitry. when jtag mode is enab led, the readi module will be held inactive. see figure 2-4 for jtag mode selection. jtag is entered by the following sequence of events: ? assert poreset /trst to reset the jtag tap controller ? hold jcomp/rsti high prior to poreset /trst negation and keep high as long as jtag mode is required (the readi module will be held inactive since only one of the multiplexed functions jcomp and rsti can be asserted at the negation of poreset /trst ). jtag mode is exited by: ? drive jcomp/rsti low. note poreset /trst and analog signals anx, extal, xtal, and tdi/tdo/tms/tck are not in the jtag scan path. table 2-13. mpc561/mpc563 mode selection options signal state when sampled affect bdm mode dsck high sreset negation bdm mode enabled low sreset negation bdm mode disabled dsdi high 8 clocks after sreset synchronous mode low 8 clocks after sreset asynchronous mode nexus configuration evti high rsti negation readi module disabled low rsti negation readi module enabled mdi0 high evti negation full port mode low evti negation reduced port mode jtag selection jcomp low poreset nexus or bdm allowed high poreset jtag mode selected signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-30 freescale semiconductor figure 2-4. debug mode selection (jtag) 2.5.2 bdm mode selection the mpc561/mpc563 has a 10 pin bdm port. see figure 2-5 for bdm mode selection. the bdm mode is entered by the following sequence of events: ? hold dsck high at reset negation (sreset ) ? configure dsdi to select bdm clock m ode, within 8 clocks of reset negation bdm mode is exited by: ? reset the device by asserting poreset /trst or hreset figure 2-5. debug mode selection (bdm) 2.5.3 nexus mode selection the readi module signals support the nexus (ieee-isto 5001-1999) a uxiliary port interface for debug. there are two modes available: full port mode and re duced port mode. reduced por t mode allows for a 1 bit input stream and a 2 bit output stream. full port mode allows for a 2-bit input stream and an 8-bit output stream. if mdi0 is held high when nexus mode is enabled, full port mode will be used during nexus debug. if mdi0 is held low when nexus mode is enabled, reduced port mode will be used. see figure 2-6 for nexus mode selection. the nexus interface is entered by the following sequence of events: ? hold jcomp/rsti low while negating poreset /trst ? hold tms/evti low to enable nexus mode and config ure tdi/dsdi/mdi0 for full or reduced port mode. both of these should be done at least 4 clocks before driving jcomp/rsti high poreset /trst jcomp/rsti jtag config jtag on jtag disabled t sreset jcomp/rsti bdm enable t dsck dsdi tms/evti (low) (low) configure bdm enable nexus bdm on nexus off signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-31 ? drive jcomp/rsti high nexus mode is exited by: ? hold jcomp/rsti low to reset nexus port ? hold tms/evti high to disable nexus mode at leas t 4 clocks before driving jcomp/rsti high ? drive jcomp/rsti high figure 2-6. debug mode selection (nexus) 2.6 reset state during reset, a 130-a (maximum) resistor ?weakly pulls? all input signals, with the exception of the power-supply and clock-related signals, to a value based on conditions described in appendix f, ?electrical characteristics .? in reset state, all i/o signals b ecome inputs, and all outputs (except for clkout, hreset , and sreset ) are pulled only by the pull-up/pull-down. 2.6.1 signal functionality co nfiguration out of reset the reset configuration word (rcw) defines the post-re set functionality of some multiplexed signals. for details on these signals and how they are configur ed, refer to section 7.5.2, ?hard reset configuration word.? the 2.6-v bus related signals have selectable output buf fer drive strengths that ar e controlled by the com0 bit in the usiu?s system clock and reset contro l register (sccr). the control is as follows: 0 = 2.6-v bus signals full drive (50-pf load) 1 = 2.6-v bus signals reduced drive (25-pf load) 2.6.2 signal state during reset while hreset is asserted, the reset-configuration value is latched from the data bus into various bits on the part. the function of many signals depends upon the value latched. if the value on the data bus changes, then the function of various signals ma y also change. this is especially tr ue if the reset configuration word (rcw) comes from the flash, because the flash does not drive the rcw until 256 cloc ks after the start of poreset /trst jcomp/rsti t tms/evti nexus on nexus off enable and configure nexus mdi0 signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-32 freescale semiconductor hreset . however, the signals must not cause any spurious conditions or consume an excessive amount of power during reset. to prevent these conditions, the signals need to have a defined reset state. table 2-14 describes the reset state of the si gnals based on signal functionality. all signals are initialized to a ?res et state? during reset. this state re mains active until reset is negated or until software disables the pull-up or pull-down device based on the signal functionality. upon assertion of the corresponding bits in the signal control regist ers and negation of reset, the signal acquires the functionality that was programmed. 2.6.3 power-on reset and hard reset power-on reset and hard reset affect the functionality of the signals out of reset. (during soft reset, the functionality of the signals is unaltered.) upon assertion of the power -on reset signal (poreset /trst ) the functionality of the signal is not yet known to the rcpu. the weak pull-up or weak pull-dow n resistors are enabled. the reset configuration word configures the system, and towards the end of reset the signal functi onality is known. based upon the signal functionality, the pull-up or pull-down devices are either disabled immediately at the negation of reset or remain enabled, as shown in table 2-14 . because hard reset can occur when a bus cycle is pending, the pdmcr bits that enable and disable the pull-up or pull-down resistors are set or reset synchronously to el iminate contention on the signals. (poreset /trst affects these bits asynchronously.) 2.6.4 pull-up/pull-down 2.6.4.1 pull-up/pull-down enable and disable for 5-v only and 2.6-v only signals the pull resistors are enab led and disabled by the co rresponding bits in the pdm cr register in the usiu (see table 2-14 ). when those bits are negate d (logic 0), the pull resistors ar e enabled. when asserted (logic 1), the devices are disabled. 2.6.4.2 pull-down enable and disabl e for 5-v/2.6-v multiplexed signals the 5-v/2.6-v multiplexed pad does not have a pull-up device. the pull-down will be controlled by the corresponding bits in the pdmcr register. when th is bit is negated, the pul l-down is enabled, when asserted the pull-down will be disabled. note all pull-up/pull-down devices are disabled when all the signals are forced to three state in jtag mode. 2.6.4.3 special pull resistor disab le control functionality (sprds) for the signals that support debug, opcode tracking, and bus control functiona lity, the pull resistors will be controlled by the sprds bit in the pdmcr register. during reset this signal will be synchronously used signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-33 to enable the pull resistors in the pads. on negation of reset, based on which functionality is selected for the signals, this signal is set to disable the pull resistor s, or is continued to be held in its reset state to indicate that the pulls ar e disabled only when the output driver is enabled. 2.6.4.4 pull device select (pull_sel) the mios14 and the tpu signals have selectable pull-up or pull-down de vices. the devices are controlled by the pull_sel signal. a high on the pull_sel si gnal enables pull-up devices on the mios14 and tpu signals. a low enables pull-dow n devices. note that the pull devices can be disabled by the pull_dis0 (mios14) and prds (tpu) bits in the pdmcr register. see section 2.3, ?pad module configuration re gister (pdmcr) .? 2.6.5 signal reset states table 2-14 summarizes the reset states of all signals on the mpc561/mpc56 3. note that pd refers to a weak pull-down, pu2.6 refers to a weak pull-up to 2.6 v, and pu5 refers to a weak pull-up to 5 v. all control of the weak-pull devices is in the pa d module configuration register, described in table 2-5 . note 2.6-v inputs are 5-v tolerant, but 2.6- v outputs are not. do not connect 2.6-v outputs to a driver or pull-up greater than 3.1 v. note depending on the application, pins ma y require a pull-down resistor to avoid getting any command due to noise. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-34 freescale semiconductor table 2-14. mpc561/mpc563 signal reset state signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst usiu addr[8:31] 3 / 2.6 v no 50 ; 25 pd until reset negates 4 , 6 no controlled by sc bit in the reset config word. see ta b l e 6 - 1 0 . sgpioa[8:31] 5 v yes 50 ; 50 5 pd until prds is set no data[0:31] 3 / 2.6 v no 50 ; 25 pd until reset negates 6 no controlled by sc bit in the reset config word. see ta b l e 6 - 1 0 . sgpiod[0:31] 5 v yes 50:50 5 pd until prds is set no irq0 / 2.6 v no na pu2.6 until prds is set 8 yes mdo4 if the nexus (readi) port is enabled, irq0 otherwise. see section 2.5 . sgpioc0 7 / 2.6 v no 50 ; 25 yes mdo4 7 2.6 v no 50 ; 25 yes irq 1 / 2.6 v no na pd until reset negates 6, 8 ye s i r q 1 rsv / 2.6 v no 50 ; 25 pd until reset negates 6 ye s sgpioc1 3 5 v yes 50 ; 50 5 pd until prds is set ye s irq2 / 2.6 v no na pd until reset negates 6, 8 ye s i r q 2 cr / 2.6 v no na pd until reset negates 6, 8 no sgpioc2 3 / 5 v yes 50 ; 50 5 pd until prds is set no mts 9 2.6 v no 50 ; 25 pd until reset negates 6 no irq3 / 2.6 v no na pd until reset negates 6, 8 ye s i r q 3 kr / 2.6 v no 50 ; 25 pd when driver not enabled 4 no retry / 2.6 v no 50 ; 25 pd when driver not enabled 4 no sgpioc3 3 5 v yes 50 ; 50 5 pd until prds is set no signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-35 irq4 / 2.6 v no na pd until reset negates 6, 8 ye s i r q 4 at2 / 2.6 v no 50 ; 25 pd until reset negates 6, 8 no sgpioc4 3 5 v yes 50 ; 50 5 pd until prds is set ye s irq5 10 / 2.6 v no na pu2.6 until reset negates yes modck1 until reset negates, then irq 5 sgpioc5 7 / 2.6 v no 50 ; 25 pu2.6 until prds is set no modck1 11 2.6 v no na pu2.6v until reset negates no irq [6:7] 10 / 2.6 v no na pu2.6 until sprds is set yes modck[2:3] until reset negates, then irq [6:7] modck[2:3] 11 2.6 v no na pu2.6 until reset negates no pull_sel 5 v no na pu5, external pull device required no pull_sel tsiz[0:1] 7 2.6 v no 50 ; 25 pd when driver not enabled or until sprds is set no tsiz[0:1] rd/wr 7 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no rd/wr burst 7 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no burst bdip 7 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no bdip ts 7,12 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no ts table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-36 freescale semiconductor ta 7, 12 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no ta tea 7, 12 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no tea oe 7 2.6 v no 50 ; 25 pu2.6 until reset negates no oe rstconf / 2.6 v no n/a pu2.6 when driver not enabled or until sprds is set no rstconf until reset negates. texp 7, 11 2.6 v no 50 ; 25 no bi 7, 12 / 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set. no controlled by dbgc in the reset configuration word. see ta b l e 6 - 8 . sts 7 2.6 v no 50 ; 25 no cs [0:3] 7 2.6 v no 50 ; 25 pu2.6 until reset negates no cs [0:3] we [0:3] 7 / 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no controlled by bit atwc (bit 12) of the reset configuration word. see ta bl e 6 - 8 . be [0:3] 7 / 2.6 v no 50 ; 25 no at[0:3] 7 2.6 v no 50 ; 25 no system control poreset / 2.6 v no na external pull-up required yes poreset /trst trst 11 2.6 v no na yes hreset 11, 12 2.6 v 13 no 50 ; 25 pu2.6 when driver not enabled or until sprds is set external pull-up required yes hreset sreset 11, 12 2.6 v 13 no 50 ; 25 pu2.6 when driver not enabled or until sprds is set external pull-up required yes sreset development and debug table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-37 sgpioc6 3 / 5 v yes 50 ; 50 5 pd until prds is set no ptr frz / 2.6 v no 50 ; 25 pd until reset negates no ptr 2.6 v no 50 ; 25 pd until reset negates no sgpioc7 3 / 5 v yes 50 ; 50 5 pd until prds is set ye s lw p 0 irqout / 2.6 v no 50 ; 25 pd until reset negates 6 no lwp0 2.6 v no 50 ; 25 pd until reset negates 6 no bg 7 / 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no controlled by dbgc in reset config word. see ta b l e 6 - 8 . vf0 7 / 2.6 v no 50 ; 25 no lwp1 7 2.6 v no 50 ; 25 no br 7 / 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no controlled by dbgc in reset config word. see ta b l e 6 - 8 . vf1 7 / 2.6 v no 50 ; 25 no iwp2 7 2.6 v no 50 ; 25 no bb 7, 12 / 2.6 v no 50 ; 25 pu2.6 when driver not enabled or until sprds is set no controlled by dbgc in reset config word. see ta b l e 6 - 8 . vf2 7 / 2.6 v no 50 ; 25 no iwp3 7 2.6 v no 50 ; 25 no iwp[0:1] 7 / 2.6 v no 50 ; 25 pu2.6 until reset negates no controlled by dbgc in the reset config word. see ta b l e 6 - 8 . vfls[0:1] 7 2.6 v no 50 ; 25 no jtag/bdm/readi tms / 2.6 v no na pu2.6 if in jtag mode, otherwise pd until sprds is set 14 no tms unless the nexus (readi) port is enabled, then evti . see section 2.5 . evti 2.6 v no na no tdi / 2.6 v no na pu2.6 if in jtag mode, otherwise pd until sprds is set 6 no dsdi unless the nexus (readi) port (mdi0) or jtag mode (tdi) is enabled. see section 2.5 . dsdi / 2.6 v no na no mdi0 2.6 v no na no tck / 2.6 v no na pd until reset negates 6 yes dsck unless the nexus (readi) port (mcki) or jtag mode (tck) is enabled. see section 2.5 . dsck / 2.6 v no na yes mcki 2.6 v no na yes table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-38 freescale semiconductor tdo 7 / 2.6 v no 50 ; 25 pu2.6 until reset negates or the driver is enabled no dsdo unless the nexus (readi) port (mdo0) or jtag mode (tdo) is enabled. see section 2.5 . dsdo 7 / 2.6 v no 50 ; 25 no mdo0 7 2.6 v no 50 ; 25 no jcomp / 2.6 v no na pd until sprds is set no see section 2.5 . rsti 2.6 v no na no clocks and pll xtal 11 2.6 v na ; na na ; na ? na xtal extal 11 2.6 v na ; na na ; na ? na extal xfc 2.6 v na ; na na ; na ? na xfc clkout 7 2.6 v no 90; 50; 25 15 ?noclkout extclk 11 2.6 v na ; na na ; na ? no extclk engclk 3 / 2.6 v / 5 v na ; na na ; na ? no engclk (2.6 v) buclk 2.6 v na ; na na ; na ? no qsmcm pcs0 / 5 v yes 50 ; 50 pu5 until pull_dis1 is set no qgpo0 ss / 5 v yes 50 ; 50 no qgpio0 5 v yes 50 ; 50 no pcs[1:3]/ 5 v yes 50 ; 50 pu5 until pull_dis1 is set no qgpio[1:3] qgpio[1:3] 5 v yes 50 ; 50 no miso / 5 v yes 200 ; 50 5 pu5 until pull_dis1 is set no qgpio4 qgpio4 5 v yes 200 ; 50 5 no mosi / 5 v yes 200 ; 50 5 pu5 until pull_dis1 is set no qgpio5 qgpio5 5 v yes 200 ; 50 5 no sck / 5 v yes 200 ; 50 5 pu5 until pull_dis1 is set no qgpio6 qgpio6 5 v yes 200 ; 50 5 no txd1 / 5 v yes 50 ; 50 pu5 until pull_dis1 is set no qgpo1 qgpo1 5 v yes 50 ; 50 no table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-39 txd2 / 5 v yes 50 ; 50 pu5 until pull_dis1 is set no qgpo2 qgpo2 / 5 v yes 50 ; 50 no c_cntx0 5 v yes 50 ; 50 no rxd1 / 5 v na na must be driven or connected to a pull device no qgpi1 qgpi1 5 v na na no rxd2 / 5 v na na must be driven or connected to a pull device no qgpi2 qgpi2 / 5 v na na no c_cnrx0 5 v na na no mios14 mda[11:15, 27:31] 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 yes mda[11:15,27:31] mpwm0 / 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 yes mpwm0 unless the nexus (readi) port is enabled, then mdi1. see section 2.5 . mdi1 2.6 v no na yes mpwm1 3 / 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 yes mpwm1 unless the nexus (readi) port is enabled, then mdo2. see section 2.5 . mdo2 2.6 v no 50 ; 25 no mpwm2 3 / 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 ye s m p w m 2 2.6 v no 50 ; 25 no ppm_tx1 5 v yes 50 ; 25 no mpwm3/ 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 ye s m p w m 3 ppm_rx1 2.6 v no na yes mpwm16 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 ye s m p w m 1 6 mpwm17 3 / 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 yes mpwm17 unless the nexus (readi) port is enabled. see section 2.5 . mdo3 2.6 v no 50 ; 25 no table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-40 freescale semiconductor mpwm[18:19] 3 / 5 v yes 50 ; 50 pull device enabled until pull_dis0 is set 16 yes mpwm[18:19] mdo[6:7] 2.6 v no 50 ; 25 no mpio32b0 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set. 16 yes mpio32b0 unless the nexus (readi) port is enabled, then mdo1. see section 2.5 . vf0 / 2.6 v no 50 ; 25 no mdo1 2.6 v no 50 ; 25 no mpio32b1 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set. 16 yes mpio32b1 unless the nexus (readi) port is enabled, then mcko. see section 2.5 . vf1/ 2.6 v no 50 ; 25 no mcko 2.6 v no 50 ; 25 no mpio32b2 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set. 16 yes mpio32b2 unless the nexus (readi) port is enabled, then msei . see section 2.5 . vf2 / 2.6 v no 50 ; 25 no msei 2.6 v no n/a yes mpio32b3 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set. 16 yes mpio32b3 unless the nexus (readi) port is enabled, then mseo . see section 2.5 . vfls0 / 2.6 v no 50 ; 25 no mseo 2.6 v no 50 ; 25 no mpio32b4 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b4 vfls1 2.6 v no 50 ; 25 no mpio32b5 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b5 unless the nexus (readi) port is enabled, then mdo5. see section 2.5 . mdo5 2.6 v no 50 ; 25 no mpio32b6 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set. 16 yes mpio32b6 unless the nexus (readi) port is enabled, then mdo6. see section 2.5 . mpwm4 / 5 v yes 50 ; 50 yes mdo6 2.6 v yes 50 ; 25 no mpio32b[7:9] / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b[7:9] mpwm[5, 20:21] 5 v yes 50 ; 50 yes mpio32b10 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b10 ppm_tsync 2.6 v no 50 ; 25 no 5 v yes 50 ; 50 mpio32b11 / 5 v yes 50 ; 50 pu5 until pull_dis0 is set yes mpio32b11 c_cnrx0 5 v yes na no table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-41 mpio32b12 / 5 v yes 50 ; 50 5 pu5 until pull_dis0 is set yes mpio32b12 c_cntx0 5 v yes 50 ; 50 no mpio32b13 3 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b13 ppm_tclk 2.6 v no 50 ; 25 no 5 v yes 50 ; 50 no mpio32b14 / 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b14 ppm_rx0 2.6 v no na yes 5 v no na yes mpio32b15 3 / ppm_tx0 5 v yes 50 ; 50 5 pull device enabled until pull_dis0 is set 16 yes mpio32b15 2.6 v no 50 ; 25 no 5 v yes 50 ; 50 no tpu_a / tpu_b a_tpuch[0:15 ] 5 v yes 50 ; 50 5 pull device enabled until prds is set 16 yes a_tpuch[0:15] a_t2clk / 5 v yes 50 ; 50 pu5 when driver not enabled or until t2clk_pu is set yes a_t2clk pcs5 5 v yes 50 ; 50 no b_tpuch[0:15 ] 5 v yes 50 ; 50 5 pull device enabled until prds is set 16 yes b_tpuch[0:15] b_t2clk / 5 v yes 50 ; 50 pu5 when driver not enabled or until t2clk_pu is set yes b_t2clk pcs4 5 v yes 50 ; 50 no qadc64e_a / qadc64e_b etrig[1:2] / 5 v yes n/a pd until pull_dis5 is set yes etrig[1:2] pcs[6:7] 5 v yes 50 ; 50 pu5 until pull_dis1 is set ye s a_an0 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an0 a_anw / 5 v yes na no a_pqb0 5 v yes 50 ; 50 5 ye s table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-42 freescale semiconductor a_an1 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an1 a_anx / 5 v yes na no a_pqb1 5 v yes 50 ; 50 5 ye s a_an2 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an2 a_any / 5 v yes na no a_pqb2 5 v yes 50 ; 50 5 ye s a_an3 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an3 a_anz / 5 v yes na no a_pqb3 5 v yes 50 ; 50 5 ye s a_an[48:51]/ 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an[48:51] a_pqb[4:7] 5 v yes 50 ; 50 5 ye s a_an[52:54] / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an[52:54] a_ma[0:2] / 5 v yes na yes a_pqa[0:2] 5 v yes 50 ; 50 5 ye s a_an[55:59]/ 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no a_an[55:59] a_pqa[3:7] 5 v yes 50 ; 50 5 ye s b_an0 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an0 b_anw / 5 v yes na no b_pqb0 5 v yes 50 ; 50 5 ye s b_an1 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an1 b_anx / 5 v yes na no b_pqb1 5 v yes 50 ; 50 5 ye s b_an2 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an2 b_any / 5 v yes na no b_pqb2 5 v yes 50 ; 50 5 ye s table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-43 b_an3 / 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an3 b_anz / 5 v yes na no b_pqb3 5 v yes 50 ; 50 5 ye s b_an[48:51]/ 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an[48:51] b_pqb[4:7] 5 v yes 50 ; 50 5 ye s b_an[52:54]/ 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an[52:54] b_ma[0:2]/ 5 v yes na yes b_pqa[0:2] 5 v yes 50 ; 50 5 ye s b_an[55:59]/ 5 v yes na pu5 when driver not enabled or until pull_dis2 is set no b_an[55:59] b_pqa[3:7] 5 v yes 50 ; 50 5 ye s toucan_a / toucan_b a_cntx0 5 v yes 50 ; 50 17 pu5 until pull_dis3 is set no a_cntx0 b_cntx0 5 v yes 50 ; 50 17 pu5 until pull_dis3 is set no b_cntx0 a_cnrx0 5 v no na pu5 until pull_dis3 is set yes a_cnrx0 b_cnrx0 5 v no na pu5 until pull_dis3 is set yes b_cnrx0 uc3f flash epee 18 2.6 v no ? pu2.6 no epee b0epee 18 2.6 v no ? pu2.6 no b0epee uc3f power supplies vflash 18 5 v ? ? ? ? vflash vddf 18 2.6 v ? ? ? ? vddf vssf 18 0 v ? ? ? ? vssf table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-44 freescale semiconductor global power supplies nvddl 2.6 v ? ? ? ? nvddl vddh 5 v ? ? ? ? vddh vdd 2.6 v ? ? ? ? vddi vss 0 v ? ? ? ? vss kapwr 11 2.6 v ? ? ? ? kapwr iramstby 19 2.6 v ? ? ? ? iramstby qvddl 2.6 v ? ? ? ? qvddl usiu power supplies vddsyn 2.6 v ? ? ? ? vddsyn vsssyn 2.6 v ? ? ? ? vsssyn qadc64e power supplies vrh 5 v ? ? ? ? vrh vrl 0 v ? ? ? ? vrl altref 5 v ? ? ? ? altref vdda 5 v ? ? ? ? vdda vssa 0 v ? ? ? ? vssa 1 this column contains only the list of signals and should not be confused with the actual pin name. for actual pin names, see appendix f, ?electrical characteristics .? 2 for 5-v outputs, the left hand value represents slew rate co ntrol off, and the right hand value represents slew rate control on. for 2.6-v outputs, the left hand value repres ents loads that are full drive, and the right hand value represents loads that are half drive. 3 care should be taken that neither a pu ll-up to greater than 3.1 v or an external output that can drive greater than 3.1 v is connected to this pin while the 2.6-v driver is enabled. 4 pull-up/pull-down is active when pin is defined as an inpu t and/or during reset, therefor e, output enable is negated. this also means that external pull-up/pu ll-down is not required unless specified. 5 for this 5-v output, a drive load of 200 pf is possible but with a rise/fall time of 300 ns. 6 during reset, the output enable to the pad driver is negated and the pd is active. after reset is negated, the pd is disabled. 7 2.6-v outputs cannot be connected to a pull-up or driver greater than 3.1 v. 8 this pin requires a pull-up to 2.6 v if interrupts are ever enabled for this irq input. 9 this signal also includes the mdo5 function on the k27s mask set of the mpc561. 10 the modck[1:3] are shared functions with irq [5:7]. if irq [5:7] are used as interrupts, the interrupt source should be removed during poreset /trst to insure the modck pins are in the correct state on the rising edge of poreset /trst . 11 these pins are powered by kapwr (keep-alive power supp ly). any pull-ups on these pins should pull-up to kapwr. table 2-14. mpc561/mpc563 signal reset state (continued) signal list 1 voltage slew rate controlled option? drive load (pf) 2 reset state hysteresi s enabled? function after hreset , poreset / trst signal descriptions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 2-45 12 an external pull-up is required in order to negate the signal in the appropriate time. 13 this pin is 5-v tolerant. 14 this signal was pd only until sprds is set on mask set k27s of the mpc561. 15 these values represent full drive, half drive and quarter drive. 16 whether the pull device is a pull-up or a pull-down is determined by the state of the pull_sel signal. 17 for this 5-v output, a drive load of 200 pf is possible, but will have a rise/fall time of 100ns. 18 mpc563 only, no connection on mpc561. 19 iramstby is the input to an approximatel y 1.7v voltage regulator. it should be connected through a resistor to a standby power supply. signal descriptions mpc561/mpc563 reference manual, rev. 1.2 2-46 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-1 chapter 3 central processing unit the risc processor (rcpu) used in the mpc500 family of microcontroll ers integrates five independent execution units: an integer unit (iu), a load/store unit (lsu), a branch processing unit (bpu), a floating-point unit (fpu) and an integer multiplier divider (imd). th e risc?s use of simple instructions with rapid execution times yields high efficien cy and throughput for powerpc isa-based systems. most integer instructions execute in one clock cycle. instructions can complete out of order for increased performance; however, the processor makes execution appear sequential. this section provides an overview of the rcpu. for a de tailed description of this processor, refer to the rcpu reference manual . the following sections descri be each block and sub-block. 3.1 rcpu block diagram figure 3-1 provides a block diagram of the rcpu. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-2 freescale semiconductor figure 3-1. rcpu block diagram control bus fpu fpr history fpr (32 x 64) load/store floating data load/ integer store data load/ address store alu/ bfu imul/ idiv gpr history gpr (32 x 32) control regs next address generation branch unit processor instruction queue pre-fetch instruction sequencer rcpu l-data l-addr source buses (4 slots/clock) i-data i-addr write back bus 2 slots/clock central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-3 3.2 rcpu key features major features of the rcpu include: ? high-performance microprocessor ? single clock-cycle execut ion for many instructions ? five independent execution un its and two register files ? independent lsu for load and store operations ? bpu featuring static branch prediction ? a 32-bit integer unit (iu) ? fully ieee 754-compliant fpu for both single- and double-precision operations except as noted in section 3.4.4, ?floating-point unit (fpu) ,? or refer to the rcpu reference manual. ? 32 general-purpose register s (gprs) for integer operands ? 32 floating-point regist ers (fprs) for single- or double-precision operands ? facilities for enhanced system performance ? atomic memory references ? in-system testability and debugging features ? high instruction and data throughput ? condition register (cr) look-ah ead operations performed by bpu ? branch-folding capability during execu tion (zero-cycle branch execution time) ? programmable static branch predic tion on unresolved conditional branches ? a pre-fetch queue that can hold up to f our instructions, providing look-ahead capability ? interlocked pipelines with fe ed-forwarding that control da ta dependencies in hardware ? class code compression model support ? efficient use of internal fl ash (mpc564) and extern al flash (mpc562/mp c564) by increasing code density up to 100% 3.3 instruction sequencer the instruction sequencer pr ovides centralized control over data flow between execution units and register files. it implements the basic inst ruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history that is used to back up the machine in the event of an exception. the instruction sequencer fetches inst ructions from the burst buffer contro ller into the instruction pre-fetch queue. the bpu extracts branch in structions from the pr e-fetch queue and, using branch prediction on unresolved conditional branches, allows the instruction sequencer to fetc h instructions fr om a predicted target stream while a conditional branch is eval uated. the bpu folds out branch instructions for unconditional or conditional branch es unaffected by instructi ons in the execution stage. instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. if branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-4 freescale semiconductor figure 3-2. sequencer data path 3.4 independent execution units the powerpc isa architecture provi des independent floating-point, in teger, load/store, and branch processing execution units, making it possible to im plement advanced features such as look-ahead operations. for example, since branch instructions do not depend on gprs , branches can often be resolved early, eliminating stalls caused by taken branches. table 3-1 summarizes the rcpu execution units. table 3-1. rcpu execution units unit description branch processing unit (bpu) includes the im plementation of all branch instructions. load/store unit (lsu) includes implementation of a ll load and store instructions, whether defined as part of the integer processor or the floating-point processor. instruction address generator cc unit 32 32 read write buses branch instruction buffer 32 condition evaluation instruction pre-fetch queue execution units and registers files instruction memory system central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-5 the following sections describe thes e execution units in greater detail. 3.4.1 branch processing unit (bpu) the bpu, located within the instruction sequencer, performs condition register look-ahead operations on conditional branches. the bpu looks through the instru ction queue for a conditional branch instruction and attempts to resolve it early, achieving th e effect of a zero-cycle branch in many cases. the bpu uses a bit in the instructi on encoding to predict the direction of the conditional branch. therefore, when it encounters an unresolved c onditional branch instruction, the pr ocessor pre-fetches instructions from the predicted target stream until the conditional branch is resolved. the bpu uses a calculation feature to compute bran ch target addresses with three special-purpose, user-accessible register s: the link register (lr), th e count register (ctr), and the condition register (cr). the bpu calculates the return pointer for a subroutine, then calls and sa ves it into the lr. the lr also contains the branch target address for the branch c onditional to link register (b clrx) instruction. the ctr contains the branch target address for the branch conditional to c ount register (bcctrx) instruction. the contents of the lr and ct r can be copied to or fr om any gpr. because the bp u uses dedicated registers rather than general-purpose or floati ng-point registers, execution of br anch instructions is independent from execution of integer instructi ons. the cr bits indicate conditions that may resu lt from the execution of relevant instructions. 3.4.2 integer unit (iu) the iu executes all integer processor instructions (except the integer storage access instructions) implemented by the load/store unit. th e iu contains the following subunits: ? the imul?idiv unit, which implements the integer multiply and divide instructions ? the arithmetic logic unit (alu)?bfu unit, whic h implements all integer logic, add, subtract, and bit-field instructions the iu also includes the integer exception register (xer) and th e general-purpose register file. imul?idiv and alu?bfu are implemented as se parate execution units. the alu?bfu unit can execute one instruction per clock cycl e. imul?idiv instructions require multiple clock cycles to execute. imul?idiv is pipelined for multiply instructions, so th at consecutive multiply instructions can be issued integer unit (iu) includes implementation of all int eger instructions except load/store instructions. this module includes the gprs (including gpr history and scoreboard) and the following subunits: the imul-idiv, whic h includes the implementation of the integer multiply and divide instructions and the alu-bfu, which includes implementation of all integer logic, add and subtract instructions, and bit field instructions. floating-point unit (fpu) includes the fprs (including fpr history and scoreboard) and the implementation of all floating-point instru ctions except load/ store floating-point instructions. table 3-1. rcpu execution units (continued) unit description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-6 freescale semiconductor on consecutive clock cycles. divide in structions are not pipeli ned; an integer divide instruction preceded or followed by an integer divide or multiply instruction results in a pr ocessor-pipeline stall. however, since imul?idiv and alu?bfu are implement ed as separate execution units, an integer divide instruction preceded or followed by an alu?bfu instructi on does not cause a delay in the pipeline. 3.4.3 load/store unit (lsu) the load/store unit handles all data transfer betwee n the general-purpose register file and the internal load/store bus (l-bus). the load/store unit is implemen ted as an independent exec ution unit so that stalls in the memory pipeline do not stall the master instruct ion pipeline (unless there is a data dependency). the unit is fully pipelined so that memo ry instructions of any size may be issued on back-to-back cycles. there is a 32-bit wide data path between the load/store unit and the general-purpose register file. single-word accesses can be achieved wi th an internal on-chip data ram, resulting in a two-clock latency. double-word accesses require two cloc ks, resulting in a three-clock late ncy. since the l-bus is 32 bits wide, double-word transfers require tw o bus accesses. the load/store uni t performs zero-fill for byte and half-word transfers and sign exte nsion for half-word transfers. addresses are formed by adding the source-one register operand specifie d by the instruction (or zero) to either a source-two register operand or to a 16- bit, immediate value embedded in the instruction. 3.4.4 floating-point unit (fpu) the fpu contains a double-precision multiply array, the floating-point status and control register (fpscr), and the fprs. the multiply-add array allows the rcpu to efficiently implement floating-point operations such as multiply , multiply-add, and divide. the rcpu depends on a software envelope to fully implement the ieee floating-point specification. overflows, underflows, nans (not a number), and denormalized numbers cause floating-point assist exceptions that invoke a software r outine to deliver (with hardware as sistance) the correct ieee result. to accelerate time-critical operations and make them more deterministi c, the rcpu provides a mode of operation that avoids invoking a software envelope and attempts to deliver result s in hardware that are adequate for most applications, if not in strict compliance with ieee st andards. in this mode, denormalized numbers, nans, and ieee invalid operati ons are legitimate, returning defa ult results rather than causing floating-point assist exceptions. 3.5 levels of the powerpc isa architecture the powerpc isa architecture consists of three levels: ? user instruction set architecture (uisa) ? defines the base user-level instruction set, user-level registers, data types, floating-point excepti on model, memory models for a uniprocessor environment, and programming mode l for a uniprocessor environment. ? virtual environment architecture (vea) ? de scribes the memory model for a multiprocessor environment, and describes other aspects of virtual environments. implementations that conform to the vea also adhere to the uisa , but may not necessarily adhere to the oea. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-7 ? operating environment architecture (oea) ? defines the memory-management model, supervisor-level registers, synchronizati on requirements, and the exception model. implementations that conform to the oea also adhere to the uisa and the vea. adherence to the powerpc isa architecture can be measured in terms of wh ich of the levels are implemented. 3.6 rcpu programming model the powerpc isa architecture defines register-to-regist er operations for most co mputational instructions. source operands for these instructio ns are accessed from the registers or are embedded in the instruction opcode. the three-register instruction format allows specificati on of a target register distinct from the two source operands. load and store inst ructions transfer data between memory and on-chip registers. powerpc isa-compliant processors ha ve two levels of priv ilege: supervisor mode (typically used by the operating environment) and user mode (used by the application software). the programming model incorporates 32 gprs, special-purpose registers (sprs), and several miscellaneous registers. supervisor-level access is provide d through the processor?s exception mechanism. that is, when an exception is taken (whether automatically, because of an error or pr oblem that needs to be serviced, or deliberately, as in the case of a tr ap instruction), the processor begins operating in supervisor mode. the access level is indicated by the privilege-level (pr) bit in the machine state register (msr). figure 3-3 illustrates the user-level and supervisor-level rcpu programming models and the three levels of the powerpc isa architecture. note that register s such as the general-purpose registers (gprs) are accessed through operands that are part of the instruct ions. registers can be ac cessed explicitly through specific instructions such as move to special-purpose register (mts pr) or move from special-purpose register (mftspr), or implicitly as part of an in struction?s execution. some registers are accessed both explicitly and implicitly. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-8 freescale semiconductor figure 3-3. rcpu programming model msr supervisor-level sprs user model vea supervisor model oea machine state register development support sprs condition register floating-point status and control register fpscr cr 0 31 031 031 gpr0 gpr1 gpr31 user-level sprs integer exception register (xer) link register (lr) count register (ctr) 0 31 0 63 031 time base lower ? read (tbl) time base upper ? read (tbu) time base facility (for reading) user model uisa fpr0 fpr1 fpr31 see ta b l e 3 - 2 for list of supervisor-level sprs. see ta b l e 3 - 3 for list of development-support sprs. 31 0 031 central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-9 table 3-2 lists the mpc561/mpc563 supervisor-l evel registers; refer also to chapter 6, ?system configuration and protection ,? chapter 11, ?l-bus to u-bus interface (l2u) ,? and chapter 4, ?burst buffer controller 2 module ,? for more information. table 3-2. supervisor-level sprs spr number (decimal) special-purpose register 18 dae/source instruction service register (dsisr) see section 3.9.2, ?dae/source instruction service register (dsisr) ,? for bit descriptions. 19 data address register (dar) see section 3.9.3, ?data address register (dar) ,? fo r b it descriptions. 22 decrementer register (dec) see section 6.1.6, ?decrementer (dec) .? for bi t descriptions. 26 save and restore register 0 (srr0) see section 3.9.6, ?machine status save/restore register 0 (srr0) ,? for bit descriptions. 27 save and restore register 1 (srr1) see section 3.9.7, ?machine status save/restore register 1 (srr1) ,? for bit descriptions. 80 external interrupt enable (eie) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers .? 81 external interrupt disable (eid) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers .? 82 non-recoverable interrupt (nri) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers .? 272 spr general 0 (sprg0) 1 see section 3.9.8, ?general sprs (sprg0?sprg3) ,? for bit descriptions. 273 spr general 1 (sprg1) 1 see section 3.9.8, ?general sprs (sprg0?sprg3) ,? for bit descriptions. 274 spr general 2 (sprg2) see section 3.9.8, ?general sprs (sprg0?sprg3) ,? for bit descriptions. 275 spr general 3 (sprg3) see section 3.9.8, ?general sprs (sprg0?sprg3) ,? for bit descriptions. 284 time base lower ? write (tbl) see section 6.1.7, ?time base (tb) .? 285 time base upper ? write (tbu) see section 6.1.7, ?time base (tb) .? central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-10 freescale semiconductor 287 processor version register (pvr) see ta bl e 3 - 1 4 for bit descriptions. 528 impu global region attribute (mi_gra) 1 see ta bl e 4 - 8 for bit descriptions. 536 l2u region attribute (l2u_gra) see table 11-10 for bit descriptions. 560 bbc module configuration register (bbc_mcr) 1 see ta bl e 4 - 4 for bit descriptions. 568 l2u module configuration register (l2u_mcr) 1 see ta bl e 1 1 - 7 for bit descriptions. 784 l2u region base address register 0 (l2u_rba0) 1 see ta bl e 4 - 5 for bit descriptions. 785 impu region base address register 1 (mi_rba1) 1 see ta bl e 4 - 5 for bits descriptions. 786 impu region base address register 2 (mi_rba2) 1 see ta bl e 4 - 5 for bits descriptions. 787 impu region base address register 3 (mi_rba3) 1 see ta bl e 4 - 5 for bits descriptions. 816 impu region attribute register 0 (mi_ra0) 1 . see ta b l e 4 - 6 for bits descriptions. 817 impu region attribute register 1 (mi_ra1) 1 . see ta b l e 4 - 6 for bits descriptions. 818 impu region attribute register 2 (mi_ra2) 1 . see ta b l e 4 - 6 for bits descriptions. 819 impu region attribute register 3(mi_ra3) 1 . see ta b l e 4 - 6 for bits descriptions. 792 l2u region base address register 0 (l2u_rba0) 1 see ta bl e 1 1 - 8 for bit descriptions. 793 l2u region base address register 1 (l2u_rba1) 1 see ta bl e 1 1 - 8 for bit descriptions. 794 l2u region base address register 2 (l2u_rba2) 1 see ta bl e 1 1 - 8 for bit descriptions. 795 l2u region base address register 3 (l2u_rba3) 1 see ta bl e 1 1 - 8 for bit descriptions. 824 l2u region attribute register 0 (l2u_ra0) 1 see ta bl e 1 1 - 9 for bit descriptions. 825 l2u region attribute register 1 (l2u_ra1) 1 see ta bl e 1 1 - 9 for bit descriptions. 826 l2u region attribute register 2 (l2u_ra2) 1 see ta bl e 1 1 - 9 for bit descriptions. table 3-2. supervisor-level sprs (continued) spr number (decimal) special-purpose register central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-11 table 3-3 lists the rcpu sprs used for development support. 827 l2u region attribute register 3 (l2u_ra3) 1 see ta bl e 1 1 - 9 for bit descriptions. 1022 floating-point exceptio n cause register (fpecr) 1 see section 3.9.10.2, ?floating-point exception cause register (fpecr) ,? for bit descriptions. 1 implementation-specific spr, no t defined by the powerpc isa architecture. table 3-3. development support sprs 1 spr number (decimal) special-purpose register 144 comparator a value register (cmpa) see table 23-17 for bit descriptions. 145 comparator b value register (cmpb) see table 23-17 for bit descriptions. 146 comparator c value register (cmpc) see table 23-17 for bit descriptions. 147 comparator d value register (cmpd) see table 23-17 for bit descriptions. 148 exception cause register (ecr) see table 23-18 for bit descriptions. 149 debug enable register (der) see table 23-19 for bit descriptions. 150 breakpoint counter a value and control (counta) see table 23-20 for bit descriptions. 151 breakpoint counter b value and control (countb) see table 23-21 for bit descriptions. 152 comparator e value register (cmpe) see table 23-22 for bit descriptions. 153 comparator f value register (cmpf) see table 23-22 for bit descriptions. 154 comparator g value register (cmpg) see table 23-23 for bit descriptions. 155 comparator h value register (cmph) see table 23-23 for bit descriptions. 156 l-bus support comparators control 1 (lctrl1) see table 23-24 for bit descriptions. 157 l-bus support comparators control 2 (lctrl2) see table 23-25 for bit descriptions. table 3-2. supervisor-level sprs (continued) spr number (decimal) special-purpose register central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-12 freescale semiconductor unless otherwise noted, reserved fields should be written with a zero when written and return zero when read. an exception to this rule is xer[16:23]; see section 3.7.5, ?integer exception register (xer) .? these bits are set to the value written to them and return that value when read. 3.7 user instruction set architecture (uisa) register set the uisa registers can be accessed by either user- or supervisor-l evel instructions. the general-purpose registers are accessed th rough instruction operands. 3.7.1 general-purpose registers (gprs) integer data is manipulated in the integer unit?s thir ty-two 32-bit gprs, shown be low. these registers are accessed as source and destin ation registers through operands in the instruction syntax. 3.7.2 floating-point registers (fprs) the powerpc isa architecture provi des 32 64-bit fprs. these regist ers are accessed as source and destination registers through operands in floati ng-point instructions. each fpr supports the double-precision, floating-point format. every instruction that interp rets the contents of an fpr as a 158 i-bus support control register (ictrl) see table 23-26 for bit descriptions. 159 breakpoint address register (bar) see table 23-28 for bit descriptions. 630 development port data register (dpdr) see section 23.6.13, ?development port data register (dpdr) ,? for bit descriptions. 1 all development-support sprs are implementation-specific. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 gpr0 gpr1 . . . . . . gpr31 reset unchanged figure 3-4. general-purpose registers (gprs) table 3-3. development support sprs 1 (continued) spr number (decimal) special-purpose register central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-13 floating-point value does so using th e double-precision floating-point form at. therefore, all floating-point numbers are stored in double-precision format. all floating-point arithmetic instru ctions operate on data located in fprs and, with the exception of the compare instructions (which update the cr), place the re sult into an fpr. information about the status of floating-point operations is placed into the floating-point status a nd control register ( fpscr) and in some cases, after the completion of the operation?s writeback stage, into the cr. for information on how the cr is affected by floati ng-point operations, see section 3.7.4, ?condition register (cr) .? 3.7.3 floating-point status and control register (fpscr) the fpscr controls the handling of floating-point ex ceptions and records status resulting from the floating-point operations. fpscr[ 0:23] are status bits. fpsc r[24:31] are control bits. fpscr[0:12] and fpscr[21:23] are floating-point exception condition bi ts. these bits are sticky, except for the floating-point enabled exception summary (f ex) and floating-point i nvalid operation exception summary (vx). once set, sticky bits remain set until th ey are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction. table 3-4 summarizes which bits in the fpscr are sticky status bits, which are normal status bits, and which are control bits. fex and vx are the logical ors of other fpscr bits . therefore these two bits are not listed among the fpscr bits directly affected by the various instructions. msb 0 lsb 63 fpr0 fpr1 . . . . . . fpr31 reset unchanged figure 3-5. floating-point registers (fprs) table 3-4. fpscr bit categories bits type [0], [3:12], [21:23] status, sticky [1:2], [13:20] status, not sticky [24:31] control central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-14 freescale semiconductor a listing of fpscr bit settings is shown in table 3-5 . msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field fx fex vx ox ux zx xx vxsn an vxisi vxidi vxzdz vximz vxvc fr fi fprf0 reset unchanged 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field fprf[1:4] 0 vx soft vx sqrt vxcvi ve oe ue ze xe ni rn reset unchanged figure 3-6. floating-point status and control register (fpscr) table 3-5. fpscr bit descriptions bits name description 0 fx floating-point exception summary. ever y floating-point instruction implicitly sets fpscr[fx] if that instruction caus es any of the floating-point exception bits in the fpscr to change from 0 to 1. the mcrfs instruction implicitly clears fpscr[fx] if the fpscr field contai ning fpscr[fx] has been copied. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 inst ructions can set or clear fpscr[fx] explicitly. sticky bit 1 fex floating-point enabled exception summ ary. this bit signals the occurrence of any of the enabled exception conditions. it is the logical or of all the floating-point exception bits masked with their respective enable bits. the mcrfs instruction implicitly clears fpscr[ fex] if the result of the logical or described above becomes zero. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear fpscr[fex] explicitly. not sticky 2 vx floating-point invalid operation exception summary. this bit signals the occurrence of any invalid operation exceptio n. it is the logical or of all of the invalid operation exceptions. the mcrf s instruction implicitly clears fpscr[vx] if the result of the logical or described above becomes zero. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 instru ctions cannot set or clear fpscr[vx] explicitly. not sticky 3 ox floating-point overflow exception. sticky bit 4 ux floating-point underflow exception. sticky bit 5 zx floating-point zero divide exception. sticky bit 6 xx floating-point inexact exception. sticky bit 7 vxsnan floating-point invalid operation exception for snan. sticky bit 8 vxisi floating-point invalid operation exception for - . sticky bit 9 vxidi floating-point invalid operation exception for / . sticky bit 10 vxzdz floating-point invalid operation exception for 0/0. sticky bit 11 vximz floating-point invalid operation exception for x 0. sticky bit central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-15 12 vxvc floating-point invalid operation exception for invalid compare. sticky bit 13 fr floating-point fraction rounded. th e last floating-point instruction that potentially rounded the intermediate result incremented the fraction. not sticky 14 fi floating-point fraction inexact. t he last floating-point instruction that potentially rounded the intermediate result produced an inexact fraction or a disabled exponent overflow. not sticky [15:19] fprf floating-point result flags. this field is based on the value placed into the target register even if that value is undefined. refer to ta b l e 3 - 6 for specific bit settings. 15 floating-point result class descriptor (c). floating-point instructions other than the compare instructions may se t this bit with the fpcc bits, to indicate the class of the result. 16-19 floating-point condition code (fpcc). floating-point compare instructions always set one of the fpcc bits to one and the other three fpcc bits to zero. other floating-point instructions may set the fpcc bits with the c bit, to indicate the class of the result. note that in this case the high-order three bits of the fpcc retain their relational significance indicating that the value is less than, greater than, or equal to zero. 16 floating-point less than or negative (fl or <) 17 floating-point greater than or positive (fg or >) 18 floating-point equal or zero (fe or =) 19 floating-point unordered or nan (fu or ?) not sticky 20 ? reserved ? 21 vxsoft floating-point invalid operation exception for softwa re request. this bit can be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. the purpose of vxsoft is to allow softw are to cause an invalid operation condition for a condition that is not nec essarily associated with the execution of a floating-point instruction. for example, it might be set by a program that computes a square root if the source operand is negative. sticky bit 22 vxsqrt floating-point invali d operation exception for invalid square root. this guarantees that software can simulate fsqrt and frsqrte, and can provide a consistent interface to handle excepti ons caused by square root operations. sticky bit 23 vxcvi floating-point invalid operation exception for invalid integer convert. sticky bit 24 ve floating-point invalid operation exception enable. ? 25 oe floating-point overflow exception enable. ? 26 ue floating-point underflow exception enable. this bit should not be used to determine whether denormalization should be performed on floating-point stores. ? 27 ze floating-point zero divide exception enable. ? 28 xe floating-point inexact exception enable. ? table 3-5. fpscr bit descriptions (continued) bits name description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-16 freescale semiconductor table 3-6 illustrates the floating-point resu lt flags that correspond to fpscr[15:19]. 3.7.4 condition register (cr) the condition register (cr) is a 32-bit register that reflects the resu lt of certain operat ions and provides a mechanism for testing and branching. the bits in the cr are grouped into eight 4-bit fields: cr0 to cr7. the cr fields can be set in the following ways: ? specified fields of the cr can be set by an in struction (mtcrf) to move to the cr from a gpr. ? specified fields of the cr can be moved from one crx field to another with the mcrf instruction. ? a specified field of the cr can be set by an inst ruction (mcrxr) to move to the cr from the xer. ? condition register logical instruct ions can be used to perform l ogical operations on specified bits in the condition register. ? cr0 can be the implicit result of an integer operation. 29 ni non-ieee mode bit. ? 30?31 rn floating-point rounding control. 00 round to nearest 01 round toward zero 10 round toward +infinity 11 round toward -infinity ? table 3-6. floating-point result flags in fpscr result flags (bits 15:19) c<>=? result value class 10001 quiet nan 01001 ? infinity 01000 ? normalized number 11000 ? denormalized number 10010 ? zero 00010 + zero 10100 + denormalized number 00100 + normalized number 00101 + infinity msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 reset unchanged figure 3-7. condition register (cr) table 3-5. fpscr bit descriptions (continued) bits name description central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-17 ? a specified cr field can be the explicit result of an integer compare instruction. instructions are provided to test individual cr bits. 3.7.4.1 condition register cr0 field definition in most integer instructions, when th e cr is set to reflect the result of the operation (that is, when rc = 1), and for addic., andi., and andis., the fi rst three bits of cr0 are set by an algebraic comparison of the result to zero; the fourth bit of cr0 is c opied from xer[so]. for integer inst ructions, cr0[0:3] are set to reflect the result as a signed quantity. th e eq bit reflects the result as an unsigned quantity or bit string. the cr0 bits are interpreted as shown in table 3-7 . if any portion of the result (the 32-bit value placed into the destination register) is undefined, the value pl aced in the first three bits of cr0 is undefined. 3.7.4.2 condition register cr1 field definition in all floating-point instructions when the cr is set to reflect the result of the operation (that is, when rc = 1), the cr1 field (bits 4 to 7 of the cr) is copi ed from fpscr[0:3] to i ndicate the floating-point exception status. for more info rmation about the fpscr, see section 3.7.3, ?floating-point status and control register (fpscr) .? the bit settings for the cr1 field are shown in table 3-8 . 3.7.4.3 condition register cr n field ? compare instruction when a specified cr field is set by a compare instruction, the b its of the specified fi eld are interpreted as shown in table 3-9 . a condition register field can also be accessed by the mfcr, mcrf, and mtcrf instructions. table 3-7. bit settings for cr0 field of cr cr0 bit description 0 negative (lt). this bit is set when the result is negative. 1 positive (gt). this bit is set when the result is positive (and not zero). 2 zero (eq). this bit is set when the result is zero. 3 summary overflow (so). this is a copy of the final state of xer[so] at the co mpletion of the instruction. table 3-8. bit settings for cr1 field of cr cr1 bit description 0 floating-point exception (fx). this is a copy of t he final state of fpscr[fx] at the completion of the instruction. 1 floating-point enabled exception (fex).this is a copy of the final state of fpscr[f ex] at the completion of the instruction. 2 floating-point invalid exception (vx).this is a copy of the final state of fpscr[vx] at the completion of the instruction. 3 floating-point overflow exception (ox).this is a copy of the final state of fpscr[ox] at the completion of the instruction. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-18 freescale semiconductor 3.7.5 integer exception register (xer) the integer exception register (xer), sp r 1, is a user-level, 32-bit register. the bit descriptions for xer, shown in table 3-10 , are based on the operation of an instruction considered as a whole, not on intermediate resu lts. for example, the result of the subtract from carrying (subfcx) instruction is specified as the sum of three values. this instruction sets bits in the xer based on the entire operation, not on an intermediate sum. in most cases, reserved fields in registers are ignored when written to and return zero when read. however, xer[16:23] are set to the value written to them and return that value when read. table 3-9. cr n field bit settings for compare instructions cr n bit 1 1 here, the bit indicates the bit number in any one of the four-bit subfields, cr0?cr7 description 0 less than, floating-point less than (lt, fl). for integer compare instructions, (ra) < simm, uimm, or (rb) (algebraic compar ison) or (ra) simm, uimm, or (rb) (logical comparison). for floating- point compare instructions, (fra) < (frb). 1 greater than, floating-poi nt greater than (gt, fg). for integer compare instructions, (ra) > simm, uimm, or (rb) (algebraic compar ison) or (ra) simm, uimm, or (rb) (logical comparison). for floating- point compare instructions, (fra) > (frb). 2 equal, floating-point equal (eq, fe). for integer compare instructions, (ra) = simm, uimm, or (rb). for floating-point compare in structions, (fra) = (frb). 3 summary overflow, floating-point unordered (so, fu). for integer compare instructions, this is a copy of the final state of xer[so] at the completion of the instruction. for floating-point compare instructions, one or both of (fra) and (frb) is not a number (nan). msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field so ov ca ? bytes reset unchanged 00_0000_0000_0000_0000_0 unchanged addr spr 1 figure 3-8. integer exception register (xer) table 3-10. integer exception register bit descriptions bits name description 0 so summary overflow (so). the summary overflow bit is set whenever an instruction sets the overflow bit (ov) to indicate overflow and remain s set until software clears it. it is not altered by compare instructions or other inst ructions that cannot overflow. 1 ov overflow (ov). the overflow bit is set to indica te that an overflow has occurred during execution of an instruction. integer and subtract instructions having oe=1 set ov if the carry out of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. the ov bit is not altered by compare instructions or other instru ctions that cannot overflow. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-19 3.7.6 link register (lr) the link register (lr), spr 8, supplies the branch target address for the branch conditional to link register (bclrx) instruction, and can be used to hold the logical address of the in struction that follows a branch and link instruction. note that although the two least-signi ficant bits can accept any values written to them, they are ignored when the lr is used as an address. both conditional and unconditional branch instructions include the option of placing the effective address of the instruction after the branch instruction in the lr. this is done regardless of whether the branch is taken. 3.7.7 count register (ctr) the count register (ctr), spr 9, is used to hold a loop count that can be d ecremented during execution of branch instructions with an appropriately coded bo field. if the value in ctr is 0 before being decremented, it is ?1 afterward. the count register provides the branch target address for the branch conditional to count regist er (bcctrx) instructio 2 ca carry (ca). in general, the carry bit is set to indicate that a carry out of bit 0 occurred during execution of an instruction. add carrying, subt ract from carrying, add extended, and subtract from extended instructions set ca if there is a ca rry out of bit 0, and cl ear it otherwise. the ca bit is not altered by compare instructions or other instructions that cannot carry, except that shift right algebraic instructions set the ca bit to indicate whether any ?1? bits have been shifted out of a negative quantity. 3:24 ? reserved 25:31 bytes this field specifies the number of bytes to be transferred by a load string word indexed (lswx) or store string word inde xed (stswx) instruction. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field branch address reset unchanged addr spr 8 figure 3-9. link register (lr) msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field loop count reset unchanged addr spr 9 figure 3-10. count register (ctr) table 3-10. integer exception register bit descriptions bits name description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-20 freescale semiconductor 3.8 vea register set ? time base (tb) the virtual environment arch itecture (vea) defines registers in addi tion to the uisa register set. the vea register set can be acces sed by all software with either user- or supervisor-level privileges. refer to section 6.1.7, ?time base (tb) ,? for more information. 3.9 oea register set the operating environment architect ure (oea) includes a number of spr s and other registers that are accessible only by supervisor-level instructions. some sprs are rcpu -specific; some rcpu sprs may not be implemented in other powerpc isa processo rs, or may not be implemented in the same way. 3.9.1 machine state register (msr) the machine state register is a 32-bit register that de fines the state of the proc essor. when an exception occurs, the contents of the msr are loaded in to srr1, and the msr is updated to reflect the exception-processing machine state. the msr can also be modified by the mtmsr, sc, and rfi instructions. it can be read by the mfmsr instruction. 11 table 3-11 shows the bit definitions for the msr. msb 012 3 45678 9101112 13 1415 field ? pow 0 ile sreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ee pr fp me fe0 se be fe1 ? ip ir dr ? dcmpen 1 1 this bit is available only on code compression-enabled options of the mpc561/mpc563. ri le sreset 000 u 0000_0 id1 2 2 the reset value is a reset configuration word val ue extracted from the internal bus line. refer to section 7.5.2, ?hard reset configuration word (rcw) .? 000 x 3 3 the reset value is defined by the equation "bbcmcr[en_comp] and bbcmcr[exc_comp]". at hreset the bbcmcr[en_comp] and bbcmcr[exc_comp] bits recieve their values from rcw bits 21 and 22. the bbcmcr does not change at sreset . thus the dcmpen reset value may be different on sreset and hreset , if software changes these bbcmcr bits from their reset values. 00 figure 3-11. machine state register (msr) table 3-11. machine state register bit descriptions bits name description 0:12 ? reserved 13 pow power management enable. 0 power management disabled (normal operation mode) 1 power management enabled (reduced power mode) central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-21 14 ? reserved 15 ile exception little-endian mode. when an exception occurs, this bit is copied into msr[le] to select the endian mode for the context establis hed by the exception. little-endian mode is not supported on the mpc561/mpc563. this bi t should be cleared to 0 at all times. 0 the processor runs in big-endian mode during exception processing. 1 the processor runs in little-endian mode during exception processing. 16 ee external interrupt enable. interrupts should only be negated while the ee bit is disabled (0). software should disable interrupts (ee = 0) in the rcpu before clearing or masking any interrupt source from the usiu or external pins . for external interrupts, it is recommended that the edge-triggered interrupt scheme be used. see section 6.1.4, ?enh anced interrupt controller .? 0 the processor delays recognition of extern al interrupts and decrementer exception conditions. 1 the processor is enabled to take an external interrupt or the decrementer exception. 17 pr privilege level. 0 the processor can execute both user- and supervisor-level instructions. 1 the processor can only execute user-level instructions. 18 fp floating-point available. 0 the processor prevents dispatch of floating-poin t instructions, including floating-point loads, stores and moves. floating-point enabled progra m exceptions can still occur and the fprs can still be accessed. 1 the processor can execute floating-point instructions, and can take floating-point enabled exception type program exceptions. 19 me machine check enable. 0 machine check exceptions are disabled. 1 machine check exceptions are enabled. 20 fe0 floating-point exception mode 0 (see ta b l e 3 - 1 2 .) 21 se single-step trace enable. 0 the processor executes instructions normally. 1 the processor generates a single-step trace e xception when the next instruction executes successfully. when this bit is se t, the processor dispatches in structions in strict program order. successful execution means the in struction caused no other exception. 22 be branch trace enable. 0 no trace exception occurs when a branch instruction is completed. 1 trace exception occurs when a branch instruction is completed. 23 fe1 floating-point exception mode 1 (see ta b l e 3 - 1 2 ). 24 ? reserved 25 ip exception prefix. the setting of this bit specifies the location of the exception vector table. 0 exception vector table starts at the physical address 0x0000 0000. 1 exception vector table starts at the physical address 0xfff0 0000. 26 ir instruction relocation. 0 instruction address translation is off; the bbc impu does not check for address permission attributes. 1 instruction address translation is on; the bbc impu checks for address permission attributes. table 3-11. machine state register bit descriptions (continued) bits name description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-22 freescale semiconductor the floating-point exception mode bi ts are interpreted as shown in table 3-12 . 3.9.2 dae/source instruction service register (dsisr) the dsisr, spr 18, identifies the cause of data access and alignment exceptions. for more information about bit settings, see section 3.15.4.2, ?machine check exception (0x0200) ,? section 3.15.4.6, ?alignment exception (0x00600) ,? and section 3.15.4.15, ?implementation-specific data protection error exception (0x1400) .? 27 dr data relocation. 0 data address translation is off; the l2u dmpu does not check for address permission attributes. 1 data address translation is on; the l2u dmpu checks for addressn permission attributes. 28 ? reserved 29 dcmpen decompression on/off. the reset valu e of this bit is (bbcmcr[en_comp] and bbcmcr[exc_comp]). note: this bit should not be set for the mpc561/mpc563. 0 the rcpu runs in normal operation mode. 1 the rcpu runs in compressed mode. note: msr[dcmpen] should not be changed by soft ware by a direct msr register write (mtmsr instruction). it can be changed only by the rfi instruction or by an exception. 30 ri recoverable exception (for machine check and non-maskable breakpoint exceptions). 0 machine state is not recoverable. 1 machine state is recoverable. 31 le little-endian mode. this mode is not s upported on mpc561/mpc563. this bit should be cleared to 0 at all times. 0 the processor operates in big-endian mode during normal processing. 1 the processor operates in little-endian mode during normal processing. table 3-12. floating-point exception mode bits fe[0:1] mode 00 ignore exceptions mode. floating-poi nt exceptions do not cause the floating-point assist error handler to be invoked. 01, 10, 11 floating-point precise mode. the system floating-poi nt assist error handler is invoked precisely at the instruction that caused the enabled exception. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field dsisr reset unchanged addr spr 18 figure 3-12. dae/source instruction service register (dsisr) table 3-11. machine state register bit descriptions (continued) bits name description central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-23 3.9.3 data address register (dar) after an alignment exception, the dar, spr 19, is set to the effective a ddress of a load or store element. 3.9.4 time base facility (tb) ? oea refer to section 6.1.7, ?time base (tb) ,? for information. 3.9.5 decrementer register (dec) refer to section 6.1.6, ?decrementer (dec) ,? for information. 3.9.6 machine status save/restore register 0 (srr0) the machine status save/r estore register 0 (srr0), spr 26, iden tifies where instruction execution should resume when an rfi instruction is executed following an exception. it also holds the effective address of the instruction that follows the system call (sc) instruction. when an exception occurs, srr0 is set to point to an instruction such that all prior instructions have completed execution and no subseque nt instruction has begun executi on. the instruction addressed by srr0 may not have completed execution, depending on the exception type. srr0 addresses either the instruction causing the exception or the instruction immediately follow ing. the instruction addressed can be determined from the exception type and status bits. 3.9.7 machine status save/restore register 1 (srr1) the machine status save/restore register 1 (srr1) , spr 27, saves the machine status on exceptions and restores the machine status when an rfi instruction is executed. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field data address reset unchanged addr spr 19 figure 3-13. data address register (dar) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field srr0 reset undefined addr spr 26 figure 3-14. machine status save/restore register 0 (srr0) central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-24 freescale semiconductor in general, when an exception occurs, srr1[0:15] are loaded with exception-specific information, and msr[16:31] are place d into srr1[16:31]. 3.9.8 general sprs (sprg0?sprg3) sprg0?sprg3, sprs 272-275, are provided for general ope rating system use, such as fast-state saves and multiprocessor-implementation s upport. sprg0?sprg3 are shown below. uses for sprg0?sprg3 are shown in table 3-13 . msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field srr1 reset undefined addr spr 27 figure 3-15. machine status save/restore register 1 (srr1) msb 0 123456789101112131415161718192021222324252627282930 lsb 31 sprg0 sprg1 sprg2 sprg3 reset unchanged figure 3-16. sprg0?sprg3 ? general special-purpose registers 0?3 table 3-13. uses of sprg0?sprg3 register description sprg0 software may load a unique physical address in this register to identify an area of memory reserved for use by the exception handler. this area must be unique for each processor in the system. sprg1 this register may be used as a scratch register by the exception handler to save the content of a gpr. that gpr then can be loaded from sprg0 and used as a base register to save other gprs to memory. sprg2 this register may be used by the operating system as needed. sprg3 this register may be used by the operating system as needed. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-25 3.9.9 processor version register (pvr) the pvr is a 32-bit, read-only regist er that identifies the version and revision level of the processor. the contents of the pvr can be copied to a gpr by the mf spr instruction. read access to the pvr is available in supervisor mode only; write access is not provided. 3.9.10 implementation-specific sprs the mpc561/mpc563 includes several implementatio n-specific sprs that are not defined by the powerpc isa architecture. these registers, listed in table 3-2 and table 3-3 , can be accessed by supervisor-level instructions only. 3.9.10.1 eie, eid, and nri special-purpose registers the rcpu includes three implementation-specific sprs that facilitate the software manipulation of the msr[ri] and msr[ee] bits: external interrupt enable (eie), extern al interrupt disable (eid), and non-recoverable interrupt (nri). i ssuing the mtspr instruction with one of these regist ers as an operand causes the ri and ee bits to be set or cleared as shown in table 3-15 . a read (mfspr) of any of these locati ons is treated as an uni mplemented instruction, re sulting in a software emulation exception. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field version revision reset 0000_0000_0000_0010 0000_0000_0010_0000 addr spr 287 figure 3-17. processor version register (pvr) table 3-14. processor version register bit descriptions bits name description 0:15 version a 16-bit number that id entifies the version of the powerp c isa processor. the rcpu value is 0x0002. 16:31 revision a 16-bit number that distinguishes betw een various releases of a particular version. the rcpu value is 0x0020. table 3-15. eie, eid, and nri registers spr number (decimal) mnemonic msr[ee] msr[ri] 80 eie 1 1 81 eid 0 1 82 nri 0 0 central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-26 freescale semiconductor 3.9.10.2 floating-point exception cause register (fpecr) the fpecr, spr 1022, is a supervisor-level internal status and control register used by the user?s floating-point assist software envelope . it contains four status bits that indicate whether the result of the operation is tiny and whether any of three source opera nds are denormalized. in addition, it contains one control bit to enable or disable sie mode. this register must not be accessed by user code. a listing of fpecr bit settings is shown in table 3-16 . note software must insert a sync inst ruction before reading the fpecr. msb 0123456789101112131415 field sie ? sreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? dnc dnb dna tr sreset 0000_0000_0000_0000 addr spr 1022 figure 3-18. floating-point ex ception cause register (fpecr) table 3-16. fpecr bit descriptions bits name description 0 sie synchronized ignore exception mode control bit. 0 disable sie mode 1 enable sie mode 1:27 ? reserved 28 dnc source operand c denormalized status bit. 0 source operand c is not denormalized 1 source operand c is denormalized 29 dnb source operand b denormalized status bit. 0 source operand b is not denormalized 1 source operand b is denormalized 30 dna source operand a denormalized status bit . 0 source operand a is not denormalized 1 source operand a is denormalized 31 tr floating-point tiny result. 0 floating-point result is not tiny 1 floating-point result is tiny central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-27 3.9.10.3 additional implemen tation-specific registers refer to the following sections for details on a dditional implementation-spec ific registers in the mpc561/mpc563: ? section 4.6, ?bbc programming model ? ? section 6.2.2.1.2, ?internal memo ry map register (immr) ? ? section 11.8, ?l2u programming model ? ? chapter 23, ?development support ? 3.10 instruction set all powerpc isa instructions are encoded as si ngle words (32 bits) and are consistent among all instruction types. the fixed instruction length and c onsistent format simplify instruction pipelining and permit efficient decoding to occur in parallel with operand accesses. the powerpc isa instructions are divi ded into the following categories: ? integer instructions, which include computational and l ogical instructions ? integer arithmetic instructions ? integer compare instructions ? integer logical instructions ? integer rotate and shift instructions ? floating-point instructions, whic h include floating-point computati onal instructions, as well as instructions that affect the floating-po int status and control register (fpscr) ? floating-point arit hmetic instructions ? floating-point mult iply/add instructions ? floating-point rounding a nd conversion instructions ? floating-point compare instructions ? floating-point status and control instructions ? load/store instructions., which include integer and floating-point load and store instructions ? integer load and store instructions ? integer load and store multiple instructions ? floating-point load and store ? primitives used to construc t atomic memory operations (l warx and stwcx. instructions) ? flow control instructions, which include bran ching instructions, condi tion register logical instructions, trap instructions, and other in structions that affect the instruction flow ? branch and trap instructions ? condition register logical instructions ? processor control instructio ns, which are used for synchronizing memory accesses. ? move to/from spr instructions ? move to/from msr central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-28 freescale semiconductor ? synchronize ? instruction synchronize note this grouping of the instructions doe s not indicate which execution unit executes a particular instruct ion or group of instructions. integer instructions operate on byte , half-word, and word operands. floa ting-point instructions operate on single-precision (one word) and double-precision ( one double word) floating-point operands. the powerpc isa architecture uses instru ctions that are four bytes long a nd word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 gprs. computational instructions do not modify memory. to use a memory operand in a computation and then modify the same or another memory location, the memory contents mu st be loaded into a register, modified, and then written back to the ta rget location with di stinct instructions. powerpc isa-compliant processors fo llow the program flow when they are in the normal execution state. however, the flow of instructions can be interrupted directly by the ex ecution of an instruction or by an asynchronous event. either kind of ex ception may cause one of several components of the system software to be invoked. 3.10.1 instruction set summary table 3-17 provides a summary of rcpu instructions. refer to the rcpu reference manual for a detailed description of the instruction set. table 3-17. instruction set summary mnemonic operand syntax name add (add. addo addo.) rd,ra,rb add addc (addc. addco addco.) rd,ra,rb add carrying adde (adde. addeo addeo.) rd,ra,rb add extended addi rd,ra,simm add immediate addic rd,ra,simm add immediate carrying addic. rd,ra,simm add immediate carrying and record addis rd,ra,simm add immediate shifted addme (addme. addmeo addmeo.) rd,ra add to minus one extended addze (addze. addzeo addzeo.) rd,ra add to zero extended and (and.) ra,rs,rb and andc (andc.) ra,rs,rb and with complement andi. ra,rs,uimm and immediate andis. ra,rs,uimm and immediate shifted b (ba bl bla) target_addr branch central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-29 bc (bca bcl bcla) bo,bi,target_addr branch conditional bcctr (bcctrl) bo,bi branch conditional to count register bclr (bclrl) bo,bi branch conditional to link register cmp crfd,l,ra,rb compare cmpi crfd,l,ra,simm compare immediate cmpl crfd,l,ra,rb compare logical cmpli crfd,l,ra,uimm compare logical immediate cntlzw (cntlzw.) ra,rs count leading zeros word crand crbd,crba,crbb condition register and crandc crbd,crba, crbb conditio n register and with complement creqv crbd,crba, crbb condition register equivalent crnand crbd,crba,crbb condition register nand crnor crbd,crba,crbb condition register nor cror crbd,crba,crbb condition register or crorc crbd,crba, crbb conditio n register or with complement crxor crbd,crba,crbb condition register xor divw (divw. divwo divwo.) rd,ra,rb divide word divwu divwu. divwuo divwuo. rd,ra,rb divide word unsigned eieio ? enforce in-order execution of i/o eqv (eqv.) ra,rs,rb equivalent extsb (extsb.) ra,rs extend sign byte extsh (extsh.) ra,rs ex tend sign half word fabs (fabs.) frd,frb floating absolute value fadd (fadd.) frd,fra,frb floating add (double-precision) fadds (fadds.) frd,fra,frb floating add single fcmpo crfd,fra,frb floating compare ordered fcmpu crfd,fra,frb float ing compare unordered fctiw (fctiw.) frd,frb floating convert to integer word fctiwz (fctiwz.) frd,frb floating convert to integer word with round toward zero fdiv (fdiv.) frd,fra,frb floating divide (double-precision) fdivs (fdivs.) frd,fra,frb floating divide single fmadd (fmadd.) frd,fra,frc,frb floating multiply-add (double-precision) table 3-17. instruction set summary (continued) mnemonic operand syntax name central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-30 freescale semiconductor fmadds (fmadds.) frd,fra,frc,frb f loating multiply-add single fmr (fmr.) frd,frb floating move register fmsub (fmsub.) frd,fra,frc,frb floating multiply-subtract (double-precision) fmsubs (fmsubs.) frd,fra,frc,frb fl oating multiply-subtract single fmul (fmul.) frd,fra,frc floating multiply (double-precision) fmuls (fmuls.) frd,fra,frc floating multiply single fnabs (fnabs.) frd,frb floating negative absolute value fneg (fneg.) frd,frb floating negate fnmadd (fnmadd.) frd,fra, frc,frb floating negative multiply-add (double- precision) fnmadds (fnmadds.) frd,fra,frc,frb floating negative multiply-add single fnmsub (fnmsub.) frd,fra,frc,frb fl oating negative multiply-subtract (double-precision) fnmsubs (fnmsubs.) frd,fra,frc,frb floating negative multiply-subtract single frsp (frsp.) frd,frb floating round to single fsub (fsub.) frd,fra,frb floating subtract (double-precision) fsubs (fsubs.) frd,fra,frb floating subtract single isync ? instruction synchronize lbz rd,d(ra) load byte and zero lbzu rd,d(ra) load byte and zero with update lbzux rd,ra,rb load byte and zero with update indexed lbzx rd,ra,rb load byte and zero indexed lfd frd,d(ra) load floating-point double lfdu frd,d(ra) load floating-point double with update lfdux frd,ra,rb load floating-point double with update indexed lfdx frd,ra,rb load floating-point double indexed lfs frd,d(ra) load floating-point single lfsu frd,d(ra) load floating-point single with update lfsux frd,ra,rb load floating-point single with update indexed lfsx frd,ra,rb load floating-point single indexed lha rd,d(ra) load half-word algebraic lhau rd,d(ra) load half-word algebraic with update lhaux rd,ra,rb load half-word algebraic with update indexed table 3-17. instruction set summary (continued) mnemonic operand syntax name central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-31 lhax rd,ra,rb load half-word algebraic indexed lhbrx rd,ra,rb load half-word byte-reverse indexed lhz rd,d(ra) load half-word and zero lhzu rd,d(ra) load half-word and zero with update lhzux rd,ra,rb load hal-word and zero with update indexed lhzx rd,ra,rb load half-word and zero indexed lmw rd,d(ra) load multiple word lswi rd,ra,nb load string word immediate lswx rd,ra,rb load string word indexed lwarx rd,ra,rb load word and reserve indexed lwbrx rd,ra,rb load word byte-reverse indexed lwz rd,d(ra) load word and zero lwzu rd,d(ra) load word and zero with update lwzux rd,ra,rb load word and zero with update indexed lwzx rd,ra,rb load word and zero indexed mcrf crfd,crfs move condition register field mcrfs crfd,crfs move to condition register from fpscr mcrxr crfd move to condition register from xer mfcr rd move from condition register mffs (mffs.) frd move from fpscr mfmsr rd move from ma chine state register mfspr rd,spr move from special purpose register mftb rd, tbr move from time base mtcrf crm,rs move to condition register fields mtfsb0 (mtfsb0.) crbd move to fpscr bit 0 mtfsb1 (mtfsb1.) crbd move to fpscr bit 1 mtfsf (mtfsf.) fm,frb move to fpscr fields mtfsfi (mtfsfi.) crfd,imm move to fpscr field immediate mtmsr rs move to machine state register mtspr spr,rs move to special purpose register mulhw (mulhw.) rd,ra,rb multiply high word mulhwu (mulhwu.) rd,ra,rb multiply high word unsigned mulli rd,ra,simm multiply low immediate table 3-17. instruction set summary (continued) mnemonic operand syntax name central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-32 freescale semiconductor mullw (mullw. mullwo mullwo.) rd,ra,rb multiply low nand (nand.) ra,rs,rb nand neg (neg. nego nego.) rd,ra negate nor (nor.) ra,rs,rb nor or (or.) ra,rs,rb or orc (orc.) ra,rs,rb or with complement ori ra,rs,uimm or immediate oris ra,rs,uimm or immediate shifted rfi ? return from interrupt rlwimi (rlwimi.) ra,rs,sh,mb,me rotate le ft word immediate then mask insert rlwinm (rlwinm.) ra,rs,sh,mb,me rotate left word immediate then and with mask rlwnm (rlwnm.) ra,rs,rb,mb,me rotate left word then and with mask sc ? system call slw (slw.) ra,rs,rb shift left word sraw (sraw.) ra,rs,rb shift right algebraic word srawi (srawi.) ra,rs,sh shift right algebraic word immediate srw (srw.) ra,rs,rb shift right word stb rs,d(ra) store byte stbu rs,d(ra) store byte with update stbux rs,ra,rb store byte with update indexed stbx rs,ra,rb store byte indexed stfd frs,d(ra) store floating-point double stfdu frs,d(ra) store floating-point double with update stfdux frs,rb store floating-point double with update indexed stfdx frs,rb store floating-point double indexed stfiwx frs,rb store floating-point as integer word indexed stfs frs,d(ra) store floating-point single stfsu frs,d(ra) store floating-point single with update stfsux frs,rb store floating-point single with update indexed stfsx frs,r b store floating-point single indexed sth rs,d(ra) store half-word table 3-17. instruction set summary (continued) mnemonic operand syntax name central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-33 note: the dot (.) suffix on a mnemonic indicates that the cr regist er update is enabled. the o suffix on a mnemonic indicates that the overflow bit update in the xer is enabled. 3.10.2 recommended simplified mnemonics to simplify assembly language coding, a set of altern ative mnemonics is provided for some frequently used operations (such as no-op, load immediate, load address, move register, and complement register). sthbrx rs,ra,rb store half-word byte-reverse indexed sthu rs,d(ra) store half-word with update sthux rs,ra,rb store half-word with update indexed sthx rs,ra,rb store half-word indexed stmw rs,d(ra) store multiple word stswi rs,ra,nb store st ring word immediate stswx rs,ra,rb store string word indexed stw rs,d(ra) store word stwbrx rs,ra,rb store word byte-reverse indexed stwcx. rs,ra,rb store word conditional indexed stwu rs,d(ra) store word with update stwux rs,ra,rb store word with update indexed stwx rs,ra,rb store word indexed subf (subf. subfo subfo.) rd,ra,rb subtract from subfc (subfc. subfco subfco.) rd,r a,rb subtract from carrying subfe (subfe. subfeo subfeo.) rd,r a,rb subtract from extended subfic rd,ra,simm subtract from immediate carrying subfme (subfme. subfmeo subfmeo.) rd,ra subtract from minus one extended subfze (subfze. subfzeo subfzeo.) rd,ra subtract from zero extended sync ? synchronize tw to,ra,rb trap word twi to,ra,simm trap word immediate xor (xor.) ra,rs,rb xor xori ra,rs,uimm xor immediate xoris ra,rs,uimm xor immediate shifted table 3-17. instruction set summary (continued) mnemonic operand syntax name central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-34 freescale semiconductor for a complete list of simplified mnemonics, see the rcpu reference manual . programs written to be portable across the various assemblers for the powe rpc isa architecture should not assume the existence of mnemonics not described in that manual. 3.10.3 calculating effective addresses the effective address (ea) is th e 32-bit address computed by the processor when executing a memory access or branch instruction or when fe tching the next sequential instruction. the powerpc isa architecture supports two simple memory addressing modes: ? ea = (ra|0) + 16-bit offset (including offset = 0) (register indirect with immediate index) ? ea = (ra|0) + rb (regist er indirect with index) these simple addressing modes allow efficient address generation for memory accesses. calculation of the effective address for aligned transf ers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is c onsidered to wrap around from the maximum effective address to effective address 0. effective address computations for both data a nd instruction accesses use 32-bit unsigned binary arithmetic. a carry from bit 0 is ignored in 32-bit implementations. 3.11 exception model the powerpc isa exception mechanism allows the processo r to change to supervisor state as a result of external signals, errors, or unusual c onditions that arise in the execution of instructions. when exceptions occur, information about the state of the processor is saved to certain registers, and the processor begins execution at an address (exception vector) predetermined for each ex ception. processing of exceptions occurs in supervisor mode. although multiple exception conditions can map to a si ngle exception vector, a more specific condition may be determined by examining a re gister associated with the excep tion ? for example, the dae/source instruction service register (dsisr). additionally, some ex ception conditions can be explicitly enabled or disabled by software. the powerpc isa architecture require s that exceptions be taken in pr ogram order; therefore, although a particular implementation may recogni ze exception conditions out of order, they are handled strictly in order with respect to the instruction stream. when an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, are required to complete before the exception is taken. for example, if a single instruction encounters multiple exce ption conditions, those exceptions ar e taken and handled sequentially. likewise, exceptions that are asynchronous and precis e are recognized when they occur, but are not handled until all instructions currently in the execu te stage successfully complete execution and report their results. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-35 note that exceptions can occur wh ile an exception handler routine is executing, and multiple exceptions can become nested. it is up to the exception handler to save the appropriate machin e state if it is desired that control be returned to the excepting program. in many cases, after the exception handler handles an exception, there is an attempt to execute the instruction that caused the exception. instruction execution continues until the next exception condition is encountered. this method of recognizing and handling exception conditions seque ntially guarantees that the machine state is recoverable and processing can resume without losing instruction results. to prevent the loss of state information, exception handl ers must save the information stored in srr0 and srr1 soon after the exception is taken to prevent this information from be ing lost due to another exception being taken. 3.11.1 exception classes the rcpu exception classes are shown in table 3-18 . 3.11.2 ordered exceptions in the rcpu, all exceptions except for reset, de bug port non-maskable interr upts, and machine check exceptions are ordered. orde red exceptions satisfy the following criteria: ? only one exception is reported at a time. if, for example, a single instruction encounters multiple exception conditions, those conditi ons are encountered sequentially. after the exception handler handles an exception, instruction execution cont inues until the next exception condition is encountered. ? when the exception is taken, no program state is lost. 3.11.3 unordered exceptions unordered exceptions may be reporte d at any time and are not guarant eed to preserve program state information. the processor can never recover from a reset exception. it can recover from other unordered exceptions in most cases. however, if a debug port non-maskable interrupt or machine check exception occurs during the servicing of a pr evious exception, the machine stat e information in srr0 and srr1 (and, in some cases, the dar and dsis r) may not be recoverable; the pr ocessor may be in the process of saving or restoring these registers. to determine whether the machine state is recoverable, the ri (recoverable exception) bit in srr1 can be read. during exception processing, the ri bit in th e msr is copied to srr1 and then cleared. the table 3-18. rcpu exception classes class exception type asynchronous, unordered machine check system reset asynchronous, ordered external interrupt decrementer synchronous (ordered, precise) instruction-caused exceptions central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-36 freescale semiconductor operating system should set th e ri bit in the msr at the end of eac h exception handler?s prologue (after saving the program state) and clear the bit at the start of each exception handler?s epilogue (before restoring the program state). then, if an unordered excepti on occurs during the serv icing of an exception handler, the ri bit in srr1 wi ll contain the correct value. 3.11.4 precise exceptions in the rcpu, all synchronous (instruction-caused) exceptions are precise. when a precise exception occurs, the processor backs the mach ine up to the instruction causing the exception. this ensures that the machine is in its correct architectu rally-defined state. the following co nditions exist at the point a precise exception occurs: 1. architecturally, no instruction following the faul ting instruction in the code stream has begun execution. 2. all instructions preceding the faulting instructi on appear to have completed with respect to the executing processor. 3. srr0 addresses either the instruction causi ng the exception or the immediately following instruction. which instruction is addressed can be determined from the exception type and the status bits. 4. depending on the type of exception, the instru ction causing the excep tion may not have begun execution, may have partially comple ted, or may have completed execution. 3.11.5 exception vector table the setting of the exception prefix (ip) bit in the msr determines how exceptions are vectored. if the bit is cleared, the exception vector table begins at the physical address 0x0000 0 000; if ip is set, the exception vector table begins at the physical address 0xfff0 0000. table 3-19 shows the exception vector offset of the first instruction of the exception ha ndler routine for each exception type. note in the mpc561/mpc563, the exception table can additionally be relocated by the bbc module to internal memory and reduce the total size required by the exception table (see section 4.3, ?exception table relocation (etr) .? table 3-19. exception vector offset table vector offset (hex) exception type section 00000 reserved ? 00100 system reset, nmi interrupt section 3.15.4.1, ?system reset exception and nmi (0x0100) ? 00200 machine check section 3.15.4.2, ?machine check exception (0x0200) ? 00300 data storage section 3.15.4.3, ?data storage exception (0x0300) ? 00400 reserved instruction storage 1 00500 external interrupt section 3.15.4.5, ?exter nal interrupt (0x0500) ? central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-37 3.12 instruction timing the rcpu processor is pipelined. becaus e the processing of an instruction is broken into a se ries of stages, an instruction does not require th e processor?s full resources. 00600 alignment section 3.15.4.6, ?alignm ent exception (0x00600) ? 00700 program section 3.15.4.7, ?progr am exception (0x0700) ? 00800 floating-point unavailable section 3.15.4.8, ?floating-point unavailable exception (0x0800) ? 00900 decrementer section 3.15.4.9, ?decreme nter exception (0x0900) ? 00a00 reserved ? 00b00 reserved ? 00c00 system call section 3.15.4.10, ?system call exception (0x0c00) ? 00d00 trace. section 3.15.4.11, ?trace exception (0x0d00) ? 00e00 floating-point assist section 3.15.4.12, ?floating-po int assist exception (0x0e00) ? 01000 implementation-dependent software emulation section 3.15.4.13, ?implementation-dependent software emulation exception (0x1000) ? 01100 reserved ? 01200 reserved ? 01300 implementation-dependent instruction protection exception section 3.15.4.14, ?implement ation-dependent instruction protection exception (0x1300) ? 01400 implementation-dependent data protection error section 3.15.4.15, ?imp lementation-specific data protection error exception (0x1400) ? 01500?01bff reserved ? 01c00 implementation-dependent data breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions ? 01d00 implementation-dependent instruction breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions ? 01e00 implementation-dependent maskable external breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions ? 01f00 implementation-dependent non-maskable external breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions ? 1 this exception will not be generated by hardware. table 3-19. exception vector offset table (continued) vector offset (hex) exception type section central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-38 freescale semiconductor the instruction pipeline in the mpc561/mpc563 has four stages: 1. the dispatch stage is implemented using a di stributed mechanism. the central dispatch unit broadcasts the instruction to all units. in a ddition, scoreboard information (regarding data dependencies) is broadcast to each execution unit. each execution unit decodes the instruction. if the instruction is not implemented, a program excep tion is taken. if the inst ruction is legal and no data dependency is found, th e instruction is accepted by the appropriate execut ion unit, and the data found in the destination register is copied to th e history buffer. if a da ta dependency exists, the machine is stalled until the dependency is resolved. 2. in the execute stage, each exec ution unit that has an executable in struction executes the instruction. (for some instructions, this occurs over multiple cycles.) 3. in the writeback stage, the execut ion unit writes the result to the de stination register and reports to the history buffer that the instruction is completed. 4. in the retirement stage, the history buffer retires instructions in architectural orde r. an instruction retires from the machine if it completes execut ion with no exceptions and if all instructions preceding it in the instruction st ream have finished execution with no exceptions. as many as six instructions can be retired in one clock. the history buffer maintains the corre ct architectural machin e state. an exception is taken only when the instruction is ready to be retired from the machine (i.e., after all previously-i ssued instructions have already been retired from the machine). when an exception is taken, all in structions following the excepting instruction are canceled, (i.e ., the values of the affected destin ation registers are restored using the values saved in the history buffer during the dispatch stage). figure 3-19 shows basic instruction pipeline timing. figure 3-19. basic instruction pipeline table 3-20 indicates the latency and blockage for each type of instruction. latency refers to the interval from the time an instruction begins execution until it produces a result that is available for use by a i1 i2 i1 i1 i1 store i3 i2 i2 i2 fetch decode read and execute write back (to dest reg) l address drive l data load write back branch decode branch execute i1 i1 i1 i1 load central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-39 subsequent instruction. blockage refers to the interval from the time an instruction begins execution until its execution unit is available for a subsequent instruction. note when the blockage equals the latency, it is not possible to issue another instruction to the same unit in the same cycle in which the first instruction is being written back. 3.13 user instruction set architecture (uisa) 3.13.1 computation modes the rcpu is a 32-bit implementation of the powerpc isa architecture. any reference in the powerpc isa architecture books (uisa, vea, oea) regard ing 64-bit implementations are not supported by the core. all registers except the floati ng-point registers are 32 bits wide. 3.13.2 reserved fields reserved fields in instructions are described unde r the specific instruction definition sections. unless otherwise noted, reserved fields s hould be written with a zero when wr itten and return a zero when read. thus, this type of invalid form instructions yield re sults of the defined instruct ions with the appropriate field zero. in most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any control register implemen ted by the mpc561/mpc563. exception to th is rule are bits [16:23] of the fixed-point exception cause register (xer) and the reserved bits of the machine state register (msr), which are set by the source value on write and return the value last set for it on read. table 3-20. instruction latency and blockage instruction type precision latency blockage floating-point multiply-add double single 7 6 7 6 floating-point add or subtract double single 4 4 4 4 floating-point multiply double single 5 4 5 4 floating-point divide double single 17 10 17 10 integer multiply ? 2 1 or 2 1 1 refer to section 7, ?instruction timing,? in the rcpu reference manual (rcpurm/ad) for details. integer divide ? 2 to 11 1 2 to 11 1 integer load/store ? see note 1 see note 1 central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-40 freescale semiconductor 3.13.3 classes of instructions non-optional instructions are im plemented by the hardware. optiona l instructions are executed by implementation-dependent code and any attempt to execute one of these commands causes the rcpu to take the implementation-dependent software emulat ion interrupt (offset 0x01000 of the vector table). illegal and reserved instruction cl ass instructions are supported by im plementation- dependent code and, thus, the rcpu hardware generates the implementati on-dependent software emul ation interrupt. invalid and preferred instruction forms treatment by the rcpu is described under the specific processor compliance sections. 3.13.4 exceptions invocation of the system software for any instruction-caused exception in the rcpu is precise, regardless of the type and setting. 3.13.5 branch processor the rcpu implements all th e instructions defined for the branch pr ocessor in the uisa in the hardware. 3.13.6 instruction fetching the core fetches a number of instructi ons into its internal buffer (the instruction pre-fetc h queue) prior to execution. if a program modifies the instructions it intends to execute, it should call a system library program to ensure that the modificat ions have been made visible to the instruction fetching mechanism prior to execution of the modified instructions. 3.13.7 branch instructions the core implements all the instructions defined fo r the branch processor by th e uisa in the hardware. for performance of various instructions, refer to table 3-20 of this manual. 3.13.7.1 invalid branch instruction forms bits marked with z in the bo encoding definition are discarded by the mpc561/mpc563 decoding. thus, these types of invalid form instructi ons yield results of the defined instru ctions with the z-bit zero. if the decrement and test ctr option is specified for the bcct r or bcctrl instructions, the target address of the branch is the new value of the ctr. condition is ev aluated correctly, including the value of the counter after decrement. 3.13.7.2 branch prediction the core uses the y bit to predict path for pr e-fetch. prediction is only done for not-ready branch conditions. no prediction is done for branches to the li nk or count register if the ta rget address is not ready. refer to the rcpu reference manual (conditional branch control) for more information. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-41 3.13.8 fixed-point processor 3.13.8.1 fixed-point instructions the core implements the following instructions: ? fixed-point arithmetic instructions ? fixed-point compare instructions ? fixed-point trap instructions ? fixed-point logical instructions ? fixed-point rotate and shift instructions ? move to/from system register instructions all instructions are define d for the fixed-point proce ssor in the uisa in the ha rdware. for performance of the various instructions, refer to table 3-20 . ? move to/from system register instructions. m ove to/from invalid spec ial registers in which spr0 = 1 yields invocation of the privilege instruction error inte rrupt handler if the processor is in problem state. for a list of all implemented special registers, refer to table 3-2 , and table 3-3 . ? fixed-point arithmetic instructions. if an atte mpt is made to perform any of the divisions in the divw[o][.] instruction (0x80000000 -1, central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-42 freescale semiconductor 3.13.10 load/store processor the load/store processor supports all of the 32-bit implementation fixed-point powerpc isa load/store instructions in the hardware. 3.13.10.1 fixed-point load with update and store with update instructions for load with update and store with update instructions , when ra = 0, the ea is written into r0. for load with update instructions, when ra = rd, ra is boundedly undefined. 3.13.10.2 fixed-point load and store multiple instructions for these types of instructions, ea must be a multiple of four. if it is not, the system alignment error handler is invoked. for a lmw instructi on (if ra is in the range of regist ers to be loaded), the instruction completes normally. ra is then loaded from the memory location as follows: ra mem(ea+(ra-rd)*4, 4) 3.13.10.3 fixed-point load string instructions load string instructions behave the same as load mult iple instructions, with respect to invalid format in which ra is in the range of registers to be loade d. when ra is in range, it is updated from memory. 3.13.10.4 storage synchronization instructions for these type of instructions, ea mu st be a multiple of four . if it is not, the system alignment error handler is invoked. 3.13.10.5 floating-point load and store with update instructions for load and store with update instructions, if rd = 0 then the ea is written into r0. 3.13.10.6 floating-point load single instructions when the operand falls in the range of a single denorm alized number, the floati ng-point assist interrupt handler is invoked. refer to the rcpu reference manual (floating-point assist for denor malized operands) for complete description of handling denorma lized floating-point numbers. 3.13.10.7 floating-point store single instructions when the operand falls in the range of a single denorm alized number, the floati ng-point assist interrupt handler is invoked. when the operand is zero it is converted to the correct signed zero in si ngle-precision format. when the operand is between the range of single denor malized and double denormalized it is considered a programming error. the hardware will handle this case as if the operand was single denormalized. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-43 when the operand falls in the range of double denormali zed numbers it is consid ered a programming error. the hardware will handle this ca se as if the operand was zero. the following check is done on the stored operand in order to determ ine whether it is a denormalized single-precision operand and invoke the floa ting-point assist interrupt handler: (frs[1:11] 0) and (frs[1:11] 896) eqn. 3-1 refer to the rcpu reference manual (floating-point assist for denormalized operands) for complete description of handling denorma lized floating-point numbers. 3.13.10.8 optional instructions no optional instructions are supported. 3.14 virtual environment architecture (vea) 3.14.1 atomic update primitives both the lwarx and stwcx instructions are implem ented according to the powerpc isa architecture requirements. the mpc561/mpc563 does not provide support for snooping an external bus activity outside the chip. the provision is ma de to cancel the reservation in side the mpc561/mpc563 by using the cr and kr input signals. internal buses are snooped for rcpu accesses, and the reservation mechanism can be used for multitask single master applications. 3.14.2 effect of operand pl acement on performance the load/store unit hardware supports all of the powerpc isa load/store in structions. an optimal performance is obtained for naturally aligned operands . these accesses result in optimal performance (one bus cycle) for up to four bytes in size and good performance (two bus cycles) for double precision floating-point operands. unaligned operands are supporte d in hardware and are broken into a series of aligned transfers. the effect of op erand placement on performance is as stated in the vea, except for the case of 8-byte operands. in that ca se, since the rcpu uses a 32-bit wi de data bus, the performance is good rather than optimal. 3.14.3 storage control instructions the rcpu does not implement the foll owing cache control instructions: ic bi, dcbt, dcbi, dc bf, dcbz, dcbst, and dcbtst . 3.14.4 instruction synchronize (isync) instruction the isync instruction causes a reflec t which waits for all prior instructions to complete and then executes the next sequential instruction. any instruction after an isync will see all effect s of prior instructions. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-44 freescale semiconductor 3.14.5 enforce in-order executio n of i/o (eieio) instruction when executing an eieio instruction, the load/store unit will wait until all previous accesses have terminated before issuing cycles associated with lo ad/store instructions following the eieio instruction. 3.14.6 time base a description of the time ba se register may be found in chapter 6, ?system confi guration and protection ,? and in chapter 8, ?clocks and power control .? 3.15 operating environment architecture (oea) the mpc561/mpc563 has an internal memory space that includes memo ry-mapped control registers and internal memory used by various modules on the chip. th is memory is part of the main memory as seen by the rcpu and can be accessed by an external system master. 3.15.1 branch processor registers 3.15.1.1 machine state register (msr) the floating-point exception mode enc oding in the rcpu is as shown in table 3-21 . : the sf bit is reserved set to zero. the ip bit initia l state after reset is set as programmed by the reset configuration as specified by the usiu characteristics. 3.15.1.2 branch processors instructions the rcpu implements all th e instructions defined for the branch pr ocessor in the uisa in the hardware. 3.15.2 fixed-point processor 3.15.2.1 special purpose registers ? unsupported registers ? the following regist ers are not supported by the mpc561/mpc563: sdr, ear, ibat0u, ibat0l, ibat1u, ib at1l, ibat2u, ibat2l, ibat3u, ibat3l, dbat0u, dbat0l, dbat1u, dbat1l, dbat2l, dbat3u, dbat3l. ? added registers ? for a li st of added special purpos e registers, refer to table 3-2 , and table 3-3 . table 3-21. floating-point exception mode encoding mode fe0 fe1 ignore exceptions 0 0 precise 0 1 precise 1 0 precise 1 1 central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-45 3.15.3 storage control instructions storage control instructions mtsr, mt srin, mfsr, mfsrin, dcbi, tlbie, tlbi a, and tlbsync ar e not implemented by the mpc561/mpc563. 3.15.4 exceptions the following paragraphs define the types of oea exceptions. the exception ta ble vector defines the offset value by exception type. refer to table 3-19 . 3.15.4.1 system reset exception and nmi (0x0100) a system reset exception occurs when: ? any reset signal is asserted: poreset , hreset , or sreset ? an internal reset is requested, such as from the so ftware watchdog timer settings caused by reset as shown in table 3-22 . a non-maskable interrupt (n mi) occurs when the irq 0 is asserted and the following registers are set. table 3-22. settings caused by reset register setting msr ip depends on internal data bus configuration word; me is unchanged. dcmpen is set according to (bbcmcr[en_comp] and bbcmcr[exc_comp]). all other bits are cleared srr0 undefined srr1 undefined fpecr 0x0000 0000 ictrl 0x0000 0000 lctrl1 0x0000 0000 lctrl2 0x0000 0000 counta[16:31] 0x0000 0000 countb[16:31] 0x0000 0000 table 3-23. register settings following an nmi register name bits description save/restore register 0 (srr0) 1 all set to the effective addre ss of the next instruction the processor executes if no interrupt conditions are present save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-46 freescale semiconductor execution begins at physic al address 0x0100 if the hard reset confi guration word ip bit is cleared to 0. execution begins at physic al address 0xfff0 0100 if the hard reset configuration word ip bit is set to 1. 3.15.4.2 machine check exception (0x0200) a machine-check exception is assumed to be caused by one of the following conditions: ? the accessed address does not exist. ? a data error was detected. ? a storage protection violation wa s detected by chip-select logic. machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 1 if the rcpu is in decompression on mode, srr0 will contain a compressed address. table 3-23. register settings following an nmi (continued) register name bits description central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-47 when a machine-check exception occurs, the processor does one of the following: ? takes a machine check exception; ? enters the checkstop state; or ? enters debug mode. which action is taken depends on th e value of the msr[me] bit, whet her or not debug mode was enabled at reset, and (if debug mode is enab led) the values of the chstpe (c heckstop enable) and mcie (machine check enable) bits in the de bug enable register (der). table 3-24 summarizes the possibilities. when the processor is in the checkstop state, instruction pr ocessing is suspended and cannot be restarted without resetting the core. an indication is sent to the usiu which may genera te an automatic reset in this condition. refer to chapter 7, ?reset ,? for more details. the register settings for machin e check exceptions are shown in table 3-25 . table 3-24. machine check exception processor actions msr[me] debug mode enable chstpe mcie action performed when exception detected 0 0 x x enter checkstop state 1 0 x x branch to machine-check exception handler 0 1 0 x enter checkstop state 0 1 1 x enter debug mode 1 1 x 0 branch to machine-check exception handler 1 1 x 1 enter debug mode table 3-25. register settings following a machine check exception register name bits description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the interrupt save/restore register 1 (srr1) 0 2 msr0 1 set to 1 for instruction fetch-related errors and 0 for load/store-related errors 2:4 cleared to 0 5:9 2 msr[5:9] 10:15 cleared to 0 16:31 2 loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-48 freescale semiconductor when a machine check exception is taken, instruc tion execution resumes at offset 0x0200 from the base address indicated by msr[ip]. 3.15.4.3 data storage exception (0x0300) a data storage exception is never generated by the rcpu . the software may branch to this location as a result of implementation-specific da ta storage protection error exception. 3.15.4.4 instruction storage exception (0x0400) an instruction storage interrupt is never generated by them rcpu. th e software may branch to this location as a result of an impl ementation-specific instruction st orage protection error exception. 3.15.4.5 external interrupt (0x0500) the external interrupt exception is take n on assertion of the internal irq line to the rcpu, that is driven by on-chip interrupt controller. the interrupt may be caused by the assertion of an external irq signal, by a usiu timer, or by an intern al chip peripheral. refer to section 6.1.4, ?enhanced interrupt controller ,? for more information on the interrupt controller. machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 data/storage interrupt status register (dsisr) 3 0:14 cleared to 0 15:16 set to bits [29:30] of the inst ruction if x-form and to 0b00 if d-form 17 set to bit 25 of the instruction if x-form and to bit 5 if d-form 18:21 set to bits [21:24] of the instruction if x-form and to bits [1:4] if d-form 22:31 set to bits [6:15] of the instruction data address register (dar) 3 all set to the effective address of the data access that caused the interrupt 1 if the exception occurs due to a data error caused by a load/store instruction and the processor in decompression on mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs due to an instruction fetch in deco mpression on mode, the srr0 register will contain an indeterminate value. 2 this bit is loaded from the corresponding bit in the msr when an interrupt is taken. the appropriate bit in msr is loaded from this bit when an rfi is executed. 3 dsisr and dar registers are only updated when the mach ine check exception is caused by a data access violation. table 3-25. register settings following a machine check exception (continued) register name bits description central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-49 the interrupt may be delayed by ot her higher priority exceptions or if the msr[ee] bit is cleared when the exception occurs. msr[ee] is au tomatically cleared by hardware to disable external interrupts when any exception is taken. upon detecting an external interrupt, the processor assigns it to the instru ction at the head of the history buffer (after retiring all instruct ions that are ready to retire). the enhanced interrupt controller mode is available for interrupt-d riven applications on mpc561/mpc563. it allows the singl e external interrupt exception vect or 0x500 to be split into up to 48 different vectors corresponding to 48 interrupt sources to speed up interr upt processing. it also supports a low priority source mask ing feature in hardware to handle nested interrupts more easily. see section 6.1.4, ?enhanced interrupt controller ,? and chapter 4, ?burst buffer controller 2 module .? the register settings for the extern al interrupt exception are shown in table 3-26 . when an external interrupt is taken, instruction execution resumes at offset 0x00500 from the physical base address indicated by msr[ip]. 3.15.4.6 alignment exception (0x00600) the following conditions caus e an alignment exception: ? the operand of a floating-point load or store instruction is not word-aligned. ? the operand of a load or store mu ltiple instruction is not word-aligned. ? the operand of lwarx or stwcx. is not word-aligned. alignment exceptions use the srr0 a nd srr1 to save the machine stat e and the dsisr to determine the source of the exception. the register settings for ali gnment exceptions are shown in table 3-27 . table 3-26. register settings following external interrupt register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during an instruction fetch in de compression on mode, the srr0 register will contain an address in compressed format. all set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditi ons were present. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from bits [16: 31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpe n this bit is set according to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-50 freescale semiconductor table 3-27. register settings for alignment exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. set to the effective address of the instruction that caused the exception. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 data/storage interrupt status register (dsisr) [0:11] cleared to 0 [12:13] cleared to 0 14 cleared to 0 [15:16] for instructions that use regi ster indirect with index addressing, set to bits [29:30] of the instruction. for instructions that use register indirect with immediate index addressing, cleared. 17 for instructions that use regist er indirect with index addressing, set to bit 25 of the instruction. for instructions that use register indirect with immediate index addressing, set to bit 5 of the instruction. [18:21] for instructions that use regi ster indirect with index addressing, set to bits [21:24] of the instruction. for instructions that use register indirect with immediate index addressing, set to bits [1:4] of the instruction. [22:26] set to bits [6:10] (source or destination) of the instruction. [27:31] set to bits [11:15] of the in struction (ra). set to either bits [11:15] of the instruction or to any register number not in the range of registers loaded by a valid form instruction, for lmw, lswi, and lswx instructions. otherwise undefined. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-51 note for load or store instructions that use register indirect with index addressing, the dsisr can be set to the same value that would have resulted if the corresponding instruction uses regi ster indirect with immediate index addressing had caused the exception. simila rly, for load or store instructions that use register indirect with im mediate index addres sing, dsisr can hold a value that would have resulted from an instruction that uses register indirect with index addr essing. (if there is no corresponding instruction, no alternative value can be specified.) when an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical base address indicated by msr[ip]. 3.15.4.7 program exception (0x0700) a program exception occurs when no hi gher priority exception exists a nd one or more of the following exception conditions, which correspond to bit settings in srr1, occur dur ing execution of an instruction: ? system floating-point enabled exception ? a sy stem floating-point enabled exception is generated when the following condition is met as a result of a move to fpscr instruction, move to msr (mtmsr) instruction, or retu rn from interrupt (rfi) instruction: ? (msr[fe0] | msr[fe1]) and- fpscr[fex] = 1. ? notice that in the rcpu implementation of the po werpc isa architecture, a program interrupt is not generated by a floating-point arithmetic instruction that resu lts in the condition shown above; a floating-point assist exce ption is generated instead. ? privileged instruction ? a privil eged instruction type program ex ception is generated by any of the following conditions: ? the execution of a privileged in struction (mfmsr, mtmsr, or rfi) is attempted and the processor is operating at the user priv ilege level (msr[pr] = 1). ? the execution of mtspr or mf spr where spr0 = 1 in the inst ruction encoding (indicating a supervisor-access register) and msr[pr] = 1 (indicating the proce ssor is operating at the user privilege level), provided the spr instru ction field encoding represents either: ? a valid internal-to-the-proce ssor special-purpos e register; or ? an external-to-the-processor special-pur pose register (either valid or invalid). ? trap ? a trap type program excep tion is generated when any of th e conditions specified in a trap instruction is met. the register settings for prog ram exceptions are shown in table 3-28 . central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-52 freescale semiconductor when a program exception is taken, instruction execu tion resumes at offset 0x0700 from the physical base address indicated by msr[ip]. 3.15.4.8 floating-point unav ailable exception (0x0800) a floating-point unavailable excepti on occurs when no higher priority ex ception exists, an attempt is made to execute a floating-point instructi on (including floating- point load, store, and move instructions), and the floating-point available bit in the msr is disabled, (msr[fp] = 0). table 3-28. register settings following program exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. all contains the effective address of the excepting instruction save/restore register 1 (srr1) 2 2 only one of bits 11, 13, and 14 can be set. [0:10] cleared to 0 11 set for a floating-point enabled program exception; otherwise cleared. 12 cleared to 0. 13 set for a privileged instruction program exception; otherwise cleared. 14 set for a trap program exception; otherwise cleared. 15 cleared to 0 if srr0 contains the address of the instruction causing the exception, and set if srr0 contains the address of a subsequent instruction. [16:31] loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri]. machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 table 3-29. register settings following a floating-point unavailable exception register bits setting description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the exception. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from msr[16:31] central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-53 3.15.4.9 decrementer exception (0x0900) a decrementer exception occurs when no higher priori ty exception exists, the decrementer register has completed decrementing, and msr[ee] = 1. the decrementer exception request is canceled when the exception is handled. the de crementer register counts down, causi ng an exception (unless masked) when passing through zero. the decrem enter implementation meets the following requirements: ? loading a gpr from the decremente r does not affect the decrementer. ? storing a gpr value to the decrem enter replaces the value in the de crementer with the value in the gpr. ? whenever bit 0 of the decrementer changes from zero to one, an exception request is signaled. if multiple decrementer exception requests are rece ived before the first can be reported, only one exception is reported. the occurrence of a decrementer exception cancels the request. ? if the decrementer is altered by software and if bit 0 is changed from zer o to one, an interrupt request is signaled. the register settings for the d ecrementer exception are shown in table 3-30 . machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. table 3-30. register settings following a decrementer exception register bits setting description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from msr[16:31] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 table 3-29. register settings following a floating-point unavailable exception (continued) register bits setting description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-54 freescale semiconductor when a decrementer exception is taken, instructi on execution resumes at offs et 0x0900 from the physical base address indicated by msr[ip]. 3.15.4.10 system call exception (0x0c00) a system call exception occurs when a system call instruction is exec uted. the effective address of the instruction following the sc instruction is placed into srr0. msr[16:31] are placed into srr1[16:31], and srr1[0:15] are set to undefined values. then a system call ex ception is generated. the system call instruction is context synchronizi ng. that is, when a system call exception occurs, instruction dispatch is halted and th e following synchronization is performed: 1. the exception mechanism waits for all instructions in execution to complete to a point where they report all exceptions they will cause. 2. the processor ensures that all in structions in execution complete in the context in which they began execution. 3. instructions dispatched after the exception is processed are fetched and executed in the context established by the exception mechanism. register settings are shown in table 3-31 . when a system call excepti on is taken, instruction ex ecution resumes at offset 0x00c00 from the physical base address indicated by msr[ip]. 3.15.4.11 trace exception (0x0d00) a trace interrupt occurs if msr[se] = 1 and any in struction except rfi is successfully completed or msr[be]= 1 and a branch is complete d. notice that the trace interrupt does not occur after an instruction that caused an interrupt (for instance, sc). monito r/debugger software must change the vectors of other 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. table 3-31. register settings following a system call exception register setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in decompre ssion on mode, the srr0 register will contain the address of the load/store instruction in co mpressed format. if the exception occurs during an instruction fetch in decompression on mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction following the system call instruction save/restore register 1 (srr1) [0:15] undefined [16:31] loaded from msr[16:31] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-55 possible interrupt addresses to single- step such instructions. if this is unacceptable, other debug features can be used. refer to chapter 23, ?development support ,? for more information. see table 3-32 for trace exception register settings. execution resumes at offset 0x0d00 from the base address i ndicated by msr[ip]. 3.15.4.12 floating-point assist exception (0x0e00) a floating point assist exce ption occurs when the foll owing conditions are true: ? a floating-point enabled exce ption condition is detected; ? the corresponding floating-point enable bit in the fpscr (floating point status and control register) is set (exception enabled); and ? msr[fe0] | msr[fe1] = 1 these conditions are summarized in the following equation: (msr[fe0] | msr[fe1]) and fpscr[fex] = 1 note that when ((msr[fe0] | msr[ fe1]) and fpscr[fex]) is set as a result of move to fpscr, move to msr or rfi, a program exception is generate d, rather than a floating-point assist exception. a floating point assist exception also occurs when a tiny result is dete cted and the floating point underflow exception is disabled (fpscr[ue] = 0). the register settings for floating-poi nt assist exceptions are shown in table 3-33 . table 3-32. register settings following a trace exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. all set to the effective address of the instruction following the executed instruction save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 table 3-33. register settings follow ing floating-point assist exceptions register name bits description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the interrupt central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-56 freescale semiconductor when a floating-point exception is taken, instructi on execution resumes at offset 0x0e00 from the base address indicated by msr[ip]. 3.15.4.13 implementation-dependent software emulation exception (0x1000) an implementation-dependent soft ware emulation exception occurs in the following instances: ? when executing any non-implemente d instruction. this includes all illegal and unimplemented optional instructions and all floating-point instructions. ? when executing a mtspr or mfspr instru ction that specifies an un-implemented internal-to-the-processor spr, regardle ss of the value of bit 0 of the spr. ? when executing a mtspr or mfspr that specifie s an un-implemented exte rnal-to-the-processor register and spr0 = 0 or msr[pr] = 0 (no program interrupt condition). table 3-34 shows the register settings set when a software emulation exception occurs. save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. table 3-34. register settings following a software emulation exception register name bits description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the interrupt save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri]. table 3-33. register settings follow ing floating-point assist exceptions register name bits description central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-57 execution resumes at offset 0x01000 from the base address indicated by msr[ip]. 3.15.4.14 implementation-dependent instruction protection exception (0x1300) the implementation-specific instruct ion storage protection error interrupt occurs in the following cases: ? the fetch access violates stor age protection and msr[ir] = 1. ? the fetch access is to guar ded storage and msr[ir] = 1. the register settings for instructi on protection exceptions are shown in table 3-35 . machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 1 if the exception occurs during an inst ruction fetch in decompression on m ode, the srr0 register will contain a compressed address. table 3-35. register settings following an instruction protection exception register name bits description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the exception save/restore register 1 (srr1) 0:2 cleared to 0 3 set to 1 if the fetch access was to a guarded storage when msr[ir] = 1, otherwise clear to 0 4 set to 1 if the storage access is not permitted by the protection mechanism (impu in bbc) and msr[ir] = 1; otherwise clear to 0 5:15 cleared to 0 16:31 loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ir] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 table 3-34. register settings following a software emulation exception register name bits description central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-58 freescale semiconductor execution resumes at offset 0x1300 from the base address indicated by msr[ip]. 3.15.4.15 implementation-specific data protection error exception (0x1400) the implementation-specific da ta protection error exception occurs in the following case: ? the data access violates the st orage protection and msr[dr]=1. see chapter 11, ?l-bus to u-bus interface (l2u) .? 1 if the exception occurs during an instruction fetch in de compression on mode, the srr0 register will contain an indeterminate value. central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-59 see table 3-36 for data-protection-error ex ception register settings. when a data protection error excep tion is taken, instruction execution resumes at offset 0x1400 from the base address indicated by msr[ip]. 3.15.4.16 implementation-dependent debug exceptions implementation-dependent debug excepti ons occur in the following cases: ? when there is an internal breakpoint match (for more details, refer to chapter 23, ?development support .? ? when a peripheral breakpoint reque st is asserted to the rcpu. ? when the development port request is asserted to the rcpu. refer to chapter 23, ?development support ,? for details on how to generate the development port-interrupt request. see table 3-37 for debug-exception register settings. table 3-36. register settings following a data protection error exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in decompre ssion on mode, the srr0 register will contain the address of the load/store instruct ion in compressed format. all set to the effective address of the instruction that caused the exception save/restore register 1 (srr1) 0:15 cleared to 0 other loaded from bits [16:31 ] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set accord ing to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 data/storage interrupt status register (dsisr) 0:3 cleared to 0 4 set to 1 if the storage access is not permitted by the protection mechanism. otherwise cleared to 0 5 cleared to 0 6 set to 1 for a store operation and cleared to 0 for a load operation 7:31 cleared to 0 data address register (dar) all set to the effect ive address of the data access that caused the exception central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-60 freescale semiconductor for data breakpoint exceptions, the register shown in table 3-38 is set. execution resumes at offset from the base address indicated by msr[ip] as follows: ? 0x01c00 ? for data breakpoint match ? 0x01d00 ? for instruction breakpoint match ? 0x01e00 ? for development port maskable request or a peripheral breakpoint ? 0x01f00 ? for development port non-maskable request 3.15.5 partially executed instructions in general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. in the core, instructions are not ex ecuted at all if an ali gnment interrupt condition is table 3-37. register settings following a debug exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during an instruction fetch in decompression on mode, the srr0 register will contain the instruction address in compressed format. all for i-breakpoints, set to the ef fective address of the instruction that caused the interrupt. for l-breakpoint, set to the effective address of the instruction followin g the instruction that caused the interrupt. for development port maskable request or a peripheral breakpoint, set to the effective address of the instruction that the processor would have executed next if no interrupt conditions were present. if the development port request is asserted at reset, the value of srr0 is undefined. save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ ri] . if the development port request is asserted at reset, the value of srr1 is undefined. machine state register (msr) ip no change me no change le bit is copied from ile dcmpe n this bit is set according to (bbcmcr[en_comp] and bbcmcr[exc_comp]) other cleared to 0 table 3-38. register settings for data breakpoint match register name bits description bar set to the effective address of the data access as computed by the instruction that caused the interrupt central processing unit mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 3-61 detected and data storage interrupt is never genera ted by the hardware. in the rcpu, the instruction can be partially executed only in the case of the load/sto re instructions that cause multiple accesses to the memory subsystem. these instructions are: ? multiple/string instructions ? unaligned load/store instructions in the last case, the store instructi on can be partially comple ted if one of the accesse s (except the first one) causes the data storage protection error. the implementation-specific da ta storage protection interrupt is taken in this case. for the update forms, the update register (ra) is not altered. 3.15.6 timer facilities descriptions of the timebase and de crementer registers can be found in chapter 6, ?system configuration and protection ,? and in chapter 8, ?clocks and power control .? 3.15.7 optional facilities and instructions any other oea optional facilities and instructions (except those that are discussed here) are not implemented by the rcpu hardware. attempting to ex ecute any of these instructions causes an implementation dependent software emulation interrupt to be taken. central processing unit mpc561/mpc563 reference manual, rev. 1.2 3-62 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-1 chapter 4 burst buffer controller 2 module the burst buffer controller module (bbc) consists of four main functional part s: the bus interface unit (biu), the instruction memory prot ection unit (impu), branch target buf fer (btb) and the instruction code decompressor unit (icdu). see figure 4-1 . information about decompression features of the bbc is found in appendix a, ?mpc562/mpc 564 compression features .? the bbc master biu interfaces between the rcpu in struction port and the inte rnal u-bus and can support burstable and non-burst able u-bus accesses. the impu allows the instruction memory to be di vided into four regions with different protection attributes. the impu compares the attributes of the rcpu memory access request with the attributes of the appropriate region. if the access is allowed, the pr oper signals are sent to the biu. if access to the memory region is disallowed because the region is pr otected, an interrupt is se nt to the rcpu and the master biu cancels u-bus access. the impu is able to relocate th e rcpu exception vectors. the impu always maps the exception vectors into the internal memory space of the mp c561/mpc563. this feature is important for a multi-mpc561/mpc563 system, where, although the internal memories of some controllers are not shifted to the lower 4 mbytes, they can still have thei r own internal exception vect or tables with the same exception addresses issued by their rcpu cores. the impu also supports an mpc 561/mpc563-enhanced inte rrupt controller by extending an exception vector?s relocation mechanism to translate the rcpu external interrupt exception vector separately and splitting it into 48 different vectors, corresponding to the code generated by the interrupt controller. see also section 6.1.4.4, ?enhanced interr upt controller operation .? the branch target buffer (btb) improves the performance of the mp c561/mpc563 by holding and supplying previously accesse d or decompressed instructions to th e rcpu core. the btb can be enabled in either decompression on or off mode. the icdu provides decompressed in structions to rcpu in the decomp ression on mode and contains a 2 kbyte ram (decram) to hold decompression vocabul aries. the decram can serve as a general purpose ram memory on the u-bus if code compression is not used. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-2 freescale semiconductor figure 4-1. bbc module block diagram 4.1 key features 4.1.1 biu key features ? supports pipelined and burstable and single acc esses to internal and external memories ? supports the decoupled interface wi th the rcpu instruction unit impu registers u-bus slave machine address buffer to addresses impu decram 2 kbytes decompressor control logic icdu btb rcpu core (sequencer) data buffer 1 x 32 address and data buffers control pipelined and burstable access control u-bus master machine biu bbc u-bus u-bus controls l/u interface siu interface 32 u-bus data compress/ uncompress data compression address sequencer address 30 32 32 32 32 / burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-3 ? implements a parked master on the u-bus, resulti ng in zero clock delays for rcpu fetch accesses to the u-bus ? fully utilizes the u-bus pipeline for fetch accesses ? avoids undesirable delays through a tight interface with the l2u module (fully utilizing u-bus bandwidth and back-to-back accesses) ? supports program trace and show cycles ? supports a special attribute for debug port fetch accesses. 4.1.2 impu key features ? there are four regions in which the base address and size can be programmed. ? available region sizes include 2 kbytes, 8 kbyt es, 16 kbytes, 32 kbytes, 64 kbytes, 128 kbytes, 256 kbytes, 512 kbytes, 1 mbyte, 2 mbytes, 4 mbytes, 8 mbytes, 16 mbytes....4 gbytes. ? overlap between regions is allowed. ? each of the four regions suppor ts the following attributes: ? user/supervisor ? guard attribute (causes an interrupt in case of speculative fetch attempt) ? compressed/non-compressed (mpc562/mpc564 only) ? regions are enabled or disabled in software. ? global region entry declares the default access at tributes for all memory areas not covered by the four regions: ? the rcpu gets the instruction stor age protection exception generated upon ? an access violation of protection attributes ? a fetch from a guarded region. ? the rcpu msr[ir] bit c ontrols impu protection. ? programming is performed by using the rcpu mts pr/mfspr instructions to/from implementation specific special- purpose registers. ? the impu supplies relocation addresses of all th e exceptions within the internal memory space. ? the impu implements external in terrupt vector splitting to redu ce the external interrupt latency. ? there is a special reset exception vector for decompression on mode (mpc562/mpc564 only). 4.1.3 icdu key features the following are instruction code decompress ion unit key features of the mpc562/mpc564. see appendix a, ?mpc562/mpc564 compression features ? for more information. ? instruction code on-line de compression based on ?instr uction classes? algorithm. ? no need for address translation between compre ssed and non-compressed a ddress spaces ? icdu provides ?next instruction address? to the rcpu ? in most cases, instruction decompression takes one clock ? code decompression is pipelined: burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-4 freescale semiconductor ? no performance penalty during se quential program flow execution ? minimal performance penalty due to change of program flow execution ? two operation modes are available: decompress ion on and decompression off. switch between compressed and non-compressed user appli cation software parts is possible. ? adaptive vocabularies scheme is supported; each user applic ation can have its own optimum vocabularies. 4.1.4 decram key features ? 2 kbytes ram for decomp ression vocabulary tables ? 2 clock read/write accesses when used as a u-bus general-purpose ram ? 4 clock load/store accesses from the l-bus ? byte, half-word (16-bit) or word ( 32-bit) read/write accesses and fetches ? special access protection functions ? low-power standby operation for data retention 4.1.5 branch target buffer key features ? consists of eight ?branch target en tries? (bte). each entry contains: ? a 32-bit register that stores the target of historical change of flow (cof) address ? four ram entries, 38 bits each, which hold up to four valid instruction opcodes (32 bits). the six extra bits are used by icdu in decompression on mode. ? a 32-bit register that stores the values used to calculate the address following the last valid instruction. ? fifo removal policy management is implemented for the eight btes ? software-controlled btb enable/disable and invalidate ? user transparent (that is, no user management is required) 4.2 operation modes 4.2.1 instruction fetch the bbc provides two instruction fe tch modes: decompression off a nd decompression on . the operational modes are defined by rcpu msr[dcmpen] bit. if the bit is set, the mode is decompression on. otherwise, it is in decompression off. 4.2.1.1 decompression off mode in this mode, the bbc bus interface unit (biu) modul e transfers fetch accesses from the rcpu to the u-bus. when a new access is issued by the rcpu, it is transferred in parallel to both the impu and the biu. the impu compares the addr ess of the access to its region programming. the biu checks if the access can be immediately transferred to the u-bus, otherwise it requests the u-bus for the next clock. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-5 the biu may be programmed for bur stable or non-burstable access. if the biu is programmed for burstable access, the u-bus address phase transaction is accompanied by the burst request attribute. if burstable access is allowed by the u-bus slave, the biu continues current access as burstable, otherwise current access is executed as a single access. if a ny protection violation is detected by the impu, the current u-bus access is aborted by the biu and an exception is signaled to the rcpu. show cycle, program trace and de bug port access attributes accompanying the rcpu access are forwarded by the biu along with the u-bus access. 4.2.1.2 decompression on mode see appendix a, ?mpc562/mpc564 compression features ? for explanation of the decompression on mode. 4.2.2 burst operation of the bbc the bbc may initiate and handle burst accesses on the u-bus. the bbcm cr[be] bit determines whether the bbc operates burst cycles or not. burst requests are enabled when the be bit is set. the bbc handles non-wrap-around bursts with up to 4 data beats on the internal u-bus. note the burst operation in the mpc561/mpc 563 is useful if a user system implements burstable memory devices on the external bus. otherwise the mode will cause performan ce degradation when running code from external memory. when the rcpu runs in serialized m ode it is recommended that bursts be disabled by the bbc to sp eed up mpc561/mpc563 operation. burst operation for decompression on and in debug mode is disabled regardless of bbcmcr[be] bit setting. the bbc burst should be turned off if the usiu burst feature is enabled. 4.2.3 access violation detection instruction memory protection is assigned on a regi onal basis. default operation of impu is done on a global region. the impu has control registers which contain the follow ing information: region protection on/off, region base addres s, size and access permissions. protection logic is activated only if the rcpu msr[ir] bit is set. during each fetch request fr om the rcpu core to instruction memory , the address is compared to a value in the region base address of enabled regions. a ny address matching the sp ecific region within its appropriate size as defined in the region at tribute register sets a match indication. when more than one match indication occurs, the eff ective region is the region with the highest priority. priority is determined by region number. the lowest region number has the highes t priority and the global region has lowest priority. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-6 freescale semiconductor when no match happens, the effect ive region is the global region. the region attribute registers contai n the region protection fields: pp, g, and cmpr. the protection fields are compared to address attributes issued by the rcpu. if the access is permitted, the address is passed to the biu and further to the u-bus. whenever the impu detects access viol ation, the following actions are taken: 1. the request forwarded to the biu is canceled 2. the rcpu is informed that the requested addr ess caused an access violat ion by exception request. however, if the required address c ontains a show cycle attribute, th e biu delivers the access onto the u-bus to obtain program tracking. the exception vector (address) that the rcpu issu es for this exception has a 0x1300 offset in the rcpu exception vector table. the access vi olation status is provi ded in the rcpu srr1 sp ecial purpose register. the encoding of the status bits is as follows: ? srr1 [1] = 0 ? srr1 [3] = guarded storage ? srr1 [4] = protected storag e or compression violation ? srr1 [10] = 0 only one bit is set at a time. 4.2.4 slave operation the bbc is operating as a u-bus slave when the im pu registers, decompre ssor ram (decram) or icdu registers are accessed from th e u-bus. the impu register progr amming is done using powerpc isa mtspr/mfspr instructions. the ic du configuration registers (dccrs) and decram are mapped into the chip memory space and accessed by load/store instructions. dccr and decram accesses may be disabled by bbcmcr[dcae]. refer to section 4.6.2.1, ?bbc module configuration register (bbcmcr) .? 4.2.5 reset behavior upon soft reset, the bbc switches to an idle stat e and all pending u-bus acce sses are ignored, the icdu internal queue is flushed and the impu switches to a disabled st ate where all memory space is accessible for both user and supervisor. hard reset sets some of the fields and bits in the bbc configuration registers to their default reset state. some bits in the bbcmcr regi ster get their values from the reset configuration word. all the registers are reset using hreset ; sreset alone has no effect on them. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-7 note because hreset resets the en_comp bit and the exc_comp bit but sreset does not, there may be differ ent behavior between hreset and sreset when both en_comp and exc_comp are set. special care must be taken to ensure operation in a know n mode whenever reset occurs. the reset states of these bits are determ ined by reset configuration words. the location of the reset vector is dependent on the valu e of the msr[ip] bit in the rcpu. if msr[ip] is set, the exce ption table relocati on feature can be used. see section 4.3.1, ?etr operation .? 4.2.6 debug operation mode when the mpc561/mpc563 rcpu core is in debug m ode, the bbc initiates non-burstable access to the debug port and icdu is bypassed (i.e., instructions tr ansmitted to the debug port must be non-compressed regardless of rcpu msr[dcmpen] bit state). 4.3 exception table relocation (etr) the bbc is able to relocate the ex ception addresses of the rcpu. the relocation feature always maps the exception addresses into the internal memory space of the mpc561/mpc563. see figure 4-2 . this feature is important in multi-mpc 561/mpc563 systems, where, although th e memory map in some was shifted to not be on the lower 4 mbytes, their rcpu cores can still access their own exce ption handlers in their internal flash in spite of several rc pus issuing the same exception addresses. the relocation also saves wasted space between th e exception table entries in the case where each exception entry contained only a branch instruction to the exception rou tine, which is located elsewhere. the exception vector table may be programmed to be located in four places in the mpc561/mpc563 internal memory space. the exception table relocation is supported in both decompression on and decompression off operation modes. the reset routine vector is relocated differently in decompression on and in decompression off modes. this feature may be used by a software code comp ression tool to guarantee that a vocabulary table initialization routine is al ways executed before appl ication code is running. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-8 freescale semiconductor figure 4-2. exception table entries mapping 4.3.1 etr operation the exception vectors generated by the rcpu are 0x100 byt es apart from each other, starting at address 0x0000 0100 or 0xfff0 0100, depending on the value of msr[ip] bit in the rcpu. if the exception table relocation is disabled by the etre bit in the bbcmcr register, th e bbc transfers the exception fetch address to the u- bus of the mpc561/mpc563 with no in terference. in this case, normal powerpc isa exception addressing is implemented. if the exception table relocation is enabled, the b bc translates the exception vector into the exception relocation address as shown in table 4-1 . at that location, a branch inst ruction with absolute addressing (ba) must be placed. each ba instruction branch es to the required exception routine. these branch instructions should be successive in that region of me mory. that way, a table of branch instructions is implemented. executing the branch inst ruction causes the core to branch twice until it gets to the exception routine. each exception relocation table entry occupies tw o words to support decompression on mode, where a branch instruction can be more than 32 bits long. the branch table can be located in four locations in the internal memory, the location is de fined by bbcmcr[oerc] as shown in table 4-2 . 100 200 300 400 500 600 700 1f00 exception table exception pointer by core internal memory structure branch to... branch to... branch to... branch to ... branch to... branch to... branch to... branch to... branch to... branch to... branch to... branch to... free memory space 0 branch to... branch to... 1ffc 1ffc 0 8 10 decompression on n y b8 . . . . . . . . burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-9 note the 8 kbytes allocated for the origin al powerpc isa exception table can be almost fully utilized. this is pos sible if the mpc 561/mpc563 system memory is not mapped to the exception addres s space, (i.e., the addresses 0xfff0 0000 to 0xfff0 1fff are not used). in such case, these 8 kbytes can be fully utilized by the compiler, except for the lower 64 words (256 bytes) which are dedicated for the branch instructions. if the rcpu, while executing an excep tion, issues any address between two successive exception en tries (e.g., 0xfff0 0104), then the operation of the mpc561/mpc563 is not guarantee d if the etr is enabled. in order to activate the exception table relocat ion feature, the following steps are required: 1. set the rcpu msr[ip] bit 2. set the bbcmcr[etre] bit. see section 4.6.2.1, ?bbc module c onfiguration register (bbcmcr) ,? for programming details. the etr feature can be activated from reset, by sett ing corresponding bits in the reset configuration word. . table 4-1. exception addresses mapping name of exception original addr ess issues by core mapped address by exception table relocation logic reserved 0xfff0 0000 page_offset+0x000 system reset 0xfff0 0100 compression disabled compression enabled page_offset 1 +0x08 page_offset 1 +0x0b8 machine check 0xfff0 0200 page_offset+0x010 reserved 0xfff0 0300 page_offset+0x018 reserved 0xfff0 0400 page_offset+0x020 external interrupt 2 0xfff0 0500 page_offset+0x028 alignment 0xfff0 0600 page_offset+0x030 program 0xfff0 0700 page_offset+0x038 floating point unavailable 0xfff0 0800 page_offset+0x040 decrementer 0xfff0 0900 page_offset+0x048 reserved 0xfff0 0a00 page_offset+0x050 reserved 0xfff0 0b00 page_offset+0x058 system call 0xfff0 0c00 page_offset+0x060 trace 0xfff0 0d00 page_offset+0x068 floating point assist 0xfff0 0e00 page_offset+0x070 implementation dependent software emulation 0xfff0 1000 page_offset+0x080 burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-10 freescale semiconductor 4.3.2 enhanced external interrupt relocation (eeir) the bbc also supports the enhanced external interrupt model of th e mpc561/mpc563 which allows the removal of the interrupt re questing a source detection stage from the interrupt routine. the interrupt controller provides the inte rrupt vector to the bbc t ogether with an interrupt request to the rcpu. when the rcpu acknowledges an interrupt re quest, it issues an external inte rrupt vector to the bbc. the bbc logic detects this address and repl aces it with another address corres ponding to the interrupt controller vector, which is defined by the highest priority inte rrupt request from a periphe rial module or external interrupt request pin. see figure 4-3 . the external interrupt relocation table should be pl aced at the physical address defined in the external interrupt relocation table base address register. see section 4.6.2.5, ?external interrupt relocation table implementation dependent instruction storage protection error 0xfff0 1300 page_offset+0x098 implementation dependent data storage protection error 0xfff0 1400 page_offset+0x0a0 implementation dependent data breakpoint 0xfff0 1c00 page_offset+0x0e0 implementation dependent instruction breakpoint 0x0fff 1d00 page_offset+0x0e8 implementation dependent maskable external breakpoint 0xfff0 1e00 page_offset+0x0f0 non-maskable external breakpoint 0xfff0 1f00 page_offset+0x0f8 1 refer to ta b l e 4 - 2 . 2 0x500 is remapped if the eeir feature is enabled. see section 4.3.2, ?enhanced external interrupt relocation (eeir) .? table 4-2. exception relocation page offset bbcmcr(oerc[0:1]) page offset comments 0 0 0x0 + isb offset 1 1 isb offset is equal 4m * isb (0x400000 * isb), where isb is value of bit field in usiu immr register. 0 0 1 0x1 0000 + isb offset 64 kbytes 2 2 this offset is diff erent from the mpc555. 1 0 0x8 0000 + isb offset 512 kbytes 1 1 0x3f e000 + isb offset l-bus (calram) address table 4-1. exception addresses mapping (continued) name of exception original addr ess issues by core mapped address by exception table relocation logic burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-11 base address register (eibadr) .? this is the base addres s of a branch table. see table 6-4 and figure 4-3 . each table entry must contain a bran ch absolute (ba) instruction to the first instruction of an interrupt service routine. each table entr y occupies two words (eight bytes ) to support decompression on mode, where a branch instruction ca n be more than 32 bits long. the memory space allocated for the external interrupt relocation table is up to 2 kbytes. if part of the external interrupt relocation table entry is not used, it may be ut ilized for another purpose such as instruction code space or data space. in order to activate the external interrupt re location feature, the following steps are required: 1. program the eibadr register to the external interrupt branch table base address. see section 4.6.2.5, ?external interrupt relocation table base address register (eibadr) .? 2. set the msr[ip] bit. 3. set the bbcmcr[eir] bit. see section 4.6.2.1, ?bbc module c onfiguration register (bbcmcr) ,? for programming details. note if both the enhanced external inte rrupt relocation and exception table relocation functions are activated simult aneously, the final external interrupt vector is defined by eeir mechanism. when the eeir function is activated, a ny branch instruction execution with the 0xfff0 0500 target address ma y cause unpredictable program execution. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-12 freescale semiconductor figure 4-3. external interrupt vectors splitting 4.4 decompressor ram (decram) functionality decompressor ram (decram) is a pa rt of the icdu. it occupies a 2-kbyte physical ram array block. it is mapped both in the icdu intern al address space and in the chip me mory address space. it is a single port memory and may not be accessed simu ltaneously from the icdu and u-bus. interrupt vector external interrupt handlers table interrupt pointer by core internal memory structure main code can start here 0x500 translated vectors external interrupt vector relocator branch absolute to handler branch absolute to handler branch absolute to handler branch absolute to handler branch absolute to handler external relocation table base address 000 interrupt (eibadr) interrupt code from interrupt controller offset eibadr burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-13 figure 4-4. decram interfaces block diagram 4.4.1 general-purpose memory operation in the case of decompression off mode, the decram can serve as a two-clock access general-purpose ram for u-bus instruction fetches or four-clock acce ss for read/write data ope rations. the base address of the decram is 0x2f 8000. see figure 4-6 . the proper access rights to the decram array may be defined by programming the r, d, and s bits of the bbcmcr register: ? read/write or read only ? instruction/data or data only ? supervisor/user or supervisor only vocabulary table (vt1) (1 kbyte) decram array vocabulary table (vt2) (1 kbyte) array u-bus address u-bus data slave biu vt1 address vt2 address vt1 data vt2 data icdu control logic icdu burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-14 freescale semiconductor u-bus access mode of the ram is activat ed by the bbcmcr[dcae] bit setting (see section 4.6.2.1, ?bbc module configurat ion register (bbcmcr) ?). in this mode the decr am can be accessed from the u-bus and cannot be accessed by the icdu logic. in this mode: ? the decram supports word, half-word and byte operations. ? the decram is emulated to be 32 bits wide. fo r example: a load access from offset 0 in the decram will deliver the concaten ation of the first word in each of the decram banks when ram 1 contains the 16 lsb of the word and ram 2 contains the 16 msb. ? load accesses at any width are suppl ied with 32 bits of valid data. ? the decram communicates with the u-bus pipeline but does not support pipelined accesses to itself. if a store operati on is second in the u-bus pipe, the store is carried out immediately and the u-bus acknowledgment is performed when the previous tran saction in the pipe completes. ? burst access is not supported. note instructions running from the decr am should not also perform store operations to the decram. 4.4.1.1 memory protection violations the decram module does not acknowledge u-bus accesses that violate th e configuration defined in the bbcmcr. this causes the machine ch eck exception for the internal rc pu or an error condition for the mpc561/mpc563 external master. 4.4.1.2 decram standby operation mode the bus interface and decram c ontrol logic are powered by v dd supply. the memory array is supplied by a separate power pin (iramstby). 4.5 branch target buffer the burst buffer controller contains a branch target buffer (btb) to reduce the impact of branches on processor performance. following is a summary of the btb features: ? software controlled btb enable/d isable, inhibit, and invalidate ? user transparent ? no user management required the btb consists of eight branch target entries (bte). refer to figure 4-5 . all entries are managed as a fully associative cache. each entry contains a ta g and several data buffers related to this tag. 4.5.1 btb operation when the rcpu generates a change of flow (cof) address for instruction fetch, the btb control logic compares it to the tag values currently stored in the tag register file where the following events can happen: burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-15 ? bte miss ? the target address and in struction code data will be st ored in one of the bte entries defined by its control logic. up to four instructions and their corresponding addresses subsequent to the cof target instruction may be saved in e ach bte entry. the number of valid instructions currently stored in the bte entry is written into the vdc field of the current bte entry. the valid flag is set at the end of this process. the entry to be replaced upon miss is chosen based on fifo replacement method. thus the btb can support up to eight different branch target addresses in a program loop. ? bte hit ? when the target address of a branch matches one of the valid bte entries, two activities take place in parallel: ? the btb supplies all the valid instructi ons in the matched entry to the rcpu. ? the biu starts to prefetch new instructions (and icdu decompresses them in compressed mode) from the address following the last instruct ion that is stored in the matched btb entry. the bbc will supply these new instructions to the rcpu after all the stored instructions in the matched btb entry were delivered. in case of a btb hit, the impact of instruction decompression latency (i n compressed mode) is eliminated as well as a latency of inst ruction storage memory device. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-16 freescale semiconductor figure 4-5. btb block diagram 4.5.1.1 btb invalidation write access to any bbc special purpose register invalidates all btb entries. note to guarantee that the btb does not contain instructi ons that may have been changed, the btb contents should be invalidated any t ime instruction memory is modified. 4.5.1.2 btb enabling/disabling the btb operation may be enabled or disabled by programming the btee bit in the bbcmcr register. 4.5.1.3 btb inhibit regions the btb operation may be inhibited regarding some memory regions. the btb caching is inhibited for a region if the btbinh bit is set in the region attrib ute register (or global regi on attribute register). see instruction buffers instruction buffers instruction buffers tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v 32-bit instruction address hit hit hit hit hit hit hit hit btb hit bte tag register file bte memory array instruction buffers instruction buffers instruction buffers instruction buffers instruction buffers burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-17 section 4.6.2.3, ?region attribut e registers (mi_ra[0:3]) ,? and section 4.6.2.4, ?global region attribute register (mi_gra) ? for details. 4.6 bbc programming model 4.6.1 address map the bbc consists of three separate ly addressable sections within th e internal chip address space: 1. bbc and impu control registers. these are mapped in the spr registers area and may be programmed by using the rcpu mtspr/mfspr instructions. 2. decompressor vocabulary ram (d ecram). the decram array o ccupies the 2-kbyte physical memory (8 kbytes of the mpc561/mpc563 address space is allocated for decram). 3. decompressor class configuration registers (dccr) block. it cons ists of 15 decompression class configuration registers. these re gisters are available for word wide read/write accesses through u-bus. the registers occupy a 64-byt e physical block (8-kbyte chip address space is allocated for the register block). figure 4-6. mpc561/mpc563 memory map 4.6.1.1 bbc special purpose registers (sprs) table 4-3. bbc sprs spr number (decimal) address for external master access (hex) register name 528 0x2100 impu global region attribute register (mi_gra). see ta b l e 4 - 8 for bits descriptions. 529 0x2300 external interrupt relocation table base address register (eibadr). see ta b l e 4 - 9 for bits descriptions. 560 0x2110 bbc module configurat ion register (bbcmcr). see ta b l e 4 - 4 for bits descriptions 0x2f 87ff 0x2f 9fff 0x2f 8800 0x2f a000 0x2f 8000 0x2f a03f reserved dccr0 ? dccr15 decram 2 kbytes burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-18 freescale semiconductor all the above registers may be accessed in the supervis or mode only. an exception is internally generated by the rcpu if there is an attempt to access them in user mode. an external master receives a transfer error acknowledge when attempting to access a register in user mode. note if one of these registers is written with in 4 instructions of a branch target, the user application may crash. to prev ent this, ensure that any instruction writing to these registers is preceded by 4 instructions that are not the target of any branch, and is followed by an isync instruction. 4.6.1.2 decram and dccr block the decram occupies addresses from 0x2f 8000 to 0x2f 87ff. the dccr block occupies addresses from 0x2f a000 to 0x2f a03f. the address for non-implemented memory blocks is not acknowledged, and causes an error condition. 784 0x2180 impu region base address register 0 (mi_rba0). see ta bl e 4 - 5 for bits descriptions. 785 0x2380 impu region base address register 1 (mi_rba1). see ta bl e 4 - 5 for bits descriptions. 786 0x2580 impu region base address register 2 (mi_rba2). see ta bl e 4 - 5 for bits descriptions. 787 0x2780 impu region base address register 3 (mi_rba3). see ta bl e 4 - 5 for bits descriptions. 816 0x2190 impu region attribute register 0 (mi_ra0). see ta bl e 4 - 6 for bits descriptions. 817 0x2390 impu region attribute register 1 (mi_ra1). see ta bl e 4 - 6 for bits descriptions. 818 0x2590 impu region attribute register 2 (mi_ra2). see ta bl e 4 - 6 for bits descriptions. 819 0x2790 impu region attribute register 3 (mi_ra3). see ta bl e 4 - 6 for bits descriptions. table 4-3. bbc sprs (continued) spr number (decimal) address for external master access (hex) register name burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-19 4.6.2 bbc register descriptions 4.6.2.1 bbc module config uration register (bbcmcr) , msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field r d s test ? hreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? be etre eir en_ comp 1 1 mpc562/mpc564 only. exc_comp 1 decomp_sc_ en 1 oerc[0:1] btee ? dcae tst hreset 000 id19 2 2 the reset value is a reset configuration word value extracted from the internal bus line. refer to section 7.5.2, ?hard reset configuration word (rcw) .? 0id21 2 id22 2 id21 2 id(24:25) 2 00_0000 addr spr 560 figure 4-7. bbc module confi guration regist er (bbcmcr) table 4-4. bbcmcr field descriptions bits name description 0 r read only. any attempt to write to the decram array while r is set is terminated with an error. this causes a machine check exception for rcpu. 0 decram array is readable and writable. 1 decram array is read only. 1 d data only. the decram array may be used for instructions and data or for data storage only. any attempt to load instructions from the decram array, while d is set, is terminated with an error this causes a machine check exception for the rcpu. 0 decram array holds data and/or instruction. 1 decram array holds data only. 2 s supervisor only. when the bit is set (s = 1), only a supervisor program may access the decram. if a supervisor program is accessing the array, normal read/write operation will occur. if a user program is attempting to access t he array, the access will be terminated with an error this causes a machine check exception for the rcpu. if s = 0, the ram array is placed in un restricted space and access by both supervisor and user programs is allowed. 3:7 test these bits can be set in factory test mode only. the user should treat these bits as reserved and always write as zeros. 8:17 ? reserved 18 be 1 burst enable 0 burst access is disabled. 1 burst access is enabled. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-20 freescale semiconductor 19 etre exception table relocation enable 0 exception table relocation is off: bbc does not map exception addresses. 1 exception table relocation is on: bbc maps exception addresses to a table holding branch instructions two memory words apart from each other. the reset value is taken from the reset configuration word bit 19. note: on the mpc562/mpc564, do not put compressed code at addresses 0xfff0 0000 to 0xffff ffff if etre = 1. 20 eir enhanced external interrupt relocation enable? this bit activates the external interrupt relocation table mechanism. this bit is independent from the value of etre bit, but if eir and etre are enabled, the mapping of external interrupt will be via eir. 0 eir function is disabled. 1 eir function is active. 21 en_comp 2 enable compression. this bit enables the operation of the mpc562/mpc564 in compression on mode. note: for rev a and later versions of the mpc563 and rev b and later of the mpc561, the default state is defined by bit 21 of t he reset configuration word, and is writable. in earlier versions, the bit can only be set by the reset configuration word. 0 decompression on mode is disabled. 1 decompression on mode is enabled. the mpc561/mpc563 operates only in decompression off mode. the mpc562/mpc564 may operate with both dec ompression on and decompression off modes. 22 exc_comp 2 exception compression. this bit determines the operation of the mpc562/mpc564 with exceptions. if this bit is set, the mpc562/mpc564 assumes that the all exception routine codes are compressed; otherwise it is assumed that all exception routine codes are not compressed. the reset value is deter mined by reset configuration word bit 22. 0 the rcpu assumes that exception routines are noncompressed. 1 the rcpu assumes that all exce ption routines are compressed. this bit has effects only when the en_c omp bit is set. the mpc561/mpc563 operates only in decompression off mode. the mpc562/mpc564 may operate with both decompression on and dec ompression off modes. 23 decomp_sc_en 2 decompression show cycle enable. this bit determines the way the mpc562/mpc564 executes instruction show cycles. the reset value is determined by configuratio n word bit 21. for further details regarding show cycles execution in ?decompression on? mode see section 4.2.1.2, ?decompression on mode .? 0 decompression show cycles do not include the bit pointer. 1 decompression show cycles include the bit pointer information on the data bus. 24:25 oerc[0:1] other exceptio ns relocation control. these bits have effect only if etre was enabled; see details in section 4.3.1, ?etr operation .? 00: offset 0 01 offset 64 kbytes 10 offset 512 kbytes 11 offset to 0x003fe000 the reset value is determined by reset configuration word bits 24 and 25 26 btee 1 branch target entries enable. this bit enables branch target entries of btb operation 0 bte operation is disabled 1 bte operation is enabled table 4-4. bbcmcr field descriptions (continued) bits name description burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-21 note when writing to the bbcmcr regist er, the following instruction after mtspr bbcmcr, rx should be isync, to make sure that the programmed value will come into effect before any further action. 4.6.2.2 region base address registers (mi_rba[0:3]) the following registers contain 32 bi ts and define the starting address of the protected regions. there is one register for each of four regions. , 27:29 ? reserved. note: bit 27 was bcmee and should be written as 0. 30 dcae decompressor configuration access enable. this bit enables decram and dccr registers access from the u-bus mast er (i.e., rcpu, external master). 0 decram and dccr registers are locked. 1 decram allows accesses from the u-bus only. dcae bit should be set before vocabulary tables are loaded via the u-bus. 31 tst reserved for bbc test operations. 1 be and btee should not both be set at the same time, setting the be bit disables the btb. 2 this bit is available on the mpc562/mpc564 only, software should write "0" to this bit for mpc561/mpc563. msb 0123456789101112131415 field ra hreset unchanged 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ra ? hreset undefined 0000_0000_0000 addr spr 784 (mi_rba0), spr 785 (mi_rba1 ), spr 786 (mi_rba2), spr 787 (mi_rba3) figure 4-8. region base address register (mi_rba[0:3]) table 4-5. mi_rba[0:3] registers bit descriptions bits name description 0:19 ra region base address. the ra field provides the base address of the region. the region base address should start on the memory block boundary for the corresponding region size, specified in the region attribute register mi_ra. 20:31 ? reserved table 4-4. bbcmcr field descriptions (continued) bits name description burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-22 freescale semiconductor note when the mpc562/mpc564 operates in decompression on mode, a minimum of four unused words must be left after the last instruction in any region. 4.6.2.3 region attribute registers (mi_ra[0:3]) the following registers define protection attributes and si ze for four memory regions. , msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field rs hreset unchanged 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field rs pp ? g cmpr btbinh ? hreset undefined 000 undefined 000 addr spr 816 (mi_ra0), spr 817 (mi_ra1), spr 818 (mi_ra2), 819 (mi_ra3) figure 4-9. region attribute register (mi_ra0[0:3]) table 4-6. mi_ra[0:3] registers bit descriptions bits name description 0:19 rs region size. for byte size by region, see ta bl e 4 - 7 . 20:21 pp 1 1 g and pp attributes perform similar protec tion activities on a region. the more prot ective attribute will be implied on the region if the attributes programming oppose each other. protection bits: 00 supervisor ? no access, user ? no access. 01 supervisor ? fetch, user ? no access. 1x supervisor ? fetch, user ? fetch. 22:24 ? reserved 25 g 1 guard attribute for region 0 speculative fetch is not prohibited from region. region is not guarded. 1 speculative fetch is prohibited from guarded regi on. an exception will occur under such attempt. 26:27 cmpr 2 2 this field is available only on the mpc562/mpc564. compressed region. x0 the region in not restricted 01 region is considered a non-compressed code region. access to the region is allowed only in ?decompression off? mode 11 region is considered a compressed code region. access to the region is allowed only in ?decompression on? mode 28 btbinh btb inhibit region 0 btb operation is not prohibited for current memory region 1 btb operation is prohibited for current memory region. 29:31 ? reserved burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-23 4.6.2.4 global region attr ibute register (mi_gra) the mi_gra register defines protection at tributes for memory region, not covered by mi_rb[0:3]/mi_rba[0:3] registers. it also contains protection regions 0-3 enable bits. , table 4-7. region size programming possible values rs field value (binary) size 0000_0000_0000_0000_0000 4 kbytes 0000_0000_0000_0000_0001 8 kbytes 0000_0000_0000_0000_0011 16 kbytes 0000_0000_0000_0000_0111 32 kbytes 0000_0000_0000_0000_1111 64 kbytes 0000_0000_0000_0001_1111 128 kbytes 0000_0000_0000_0011_1111 256 kbytes 0000_0000_0000_0111_1111 512 kbytes 0000_0000_0000_1111_1111 1 mbyte 0000_0000_0001_1111_1111 2 mbytes 0000_0000_0011_1111_1111 4 mbytes 0000_0000_0111_1111_1111 8 mbytes 0000_0000_1111_1111_1111 16 mbytes 0000_0001_1111_1111_1111 32 mbytes 0000_0011_1111_1111_1111 64 mbytes 0000_0111_1111_1111_1111 128 mbytes 0000_1111_1111_1111_1111 256 mbytes 0001_1111_1111_1111_1111 512 mbytes 0011_1111_1111_1111_1111 1 gbyte 0111_1111_1111_1111_1111 2 gbytes 1111_1111_1111_1111_1111 4 gbytes msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field enr 0 enr1 enr2 enr3 ? hreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? pp ? g cmpr btbinh ? hreset 0000_0000_0000_0000 addr spr 528 figure 4-10. global region attribute register ( mi_gra) burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-24 freescale semiconductor note the mi_gra register should be program med to enable fetch access (pp and g bits) before rcpu msr[ir] is set. table 4-8. mi_gra field descriptions bits name description 0 enr0 enable impu region 0 0 region 0 is off. 1 region 0 is on. 1 enr1 enable impu region 1 0 region 1 is off. 1 region 1 is on. 2 enr2 enable impu region 2 0 region 2 is off. 1 region 2 is on. 3 enr3 enable impu region 3 0 region 3 is off. 1 region 3 is on. 4:19 ? reserved 20:21 pp protection bits 00 supervisor ? no access, user ? no access. 01 supervisor ? fetch, user ? no access. 1x supervisor ? fetch, user ? fetch. 22:24 ? reserved 25 g guard attribute for region 0 fetch is not prohibited from region. region is not guarded. 1 fetch is prohibited from guarded region. an exception will occur under such attempt. 26:27 cmpr 1 1 this field is available only on the mpc562/mpc564. compressed region. x0 the region is not restricted 01 region is considered a non-compressed code region access to the region is allowed only in ?decompression off? mode 11 region is considered a compressed code region. access to the region is allowed only in ?decompression on? mode 28 btbinh btb inhibit region 0 btb operation is not prohibited for current memory region 1 btb operation is prohibited for current memory region. 29:31 ? reserved burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 4-25 4.6.2.5 external interrupt relocation ta ble base address register (eibadr) , 4.6.3 decompressor class configuration registers see section a.4, ?decompressor class c onfiguration registers (dccr0-15) ? for the registers of the icdu. msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field ba ? hreset unchanged 000_0000_0000 figure 4-11. external interrupt relocation table base address register (eibadr) table 4-9. eibadr external interrupt relocation table base address register bit descriptions bits name description 0:20 ba external interrupt relocation table base address bits [0:20] 21:31 ? reserved. eibadr must be set on a 4k page boundary. burst buffer controller 2 module mpc561/mpc563 reference manual, rev. 1.2 4-26 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 5-1 chapter 5 unified system interface unit (usiu) overview the unified system interface unit (u siu) of the mpc561/mpc563 consists of several functional modules that control system start-up, system initialization and operation, system protection, and the external system bus. the mpc561/mpc563 usiu functions include the following a nd are discussed in the designated chapters: ? system configuration and protecti on with gpio capability and an enhanced interrupt controller. refer to chapter 6, ?system confi guration and protection .? ? system reset monitoring and generation, refer to chapter 7, ?reset .? ? clock synthesis, power manageme nt, and debug support. refer to chapter 8, ?clocks and power control .? ? external bus interface (ebi), refer to chapter 9, ?external bus interface .? ? memory controller that supports four memory banks. refer to chapter 10, ?memory controller .? the usiu provides system configur ation and protection features th at control the overall system configuration and supply various moni tors and timers including the bus monitor, software watchdog timer, periodic interrupt timer, decremen ter, time base, and real-time cl ock. freeze support and low power stop is provided. the interrupt controller supports up to eight external interr upts, eight levels for all internal usiu interrupt sources and 32 levels for internal peripheral modules on the imb bus. it has an enhanced mode of operation, which simplifi es the mpc561/mpc563 interrupt st ructure and speeds up interrupt processing. additionally, the usiu provides several pinout confi gurations that allow up to 64 general-purpose i/o, external 32-bit port that supports internal and external master s, and various debug functions. reset logic for the mpc561/mpc563 provides soft a nd hard resets, checkstop and watchdog resets, and other types of reset. the reset stat us register (rsr) reflects the mo st recent source to cause a reset. the clock synthesizer generates the clock signals used by the usiu as well as the other modules and external devices. this circuitry can generate a system clock from a range of crystals, typically in the 4 mhz or 20 mhz range. the usiu supports various low-power modes. each one supplies a differ ent range of power consumption, functionality and wake-up time. refer to chapter 8, ?clocks and power control ,? for details. the ebi handles the transfer of info rmation between the internal busses and the memory or peripherals in the external address space. the mp c561/mpc563 is designed to allow exte rnal bus masters to request and obtain mastership of the system bus , and if required access the on-chip memory and registers. refer to chapter 9, ?external bus interface ,? for details. the memory controller module provides glueless interface to many types of memory devices and peripherals. it supports up to four memory banks. refer to chapter 10, ?memory controller ,? for details. unified system interface unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 5-2 freescale semiconductor the usiu supports the internal fl ash censorship mechanism on the mp c561/mpc563 to protect the flash contents. refer to chapter 21, ?cdr3 flash (uc3f) eeprom .? it is not possible to operate the mpc561/mpc563 from the external world while the flash is in censorship mode a nd in a censorship state. the internal flash array will be either locked or acce ssible only after the entire array contents have been erased. the mpc561/mpc563 is in censored mode if one of the following events occurs: ? booting from external memory ? operating in peripheral mode or if accessed from an external master ? operating in debug mode (bdm or nexus) figure 5-1 shows the usiu block diagram. figure 5-1. usiu block diagram 5.1 memory map and registers table 5-1 is an address map of the usiu registers and, unless otherwise noted, regi sters are 32 bits wide. the address shown for each register is relative to the base address of the mpc561/mpc563 internal memory map. the internal memory block can reside in one of eight possible 4 mbyte memory spaces. see figure 1-3 for details. memory control lines memory controller e-bus u-bus slave clocks & reset u-bus sgpio interface interface configuration registers software watchdog bus monitor periodic interrupt timer and decrementer real-time clock debug pin multiplexing interrupt controller address data e-bus interface usiu sub bus unified system interfa ce unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 5-3 table 5-1. usiu address map address register 0x2f c000 usiu module config uration register (siumcr) see ta bl e 6 - 7 for bit descriptions. 0x2f c004 system protection control register (sypcr) see ta bl e 6 - 1 5 for bit descriptions. 0x2f c008 reserved 0x2f c00e 1 software service register (swsr) see ta bl e 6 - 1 6 for bit descriptions. 0x2f c010 interrupt pending register (sipend). 0x2f c014 interrupt mask register (simask) see section 6.2.2.2 .4, ?siu interrupt mask register (simask) ,? for bit descriptions. 0x2f c018 interrupt edge level mask (siel) see section 6.2.2.2.7, ?siu interrupt edge level register (siel) ,? for bit descriptions. 0x2f c01c interrupt vector (sivec) see section 6.2.2.2.8, ?siu interrupt vector register (sivec) ,? for bit descriptions. 0x2f c020 transfer error status register (tesr) see ta bl e 6 - 1 7 for bit descriptions. 0x2f c024 usiu general-purpose i/o data register (sgpiodt1) see ta bl e 6 - 2 3 for bit descriptions. 0x2f c028 usiu general-purpose i/ o data register 2 (sgpiodt2) see ta bl e 6 - 2 4 for bit descriptions. 0x2f c02c usiu general-purpose i/o control register (sgpiocr) see ta bl e 6 - 2 5 for bit descriptions. 0x2f c030 external master mode control register (emcr) see ta bl e 6 - 1 3 for bit descriptions. 0x2f c038 pads module configuration register 2 (pdmcr2) see ta bl e 2 - 6 for bit descriptions. 0x2f c03c pads module configuration register (pdmcr) see ta bl e 2 - 5 for bit descriptions. 0x2f c040 interrupt pend2 register (sipend2) see section 6.2.2.2.2, ?siu interrupt pending register 2 (sipend2) ,? for bit descriptions. 0x2f c044 interrupt pend3 register (sipend3) see section 6.2.2.2.3, ?siu interrupt pending register 3 (sipend3) ,? for bit descriptions. 0x2f c048 interrupt mask2 register (simask2) see section 6.2.2 .2.5, ?siu interrupt ma sk register 2 (simask2) ,? for details. 0x2f c04c interrupt ma sk3 register (simask3) see section 6.2.2 .2.6, ?siu interrupt ma sk register 3 (simask3) ,? for details. 0x2f c050 interrupt in-service2 register (sisr2) see section 6.2.2.2.9, ?interrupt in-service registers (sisr2 and sisr3) ,? fo r d e t a i l s. 0x2f c054 interrupt in-service3 register (sisr3) see section 6.2.2.2.9, ?interrupt in-service registers (sisr2 and sisr3) ,? fo r d e t a i l s. unified system interface unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 5-4 freescale semiconductor 0x2f c0fc?0x2f c0ff reserved memory controller registers 0x2f c100 base register 0 (br0) see table 10-8 for bit descriptions. 0x2f c104 option register 0 (or0) see table 10-10 for bit descriptions. 0x2f c108 base register 1 (br1) see table 10-8 for bit descriptions. 0x2f c10c option register 1 (or1) see table 10-10 for bit descriptions. 0x2f c110 base register 2 (br2) see table 10-8 for bit descriptions. 0x2f c114 option register 2 (or2) see table 10-10 for bit descriptions. 0x2f c118 base register 3 (br3) see table 10-8 for bit descriptions. 0x2f c11c option register 3 (or3) see table 10-10 for bit descriptions. 0x2f c120?0x2f c13c reserved 0x2f c140 dual-mapping base register (dmbr) see table 10-11 for bit descriptions. 0x2f c144 dual-mapping option register (dmor) see table 10-12 for bit descriptions. 0x2f c148?0x2f c174 reserved 0x2f c178 1 memory status (mstat) see table 10-7 for bit descriptions. 0x2f c17a?0x2f c1fc reserved system integration timers 0x2f c200 time base status and control (tbscr) see ta bl e 6 - 1 8 for bit descriptions. 0x2f c204 time base reference 0 (tbref0) see section 6.2.2.4.3, ?time base reference registers (tbref0 and tbref1) ,? for b it descriptions. 0x2f c208 time base reference 1 (tbref1) see section 6.2.2.4.3, ?time base reference registers (tbref0 and tbref1) ,? for b it descriptions. 0x2f c20c?0x2f c21c reserved table 5-1. usiu address map (continued) address register unified system interfa ce unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 5-5 0x2f c220 real-time clock status and control (rtcsc) see ta bl e 6 - 1 9 for bit descriptions. 0x2f c224 real-time clock (rtc) see section 6.2.2.4.6, ?real-time clock register (rtc) ,? for bit descriptions. 0x2f c228 real-time alarm seconds (rtsec) ? reserved 0x2f c22c real-time alarm (rtcal) see section 6.2.2.4.7, ?real-time clock alarm register (rtcal) ,? for bit descriptions. 0x2f c230?0x2f c23c reserved 0x2f c240 pit status and control (piscr) see ta bl e 6 - 2 0 for bit descriptions. 0x2f c244 pit count (pitc) see ta bl e 6 - 2 1 for bit descriptions. 0x2f c248 pit register (pitr) see ta bl e 6 - 2 2 for bit descriptions. 0x2f c24c?0x2f c27c reserved clocks and reset 0x2f c280 system clock control register (sccr) see ta bl e 8 - 9 for bit descriptions. 0x2f c284 pll low-power and reset control register (plprcr) see ta bl e 8 - 1 1 for bit descriptions. 0x2f c288 1 reset status register (rsr) see ta bl e 7 - 3 for bit descriptions. 0x2f c28c 1 change of lock interrupt register (colir) see ta bl e 8 - 1 2 for bit descriptions. 0x2f c290 1 iramstby control register (vsrcr) see ta bl e 8 - 1 3 for bit descriptions. 0x2f c294?0x2f c2fc reserved system integration timer keys 0x2f c300 time base status and control key (tbscrk) see ta bl e 8 - 8 for bit descriptions. 0x2f c304 time base reference 0 key (tbref0k) see ta bl e 8 - 8 for bit descriptions. 0x2f c308 time base reference 1 key (tbref1k) see ta bl e 8 - 8 for bit descriptions. 0x2f c30c time base and decrementor key (tbk) see ta bl e 8 - 8 for bit descriptions. 0x2f c310?0x2f c31c reserved table 5-1. usiu address map (continued) address register unified system interface unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 5-6 freescale semiconductor 5.1.1 usiu special-purpose registers table 5-2 lists the mpc561/mpc563 special purpose regist ers (spr) used by the usiu. these registers reside in an alternate internal memory space th at can only be accessed with the mtspr and mfspr instructions, or from an ex ternal master (refer to section 6.1.2, ?external master modes ,? for details). all registers are 32 bits wide. note rcpu special purpose registers cannot be accessed by an external master. only sprs in the usiu can be accessed by an external master. 0x2f c320 real-time clock status and control key (rtcsck) see ta bl e 8 - 8 for bit descriptions. 0x2f c324 real-time clock key (rtck) see ta bl e 8 - 8 for bit descriptions. 0x2f c328 real-time alarm seconds key (rtseck) see ta bl e 8 - 8 for bit descriptions. 0x2f c32c real-time alarm key (rtcalk) see ta bl e 8 - 8 for bit descriptions. 0x2f c330?0x2f c33c reserved 0x2f c340 pit status and control key (piscrik) see ta bl e 8 - 8 for bit descriptions. 0x2f c344 pit count key (pitck) see ta bl e 8 - 8 for bit descriptions. 0x2f c348?0x2f c37c reserved clocks and reset keys 0x2f c380 system clock control key (sccrk) see ta bl e 8 - 8 for bit descriptions. 0x2f c384 pll low-power and reset control register key (plprcrk) see ta bl e 8 - 8 for bit descriptions. 0x2f c388 reset status register key (rsrk) see ta bl e 8 - 8 for bit descriptions. 0x2f c38c?0x2f c3fc reserved 1 16-bit register. table 5-1. usiu address map (continued) address register unified system interfa ce unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 5-7 table 5-3 shows the mpc561/mpc563 address format for spec ial purpose register access. for an external master, accessing an mpc500 spr , address bits [0:17] a nd [28:31] are compared to zeros to confirm that an spr access is valid. see section 6.1.2.1, ?operation in external master modes ,? for more details. . table 5-2. usiu special-purpose registers internal address[0:31] register decimal address spr[5:9]:spr[0:4] 1 1 bits [0:17] and [28:31] are all 0. 0x2c00 decrementer (dec). see section 3.9.5, ?decrementer register (dec) ,? for more information. 22 0x1880 time base lower ? read (tbl). see section 6.2.2.4.2, ?time base sprs (tb) ,? for bit descriptions. 268 0x1a80 time base upper ? read (tbu). see section 6.2.2.4.2, ?time base sprs (tb) ,? for bit descriptions. 269 0x3880 time base lower ? write (tbl). seesee section 6.2.2.4.2, ?time base sprs (tb) ,? for bit descriptions. 284 0x3a80 time base upper ? write (tbu). see section 6.2.2.4.2, ?time base sprs (tb) ,? for bit descriptions. 285 0x3d30 internal memory mapping register (immr). see ta bl e 6 - 1 2 for bit descriptions. 638 table 5-3. hex address format for spr cycles a[0:17] a[18:22] a[23:27] a[28:31] 0 spr5:9 spr0:4 0 unified system interface unit (usiu) overview mpc561/mpc563 reference manual, rev. 1.2 5-8 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-1 chapter 6 system configuration and protection the mpc561/mpc563 incorporatedmaes many system functions that normally must be provided in external circuits. in addition, it is designed to provide maximum syst em safeguards against hardware and software faults. the system configuration and pr otection sub-module provides the following features: ? system configuration ( section 6.1.1, ?system configuration ?)?the usiu allows the configuration of the system accord ing to the particular requirement s. the functions include control of show cycle operation, pin multiplexing, a nd internal memory map location. system configuration also includes a regi ster containing part and mask num ber constants to identify the part in software. ? external master modes support ( section 6.1.2, ?external master modes ?)?external master modes are special modes of operati on that allow an alternate master on the external bus to access the internal modules for debugging and backup purposes. ? general-purpose i/o ( section 6.1.3, ?usiu general-purpose i/o ?)?the usiu provides 64 pins for general-purpose i/o. the sgpio pins are mu ltiplexed with the address and data pins. ? enhanced interrupt controller ( section 6.1.4, ?enhanced interrupt controller ?)?the interrupt controller receives interrupt requ ests from a number of internal and external sources and directs them on a single interrupt-request line to the rcpu. ? bus monitor ( section 6.1.5, ?hardware bus monitor ?)?the siu provides a bus monitor to watch internal to external accesses. it monitors the transfer acknowledge (ta ) response time for internal to external transfers. a tr ansfer error acknowledge (tea ) is asserted if the ta response limit is exceeded. this functi on can be disabled. ? decrementer ( section 6.1.6, ?decrementer (dec) ?)?the dec is a 32-bit decrementing counter defined by the mpc500 architecture to provide a decrementer interrupt. this binary counter is clocked by the same frequency as the time base (also defined by the mpc561/mpc563 architecture). the period for the dec when driven by a 4-mhz oscill ator can be up to 4295 seconds, which is approxima tely 71.6 minutes. refer to table 6-6 . ? time base counter ( section 6.1.7, ?time base (tb) ?)?the tb is a 64-bit counter defined by the mpc500 architecture to provide a time base reference for the operating system or application software. the tb has four independent reference re gisters that can generate a maskable interrupt when the time-base counter reache s the value programmed in one of the four reference registers. the associated bit in the tb status register will be set for the reference register which generated the interrupt. ? real-time clock ( section 6.1.8, ?real-time clock (rtc) ?)?the rtc is used to provide time-of-day information to the opera ting system or application softwa re. it is composed of a 45-bit counter and an alarm register. a ma skable interrupt is generated wh en the counter reaches the value programmed in the alarm register. the rtc is clocked by the same clock as the pit. system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-2 freescale semiconductor ? periodic interrupt timer ( section 6.1.9, ?periodic in terrupt timer (pit) ?)?the siu provides a timer to generate periodic interrupts for use with a real-time operating syst em or the application software. the pit provides a period from 1 s to 4 seconds with a four-mhz crystal or 200 ns to 0.8 ms with a 20-mhz crystal. th e pit function can be disabled. ? software watchdog timer ( section 6.1.10, ?software watchdog timer (swt) ?)?the swt asserts a reset or non-maskable interrupt, as sele cted by the system protection control register (sypcr), if the software fails to service the swt for a designate d period of time (e.g., because the software is trapped in a loop or lost). after a syst em reset, this function is enabled with a maximum time-out period and assert s a system reset if the time-out is reached. the swt can be disabled or its time-out period can be changed in the sypcr. once the sypc r is written, it cannot be written again until a system reset. ? freeze support ( section 6.1.11, ?freeze operation ?)?the siu allows control of whether the swt, pit, tb, dec, and rtc should c ontinue to run during freeze mode. ? low power stop ( section 6.1.12, ?low power stop operation ?)?in low power modes, specific timers are frozen but others are not. figure 6-1 shows a block diagram of the system configuration and protection logic. system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-3 figure 6-1. system configur ation and protection logic 6.1 system configuration and protection features the system configuration and protec tion sub-module provides features desc ribed in the following sections. 6.1.1 system configuration the siu allows the configuration of the system acco rding to the particular requirements. the functions include control of show cycle operation, pin multip lexing, and internal memory map location. system configuration also includes a register containing part and mask number c onstants to identify the part in software. system configuration registers incl ude the siu module confi guration register (siumc r), and the internal memory mapping register (immr). refer to section 6.2.2, ?system conf iguration and protection registers ,? for register diagrams and bit descriptions. interrupt controller bus monitor periodic interrupt timer software watchdog timer decrementer time base counter real-time clock clock tea interrupt interrupt or system reset interrupt interrupt module configuration decrementer exception ta internal and external interrupt requests ts system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-4 freescale semiconductor 6.1.1.1 usiu pin multiplexing some of the functions defined in the various secti ons of the usiu (externa l bus interface, memory controller, and general- purpose i/o) share pins. table 6-1 summarizes how the pin functions of these multiplexed pins are assigned. . 6.1.1.2 arbitration support two bits in the siumcr control usiu bus arbitrati on. the external arbitrati on (earb) bit determines whether arbitration is perfo rmed internally or externally. if earb is cleared (interna l arbitration), the external arbitration request priority (earp) bit determin es the priority of an exte rnal master?s arbitration request. the operation of the inte rnal arbiter is described in section 9.5.7.4, ?inter nal bus arbiter .? 6.1.2 external master modes external master modes are special m odes of operation that allow an alte rnative master on the external bus to access the internal modules for debugging and backup purposes. they provide access to the internal buses (u-bus and l-bus) and to the intermodule bus (imb3). there are two external master modes: ? peripheral mode (enabled by setti ng prpm in the external master control (emcr) register) uses a special slave mechanism that shuts down the rcpu and an alternative master on the external bus can perform accesses to any internal bus slave. table 6-1. usiu pin multiplexing control pin name multiplexing controlled by: irq 0 / sgpioc0 / mdo4 irq 1 / rsv / sgpioc1 irq 2 / cr / sgpioc2 / mts irq 3 / kr / retry / sgpioc3 irq4 / at2 / sgpioc4 irq 5 / sgpioc5 / modck1 irq 6 / modck2 irq 7 / modck3 at power-on reset: modck[1:3] otherwise: programmed in siumcr note: mdo4 is controlled by readi enable. sgpioc6 / frz / ptr sgpioc7 / irqout / lwp0 bg / vf0 / lwp1 br / vf1 / iwp2 bb / vf2 / iwp3 iwp[0:1] / vfls[0:1] bi / sts we [0:3] / be [0:3] / at[0:3] tdi/dsdi / mdi0 tck / dsck / mcki tdo / dsdo / mdo0 programmed in siumcr and hard reset configuration note: mdio, mcki, and mdo0 are controlled by readi enable. data[0:31] / sgpiod[0:31] addr[8:31] / sgpioa[8:31] programmed in siumcr rstconf /texp at power-on reset: rstconf otherwise: programmed in siumcr system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-5 ? slave mode (enabled by setting emcr[slvm] a nd clearing emcr[prpm]) enables an external master to access any internal bus slav e while the rcpu is fully operational. both modes can be enabled and disabled by software. in addition, peripheral mode can be selected from reset. the internal bus is not capable of providing priority between internal rcpu accesses and external master accesses. if the bandwidth of external master accesses is large, it is recommended that the system force gaps between external master ac cesses in order to avoid suspensi on of internal rcpu activity. the mpc561/mpc563 does not support bur st accesses from an external mast er; only single accesses of 8, 16, or 32 bits can be perfo rmed. the mpc561/mpc563 a sserts burst inhibit (bi ) on any attempt to initiate a burst access to internal memory. the mpc561/mpc563 provides memory controller serv ices for external master accesses (single and burst) to external memories. see chapter 10, ?memory controller ,? for details. 6.1.2.1 operation in external master modes the external master modes are controlled by th e emcr register, which contains the internal bus attributes. the default attributes in the emcr allow an extern al master to configure the emcr with the required attributes and access internal register s. the external master must be granted external bus ownership in order to initiate the external master access. the si u compares the address on the external bus to the allocated internal address space. if the address is with in the internal space, the access is performed with the internal bus. the internal address space is determined according to immr[isb] (see section 6.2.2.1.2, ?internal memory map register (immr) ,? for details). the external master access is terminated by the ta , tea , or retry signal on the external bus. a deadlock situation might occur if an internal-to-exte rnal access is attempted on the internal bus while an external master access is initiated on the external bus. in this case, the siu will assert retry on the external bus in order to relinquish and retry the external access until th e internal access is completed. the internal bus will deny other internal accesses for the next eight clocks in order to complete the pending accesses and prevent additi onal internal accesses from being initiated on the internal bus. the siu will also mask internal accesses to support consecutive exte rnal accesses if the delay between the external accesses is less than four clocks. the external master access and retry ti mings are described in section 9.5.12, ?bus operation in external master modes .? the external master may access the internal mpc561/ mpc563 special registers th at are located outside the rcpu. to access one of these special purpose registers (see section 5.1.1, ?usiu special-purpose registers ?), emcr[cont] must be set and emcr[supu] must be cleared. th e external master can then access the special register when it is provided the addres s according to the mpc 561/mpc563 address map. only the first external master access that follows em cr setting will be assigne d to the special register map; any subsequent accesses will be directed to the nor mal address map. this is done in order to enable access to the emcr again after the requi red mpc561/mpc563 special register access. peripheral mode does not require exte rnal bus arbitration between the ex ternal master and the internal rcpu, since the internal rcpu is disabled. the br and bb signals should be connected to ground, and the internal bus arbitration should be selected in order to prevent the ?s lave? mpc561/mpc563 from system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-6 freescale semiconductor occupying the external bus. internal bus arbitrat ion is selected by clea ring siumcr[earb] (see section 6.2.2.1.1, ?siu module confi guration register (siumcr) ?). 6.1.2.2 address decoding for external accesses during an external master access, the usiu compares the external address with the internal address block to determine if mpc561/mpc563 ope ration is required. since only 24 of the 32 internal address bits are available on the external bus, the us iu assigns zeros to the most signi ficant address bits (addr[0:7]). the address compare sequence ca n be summarized as follows: ? normal external access. if emcr[cont] is cleare d, the address is compared to the internal address map. refer to section 6.2.2.1.3, ?external master control register (emcr) ?. ? mpc561/mpc563 special register external access. if emcr[cont] is set by the previous external master access, the address is co mpared to the mpc561/mpc563 special address range. see section 5.1.1, ?usiu special-purpose registers ,? for a list of the sprs in the usiu. ? memory controller external acce ss. if the first two comparis ons do not match, the internal memory controller determines whether the addr ess matches an address assigned to one of the regions. if it finds a ma tch, the memory controller generate s the appropriate chip select and attribute accordingly when trying to fetch an mpc561/mpc563 special register from an external mast er, the address might be aliased to one of the external devices on the external bus. if th is device is selected by the mpc561/mpc563 internal memory controller, this aliasing does not occur since the chip select is disabled. if the device has its own address decoding or is be ing selected by external logic, this case is resolved. note this section does not address slave accesses to internal resources. for internal resources, the accesses compare against addr[8:9] = isb[1:2]. isb0 must be cleared. 6.1.3 usiu general-purpose i/o the usiu provides 64 general-pur pose i/o (sgpio) pins (see table 6-2 ). the sgpio pins are multiplexed with the address and data pins. in si ngle-chip mode, where communicating with external devices is not required, all 64 sgpio pins can be used. in multiple -chip mode, only eight sgpio pins are available. another configur ation allows the use of the address bus for instruction show cycles while the data bus is dedicated to sgpio functionality. the functionality of th ese pins is assigne d by the single-chip (sc) bit in the siumcr. (see section 6.2.2.1.1, ?siu module confi guration register (siumcr) .?) sgpio pins are grouped as follows: ? six groups of eight pins each, whose direction is set uniformly for the whole group ? 16 single pins whose direction is set separately for each pin table 6-2 describes the sgpio signals, and all availa ble configurations. th e sgpio registers are described in section 6.2.2.5, ?general-purpose i/o registers .? system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-7 figure 6-2 illustrates the functionality of the sgpio. figure 6-2. circuit paths of reading and writing to sgpio table 6-2. sgpio configuration sgpio group name individual pin control direction control available when sc = 00 (32-bit port size mode) available when sc = 01 (16-bit port size mode) available when sc = 10 (single-chip mode with trace) available when sc = 11 (single-chip mode) sgpiod[0:7] gddr0 x x sgpiod[8:15] gddr1 x x sgpiod[16:23] gddr2 x x x sgpiod[24:31] x sddrd[23:31] x x x sgpioc[0:7] 1 1 sgpioc[0:7] is selected according to gpc and mlrc fields in siumcr. see section 6.2.2.1.1, ?siu module configuration register (siumcr) .? x sddrc[0:7] sgpioa[8:15] gddr3 x sgpioa[16:23] gddr4 x sgpioa[24:31] gddr5 x bus oe internal clock sgpio pad path of write operation path of read operation write path read path gpio sgpio circuitry write read write read gpio write register read register system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-8 freescale semiconductor 6.1.4 enhanced interrupt controller 6.1.4.1 key features ? significant interrupt latency re duction from that of the mpc555. ? simplified interrupt structure ? up to 48 different interrupt requests ? splitting of single external interrupt vector into up to 48 vectors, one for each source ? automatic lower priority requests masking ? full backward compatibility w ith mpc555/mpc556 (enhanced mode is software programmable.) 6.1.4.2 interrupt configuration an overview of the mpc561/mpc563 in terrupt structure is shown in figure 6-3 . the interrupt controller receives interrupts from usiu internal sources, such as pit, rtc, from the ui mb module (which has its own interrupt controller) or from the imb3 bus (d irectly from imb modules) and from external pins irq [0:7]. system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-9 figure 6-3. mpc561/mpc563 interrupt structure if programmed to generate an inte rrupt, the swt and external pin irq0 always generate an nmi, non-maskable interrupt to the rcpu. note the rcpu takes the system reset exception when an nmi is asserted, the external interrupt excepti on for any other asserted interrupt request, and the decrementer exception when the decrementer msb changes from 0 to 1. level 2 level 7 level 6 level5 level 4 level 3 level 1 level 0 irq [0:7] ireq to rcpu nmi gen usiu swt i0 regular interrupt controller selector edge det i7 i6 i5 i4 i3 i2 i1 i0 8 timers, change of lock enhanced interrupt controller u-bus int levels [0:7] imb3 ilbs[0:1] imbirq sequencer offset in branch table 6 48 16 mux sivec nmi to rcpu wake up from low-power mode siumcr eicen irqout [eicen, lpmasken] dec dec_irq to rcpu lpmasken bbc/impu level[0:6] level7 uimb imb_irq [0:6] imb_irq [0:6] levels[0:7] internal bus system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-10 freescale semiconductor the decrementer interrupt request is not a part of the interr upt controller. each one of the external pins irq [1:7] has its own dedicated as signed priority level. irq0 is also mapped, but it should be used only as a status bit indi cating that irq0 was asserted and generated nmi in terrupt. there are eight additional interrupt priority levels. each one of the siu intern al interrupt sources, or a ny of the peripheral module interrupt sources can be assi gned by software to any one of the eight interrupt prio rity levels. thus, a very flexible interrupt scheme is implemented. the interrupt request signal generated by the interrupt controller is driven to the rpcu core and to the irqout pin (optionally). th is pin may be used in peripheral mode, when the rcpu is disabled, and the internal modules ar e accessed externally. the imb interrupts are controlled by the uimb. the imb provides 32 interr upt levels, and any inte rrupt source could be configured to any imb interrupt leve l. the uimb contains a 32-bit regi ster that holds the imb interrupt requests, and maps them to th e usiu eight interrupt levels. note if one interrupt level was configured to more than one interrupt source, the software should read the uipend regi ster in the uimb module, and the particular status bits in order to identify whic h interrupt was asserted. the interrupt controller may be programmed to opera te in two modes?a regular mode or an enhanced mode. 6.1.4.3 regular interrupt controller operation (mpc555/mpc556-compatible mode) in regular operation mode (default se tting) the interrupt controller receive s interrupt requests from internal sources, such as timers, pll lock detector , imb modules and from external pins irq [0:7]. all the internal interrupt sources may be programmed to drive one or more of eight u-bus interr upt level lines while the rcpu, upon receiving an interrupt request, has to read the usiu and uimb status register in order to determine the interrupt source. the sivec register contains an 8-bit code representing the unmaske d interrupt request which has the highest priority level. the priori ty between all interrupt sources fo r the regular interrupt controller operation is shown in table 6-3 . table 6-3. priority of interrupt sources?regular operation number priority level interrupt source description offset in branch table (hex) sivec interrupt code 1 0 highest ext_irq0 0x0000 00000000 1 ? level 0 0x0008 00000100 2 ? ext_irq 1 0x0010 00001000 3 ? level 1 0x0018 00001100 4 ? ext_irq2 0x0020 00010000 5 ? level 2 0x0028 00010100 6 ? ext_irq3 0x0030 00011000 7 ? level 3 0x0038 00011100 system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-11 each interrupt request from external lines and from usiu internal inte rrupt sources in the case of its assertion will set a co rresponding bit in sipend register. the in dividual sipend bits may be masked by clearing an appropriate bit in simask register. 6.1.4.4 enhanced interrupt controller operation the enhanced interrupt controller operation may be turned on by setting the eicen control bit in the siumcr register. in this mode the 32 imb interrupt levels will be latched by usiu using eight imb interrupt lines and two lines of ilbs via the time multiplexing scheme defined by the uimb module. in addition to the imb interrupt sources the external inte rrupts and timer interrupts ar e available in the same way as in the regular scheme. in th is mode, the uimb module does not drive u-bus interr upt level lines. each interrupt request will set a corresponding b it in sipend2 or sipend3 registers. sipend2 an sipend3 may be masked by clearing an appropri ate bit in simask2 or simask3 registers. the priority logic is provi ded in order to determine the highest unmasked interr upt request, and interrupt code is generated in the sivec register. see table 6-4 . note if the enhanced interrupt controller is enabled, a delay is required prior to re-enabling interrupts. before clearing an interrupt related register, clear the msr[ee] bit (ee = 0). expect a vector offset of 0x0 if an interrupt is cleared or disabled while msr[ee] = 1. this vector should be handled as if no interrupt has occured, that is, perform an rfi instruction. after clearing an interrupt source, sufficient time mu st elapse before re-enabling the msr[ee] bit (ee = 1). this time shoul d take longer than the time needed for a load of the same register that was just cleared. to guarantee enough time, include this load instruction before the instruction that sets msr[ee]. 8 ? ext_irq4 0x0040 00100000 9 ? level 4 0x0048 00100100 10 ? ext_irq 5 0x0050 00101000 11 ? level 5 0x0058 00101100 12 ? ext_irq 6 0x0060 00110000 13 ? level 6 0x0068 00110100 14 ? ext_irq 7 0x0070 00111000 15 lowest level 7 0x0078 00111100 1 this is the value in the 8 most significan t bits of the sivec re gister (sivec[25:31]). table 6-3. priority of interrupt sources?regular operation number priority level interrupt source description offset in branch table (hex) sivec interrupt code 1 system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-12 freescale semiconductor table 6-4. priority of interrupt sources?enhanced operation number priority level interrupt source description offset in branch table (hex) 1 , 2 sivec interrupt code 3 0 highest (see note above) 4 0x0000 00000000 1 ? level 0 0x0008 00000100 2 ? imb_irq 0 0x0010 00001000 3 ? imb_irq 1 0x0018 00001100 4 ? imb_irq 2 0x0020 00010000 5 ? imb_irq 3 0x0028 00010100 6 ? ext_irq2 0x0030 00011000 7 ? level 1 0x0038 00011100 8 ? imb_irq 4 0x0040 00100000 9 ? imb_irq 5 0x0048 00100100 10 ? imb_irq 6 0x0050 00101000 11 ? imb_irq 7 0x0058 00101100 12 ? ext_irq2 0x0060 00110000 13 ? level 2 0x0068 00110100 14 ? imb_irq 8 0x0070 00111000 15 ? imb_irq 9 0x0078 00111100 16 ? imb_irq 10 0x0080 01000000 17 ? imb_irq 11 0x0088 01000100 18 ? ext_irq3 0x0090 01001000 19 ? level 3 0x0098 01001100 20 ? imb_irq 12 0x00a0 01010000 21 ? imb_irq 13 0x00a8 01010100 22 ? imb_irq 14 0x00b0 01011000 23 ? imb_irq 15 0x00b8 01011100 24 ? ext_irq4 0x00c0 01100000 25 ? level 4 0x00c8 01100100 26 ? imb_irq 16 0x00d0 01101000 27 ? imb_irq 17 0x00d8 01101100 28 ? imb_irq 18 0x00e0 01110000 29 ? imb_irq 19 0x00e8 01110100 30 ? ext_irq5 0x00f0 01111000 31 ? level 5 0x00f8 01111100 system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-13 the value of the sivec register is supplied internally to the bbc module and can be used as an offset to the branch table start address for th e external interrupt relocation featur e. thus a fast way to a specific interrupt source routine is provided wi thout software overhead. the bbcmcr (see section 4.6.2.1, ?bbc module configuration register (bbcmcr) ?) and eibadr (see section 4.6.2.5, ?external interrupt relocation table base a ddress register (eibadr) ?) registers must be programm ed to enable this feature in the bbc. additionally, the sipe nd2 and sipend3 registers contai n the information about all the interrupt requests that are asserted at a given time, so that software can always read them. note when the enhanced interrupt controller is enabled the sipend and simask registers are not used. 32 ? imb_irq 20 0x0100 10000000 33 ? imb_irq 21 0x0108 10000100 34 ? imb_irq 22 0x0110 10001000 35 ? imb_irq 23 0x0118 10001100 36 ? ext_irq6 0x0120 10010000 37 ? level 6 0x0128 10010100 38 ? imb_irq 24 0x0130 10011000 39 ? imb_irq 25 0x0138 10011100 40 ? imb_irq 26 0x0140 10100000 41 ? imb_irq 27 0x0148 10100100 42 ? ext_irq7 0x0150 10101000 43 ? level 7 0x0158 10101100 44 ? imb_irq 28 0x0160 10110000 45 ? imb_irq 29 0x0168 10110100 46 ? imb_irq 30 0x0170 10111000 47 lowest imb_irq 31 0x0178 10111100 1 the branch table feature can be used only if the bbcmcr[eir] is set. 2 this offset is added to the table base address from the eibdr register. 3 this is the value in the 8 most sign ificant bits of the sivec register. 4 this vector is reserved and normally is not generated. it ma y be generated, if any other interrupt source disappears, before being acknowleged by the rcpu as a result of any change in the interrupt scheme, module stopping, masking interrupt sources in a module by application software while interrupts are enabled in the rcpu by setting msr[ee]. table 6-4. priority of interrupt sources?enhanced operation (continued) number priority level interrupt source description offset in branch table (hex) 1 , 2 sivec interrupt code 3 system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-14 freescale semiconductor 6.1.4.4.1 lower prio rity request masking this feature (if enabled) simplifies the masking of lower priority in terrupt requests when a request of certain priority is in service in a pplications that require interrupt nest ing. the highest (pending) request is also masked by itself. the masking is accomplished in the following way. upon asserting an interrupt request the bbc generates an acknowledge signal to notify the interrupt controller that the request and the branch table offset have been latched. the interr upt controller then sets a bit in the sisr register (interrupt in-service register ), according to the asserted request. all other requests whose priority is lower than or equal to the one th at is currently in-service, become masked. the mask remains set until the sisr bit is cleared by software (by the interrupt handler r outine), writing a ?1? value to the corresponding bit. the lower priority request masking diagram is presented in figure 6-4 . the lower priority request maski ng feature is disa bled by hreset and it may be enabled by setting the lpmask_en bit in the siumcr register. note in the regular mode of the interrupt controller the lower priority request masking feature is not available. the feature must be activated only together with exception ta ble relocation in the bbc module. figure 6-4. lower priority request masking?one bit diagram 6.1.4.4.2 backward compat ibility with mpc555/mpc556 the enhanced interrupt controller is a feature that ma y be enabled according to a user?s application using the eicen control bit in siumcr regi ster, which can be set and cleared at any time by so ftware. if the bit is cleared, the default interrupt controller operation is availabl e, as described in section 6.1.4.3, ?regular interrupt controller operation (mpc555/mpc556-compatible mode) .? the regular operation is fully compatible with the interrupt controll er already implemented in mpc555/mpc556. figure 6-5 illustrates the interrupt controller functionality in the mpc561/mpc563. enable control bit from bit i - 1 to b i t i + 1 set reset by software sipend [i] simask [i] to rcpu sisr[i] generation (or between all the bits) to sivec generation impu (lpmask_en) reset external interrupt request acknowledge system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-15 figure 6-5. mpc561/mpc563 interrupt controller block diagram sipend siel s i v e c priority encoder 8 interrupt vector (6 from 48) (enables branch to the highest priority interrupt routine) sipend2 sipend3 simask2 simask3 interrupt request (to rcpu and irqout pad) u-bus int (offset to branch table ? to bbc) imb irq sequencer 32 8 irq[0:7] ilbs[0:1] simask synchronizer external irq 8 wake up from low-power mode mux enhanced interrupt controller enabled sisr2 sisr3 from imb: 5 5 48 16 0 1 ...... levels[0:7] ...... ...... ...... ...... system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-16 freescale semiconductor 6.1.4.5 interrupt overhead estimation for enhanced interrupt controller mode the interrupt overhead cons ists of two main parts: ? storage of general and special purpose registers ? recognition of the interrupt source the interrupt overhead can increase latency, and decr ease the overall system pe rformance. the overhead of register saving time can be reduced by improving the operating syst em. the number of registers that should be saved can be reduced if e ach interrupt event has its own interrupt vector. this solution solves the interrupt source recognition overhead. table 6-5 below illustrates the improvements. only registers required for the recognition routine are c onsidered to be saved in the calculations below. recognition of module internal events/c hannels is out of the scope of th e calculations. see also the typical interrupt handler flowchart in figure 6-6 . note compiler and bus collision overhead are not included in the calculations. table 6-5. interrupt latency estimation for three typical cases mpc561/mpc563 architecture without using sivec mpc561/mpc563 architecture using sivec mpc561/mpc563 architecture using enhanced interrupt controller features operation details interrupt propagation from request module to rcpu ? 8 clocks store of some gpr and spr?10 clocks read sipend?4 clocks read simask?4 clocks sipend data processing ? 20 clocks (find first set, access to lut in the flash, branches) read uipend?4 clocks uipend data processing?20 clocks (find first set, access to lut in the flash, branches) interrupt propagation from request module to rcpu ? 8 clocks store of some gpr and spr ?10 clocks read sivec?4 clocks branch to routine?10 clocks read uipend?4 clocks uipend data processing ? 20 clocks (find first set, ac cess to lut in the flash, branches) interrupt propagation from request module to rcpu ? 6 clocks store of some gpr and spr?10 clocks only one branch is executed to reach the interrupt handler routine of the device requesting interrupt servicing?2 clocks notes: if there is a need to enable nesting of interrupts during source recognition procedure, at least 30 clocks should be added to the interrupt latency estimation to use this feature in compressed mode some undetermined latency is added to make a branch to compressed address of the routine. this latency is dependant on how the user code is implemented. ? total: at least 70-80 clocks at least 50-60 clocks 20 clocks system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-17 . figure 6-6. typical interrupt handler routine 6.1.5 hardware bus monitor the bus monitor ensures that each bus cycle is term inated within a reasonable period of time. the usiu provides a bus monitor option to monitor internal to external bus accesses on the external bus. the monitor counts from transfer start to tran sfer acknowledge and from transfer ac knowledge to transfer acknowledge within bursts. if the monitor time s out, transfer e rror acknowledge (tea ) is asserted internally by the start saving the cpu context masking lower priority requests clearing interrupt source clearing mask rfi clearing in-service bit flow with lower priority masking enabled restoring the cpu context flow without lower priority masking enabled disabling interrupt handler body enabling interrupt system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-18 freescale semiconductor mpc561/mpc563, and rcpu access is terminated with a data error, causing a machine check state or exception. the bus monitor timing bit in the system protection control regist er (sypcr[bmt]) defines the bus monitor time-out period. the programmability of the time-out a llows for variation in system peripheral response time. the timing me chanism is clocked by the external bus clock divided by eight. the maximum value is 2040 system clock cycles. sypcr[bme] enables or disables the bus monitor. but regardless of the state of this bit the bus monitor is always enabled when freeze is asserted in debug mode. 6.1.6 decrementer (dec) the decrementer (dec) is a 32-bi t decrementing counter defined by the mpc561/mpc563 architecture to provide a decrementer interrupt. th is binary counter is cl ocked by the same freque ncy as the time base (also defined by the mpc500 architectu re). the operation of the time ba se and decrementer are therefore coherent. the dec is clocked by the tmbclk clock. the decrementer period is computed as follows: the state of the dec is not affected by any resets and should be initialized by software. the dec runs continuously after power-up once the time base is enabled by setti ng the tbe bit of the tbscr (see table 6-18 ) (unless the clock module is pr ogrammed to turn off the clock). the decrementer continues counting while reset is asserted. reading from the decrementer has no effect on the counter value. writi ng to the decrementer replaces the value in the decrementer with the value in the gpr. whenever bit 0 (the msb) of the decrementer changes from zero to one, a decrem enter exception occurs. if software alters the decrementer such that the cont ent of bit 0 is changed to a value of 1, a decrementer exception occurs. a decrementer exception causes a de crementer interrupt request to be pending in the rcpu. when the decrementer exception is taken, the decrementer interrupt request is automatically cleared. table 6-6 illustrates some of the peri ods available for the decremente r, assuming a 4-mhz or 20-mhz crystal, and tbs = 0 which selects tmbclk division to 4. note time base must be enabled to use the decrementer. see section 6.2.2.4.4, ?time base control and status register (tbscr) ,? for more information. table 6-6. decrementer time-out periods count value time-out @ 4 mhz time-out @ 20 mhz 0 1.0 s 0.2 s 9 10 s 2.0 s t dec = 2 32 f tmbclk system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-19 refer to section 3.9.5, ?decrementer register (dec) ,? for more information. 6.1.7 time base (tb) the time base (tb) is a 64-bit fr ee-running binary counter defined by the mpc500 architecture. the tb has two independent reference regist ers which can generate a maskable interrupt when the time base counter reaches the value programmed in one of the two refe rence registers. the pe riod of the tb depends on the driving frequency. the tb is clocked by the tmbclk clock. the period for the tb is: the state of tb is not affected by any resets and should be initialized by software. reads and writes of the tb are restricted to special instructions. separate special-purpose registers are defined in the mpc500 architecture for reading and writ ing the tb. for the mp c561/mpc563 implementati on, it is not possible to read or write the entire tb in a single instruction. therefor e, the mttb and mftb in structions are used to move the lower half of the time ba se (tbl) while the mttbu and mftbu in structions are used to move the upper half (tbu). two reference registers are associat ed with the time base: tbref0 a nd tbref1. a maskable interrupt is generated when the tb count reaches to the value programmed in one of the two reference registers. two status bits in the time base control and status re gister (tbscr) indicate which one of the two reference registers generated the interrupt. refer to section 6.2.2.4, ?system timer registers ,? for diagrams and bit descriptions of tb registers. refer to section 3.9.4, ?time base facility (tb) ? oea ,? and to the rcpu reference manual for additional information. 6.1.8 real-time clock (rtc) the rtc is a 32-bit counter and pre-divider used to provide a time-of-day i ndication to the operating system and application software as show in figure 6-7 . it is clocked by the pi trtclk clock. the counter 99 100 s 20 s 999 1.0 ms 200 s 9999 10.0 ms 2 ms 999999 1.0 s 200 ms 9999999 10.0 s 2.0 s 99999999 100.0 s 20 s 999999999 1000 s 200 s (hex) ffffffff 4295 s 859 s table 6-6. decrementer time-out periods (continued) count value time-out @ 4 mhz time-out @ 20 mhz t tb 2 64 f tmbclk ----------------------------- - = system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-20 freescale semiconductor is not affected by reset and operates in all low-power modes. it is initialized by software. the rtc can be programmed to generate a maskable interrupt when the time value matches the value programmed in its associated alarm register. it can al so be programmed to generate an interrupt once a second. a control and status register is used to enable or disable the differen t functions and to report the interrupt source. note pitrtclk can be divided by 4 or 256. see table 8-1 for default settings. figure 6-7. rtc block diagram 6.1.9 periodic interrupt timer (pit) the periodic interrupt timer consis ts of a 16-bit counter clocked by the pitrtclk clock signal supplied by the clock module as shown in figure 6-8 . the 16-bit counter counts down to zero when loaded wi th a value from the pitc register. after the timer reaches zero, the ps bit is set and an interrupt is generated if the pie bit is a logic one. the software service routine should read the ps bit and th en write a zero to terminate the inte rrupt request. at the next input clock edge, the value in the pitc is loaded in to the counter, and the pr ocess starts over again. when a new value is written into the pitc, the peri odic timer is updated, the divider is reset, and the counter begins counting. if the ps bit is not cleared, an interrupt request is ge nerated. the request remains pending until ps is cleared. if the ps bit is set again prior to bei ng cleared, the interrupt remains pending until ps is cleared. any write to the pitc stops the cu rrent countdown, and the count resume s with the new value in pitc. if the piscr[pte] bit is not set, the pit is unable to count and retains th e old count value. reads of the pit have no effect on the counter value. pitrtclk freeze divide 32-bit register (rtcal) sec alarm = clock disable divide mux 4-mhz/20-mhz crystal interrupt interrupt by 78125 by 15625 clock rtsec 32-bit counter (rtc) system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-21 figure 6-8. pit block diagram the timeout period is calculated as: solving this equation using a 4-mhz extern al clock and a pre-divider of 256 gives: this gives a range from 64 micros econds, with a pitc of 0x0000, to 4.19 seconds, with a pitc of 0xffff. when a 20-mhz crystal is used w ith a pre-divider of 256, the range is between 12.8 mi croseconds to 0.84 seconds. 6.1.10 software watchdog timer (swt) the software watchdog timer (swt) prevents system lo ckout in case the software becomes trapped in loops with no controlled exit. the swt is enabled after system reset to cause a system reset if it times out. the swt requires a special service se quence to be executed on a periodic basis. if this periodic servicing action does not occur, the swt times out and issues a reset or a non-maskable interrupt (nmi), depending on the value of the swri bit in the sypcr register. the swt can be disabled by cleari ng the swe bit in the sypcr. once the sypcr is written by software, the state of the swe bit cannot be changed. the swt service sequence consists of the following two steps: 1. write 0x556c to the software service register (swsr) 2. write 0xaa39 to the swsr the service sequence clears the watchdog timer and th e timing process begins again. if any value other than 0x556c or 0xaa39 is written to the swsr, the entire sequence must start over. clock 16-bit pitc pitrtclk ps (piscr) pie (piscr) pit pte disable clock modulus counter interrupt pitf (piscr) (piscr) (piscr) pit period pitc 1 + f pitrtclk ---------------------------------- - pitc 1 + externalclock 4 or 256 ---------------------------------------- - ?? ---------------------------------------------- - == pit period pitc 1 + 15625 ------------------------ = system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-22 freescale semiconductor although the writes must occu r in the correct or der prior to time-out, any num ber of instructions may be executed between the writes. this a llows interrupts and exceptions to o ccur, if necessary, between the two writes. figure 6-9. swt state diagram although most software disciplines support the watc hdog concept, different systems require different time-out periods. for this reason, the software watc hdog provides a selectable range for the time-out period. in figure 6-10 , the range is determined by th e value in the swtc field. the value held in the swtc field is then loaded into a 16-bit decrementer clocke d by the system clock. an additional divide by 2048 prescaler is used if necessary. the decrementer be gins counting when loaded with a value from the software watchdog timing count fi eld (swtc). after the timer re aches 0x0, a software watchdog expiration request is issued to the reset or nmi control logic. upon reset, the value in the swtc is set to the ma ximum value and is again loaded into the software watchdog register (swr), starting th e process over. when a new value is loaded into the swtc, the software watchdog timer is not updated until the servic ing sequence is written to the swsr. if the swe is loaded with the value zero, the modulus c ounter does not count (i.e . swtc is disabled). 0x556c/don?t reload reset 0xaa39/reload state 0 waiting for 0x556c state 1 waiting for 0xaa39 not 0xaa39/don?t reload not 0x556c/don?t reload not 0x556c/don?t reload system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-23 figure 6-10. swt block diagram 6.1.11 freeze operation when the freeze line is asserted, the clocks to the so ftware watchdog, the period ic interrupt timer, the real-time clock, the time base count er, and the decrementer can be disa bled. this is controlled by the associated bits in the control re gister of each timer. if programme d to stop during fr eeze assertion, the counters maintain their values while freeze is asse rted. the bus monitor rema ins enabled regardless of this signal. 6.1.12 low power stop operation when the processor is set in a lo w-power mode (doze, sleep, or deep -sleep), the software watchdog timer is frozen. it remains frozen and ma intains its count value until the pro cessor exits this state and resumes executing instructions. the periodic interrupt timer, decremen ter, and time base ar e not affected by these low-power modes. they continue to run at their respective fr equencies. these timers are capable of generating an in terrupt to bring the mcu out of these low-power modes. 6.2 memory map and register definitions this section provides the mpc561/mpc563 memory map, register diagrams and bit descriptions of the system configuration a nd protection registers. 6.2.1 memory map the mpc561/mpc563 internal memory space can be assigned to one of eight locations. disable clock freeze swr/decrementer time-out 16-bit swtc swe service logic reload rollover = 0 reset swsr mux 2048 system swp clock divide by or nmi (sypcr) (sypcr) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-24 freescale semiconductor the internal memory map is organize d as a single 4-mbyte bl ock. the user can assign this block to one of eight locations by programming the is b field in the internal memory mapping register (immr). the eight possible locations are the first eight 4-mbyte memory blocks starting with address 0x0000 0000. (refer to figure 6-11 .) figure 6-11. mpc561/mpc563 memory map 6.2.2 system configuration and protection registers this section describes th e mpc561/mpc563 registers. 6.2.2.1 system configuration registers system configuration register s include the siumcr, the im mr, and the emcr registers. 0x0000 0000 0x003f ffff 0x0040 0000 0x007f ffff 0x0080 0000 0x00bf ffff 0x00c0 0000 0x00ff ffff 0x0100 0000 0x013f ffff 0x0140 0000 0x017f ffff 0x0180 0000 0x01bf ffff 0x01c0 0000 0x01ff ffff 0xffff ffff internal 4-mbyte memory block (resides in one of eight locations) system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-25 6.2.2.1.1 siu module confi guration register (siumcr) the siumcr contains bits which configure various feat ures in the siu module. th e register contents are shown below. warning all siumcr fields which are controll ed by the reset configuration word should not be changed by software while the correspondi ng functions are active. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field earb earp ? dshw dbgc ? at w c g p c d l k hreset id0 1 000_0000_0 id[9:10] 1 id11 1 id12 1 000 addr 0x2f c000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sc rctx mlrc ? mtsc nos how eicen lpmask _en burst _en ? hreset 0 id[17:18] 1 0_0000_0000_0000 1 the reset value is a reset configuration word value, extracted from the internal data bus line. refer to section 7.5.2, ?hard reset configuration word (rcw) .? figure 6-12. siu module config uration register (siumcr) table 6-7. siumcr bit descriptions bits name description 0 earb external arbitration 0 internal arbitration is performed 1 external arbitration is assumed 1:3 earp external arbitration request priority. this fi eld defines the priority of an external master?s arbitration request. this field is valid when earb is cleared. refer to section 9.5.7.4, ?internal bus arbiter ,? for details. 4:7 ? reserved 8 dshw data show cycles. this bit selects the show cycle mode to be applied to u-bus data cycles (data cycles to imb modules and flash eeprom). this field is locked by the dlk bit. note that instruction show cycles are programmed in the ictrl and l-bus data show cycles are programmed in the l2umcr. 0 disable show cycles for all internal data cycles 1 show address and data of all internal data cycles 9:10 dbgc debug pins conf iguration. refer to ta bl e 6 - 8 . 11 dbpc reserved. 12 atwc address write type enable config uration. this bit configures the pins to function as byte write enables or address types for debugging purposes. 0we [0:3]/be [0:3]/at[0:3] functions as we [0:3]/be [0:3] 1 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-26 freescale semiconductor 13:14 gpc this bit configures the pins as shown in ta bl e 6 - 9 . 15 dlk debug register lock 0 normal operation 1 siumcr is locked and can be written only in test mode or when the internal freeze signal is asserted. 16 ? reserved 17:18 sc single-chip select. this field configures the functionality of the address and data buses. changing the sc field while external accesses are performed is not supported. refer to ta b l e 6 - 1 0 . 19 rctx reset configuration/timer expired. duri ng reset the rstconf/ texp pin functions as rstconf. after reset the pin can be configured to function as texp, the timer expired signal that supports the low-power modes. 0 rstconf/texp functions as rstconf 1 rstconf/texp functions as texp 20:21 mlrc multi-level reservation control. this field selects between the functionalit y of the reservation logic and irq pins, refer to ta b l e 6 - 1 1 . 22:23 ? reserved 24 mtsc memory transfer start control. 0irq2 /cr/ sgpioc2/mts functions according to the mlrc bits setting 1irq2 /cr/ sgpioc2/mts functions as mts 25 noshow instruction show cycl es disabled. if the noshow bit is set (1), then all instruction show cycles are not transmitted to the external bus. 26 eicen enhanced interrupt controller enable. see section 6.1.4.4, ?enhanced interrupt controller operation ,? for more information. 0 enhanced interrupt controller operates in regular mode (compatible with mpc555/mpc556) 1 enhanced interrupt controller is enabled 27 lpmask_en low priority request masking enable. 0 lower priority interrupt request masking is disabled 1 lower priority interrupt request masking is enabled 28 burst_en burst enable. 0 burst operation is enabled by the bbcmcr[be]. maximum burst length is fixed at 4 beats. 1 usiu initiated burst accesses on the external bus. maximim burst length can be 4 or 8 beats and this may be programmed per memory region. refer to section 10.2.5, ?burst support ,? for more information. note: do not assert tea on the external bus for instruction fetch while siumcr[burst_en] = 1. do not pl ace code at the last 8 words of a memory controller region while siumcr[burst_en] = 1. 29:31 ? reserved 1 we /be is selected per memory region by webs in the appropriate br register in the memory controller. table 6-7. siumcr bit descriptions (continued) bits name description system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-27 table 6-8. debug pins configuration dbgc pin function iwp[0:1]/vfls[0:1] bi /sts bg /vf0/lwp1 br /vf1/iwp2 bb /vf2/iwp3 00 vfls[0:1] bi bg br bb 01 iwp[0:1] sts bg br bb 10 vfls[0:1] sts vf0 vf1 vf2 11 iwp[0:1] sts lwp1 iwp2 iwp3 table 6-9. general pins configuration gpc pin function frz/ptr/sgpioc6 irqout /lwp0/sgpioc7 00 ptr lwp0 01 sgpioc6 sgpioc7 10 frz lwp0 11 frz irqout table 6-10. single-chip sel ect field pin configuration sc pin function data[0:15]/ sgpiod[0:15] data[16:31] sgpiod[16:31] addr[8:31]/ sgpioa[8:31] 00 (multiple chip, 32-bit port size) data[0:15] data[16:31] addr[8:31] 01 (multiple chip, 16-bit port size data[0:15] spgiod[16:31] addr[8:31] 10 (single-chip with address show cycles for debugging) spgiod[0:15] spgiod[16:31] addr[8:31] 11 (single-chip) spgiod[0: 15] spgiod[16:31] spgioa[8:31] system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-28 freescale semiconductor 6.2.2.1.2 internal memory map register (immr) the internal memory map register (immr) is a re gister located within the mpc561/mpc563 special register space. the immr contains id entification of a specific device as well as the base for the internal memory map. based on the value read from this register, software can deduce availability and location of any on-chip system resources. this register can be read by the mfspr instruction. the isb field can be written by the mtspr instruction. the partnum and masknum fields are ma sk programmed and cannot be changed. table 6-11. multi-level reservation control pin configuration mlrc pin function irq0 / sgpioc0/ mdo4 irq1 /rsv / sgpioc1 irq2 /cr/ sgpioc2/mts irq3 /kr / retry /sgpioc3 irq4 /at2/ sgpioc4 irq5 / sgpioc5/modck1 1 1 operates as modck1 during reset. 00 irq0 irq1 irq2 2 2 this is true if mtsc is reset to 0. otherwise, irq2 /cr/ sgpioc2/mts will function as mts . irq3 irq4 irq5 /modck1 01 irq0 rsv cr 2 kr /retry at 2 i r q 5/ modck1 10 sgpioc0 sgpioc1 sgpioc2 2 sgpioc3 sgpioc4 sgpioc5/modck1 11 irq0 irq1 sgpioc2 2 kr /retry at2 sgpioc5/modck1 msb 0 1 2 3 4 5 6 7 8 9 101112131415 field partnum masknum hreset 0 011 0 x 1 x 1 x 1 read-only fixed value 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? flen ? ? ? isb ? hreset 0000 id20 1 00 id23 2 0000 id[28:30] 1 0 addr spr 638 1 the reset value is 101 for mpc561 and 110 for mpc563. 2 the reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. refer to section 7.5.2, ?hard reset configuration word (rcw) .? figure 6-13. internal memory mapping register (immr) system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-29 6.2.2.1.3 external master control register (emcr) the external master control register selects the exte rnal master modes and determines the internal bus attributes for external-to-internal accesses. table 6-12. immr bit descriptions bits name description 0:7 partnum this read-only field is mask programmed with a code corresponding to the part number of the part on which the siu is located. it is int ended to help factory test and user code which is sensitive to part changes. this changes when the part number changes. for example, it would change if any new module is added, if th e size of any memory module is changed. it would not change if the part is changed to fi x a bug in an existing module. the mpc561 has an id of 0x35. the mpc563 has an id of 0x36. 8:15 masknum this read-only field is mask programmed with a code corresponding to the mask number of the part. it is intended to help factory test and user code which is sensitive to part changes. 16:19 ? reserved 20 flen flash enable is a read-write bit. the defaul t state of flen is negated, meaning that the boot is performed from external memory. this bit can be set at reset by the reset configuration word. 0 on-chip flash memory is disa bled, and all in ternal cycles to the allocated flash address space are mapped to external memory 1 on-chip flash memory is enabled 21:22 ? reserved 23 ? reserved. this bit should be programmed to 0 at all times. 24:27 ? reserved 28:30 isb this read-write field defines the base address of the internal memory space. the initial value of this field can be configured at reset to one of eight addresses, and then can be changed to any value by software. internal base addresses are as follows: 000 0x0000 0000 001 0x0040 0000 010 0x0080 0000 011 0x00c0 0000 100 0x0100 0000 101 0x0140 0000 110 0x0180 0000 111 0x01c0 0000 31 ? reserved system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-30 freescale semiconductor msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ? hreset 0000_0000_0000_0000 addr 0x2f c030 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field prpm slvm ? size supu inst ? resv cont ? trac sizen ? hreset id16 1 00 01 01 00 1 101 1 00 1 the reset value is a reset configuration word value, extr acted from the indicated internal data bus line. refer to section 7.5.2, ?hard reset configuration word (rcw) .? figure 6-14. external master control register (emcr) table 6-13. emcr bit descriptions bits name description 0:15 ? reserved 16 prpm peripheral mode. in this mode, the internal rcpu core is shut off and an alternative master on the external bus can access any internal slave module. the reset value of this bit is determined by the reset configuration word bit 16. the bit can also be written by software. 0 normal operation 1 peripheral mode operation 17 slvm slave mode (valid only if prpm = 0). in this mode, an alternative master on the external bus can access any internal slave module while the internal rcpu core is fully operational. if prpm is set, the value of slvm is a ?don?t care.? 0 normal operation 1slave mode 18 ? reserved 19:20 size size attribute. if sizen = 1, the size bits controls the in ternal bus attributes as follows: 00 double word (8 bytes) 01 word (4 bytes) 10 half word (2 bytes) 11 byte 21 supu supervisor/user attribute. supu controls the supervisor/user attribute as follows: 0 supervisor mode access permitted to all registers 1 user access permitted to registers designated ?user access? 22 inst instruction attribute. inst controls the internal bus instruction attribute as follows: 0 instruction fetch 1 operand or non-cpu access 23:24 ? reserved 25 resv reservation attribute. resv controls the internal bus reservation attribute as follows: 0 storage reservation cycle 1 not a reservation system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-31 6.2.2.2 siu interrupt controller registers the siu interrupt controller contai ns the following registers: sipend, sipend2 and sipend3 (interrupt pending registers), simask, simask 2 and simask3 (interrupt mask registers), siel, sivec, sisr2 and sisr3. the sipend and simask registers are used when the interrupt controller is configured for regular, mpc555/mpc556 compatible, operation. sipe nd2, sipend3, simask2, simask3, sisr2 and sisr3 registers are used only when the interrupt c ontroller is operating in enhanced interrupt mode. sipend, sipend2 and sipend3 are 32-bi t registers. each bit in the regi ster corresponds to an interrupt request. the bits associated with inte rnal exceptions indicate, if set, th at an interrupt service is requested. these bits reflect the status of the internal request ing device, and will be cleared when the appropriate actions are initiated by software in the device itself. writing to these bits has no effect. the bits associated with the irq pins have a different behavior de pending on the sensitivity defined for them in the siel register. when the irq is defined as a ?level? interr upt the corresponding bit behaves in a manner similar to the bits associated with internal in terrupt sources, (i.e., it re flects the status of the irq pin). this bit can not be changed by software, it will be cl eared when the external signal is negated. when the irq is defined as an ?edge? interrupt, if the corresponding bit is set, it indicates that a falling edge was detected on the line. the bit must be re set by software by writing a ?1? to it. the following acronym definitions a pply to the various bits implemente d in the siu interrupt controller registers. 26 cont control attribute. cont drives the internal bus control bit attribute as follows: 0 access to mpc561/mpc563 control register, or control cycle access 1 access to global address map 27 ? reserved 28 trac trace attribute. trac controls the internal bus program trace attribute as follows: 0 program trace 1 not program trace 29 sizen external size enable control bit. sizen determ ines how the internal bus size attribute is driven: 0 drive size from external bus signals tsize[0:1] 1 drive size from size0, size1 in emcr 30:31 ? reserved table 6-14. siu interrupt controller ? bit acronym definitions name description irq n interrupt signal n request lv l n interrupt level n request imbirq n intermodule bus interrupt level n request irm n interrupt signal n mask table 6-13. emcr bit descriptions (continued) bits name description system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-32 freescale semiconductor 6.2.2.2.1 siu interrupt pe nding register (sipend) 6.2.2.2.2 siu interrupt pend ing register 2 (sipend2) lv m n interrupt level n mask ed n falling edge detect, interrupt signal n wm n wakeup mask, interrupt signal n msb 0123456789101112131415 fieldirq0lvl0irq1lvl1irq2lvl2irq3lvl3irq4lvl4irq5lvl5irq6lvl6irq7lvl7 sreset 0000_0000_0000_0000 addr 0x2f c010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 6-15. siu interrupt pending register (sipend) msb 0123456789101112131415 field irq0 lvl0 imb irq0 imb irq1 imb irq2 imb irq3 irq1 lvl1 imb irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset 0000_0000_0000_0000 addr 0x2f c040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field imb irq10 imb irq1 1 irq3 lvl3 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset 0000_0000_0000_0000 figure 6-16. siu interrupt pending register 2 (sipend2) table 6-14. siu interrupt controller ? bit acronym definitions name description system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-33 6.2.2.2.3 siu interrupt pend ing register 3 (sipend3) 6.2.2.2.4 siu interrupt mask register (simask) simask is a 32-bit read/write register . each bit in the register correspo nds to an interrupt request bit in the sipend register. simask2 is a 32-bit read/write regist er. each bit in the register corres ponds to an interrupt request bit in the sipend2 register. simask3 is a 32-bit read/write regist er. each bit in the register corres ponds to an interrupt request bit in the sipend3 register. when the bit is set, it enables the generation of an interrupt request to the rcpu. simask, simask2, simask3 are updated by software and cleared upon reset. it is the responsibility of the software to determine which of the interrupt s ources are enabled at a given time. note disable external interrupts in the co re prior to changing any interrupt controller related register (simask, sipend, siel, or sisr). refer to msr[ee] bit description in table 3-11 and the note regarding special handling of the eic in section 6.1.4.4, ?enhanced interrupt controller operation .? msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field imb irq20 imb irq21 imb irq22 imb irq23 irq 6 lv l 6 imb irq24 imb irq25 imb irq26 imb irq27 irq 7 lv l 7 imb irq28 imb irq29 imb irq30 imb irq31 sreset 0000_0000_0000_0000 addr 0x2f c044 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 6-17. siu interrupt pending register 3 (sipend3) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-34 freescale semiconductor 6.2.2.2.5 siu interrupt mask register 2 (simask2) msb 0 123456789101112131415 field irm0 1 lvm0 irm1 lvm1 irm2 lvm2 irm3 lvm3 irm4 lvm4 irm5 lvm5 irm6 lvm6 irm7 lvm7 sreset 0000_0000_0000_0000 addr 0x2f c014 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 1 irq0 of the sipend register is not affe cted by the setting or clearing of the irm0 bit of the simask register. irq0 is a non-maskable interrupt. figure 6-18. siu interrupt mask register (simask) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field irq0 1 lv l 0 i m b irq0 imb irq1 imb irq2 imb irq3 irq1 lvl1 imb irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset 0000_0000_0000_0000 addr 0x2f c048 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field imb irq10 imb irq1 1 irq3 lvl3 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset 0000_0000_0000_0000 1 irq 0 of the sipend2 register is not affect ed by the setting or clearing of the irq0 bit of the si mask2 register. irq 0 is a non-maskable interrupt figure 6-19. siu interrupt mask register 2 (simask2) system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-35 6.2.2.2.6 siu interrupt mask register 3 (simask3) 6.2.2.2.7 siu interrupt ed ge level register (siel) the siel is a 32-bit read/write regist er. each pair of bits corresponds to an external interrupt request. the edx bit, if set, specifies that a falling edge in the corresponding irq line will be detect ed as an interrupt request. when the edx bit is 0, a low logical level in the irq line will be detected as an interrupt request. the wmx (wake-up mask) bit, if set, indicates that an interrupt request detection in th e corresponding line causes the mpc561/mpc563 to exit low-power mode. 6.2.2.2.8 siu interrupt vector register (sivec) the sivec is a 32-bit read-only regi ster that contains an 8-bit code representing the unmasked interrupt source of the highest priority level. the sivec can be read as either a byte, ha lf word, or word. when read as a byte, a branch table ca n be used in which each entry contains one instruction (branch). when read as a half-word, each entry can contain a full routine of up to 256 instructions. the interrupt code is defined such that its two least si gnificant bits are 0, thus allowing indexi ng into the table. the two possible ways of the code usage are shown on figure 6-23 . msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field imb irq20 imb irq21 imb irq22 imb irq23 irq 6 lv l 6 imb irq24 imb irq25 imb irq26 imb irq27 irq 7 lv l 7 imb irq28 imb irq29 imb irq30 imb irq31 sreset 0000_0000_0000_0000 addr 0x2f c04c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 6-20. siu interrupt mask register 3 (simask3) msb 0123456789101112131415 fielded0wm0ed1wm1ed2wm2ed3wm3ed4wm4ed5wm5ed6wm6ed7wm7 hreset 0000_0000_0000_0000 addr 0x2f c018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? hreset 0000_0000_0000_0000 figure 6-21. siu interrupt edge level register (siel) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-36 freescale semiconductor figure 6-23. example of sivec register usage for interrupt table handling msb 0123456789101112131415 field interrupt code ? reset 0011_1100 0000_0000 addr 0x2f c01c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? reset 0000_0000_0000_0000 figure 6-22. siu interrupt vector register (sivec) intr: ... save state r3 @sivec r4 base of branch table ... lbz rx, r3 (0)# load as byte add rx, rx, r4 mtsprctr, rx bctr intr: ... save state r3 @sivec r4 base of branch table ... lhz rx, r3 (0)# load as half add rx, rx, r4 mtspr ctr, rx bctr base b routine1 b routine2 b routine3 b routine4 ? ? base + n base + 4 base + 8 base + c base +10 base 1st instructio n of routine1 1st instructio n of routine2 1st instructio n of routine3 1st instructio n of routine4 ? ? base + n base + 400 base + 800 base + c00 base +1000 ? ? ? ? ? ? ? ? ? ? ? ? system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-37 6.2.2.2.9 interrupt in-service registers (sisr2 and sisr3) sisr2, sisr3 are 32-bit read/write regi sters. each bit in the register corresponds to an interrupt request. a bit is set if: ? there is a pending interrupt request (sipend2/3 ), that is not masked by (simask2/3), and ? the bbc/impu acknowledges interrupt request and latches sivec value. once a bit is set, all request s with lower or equal prior ity become masked (i.e. th ey will not generate any interrupt request to the rcpu) until th e bit is cleared. a bit is cleared by writing a ?1? to it. writing zero has no effect. 6.2.2.3 system protection registers 6.2.2.3.1 system protection control register (sypcr) the system protection control register (sypcr) c ontrols the system monitors, the software watchdog period, and the bus monitor timing. this register can be read at any time , but can be wri tten only once after system reset. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field irq0 lv l 0 imb irq0 imb irq1 imb irq2 imb irq3 irq1 lv l 1 i m b irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset 0000_0000_0000_0000 addr 0x2f c050 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field imb irq10 imb irq11 irq3 lvl4 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset 0000_0000_0000_0000 figure 6-24. interrupt in-service register 2 (sisr2) msb 0 1 2 3456 7 8 9101112131415 field imb irq20 imb irq21 imb irq22 imb irq23 irq 6 lv l 6 imb irq24 imb irq25 imb irq26 imb irq27 irq 7 lv l 7 imb irq28 imb irq29 imb irq30 imb irq31 sreset 0000_0000_0000_0000 addr 0x2f c054 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 6-25. interrupt in-service register 3 (sisr3) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-38 freescale semiconductor 6.2.2.3.2 software serv ice register (swsr) the swsr is the location to which the swt servici ng sequence is written. to prevent swt time-out, a 0x556c followed by 0xaa39 should be writ ten to this register. the swsr can be written at any time but returns all zeros when read. msb 01234567 8 9101112131415 field swtc hreset 1111_1111_1111_1111 addr 0x2f c004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field bmt bme ? swf swe swri swp hreset 1111_1111 0 000 0 1 1 1 figure 6-26. system protection control register (sypcr) table 6-15. sypcr bit descriptions bits name description 0:15 swtc software watchdog timer count. this field contains the count value of the software watchdog timer. 16:23 bmt bus monitor timing. this fiel d specifies the ti me-out period, in eight-syst em-clock resolution, of the bus monitor. bmt must be set to non zero even if the bus monitor is not enabled. 24 bme bus monitor enable 0 disable bus monitor 1 enable bus monitor 25:27 ? reserved 28 swf software watchdog freeze 0 software watchdog continues to run while freeze is asserted 1 software watchdog stops while freeze is asserted 29 swe software watchdog enable. software should cl ear this bit after a system reset to disable the software watchdog timer. 0 watchdog is disabled 1 watchdog is enabled 30 swri software watchdog reset/interrupt select 0 software watchdog time-out causes a non-maskable interrupt to the rcpu 1 software watchdog time-out causes a system reset 31 swp software watchdog prescale 0 software watchdog timer is not prescaled 1 software watchdog timer is prescaled by 2048 system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-39 6.2.2.3.3 transfer error status register (tesr) the transfer error status register contains a bit for each exception source generated by a transfer error. a bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were cleared by reset or by the normal softwa re status bit-clearing mechanism. note these bits may be set due to cance led speculative accesses which do not cause an interrupt. the regi ster has two identical sets of bit fields; one is associated with instruction transfer s and the other with data transfers. msb 01234567891011121314 lsb 15 field swsr reset 0000_0000_0000_0000 addr 0x2f c00e figure 6-27. software service register (swsr) table 6-16. swsr bit descriptions bits name description 0:15 swsr swt servicing sequence is written to this register. to prevent swt time-out, a 0x556c followed by 0xaa39 should be written to this register. the swsr can be written at any time but returns all zeros when read. msb 0123456789101112131415 field ? reset 0000_0000_0000_0000 addr 0x2f c020 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? iext ibmt ? dext dbm ? reset 0000_0000_0000_0000 figure 6-28. transfer error status register (tesr) table 6-17. tesr bit descriptions bits name description 0:17 ? reserved 18 iext instruction external transfer error acknowledge. this bit is set if the cycle was terminated by an externally generated tea signal when an instruction fetch was initiated. 19 ibmt instruction transfer monitor time out. this bit is set if the cycl e was terminated by a bus monitor time-out when an instruction fetch was initiated. system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-40 freescale semiconductor 6.2.2.4 system timer registers the following sections describe regi sters associated with the system timers. these facilities are powered by the kapwr and can preserve their value when the main power supply is off. refer to section 8.2.3, ?pre-divider ,? for details on the required act ions needed in order to guarantee this data retention. a list of kapwr registers affected by the key/lock mechanism is found in table 8-8 . 6.2.2.4.1 decrementer register (dec) the 32-bit decrementer register is de fined by the powerpc architecture. the values stored in this register are used by a down counter to cause decremente r exceptions. the decremen ter causes an exception whenever bit zero changes from a logi c zero to a logic one. a read of this register always returns the current count value from the down counter. contents of this register can be r ead or written to by the mfspr or th e mtspr instruction. the decrementer register is reset by poreset . hreset and sreset do not affect this register. the decrementer is powered by standby power and can continue to count when standby power is applied. decrementer counts down the time ba se clock and the counting is enab led by tbe bit in tbcsr register section 6.2.2.4.4, ?time base control and status register (tbscr) .? refer to section 3.9.5, ?decrementer register (dec) ? for more information on this register. 6.2.2.4.2 time base sprs (tb) the tb is a 64-bit register cont aining a 64-bit integer that is in cremented periodically. there is no automatic initialization of the tb; th e system software must perform this initialization. the contents of the 20:25 ? reserved 26 dext data external transfer error acknowledge. th is bit is set if the cycle was terminated by an externally generated tea signal when a data load or store is requested by an internal master. 27 dbm data transfer monitor time out. this bit is set if the cycle was te rminated by a bus monitor time-out when a data load or store is requested by an internal master. 28:31 ? reserved msb 0 lsb 31 field decrementing counter poreset 0000_0000_0000_0000_0000_0000_0000_0000 hreset sreset unaffected addr spr 22 figure 6-29. decrementer register (dec) table 6-17. tesr bit descriptions (continued) bits name description system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-41 register may be written by the mttb l or the mttbu instructions, see section 3.9.4, ?time base facility (tb) ? oea .? refer to section 3.8, ?vea register set ? time base (tb) ? and section 3.9.4, ?time base facility (tb) ? oea ? for more information on reading and writing the tbu and tbl registers. 6.2.2.4.3 time base referen ce registers (t bref0 and tbref1) two reference registers (tbref0 and tbref1) are associated with the lo wer part of the time base (tbl). each is a 32-bit read/write register. upon a match be tween the contents of tbl and the reference register, a maskable interrupt is generated. msb 03132 lsb 63 field tbu tbl poreset unaffected addr spr 269, spr 268 figure 6-30. time base (reading) (tb) msb 03132 lsb 63 field tbu tbl poreset unaffected addr spr 285, spr 284 figure 6-31. time base (writing) (tb) msb 0 lsb 31 field tbref0 reset unaffected addr 0x2f c204 figure 6-32. time base reference register 0 (tbref0) msb 0 lsb 31 field tbref1 reset unaffected addr 0x2f c208 figure 6-33. time base reference register 1 (tbref1) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-42 freescale semiconductor 6.2.2.4.4 time base contro l and status register (tbscr) the tbscr is 16-bit read/write regi ster. it controls the tb, decrementer count enable, and interrupt generation and is used for reporting th e source of the interrupts. the regist er can be read anytime. a status bit is cleared by writing a one to it. (writing a zero has no effect.) more than one bit can be cleared at a time. 6.2.2.4.5 real-time clock status and control register (rtcsc) the rtcsc enables the different rtc functions and repor ts the source of the interrupts. the register can be read anytime. a status bit is cl eared by writing a one to it. (writing a zero does not affect a status bit?s value.) more than one status bit can be cleared at a time. this register is locked after reset by default. unlocking is accomplished by writing 0x55cc a a33 to its associated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism .? msb 01234567 8 9 1011 12 13 14 lsb 15 field tbirq refa refb ? refae refbe tbf tbe poreset 0000_0000_0000_0000 addr 0x2f c200 figure 6-34. time base control and status register (tbscr) table 6-18. tbscr bit descriptions bits name description 0:7 tbirq time base interrupt request. these bits dete rmine the interrupt priority level of the time base. refer to section 6.1.4, ?enhanced interrupt controller ? for interrupt level encoding. 8 refa reference a (tbref0) interrupt status. 0 no match detected 1 tbref0 value matches value in tbl 9 refb reference b (tbref1) interrupt status. 0 no match detected 1 tbref1 value matches value in tbl 10:11 ? reserved 12 refae reference a (tbref0) interrupt enable. if this bit is set, the time base generates an interrupt when the refa bit is set. 13 refbe reference b (tbref1) interrupt enable. if this bit is set, the time base generates an interrupt when the refb bit is set. 14 tbf time base freeze. if this bit is set, the time base and decrementer stop while freeze is asserted. 15 tbe time base enable 0 time base and decrementer are disabled 1 time base and decrementer are enabled system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-43 6.2.2.4.6 real-time clock register (rtc) the real-time clock register is a 32- bit read write register. it contains the current value of the real-time clock. a write to the rtc resets the seconds timer to zero. this register is locked after reset by default. unlocking is accomplished by writing 0x55cc a a33 to its associated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism .? msb 01234567 8 9 10 11 12 13 14 lsb 15 field rtcirq sec alr ? 4m sie ale rtf rte poreset 0000_0000_000 u 000 u addr 0x2f c220 figure 6-35. real-time clock status and control register (rtcsc) table 6-19. rtcsc bit descriptions bits name description 0:7 rtcirq real-time clock interrupt request. thee bits determine the interrupt priority level of the rtc. refer to section 6.1.4, ?enhanced interrupt controller ? for interrupt level encoding. 8 sec once per second interrupt. this status bit is set every second. it should be cleared by the software. 9 alr alarm interrupt. this status bit is set when the value of the rtc equals the value programmed in the alarm register. 10 ? reserved 11 4m real-time clock source 0 rtc assumes that it is driven by 20 mhz to generate the seconds pulse. 1 rtc assumes that it is driven by 4 mhz 12 sie second interrupt enable. if th is bit is set, the rtc generates an interrupt when the sec bit is set. 13 ale alarm interrupt enable. if this bit is set, the rtc generates an interrupt when the alr bit is set. 14 rtf real-time clock freeze. if this bit is set, the rtc stops while freeze is asserted. 15 rte real-time clock enable 0 rtc is disabled 1 rtc is enabled msb 0 lsb 31 field rtc reset unaffected addr 0x2f c224 figure 6-36. real-time clock register (rtc) system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-44 freescale semiconductor 6.2.2.4.7 real-time clock alarm register (rtcal) the rtcal is a 32-bit read/write register. when the value of the rtc is equal to the value programmed in the alarm register, a maskable interrupt is generated. the alarm interrupt will be gene rated as soon as there is a matc h between the alarm field and the corresponding bits in the rtc. the resolution of the al arm is 1 second. this regist er is locked after reset by default. unlocking is accomplished by writing 0x55cc aa33 to its associ ated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism .? 6.2.2.4.8 periodic interrupt stat us and control register (piscr) the piscr contains the interrupt reques t level and the interrupt status bit. it also contains the controls for the 16-bits to be loaded into a modulus counter. th is register can be read or written at any time. msb 0 lsb 31 field alarm reset unaffected addr 0x2f c22c figure 6-37. real-time clock alarm register (rtcal) msb 01234567 8 910111213 14 lsb 15 field pirq ps ? pie pitf pte poreset 0000_0000_0000_0000 addr 0x2f c240 figure 6-38. periodic interrupt status and control register (piscr) table 6-20. piscr bit descriptions bits name description 0:7 pirq periodic interrupt request. these bits determine the interrupt priority level of the pit. refer to section 6.1.4, ?enhanced interrupt controller ? for interrupt level encoding. 8 ps periodic interrupt status. this bit is set if the pit issues an interrupt. the pit issues an interrupt after the modulus counter counts to zero. ps can be negated by writing a one to it. a write of zero has no affect. 9:12 ? reserved 13 pie periodic interrupt enable. if this bit is set, th e time base generates an interrupt when the ps bit is set. 14 pitf pit freeze. if this bit is set, the pit stops while freeze is asserted. 15 pte periodic timer enable 0 pit stops counting and maintains current value 1 pit continues to decrement system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-45 6.2.2.4.9 periodic interrupt timer count register (pitc) the pitc register contains the 16-bi ts to be loaded in a modulus count er. this register is readable and writable at any time. 6.2.2.4.10 periodic interrupt timer register (pitr) the periodic interrupt register is a re ad-only register that shows the curr ent value in the periodic interrupt down counter. read or writing this re gister does not affect the register. msb 0123456789101112131415 field pitc reset unaffected addr 0x2f c244 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? reset unaffected figure 6-39. periodic interrupt timer count (pitc) table 6-21. pitc bit descriptions bits name description 0:15 pitc periodic interrupt timing count. this field cont ains the 16-bit value to be loaded into the modulus counter that is loaded into the periodic timer. this register is readable and writable at any time. 16:31 ? reserved msb 0123456789101112131415 field pit reset unaffected addr 0x2f c248 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? reset unaffected figure 6-40. periodic interru pt timer register (pitr) table 6-22. pit bit descriptions bits name description 0:15 pit periodic interrupt timing count?this field contains the current count remaining for the periodic timer. writes have no effect on this field. 16:31 ? reserved system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-46 freescale semiconductor 6.2.2.5 general-purpose i/o registers 6.2.2.5.1 sgpio data r egister 1 (sgpiodt1) msb 0123456789101112131415 field sgpiod[0:7] sgpiod[8:15] reset 0000_0000_0000_0000 1 addr 0x2f c024 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field sgpiod[16:23] sgpiod[24:31] reset 0000_0000_0000_0000 1 1 if the device is configured not in full bus mode (i.e., siumcr[sc]=0b01, 0x10, or 0b11), the gpio pins will be in input mode and this register will reflect the state of the pins. figure 6-41. sgpio data register 1 (sgpiodt1) table 6-23. sgpiodt1 bit descriptions bits name description 0:7 sgpiod[0:7] siu general-purpose i/o group d[0:7]. this 8-bit register controls the data of general-purpose i/o pins sgpiod[0:7]. the directio n (input or output) of this group of pins is controlled by the gddr0 bit in the sgpio control register. 8:15 sgpiod[8:15] siu general-purpose i/o group d[8:15 ]. this 8-bit register controls the data of general-purpose i/o pins sgpiod[8:15]. the direction (input or output) of this group of pins is controlled by the gddr1 bi t in the sgpio control register. 16:23 sgpiod[16:23] siu general-purpose i/o group d[16: 23]. this 8-bit register controls the data of the general-purpose i/o pins sgpiod[16:23]. the dire ction (input or output) of this group of pins is controlled by the gddr2 bit in the sgpio control register 24:31 sgpiod[24:31] siu general-purpose i/o group d[24: 31]. this 8-bit register controls the data of the general-purpose i/o pins sgpiod[24:31]. the di rection of sgpiod[24:31] is controlled by eight dedicated direction control signals sddrd[24:31]. each pin in this group can be configured separately as general-purpose input or output. system configurat ion and protection mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 6-47 6.2.2.5.2 sgpio data r egister 2 (sgpiodt2) msb 0123456789101112131415 field sgpioc[0:7] sgpioa[8:15] reset 0000_0000_0000_0000 1 addr 0x2f c028 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field sgpioa[16:23] sgpioa[24:31] reset 0000_0000_0000_0000 1 1 if the device is configured not in full bus mode (i.e., si umcr[sc]=0b01, 0x10, or 0b11), the gpio pins will be in input mode and this register will re flect the state of the pins. figure 6-42. sgpio data register 2 (sgpiodt2) table 6-24. sgpiodt2 bit descriptions bits name description 0:7 sgpioc[0:7] siu general-purpose i/o group c[0:7]. this 8-bit register c ontrols the data of the general-purpose i/o pins sgpioc[0:7]. the di rection of sgpioc[0:7] is controlled by 8 dedicated direction control signals sddrc[0:7] in the sgpio control register. each pin in this group can be configured separately as general-purpose input or output. 8:15 sgpioa[8:15] siu general-purpose i/o group a[8:15]. this 8-bit regi ster controls the data of the general-purpose i/o pins sgpioa[8:15]. the gddr3 bit in the sgpio control register configures these pins as a group as general-purpose input or output. 16:23 sgpioa [16:23] siu general-purpose i/o group a[16:23]. this 8-bit register controls the data of the general-purpose i/o pins sgpioa[16:23]. the gddr4 bit in the sgpio control register configures these pins as a group as general-purpose input or output. 24:31 sgpioa [24:31] siu general-purpose i/o group a[24:31]. this 8-bit register controls the data of the general-purpose i/o pins sgpioa[24:31]. the gddr5 bit in the sgpio control register configures these pins as a group as general-purpose input or output. system configuration and protection mpc561/mpc563 reference manual, rev. 1.2 6-48 freescale semiconductor 6.2.2.5.3 sgpio contro l register (sgpiocr) 1 table 6-26 describes the bit values for data direction control. msb 0123456789101112131415 field sddrc[0:7] ? hreset 0000_0000_0000_0000 addr 0x2f c02c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field gddr 0 gddr 1 gddr 2 gddr 3 gddr 4 gddr 5 ? sddrd[24:31] hreset 0000_0000_0000_0000 figure 6-43. sgpio control register (sgpiocr) table 6-25. sgpiocr bit descriptions bits name description 0:7 sddrc[0:7] sgpio data direction fo r sgpioc[0:7]. each sddr bit zero to seven controls the direction of the corresponding sgpioc pin zero to seven 8:15 ? reserved 16 gddr0 group data direction for sgpiod[0:7] 17 gddr1 group data direction for sgpiod[8:15] 18 gddr2 group data direction for sgpiod[16:23] 19 gddr3 group data direction for sgpioa[8:15] 20 gddr4 group data direction for sgpioa[16:23] 21 gddr5 group data direction for sgpioa[24:31] 22:23 ? reserved 24:31 sddrd [24:31] sgpio data direction for sgpiod[24:31]. each sddrd bits 24:31 controls the direction of the corresponding sgpiod pin [24:31]. table 6-26. data direction control sddr/gddr operation 0 sgpio configured as input 1 sgpio configured as output mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-1 chapter 7 reset this section describes the mpc561/mpc563 rese t sources, operation, control, and status. 7.1 reset operation the mpc561/mpc563 has several inputs to the reset logic which include the following: ? power-on reset ? external hard reset pin (hreset ) ? external soft reset pin (sreset ) ? loss of pll lock ? on-chip clock switch ? software watchdog reset ? checkstop reset ? debug port hard reset ? debug port soft reset ? jtag reset ? illegal bit change (ilbc) all of these reset sources are fed into the reset cont roller. the control logic de termines the cause of the reset, synchronizes it, and resets the appropriate logic modules, dependi ng on the source of the reset. the memory controller, system protection logic, interrupt controller, and parallel i/ o pins are initialized only on hard reset. external soft reset initializes inte rnal logic while maintain ing system configuration. the reset status register (rsr) reflects the most recent source to cause a reset. 7.1.1 power-on reset the power-on reset pin, poreset , is an active low input. in a syst em with power-down low-power mode, this pin should be activated only as a result of a voltage failure on the kapwr pin. after detecting the assertion of poreset , the mpc561/mpc563 enters the power-on reset state. during this state the modck[1:3] signals determine the oscillator frequency, pll multip lication factor, and the pitrtclk and tmbclk clock sources. in additi on, the mpc561/mpc563 asserts the sreset and hreset pins at the rising edge of poreset . the poreset pin should be asserted for a minimum time of 100,000 of clock oscilla tor cycles after a valid level has been reached on the kapwr suppl y. after detecting the assertion of poreset , the mpc561/mpc563 remains in the power-on reset state unt il the last of the following two events occurs: reset mpc561/mpc563 reference manual, rev. 1.2 7-2 freescale semiconductor ? the internal pll enters the lock state and the system clock is active. ? the poreset pin is negated. if limp mode is enabled, the internal pll is not required to be locked before the ch ip exits power-on reset. the internal modck[1:3] values are sa mpled at the rising edge of poreset . after exiting the power-on reset state, the mpc561/mpc563 continues to drive the hreset and sreset pins for 512 system clock cycles. when the timer expi res (after 512 cycles), the configurati on is sampled from data bus pins, if required (see section 7.5.1, ?hard reset configuration ?) and the mpc561/mpc 563 stops driving the hreset and sreset pins. the poreset pin has a glitch detector to ensure that lo w spikes of less than 20 ns are rejected. the internal poreset signal asserts only if the poreset pin asserts for more than 100 ns. 7.1.2 hard reset hreset (hard reset) is an ac tive low, bidirectional i/ o pin. the mpc561/mpc563 can detect an external assertion of hreset only if it occurs while the mpc 561/mpc563 is not asserting hreset . when the mpc561/mpc563 detects as sertion of the external hreset pin or a cause to assert the internal hreset line is detected, the chip starts to drive the hreset and sreset for 512 cycles. when the timer expires (after 512 cycles) the configurati on is sampled from data pins (refer to section 7.5.1, ?hard reset configuration ?) and the chip stops driving the hreset and sreset pins. an external pull-up resistor should drive the hreset and sreset pins high. after detect ing the negation of hreset or sreset , the mpc561/mpc563 waits 16 clock cycles before testing the presence of an external hard or soft reset. the hreset pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. the internal hreset will be asserted only if hreset is asserted for more than 100 ns. the hreset is an open collector type pin. 7.1.3 soft reset sreset (soft reset) is an active low, bidirectiona l i/o pin. the mpc561/mpc563 can only detect an external assertion of sreset if it occurs while the mpc 561/mpc563 is not asserting sreset . when the mpc561/mpc563 detects th e assertion of external sreset or a cause to assert the internal sreset line, the chip starts to drive the sreset for 512 cycles. when the timer expires (after 512 cycles) the debug port configuration is sampled from the ds di and dsck pins and the chip stops driving the sreset pin. an external pull-up resi stor should drive the sreset pin high. after the mpc561/mpc563 detects the negation of sreset , it waits 16 clock cycles before testing the presence of an external soft reset. the sreset is an open collector type pin. 7.1.4 loss of pll lock if the pll detects a loss of lock, erroneous exte rnal bus operation will occu r if synchronous external devices use the mpc561/mpc563 input clock. erroneous operation could also occur if devices with a pll reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-3 use the mpc561/mpc563 clkout signal. this source of reset can be opt ionally asserted if the lolre bit in the pll, low-power, and reset control register (plprcr) is set. the enabled pll loss of lock event generates an internal hard reset sequence. refer to chapter 8, ?clocks and power control ,? for more information on loss of pll lock. 7.1.5 on-chip clock switch if the system clock is switched to the backup clock or switched from b ackup clock to another clock source an internal hard reset sequence is generated. refer to chapter 8, ?clocks and power control .? 7.1.6 software watchdog reset when the mpc561/mpc563 software watchdog counts to zero, a software watchdog reset is asserted. the enabled software watchdog event generates an internal hard reset sequence. 7.1.7 checkstop reset when the rcpu enters a checkstop state, and the check stop reset is enabled (the csr bit in the plprcr is set), a checkstop reset is asserted. the enabled check stop event generates an inte rnal hard reset sequence. refer to the rcpu reference manual for more information. 7.1.8 debug port hard reset when the development port receives a hard reset request from the developm ent tool, an internal hard reset sequence is generated. in this ca se the development tool must r econfigure the debug port. refer to chapter 23, ?development support ,? for more information. 7.1.9 debug port soft reset when the development port receives a so ft reset request from the developm ent tool, an internal soft reset sequence is generated. in this ca se the development tool must r econfigure the debug port. refer to chapter 23, ?development support ,? for more information. 7.1.10 jtag reset when the jtag logic asserts the jtag soft reset signal, an internal soft reset sequence is generated. refer to chapter 25, ?ieee 1149.1-compliant interface (jtag) ,? for more information. 7.1.11 ilbc illegal bit change when locked bits in the plprcr regi ster are changed, an internal hard reset sequence is generated. refer to chapter 8, ?clocks and power control .? 7.2 reset actions summary table 7-1 summarizes the action taken for each reset. reset mpc561/mpc563 reference manual, rev. 1.2 7-4 freescale semiconductor 7.3 data coherency during reset the mpc561/mpc563 supports data cohe rency and avoids data corrupti on during reset. if a cycle is executing when any sreset or hreset source is detected, then the cycl e will either complete or will not start before generating the co rresponding reset control signal. ther e are reset sources, however, when the mpc561/mpc563 generates an internal reset due to sp ecial internal situations where this protection is not supported. see section 7.4, ?reset status register (rsr) .? in the case of large operand size (32 or 16 bits) trans actions to a smaller port size, the cycle is split into two 16-bit or four 8-bit cycles. in this case, data coherency is assured and da ta will not be corrupted. in the case where the core executes an unaligned lo ad/store cycle which is broken down into multiple cycles, data coherency is not assured between these cycles (i .e., data could be corrupted). contention may occur if a write access is in progress to external memory and sreset /hreset is asserted and the external reset configuration word (rcw ) is used. in this case, the external rcw drivers, usually activated by hreset /sreset lines, will drive the data bus together with the mpc561/mpc563. thus the data in the ram may be corrupted rega rdless of the data coherency mechanism in the mpc561/mpc563. table 7-1. reset action taken for each reset cause reset source reset logic and pll states reset system configuratio n reset clock module reset hreset pin driven debug port configuratio n other internal logic reset sreset pin driven power-on reset (poreset ) ye s ye s ye s ye s ye s ye s ye s hard reset (hreset ) sources: external hard reset loss of lock on-chip clock switch illegal low-power mode software watchdog checkstop debug port hard reset n o ye s ye s ye s ye s ye s ye s soft reset (sreset ) sources: external soft reset debug port soft reset jtag reset no no no no yes yes yes table 7-2. reset configuration word and data corruption/coherency reset driven reset to use for data coherency (ext_reset ) comments hreset sreset reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-5 7.4 reset status register (rsr) all of the reset sources are fed into the reset controller . the 16-bit reset status register (rsr) reflects the most recent source, or sour ces, of reset. (simultaneous reset requests can cause more than one bit to be set at the same time.) this register c ontains one bit for each reset source. a bit set to logic one indicates the type of reset that occurred. once set, individual bits in the rsr remain set until software clears them . bits in the rsr can be cleared by writing a one to the bit. a write of zero has no effect on the bit. the re gister can be read at all times. the reset status register receives its default reset values during power-on reset. the rsr is powered by the kapwr pin. sreset hreset hreset & sreset hreset || sreset provided only one of them is driven into the mpc561/mpc563 at a time msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ehrs esrs llrs swrs csrs dbhrs dbsrs jtrs occs ilbc gpor ghrst gsrst ? poreset 0000_0000 0 1 0 1 1 1 000 hreset 0000_0000_000 1 1 000 sreset 0000_0000_0000 1 000 addr 0x2f c288 1 occs will be set (1) if limp mode is enabled (sccr[lme]=1). figure 7-1. reset status register (rsr) table 7-3. reset status register bit descriptions bits name description 0 ehrs 1 external hard reset status 0 no external hard reset has occurred 1 an external hard reset has occurred 1 esrs 1 external soft reset status 0 no external soft reset has occurred 1 an external soft reset has occurred 2 llrs loss of lock reset status 0 no enabled loss-of-lock reset has occurred 1 an enabled loss-of-lock reset has occurred table 7-2. reset configuration word and data corruption/coherency (continued) reset driven reset to use for data coherency (ext_reset ) comments reset mpc561/mpc563 reference manual, rev. 1.2 7-6 freescale semiconductor 3 swrs software watchdog reset status 0 no software watchdog reset has occurred 1 a software watchdog reset has occurred 4 csrs checkstop reset status 0 no enabled checkstop reset has occurred 1 an enabled checkstop reset has occurred 5 dbhrs debug port hard reset status 0 no debug port hard reset request has occurred 1 a debug port hard reset request has occurred 6 dbsrs debug port soft reset status 0 no debug port soft reset request has occurred 1 a debug port soft reset request has occurred 7 jtrs jtag reset status 0 no jtag reset has occurred 1 a jtag reset has occurred 8 occs on-chip clock switch 0 no on-chip clock switch reset has occurred 1 an on-chip clock switch reset has occurred 9 ilbc illegal bit change. this bit is set when the mpc561/mpc563 changes any of the following bits when they are locked: lpm[0:1], locked by the lpml bit mf[0:11], locked by the mfpdl bit divf[0:4], locked by the mfpdl bit 10 gpor glitch detected on poreset pin. this bit is set when the poreset pin is asserted for more than 20ns 0 no glitch was detected on the poreset pin 1 a glitch was detected on the poreset pin 11 ghrst glitch detected on hreset pin. this bit is set when the hreset pin is asserted for more than 20ns 0 no glitch was detected on the hreset pin 1 a glitch was detected on the hreset pin 12 gsrst glitch detected on sreset pin. if the sreset pin is asserted for more than 20ns the ghrst bit will be set. if an internal or external sreset is generated the sreset pin is asserted and the gsrst bit will be set. 0 no glitch was detected on sreset pin 1 a glitch was detected on sreset pin . 13:15 ? reserved 1 in the usiu rsr, if both ehrs and esrs are set, the re set source is internal. the ehrs and esrs bits in rsr register are set for any internal reset source in addition to external hreset and external sreset events. if both internal and external indicator bits are set, then the reset source is internal. table 7-3. reset status register bit descriptions (continued) bits name description reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-7 7.5 reset configuration 7.5.1 hard reset configuration when a hard reset event occurs, the mpc561/mpc563 r econfigures its hardware system as well as the development port configurati on. the logical value of the bits that determ ine its initial mode of operation, are sampled from the following: ? the external data bus pins data[0:31] ? an internal default constant (0x0000 0000) ? an internal nvm register value (uc3fcfi g). available on the mpc563/mpc564 only. if at the sampling time rstconf is asserted, then the configuration is sampled from the external data bus. if rstconf is negated and a valid nvm value exists (uc3fcfig[hc]=0), then the configuration is sampled from the nvm register in the uc3f module. if rstconf is negated and no valid nvm value exists (uc3fcfig[hc]=1), then the c onfiguration word is sampled from the internal default (all zeros). hc will be ?1? if the internal flash is erased. table 7-4 summarizes the reset configuration options. if the prds control bit in the pd mcr register is cleared and hreset and rstconf are asserted, the mpc561/mpc563 pulls the data bus low with a weak resistor. the user can ove rwrite this default by driving the appropriate bit high. see figure 7-2 for the basic reset configuration scheme. table 7-4. reset configuration options rstconf has configuration (hc) internal configuration word 0 x data[0:31] pins 1 0 nvm flash eeprom register (uc3fcfig) 1 1 internal data word default (0x0000 0000) reset mpc561/mpc563 reference manual, rev. 1.2 7-8 freescale semiconductor figure 7-2. reset configuration basic scheme during the assertion of the poreset input signal, the chip assumes th e default reset configuration. this assumed configuration changes if the input signal rstconf is asserted when the poreset is negated or the clkout starts to oscillate. to ensure that stable data is sampled, the hardware configuration is sampled every eight clock cycles on the rising edge of clkout with a double buffer. the setup time required for the data bus is approximately 15 cycles (defined as tsup in the following figures) and the maximum rise time of hreset should be less than six clock cycles. in systems where an external reset configuration word and the texp out put function are both required, rstconf should be asserted until sreset is negated. figure 7-3 to figure 7-6 provide sample reset configuration timings. note timing diagrams in the follow ing figures are not to scale. int_reset mux flash 32 32 32 has configuration (hc ) oe ext_reset (see ta b l e 7 - 2 ) hreset /sreset rstconf reset config. word dx (data line) data coherency reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-9 figure 7-3. reset configuration sa mpling scheme for ?short? poreset assertion, limp mode disabled figure 7-4. reset configuration timing for ?short? poreset assertion, limp mode enabled clkout poreset hreset rstconf internal poreset default rstconf controlled ts u p internal data[0:31] clkout poreset hreset rstconf internal default rstconf controlled ts u p internal data(0:31) (backup clock) poreset 512 clocks reset mpc561/mpc563 reference manual, rev. 1.2 7-10 freescale semiconductor figure 7-5. reset conf iguration timing for ?long? poreset assertion, limp mode disabled figure 7-6. reset configuratio n sampling timing requirements clkout poreset hreset rstconf internal default rstconf controlled ts u p internal data[0:31] pll lock poreset clkout hreset rstconf data 1 2 3 8 9 10111213141516 maximum time of reset recognition reset configuration word tsup = minimum setup time of reset recognition = 15 clocks sample data configuration sample data configuration (maximum rise time - up to 6 clocks) internal reset 8 910 8 reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-11 7.5.2 hard reset configuration word (rcw) following is the hard reset configuration word that is sampled from the internal data bus, data_sgpiod(0:31) on th e negation of hreset . if the external reset config word is selected (rstconf = 0), the internal data bus will reflect the state of external data bus. if the internal reset config word is selected and neither of the flash reset config words are enab led (uc3fcfig[hc] = 1), the internal data bus is internally driven with all zeros. th e reset configuration word is not a re gister in the memory map. most of the bits in the configuration are locate d in registers in the siu. refer to table 7-5 for a detailed description of each control bit. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field earb ip bdrv bdis bps[0:1] ? dbgc[0:1] ? atwc ebdf[0:1] ? hreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field prpm sc etre flen en_ comp 1 1 available only on the mpc562/mpc564, software s hould write "0" to this bit for mpc561/mpc563. exc_ comp 1 ? oerc ? isb dme hreset 0000_0000_0000_0000 figure 7-7. reset configuration word (rcw) table 7-5. rcw bit descriptions bits name description 0 earb external arbitration ? refer to section 9.5.7, ?arbitration phase ,? for a detailed description of bus arbitration. the default value is th at internal arbitration hardware is used. 0 internal arbitration is performed 1 external arbitration is assumed 1 ip initial interrupt prefix ? this bit defines the initial value of msr[ip] immediately after reset. msr[ip] defines the interrupt table location. if ip is zero then the initial value of msr[ip] is zero, if the ip is one, then the initial value of msr[ip] is one. default value is zero. see ta bl e 3 - 1 1 for more information. 0 msr[ip] = 0 after reset 1 msr[ip] = 1 after reset 2 bdrv bus pins drive strength ? this bit determines the bus pins (address, data and control) driving capability to be either full or reduced drive. the bus default drive strength is full; upon default, it also effects the clkout driv e strength to be full. see ta b l e 6 - 7 for more information. bdrv controls the default state of com1 in the siumcr. 0 full drive 1 reduced drive 3 bdis boot disable ? if the bdis bit is set, then memory controller is not activated after reset. if it is cleared then the memory controller bank 0 is active immediately after reset such that it matches any addresses. if a write to the or0 register occurs after reset this bit definition is ignored. the default value is that the memory controller is enabled to control the boot with the cs0 pin. see section 10.7, ?global (boot) chip-select operation ,? for more information. 0 memory controller bank 0 is active and ma tches all addresses immediately after reset 1 memory controller is not activated after reset. reset mpc561/mpc563 reference manual, rev. 1.2 7-12 freescale semiconductor 4:5 bps boot port size ? this field defines the port size of the boot device on reset (br0[ps]). if a write to the or0 register occurs after reset this field definition is ignored. see ta b l e 1 0 - 5 and ta b l e 1 0 - 8 for more information. 00 32-bit port (default) 01 8-bit port 10 16-bit port 11 reserved 6:8 ? reserved. these bits must not be high in the reset configuration word. 9:10 dbgc[0:1] debug pins configuration ? see section 6.2.2.1.1, ?siu module configuration register (siumcr) ,? for this field definition. the default value is that these pins function as: vfls[0:1], bi , br , bg and bb . see ta bl e 6 - 8 . 11 ? reserved. 12 atwc address type write enable configuration ? the default value is that these pins function as we pins. see ta b l e 6 - 7 . 0we [0:3]/be [0:3]/at[0:3] functions as we [0:3]/be [0:3] 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] 13:14 ebdf external bus division factor ? this field defi nes the initial value of the external bus frequency. the default value is that clkout frequency is equa l to that of the internal clock (no division). see ta bl e 8 - 9 . 15 1 ? reserved. this bit must be 0 in the reset configuration word. 16 prpm peripheral mode enable ? this bit determines if the chip is in peripheral mode. a detailed description is in ta bl e 6 - 1 3 the default value is no peripheral mode enabled. 17:18 sc single chip select ? this field def ines the mode of thempc562/mpc564. see ta b l e 6 - 1 0 . 00 extended chip, 32 bits data 01 extended chip, 16 bits data 10 single chip and show cycles (address) 11 single chip 19 etre exception table relocation enable ? this fi eld defines whether the e xception table relocation feature in the bbc is enabled or disabled; the default state for this field is disabled. for more details, see ta b l e 4 - 4 . 20 2 , 3 flen flash enable ? this field determines whether th e on-chip flash memory is enabled or disabled out of reset. the default state is disabled, which means that by default, the boot is from external memory. refer to ta b l e 6 - 1 2 for more details. 0 flash disabled ? boot is from external memory 1 flash enabled 21 en_ comp 4 enable compression ? this bit enables the operation of the mpc562/mpc564 with compressed code. the default state is disabled. see ta b l e 4 - 4 and reset mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 7-13 7.5.3 soft reset configuration when a soft reset event occurs, the mpc561/mpc 563 reconfigures the development port. refer to chapter 23, ?development support ,? for details. 24:25 oerc other exceptions reloca tion control ? these bits effect only if etre was enabled. see ta b l e 4 - 2 . relocation offset: 00 offset 0 01 offset 64 kbytes 10 offset 512 kbytes 11 offset to 0x003f e000 26:27 ? reserved 28:30 isb internal space base select ? this field defin es the initial value of the isb field in the immr register. a detailed description is in ta bl e 6 - 1 2 . the default state is that the internal memory map is mapped to start at address 0x0000_0000. this bit must not be high in the reset configuration word. 31 dme dual mapping enable ? this bit determines whether dual mapping of the internal flash is enabled. for a detailed description refer to table 10-11 . the default state is that dual mapping is disabled. 0 dual mapping disabled 1 dual mapping enabled 1 bit 15 always comes from the internal flash reset configuration word (mpc563 only). 2 this bit should not be set on the mpc561/mpc562. 3 this bit is hc if read from the internal flash reset configuration word. see section 21.2.3.1, ?reset configuration word (uc3fcfig) ." 4 available only on the mpc562/mpc564, software s hould write "0" to this bit for mpc561/mpc563. table 7-5. rcw bit descriptions (continued) bits name description reset mpc561/mpc563 reference manual, rev. 1.2 7-14 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-1 chapter 8 clocks and power control the main timing reference for the mpc561/mp c563 can monitor any of the following: ? an external crystal with a frequency of 4 or 20 mhz ? an external frequency source with a frequency of 4 mhz ? an external frequency source at the system frequency the system operating frequency is generated through a programmable ph ase-locked loop, the system pll (spll). the spll runs at twice the system speed. th e spll is programmable in integer multiples of the input frequency to generate the internal (vco/2) operating frequency. a pre- divider before the spll enables the division of the high frequency crystal os cillator. the internal operating spll frequency should be at least 30 mhz. it can be divided by a power -of-two divider to generate the system operating frequencies. in addition to the system clock, the cl ocks submodule provides the following: ? tmbclk to the time base (tb) and decrementer (dec) ? pitrtclk to the periodic interrupt ti mer (pit) and real-time clock (rtc) the oscillator, tb, dec, rtc, a nd the pit are powered from the keep alive pow er supply (kapwr) pin. this allows the counters to continue to increment/decrement at the os cillator frequency even when the main power to the mcu is off. while the power is of f, the pit may be used to signal the power supply ic to enable power to the system at specific intervals. this is the power-down wake-up feature. when the chip is not in power-down low-power mode , the kapwr is powered to the sa me voltage value as the voltage of the i/o buffers and logic. the mpc561/mpc563 clock module consists of the ma in crystal oscillator, the spll, the low-power divider, the clock generator, the system low-power control block, and the limp mode control block. the clock module receives control bits from the system clock control register (sccr), change of lock interrupt register (colir), the pll lo w-power and reset-control regi ster (plprcr), and the pll. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-2 freescale semiconductor figure 8-1 is a functional block di agram of the clock unit. figure 8-1. clock unit block diagram 2:1 spll clock gclk1 / gclk2 gclk1c / gclk2c vcoout clkout 3:1 mux xfc tmbclk tmbclk lock vddsyn drivers driver main clock xtal extal 3:1 mux rtc / pit clock and driver oscillator mux tbclk (/4 or /16) modck[1:3] pitrtclk extclk 2:1 mux low power dividers (1/2n) /4 or gclk2 backup clock detector oscillator loss engclk vsssyn drivers system clock system clock to rcpu and bbc system low power control /256 clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-3 8.1 system clock sources the system clock can be provided by the main system oscillator, an external clock input, or the backup clock (buclk) on-chip ring oscillator, see figure 8-1 . the main system oscillator uses either a 4-mhz or 20-mhz crystal to generate the pll reference clock. when the main system oscillator output is the timi ng reference to the system pll, skew elimination between the xtal/extal pins and clkout is not guaranteed. there is also an on-chip crystal feedback resistor on the mpc561/mpc5 63; however, space should be reserv ed for an off-chip resistor to allow for future configurations. figure 8-2 illustrates the main system os cillator crysta l configuration. the external clock input (extclk pin) can receive a clock signal from an external source. the clock frequency must be in the range of 3-5 mhz or, for 1:1 mode, at the syst em frequency of at least 15 mhz. when the external clock input is the timing referen ce to the system pll, the skew between the extclk pin and the clkout is less than 1 ns. the backup clock on-chip ring oscillator allows the mpc561/mpc563 to function with a less precise clock. when operating from the backup clock, the mp c561/mpc563 is in limp mode. this enables the system to continue minimum func tionality until the system is fixed. the buclk frequency is approximately 11 mhz for the mpc561/mpc563 (see appendix f, ?electrical characteristics ? for the complete frequency range). for normal operation, at least one clock source (extclk or main system oscillat or) must be active. a configuration with both cloc k sources active is possible as well. at this configurati on extclk provides the system clock and main system oscillator pr ovides the pitrtclk. the i nput of an unused timing reference (extclk or extal) must be grounded. figure 8-2. main system oscillator crystal configuration 8.2 system pll the pll allows the processor to operate at a high in ternal clock frequency using a low frequency clock input, a feature which offers two be nefits: reduces the overall electr omagnetic interfer ence generated by the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add an additional oscillator to a system. the pll can perform the following functions: ? frequency multiplication ? skew elimination ? frequency division extal xtal cl cl 1 m ? 1 1. resistor is not currently requir ed on the board but space should be av ailable for its addition in the future. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-4 freescale semiconductor 8.2.1 frequency multiplication the pll can multiply the input fr equency by any integer between one and 4096. the multiplication factor depends on the value of the mf[0:11] bits in the pl prcr register. while any integer value from one to 4096 can be programmed, the resulting vco output frequency must be at least 15 mhz. the multiplication factor is set to a predetermined valu e during power-on reset as defined in table 8-1 . 8.2.2 skew elimination the pll is capable of eliminating the skew between the external clock entering the chip (extclk) and both the internal clock pha ses and the clkout pin, ma king it useful for tight synchronous timings. skew elimination is active only when the pll is enabled and progr ammed with a multiplicat ion factor of one or two (mf = 0 or 1). the timing reference to the syst em pll is the external clock input (extclk pin). 8.2.3 pre-divider a pre-divider before the phase comp arator enables additional system clock resolution when the crystal oscillator frequency is 20 mhz. th e division factor is determined by the divf[0:4] bits in the plprcr. 8.2.4 pll block diagram as shown in figure 8-3 , the reference signal, oscclk, goes to the phase comparator. the phase comparator controls the direction ( up or down) that the charge pump dr ives the voltage across the external filter capacitor (xfc). the direct ion depends on whether the feedback signal phase lags or leads the reference signal. the output of the charge pump dr ives the vco. the output frequency of the vco is divided down and fed back to the phase comparator for comparison wi th the reference signal, oscclk. the mf values, zero to 4095, are mapped to multiplicat ion factors of one to 4096. note that when the pll is operating in 1:1 mode (refer to table 8-1 ), the multiplication factor is one (mf = 0). the pll output frequency is twice the maximum sy stem frequency. this double frequency is needed to generate gclk1 and gclk2 clocks. on power-up, wi th a 4-mhz or 20-mhz crystal and the default mf settings, vcoout will be 40 mhz and the sy stem clock will be 20 mhz. the equation for vcoout is: note when operating with the backup clock, the system clock (and clkout) is one-half of the ring oscillator freq uency, (i.e., the system clock is approximately 11 mhz). the time base and pit clocks will be twice the system clock frequency. in the case of initial system power up, or if kapwr is lost, an external circuit must asse rt power on reset (poreset ). once kapwr is valid, poreset must be asserted long e nough to allow the external oscillator to start up and stabiliz e for the device to come out of reset in normal (non limp) mode. vcoout = oscclk divf + 1 x (mf + 1) x 2 clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-5 if limp mode is enabled (by th e modck[1:3] pins), and poreset is negated before the external oscillator has started up, the backup cl ock, buclk, will be used to cloc k the device. the device will start to run in limp mode. software can then switch th e clock mode from buclk to pll. if an application requires that the device always comes out of reset in normal mode, poreset should be asserted long enough for the external oscillator to start up. the maximu m start-up time of an extern al oscillator is given in appendix f, ?electrical characteristics ? and poreset should be asserted for th is time and at least an additional 100, 000 input clock cycles. if limp mode is disabled at reset, a short reset of at least 3 s is enough to obtain normal chip operation, because the buclk will not start. the system will wait for the exte rnal oscillator to start-up and stabilize. the pll will begin to lock once poreset has been negated, assuming stable kapwr and vddsyn power supplies and internal oscillat or (or external clock). the pll ma ximum lock time is determined by the input clock to the phase compar ator. the pll locks within 500 input clock cycles if the plprcr[mf] <= 4. the pll locks within 1000 input cl ock cycles if plprcr[mf] >4. hreset will be released 512 system clock cycles after the pll locks. whenever poreset is asserted, the mf bi ts are set according to table 8-1 , and the division factor high frequency (dfnh) and division factor low frequency (dfnl) bits in s ccr are set to the value of 0 ( 1 for dfnh and 2 for dfnl). figure 8-3. system pll block diagram 8.2.5 pll pins the following pins are dedicated to the pll operation: ? vddsyn ? drain voltage. this is the v dd dedicated to the analog pll circuits. the voltage should be well-regulated and the pin should be provided with an extremely low impedance path to the v dd power rail. vddsyn should be bypassed to vsssyn by a 0.1 f capacitor located as close as possible to the chip package. ? vsssyn ? source voltage. this is the v ss dedicated to the analog p ll circuits. the pin should be provided with an extremely low impedanc e path to ground. vsssy n should be bypassed to vddsyn by a 0.1 f capacitor located as close as possible to the chip package. phase comparator multiplication factor mf[0:11] xfc oscclk up down vcoout feedback clock delay charge pump vco division factor divf[0:4] vsssyn vddsyn clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-6 freescale semiconductor ? xfc ? external filter capacitor. xfc connects to the off-chip capacitor for the pll filter. one terminal of the capacitor is connected to xfc, and the other terminal is connected to vddsyn. ? the off-chip capacitor must have the following values: ? 0 < mf + 1 < 4 (1130 x (mf + 1) ? 80) pf ?mf + 1 42100 x (mf + 1) pf where mf = the value stored on mf[0:11] . this is one less than the desired frequency multiplication. 8.3 system clock during pll loss of lock at reset, until the spll is locked, the spll output clock is disabled. during normal operation (once the pll has locked), either the oscillator or an external clock source is generating the system clock. in this case, if loss of lock is dete cted and the lolre (loss of lock reset enable) bit in the plprcr is cleared, the system cl ock source continues to f unction as the pll?s output clock. the usiu timers can operate wi th the input clock to the pll, so that these timers are not affected by the pll loss of lock. software can use these time rs to measure the loss-of -lock period. if the timer reaches the user-preset software criterion, the mpc 561/mpc563 can switch to the backup clock by setting the switch to backup clock (stbuc) bit in the sccr , provided the limp mode enable (lme) bit in the sccr is set. if loss of lock is detected duri ng normal operation, assertion of hreset (for example, if lolre is set) disables the pll output clock until th e lock condition is met. during hard reset, the stbuc bit is set as long as the pll lock condi tion is not met and clears when the pll is locked. if stbuc and lme are both set, the system clock switches to the backup clock (buclk), and the ch ip operates in limp mode until stbuc is cleared. every change in the lock status of th e pll can generate a maskable interrupt. note when the vco is the syst em clock source, chip operation is unpredictable while the pll is unlocked. no te further that a switch to the backup clock is possible only if the lme bit in the sccr is set. 8.4 low-power divider the output of the pll is sent to a low-power divi der block. (in limp mode the buclk is sent to a low-power divider block.) th is block generates all other clocks in normal operation, but has the ability to divide the output frequency of the vc o before it generates the general syst em clocks sent to the rest of the mpc561/mpc563. the pll vcoout is always divided by at least two. the purpose of the low-power divider block is to allow reduction and rest oration of the operating frequencies of different sections of the mpc 561/mpc563 without losing the pll lock. using the low-power divider block, full chip ope ration can still be obtain ed, but at a lower frequency. this is called gear mode. the selection and speed of gear mode ca n be changed at any time, with changes occurring immediately. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-7 the low-power divider block is contro lled in the system clock control register (sccr). the default state of the low-power divider is to divide all clocks by one. thus, for a 40-mhz sy stem, the general system clocks are each 40 mhz. whenever power-on reset is asserted, the mf bits are set according to table 8-1 , and the division factor hi gh frequency (dfnh) and division factor low frequency (dfnl) bits in sccr are set to the value of 0 ( 1 for dfnh and 2 for dfnl). 8.5 internal clock signals the internal clocks generated by the clocks module are shown in figure 8-4 . the clocks module also generates the clkout and engclk external clock signals. the pll synchronizes these signals to each other. the pitrtclk frequency and source are spec ified by the rtdiv and rtsel bits in the sccr. when the backup clock is functioning as the system cl ock, the backup clock is au tomatically selected as the time base clock source and is twice the mpc561/m pc563 system clock. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-8 freescale semiconductor figure 8-4. mpc561/mpc563 clocks note that gclk1_50, gclk2_50, and clkout can have a lower fre quency than gclk1 and gclk2. this is to enable the external bus operation at lower fr equencies (controlled by ebdf in the sccr). gclk2_50 always rises simultaneously with gclk2. when dfnh = 0, gclk2_50 has a 50% duty cycle. with other values of dfnh or dfnl, the duty cycle is less than 50%. refer to figure 8-7 . gclk1_50 rises simultaneously with gclk1. when the mpc561/mpc563 is not in gear mode, the falling edge of gclk1_50 occurs in the middle of the high phase of gclk2_50. ebdf determines the division factor between gclk 1/gclk2 and gclk1_50/gclk2_50. during power-on reset, the modck 1, modck2, and modck3 pins dete rmine the clock source for the pll and the clock drivers. these pins ar e latched on the positive edge of poreset . their values must be stable as long as this line is assert ed. the configuration modes are shown in table 8-1 . modck1 specifies gclk1 gclk2 gclk1_50 gclk2_50 clkout t1 t2 t3 t4 gclk1_50 gclk2_50 (ebdf = 00) (ebdf = 00) (ebdf = 01) (ebdf = 01) clkout (ebdf = 00) (ebdf = 01) clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-9 the input source to the spll (main system oscilla tor or extclk). modck1, modck2, and modck3 together determine the multiplication factor at reset and the functionality of limp mode. if the configuration of pitrtclk and tmbclk and the spll multiplication factor is to remain unchanged in power-down low-power mode, the modck signals should not be sampled at wake-up from this mode. in this case the poreset pin should remain negated and hreset should be asserted during the power supply wake-up stage. when modck1 is cleared, the output of the main osci llator is selected as the input to the spll. when modck1 is asserted, the ex ternal clock input (extclk pin) is sel ected as the input to the spll. in all cases, the system cl ock frequency (freq gclk2 ) can be reduced by the dfnh[0:2] bits in the sccr. note that freq gclk2(max) occurs when the dfnh bits are cleared. the tbs bit in the sccr selects the time base clock to be either th e spll input clock or gclk2. when the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. the pitrtclk frequency and source are specified by the rtdiv and rtsel bits in the sccr. when the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. when the poreset pin is negated (driven to a high va lue), the modck1, modck2, and modck3 values are not affected. they remain the same as th ey were defined during the most recent power-on reset. table 8-1 shows the clock configuration m odes during power-on reset (poreset asserted). note the modck[1:3] are shared f unctions with irq[5:7]. if irq [5:7] are used as interrupts, the interrupt source should be removed during poreset to insure the modck pins are in the correct state on the rising edge of poreset . table 8-1. reset clocks source configuration modck[1:3] 1 default values after poreset spll options lme rtsel rtdiv mf + 1 pitclk division tmbclk division 000 0 0 0 1 4 4 used for testing purposes. 001 0 0 1 1 256 16 normal operation, pll enabled. main timing reference is crystal osc (20 mhz). limp mode disabled. 010 1 0 1 5 256 4 normal operation, pll enabled. main timing reference is crystal osc (4 mhz). limp mode enabled. 011 1 0 1 1 256 16 normal operation, pll enabled. main timing reference is crystal osc (20 mhz). limp mode enabled. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-10 freescale semiconductor note the reset value of the pll pre-divider is one. the values of the pitrtclk clock division and tmbclk clock division can be changed by software. the rtdiv bit value in the sccr re gister defines the division of pi trtclk. all possible combinations of the tmbclk divisi ons are listed in table 8-2 . 8.5.1 general system clocks the general system clocks (gclk1c, gclk 2c, gclk1, gclk2, gclk1_50, and gclk2_50) are the basic clock supplied to all m odules and sub-modules on the mp c561/mpc563. gclk1c and gclk2c are supplied to the rcpu and to the bbc. gclk1c and gclk2c are stopped when the chip enters the doze-low power mode. gclk1 and gc lk2 are supplied to the siu and the clock module. the external bus clock gclk2_50 is the same as clkout. the ge neral system clock defaults to vco/2 = 20 mhz (assuming a 20-mhz system fr equency) with default power-on reset mf values. 100 101 011 1 256 16 normal operation, pll enabled. 1:1 mode main timing reference is ext- clk pin (>15mhz) limp mode disabled. 110 0 1 1 5 256 4 normal operation, pll enabled. main timing reference is ext- clk (3-5 mhz). limp mode disabled. 111 1 1 1 1 256 16 normal operation, pll enabled. 1:1 mode main timing reference is ext- clk pin (>15mhz) limp mode enabled. 1 indicates modck pins value during power-on reset table 8-2. tmbclk divisions 1 1 to ensure correct operatio n of the time base, keep the system clock to time base clock ratio above 4 and always set sccr[tbs] = 1 when running on the backup clock (limp mode). sccr[tbs] mf + 1 tmbclk division 1?16 01, 216 0> 24 table 8-1. reset clocks source configuration (continued) modck[1:3] 1 default values after poreset spll options lme rtsel rtdiv mf + 1 pitclk division tmbclk division clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-11 the general system clock frequenc y can be switched between differen t values. the hi ghest operational frequency can be achieved when the system clock fr equency is determined by dfnh (csrc bit in the plprcr is cleared) and dfnh = 0 (d ivision by one). the general system clock can be ope rated at a low frequency (gear mode) or a high freq uency. the dfnl bits in sccr defi ne the low frequency. the dfnh bits in sccr define the high frequency. the frequency of the general syst em clock can be changed dynamically with the system clock control register (sccr), as shown in figure 8-5 . figure 8-5. general system clocks select the frequency of the general system clock can be changed ?on the fly? by software. the user may simply cause the general system clock to switch to its low fr equency. however, in some applications, there is a need for a high frequency during certain periods. in terrupt routines, for example, may require more performance than the low frequency operation provides, but must consume less power than in maximum frequency operation. the mpc561/mpc 563 provides a method to automati cally switch between low and high frequency operation whenever one of the following conditions exists: ? there is a pending interrupt from the interrupt controller. this opt ion is maskable by the prqen bit in the sccr. ?the (pow) bit in the msr is clear in normal ope ration. this option is maskable by the prqen bit in the sccr. when neither of these conditions exists and the csrc bit in plprcr is set, the general system clock switches automatically back to the low frequency. abrupt changes in the divide ratio can cause li near changes in the operating currents of the mpc561/mpc563. when the multiplication factor (plp rcr[mf]) for the pll is changed, th e pll stops all internal clocks until the pll adjusts to the new frequency. this includes stopping the clock to the watchdog timer, therefore swt cannot reset the system during this period. when the clock stops, the current consumed by the devi ce from vdd will fall; it will then rise sharply when the pll turns on the pll output clocks at the ne w frequency. these abrupt changes in the divide ratio can cause linear changes in th e operating currents of the device. insure that the proper power supply filtering is available to handle ch anges instantaneously. the gear m odes (dfnh and dfnl) can be used to temporarily decrease the system frequency to minimize the demand on the pow er supply when the mf or divf multiply/divide ratio is changed. when the general system clock is divided, its duty cycle is changed. one phase remains the same (for example, 12.5 ns at 40 mhz) while the other becomes longer. dfnh divider dfnl divider vco/2 (e.g., 40 mhz) dfnh normal low power general system clock dfnl o o o o clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-12 freescale semiconductor note clkout does not have a 50% duty cycl e when the general system clock is divided. the clkout wave form is the same as that of gclk2_50. figure 8-6. divided system clocks timing diagram the system clocks gclk1 and gclk2 frequency is: therefore, the complete equation for dete rmining the system clock frequency is: gclk1 divide by 1 gclk2 divide by 1 gclk1 divide by 2 gclk2 divide by 2 gclk1 divide by 4 gclk2 divide by 4 freq sys freqsysmax 2 dfnh () or 2 dfnl 1 + () ------------------------------------------------------------------- = where freqsysmax = vcoout/2 system frequency= oscclk divf + 1 x (mf + 1) (2 dnfh ) or (2 dfnl + 1) 2 2 x clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-13 the clocks gclk1_50 and gclk2_50 frequency is: figure 8-7 shows the timing of usiu clocks when dfnh = 1 or dfnl = 0. figure 8-7. clocks timing for dfnh = 1 (or dfnl = 0) 8.5.2 clock out (clkout) clkout has the same frequency as the general system clock (gclk2_50) . unlike the main system clock gclk1/gclk2 however, clkout (and gc lk2_50) represents the external bus clock, and thus will be one-half of the main system clock if the extern al bus is running at half speed (ebdf = 0b01). the clkout frequency (system frequency) defaults to vco/2. clkout can drive full, half, or quarter strength; it can also be disabled. th e drive strength is controlled in the system clock and reset-control register (sccr) by the com[ 0:1] and cqds bits. (see section 8.11.1, ?system clock control register (sccr)? ). disabling or decreasing th e strength of clkout can reduc e power consumption, noise, and electromagnetic interference on the printed circuit board. when the pll is acquiring lock, the clkout signal is disabled and remains in the low state (provided that bucs = 0). freq 50 freqsysmax 2 dfnh () or 2 dfnl 1 + () ------------------------------------------------------------------- x 1 ebdf 1 + -------------------------- = gclk1 gclk2 gclk1_50 gclk2_50 clkout gclk1_50 gclk2_50 (ebdf = 00) (ebdf = 00) (ebdf = 01) (ebdf = 01) clkout (ebdf = 00) (ebdf = 01) clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-14 freescale semiconductor 8.5.3 engineering clock (engclk) engclk is an output clock with a 50% duty cycle. its frequency defa ults to vco/128, which is 1/64 of the main system frequency. engc lk frequency can be programmed to the main system frequency divided by a factor from one to 64, as controlled by the engdiv[0:5 ] bits in the sccr. engclk can drive full- or half-strength, or it can also be disabled (remaining in the high state). the drive strength is controlled by the eeclk[0:1] bits in the sccr . disabling engclk can reduce power consumption, noise, and electromagnetic interfer ence on the printed circuit board. note the full strength engclk setting (sccr[eeclk]=0b01) selects a 5-v driver while the half-strength se lection (sccr[eeclk]=0b00) is a 2.6-v driver. when the pll is acquiring lock, the engclk signal is disabled and remains in the low state (provided that bucs = 0). note skew elimination between clkout and engclk is not guaranteed. 8.6 clock source switching for limp mode support, clock source sw itching is supported. if for any reason the cloc k source for the chip is not functioning, the option is to switch the syst em clock to the backup cl ock ring oscillator, buclk. this circuit consists of a loss-of-clock detector, wh ich sets the locs status bit and locss sticky bit in the plprcr. if the lme bit in the sc cr is set, whenever locs is a sserted, the clock logic switches the system clock automatically to bucl k and asserts hard reset to the ch ip. switching the system clock to buclk is also possible by software setting the stbuc bit in sccr. switching from limp mode to normal system operation is accomplished by clearing stbuc and locss bits. th is operation also asserts hard reset to the chip. at hreset assertion, if the pll output clock is not vali d, the buclk will be se lected until software clears locss bit in sccr. at hreset assertion, if the pll output clock is valid, th e system will switch to oscillator/external clock. if during hreset the pll loses lock or the cl ock frequency becomes slower than the required value, the system wi ll switch to the buclk. after hreset negation the pll lock condition does not effect the sy stem clock source selection. if the lme bit is clear, the switch to the backup clock is disabled and assertion of stbu c bit is ignored. if the chip is in limp mode, clea ring the lme bit switches the system to normal operation and asserts hard reset to the chip. figure 8-8 describes the clock sw itching control logic. table 8-3 summarizes the status and control for each state. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-15 figure 8-8. clock source switching flow chart note buclk_enable = (stbuc | lo c) and lme lock indicates loss of lock status bit (locs) for all cases and loss of clock sticky bit (locss) when state 3 is active. when buclk_enable is changed, the chip asserts hreset to switch the system clock to buclk or pll. at poreset negation, if the pll is not lock ed, the loss-of-clock sticky bit (locss) is asserted, and the ch ip should operate with buclk. hreset_b = 1 buclk_enable = 1 a sser t hr e set_b buclk_enable = 1 & hreset_b = 0 lme = 1 poreset_b = 0 1,buclk 2,buclk 5, osc poreset_b = 1 lme = 1 3,buclk 4, osc 6,bulck poreset_b = 0 hresert_b = 0 hreset_b = 1 buclk_enable = 1 h r ese t _b = 1 b u c l k _ e n a b l e = 0 h r e s e t _ b = 1 else hreset_b = 0 locs=0 lme = 0 buclk_enable = 0 & hreset_b = 0 else buclk_enable=0 & hreset_b=0 buclk_enable = 1 & hreset_b = 0 else clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-16 freescale semiconductor the switching from state three to stat e four is accomplis hed by clearing the stbuc and locss bits. if the switch ing is done when the pll is not locked, the system clock will not oscillate until lock condition is met. the default value of the lme bit is determined by modck[1:3] during assertion of the poreset line. the configuration m odes are shown in table 8-1 . 8.7 low-power modes the lpm and other bits in the pl prcr are encoded to provide one normal operating mode and four low-power modes. in normal and doz e modes the system can be in hi gh state with frequency defined by the dfnh bits, or in the low state with frequency defined by the dfnl bits. the normal-high operating mode is the state out of reset. this is also the stat e of the bits after the low-pow er mode exit signal arrives. there are four low-power modes: ? doze mode ? sleep mode ? deep-sleep mode ? power-down mode 8.7.1 entering a low-power mode low-power modes are enabled by se tting the msr[pow] and clearing the sccr[lpml]. once enabled, a low-power mode is entered by setting the lpm bits to the appropriate value. this can be done only in one of the normal modes. the user cannot change the plprcr[lpm or csrc] when the mcu is in doze mode. note higher than desired currents during low-power mode can be avoided by executing a mullw instruction before entering the low-power mode, i.e., anytime after reset and prior to entering the low-power mode. table 8-3. status of clock source state poreset hreset lme locs (status) locss (sticky) stbuc bucs chip clock source 10 010001buclk 21 010/1001buclk 3 1 1 at least one of the two bits, locss or bucs, must be asserted (one) in this state. 111x 2 2 x = don?t care. 0/1 0/1 1 buclk 41 00/10x 2 0 0 oscillator 51 10/10x 2 0 0 oscillator 61 010/110/11buclk clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-17 table 8-6 summarizes the control bit settings for the different clock power modes. 8.7.2 power mode descriptions table 8-5 describes the clock frequency and ch ip functionality for each power mode. 8.7.3 exiting from low-power modes exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt generated by the interrupt controller. any enabled as ynchronous interrupt clears the lpm bits but does not change the plprcr[csrc] bit. table 8-4. power mode control bit settings power mode lpm[0:1] csrc texps normal-high 00 0 x normal-low (?gear?) 00 1 x doze-high 01 0 x doze-low 01 1 x sleep 10 x x deep-sleep 11 x 1 power-down 11 x 0 table 8-5. power mode descriptions operation mode spll clocks functionality power pins that need to be powered-up normal-high active full frequency 2 dfnh full functions not in use are shut off all on normal-low (?gear?) active full frequency 2 dfnl+1 all on doze-high active full frequency 2 dfnh enabled: rtc, pit, tb and dec, controller disabled: extended core (rcpu, bbc, fpu) kapwr, vddsyn, vdd, qvddl, nvddl, iramstby doze-low active full frequency 2 dfnl+1 kapwr, vddsyn, vdd, qvddl, nvddl, iramstby sleep active not active enabled: rtc, pit, tb and dec kapwr, vddsyn, iramstby deep-sleep not active no t active kapwr, iramstby power-down not active not active kapwr, iramstby sram standby not active not active sram data retention iramstby clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-18 freescale semiconductor the return to normal-high mode fr om normal-low, doze-high, low, and sleep mode is accomplished with the asynchronous interrupt. the source s of the asynchronous interrupt are: ? asynchronous wake-up interrupt from the interrupt controller ? rtc, pit, or time base interrupts (if enabled) ? decrementer exception the system responds quickly to as ynchronous interrupts. the wake-up time from normal-low, doze-high, doze-low, and sleep mode caused by an asynchronous in terrupt or a decrementer exception is only three to four clock cycles of maximum system frequency. in 40-mhz systems, this wa ke-up requires 75 to 100 ns. the asynchronous wake-up in terrupt from the interrupt controller is level sensitive one. it will therefore be negated only after the reset of interr upt cause in the interrupt controller. the timers? (rtc, pit, time base, or decrementer) in terrupts indications set stat us bits in the plprcr (tmist). the clock module considers this interrupt to be pending asynchronous interrupt as long as the tmist is set. the tmist status bit should be cleared before enteri ng any low-power mode. table 8-7 summarizes wake-up operation for each of the low-power modes. 8.7.3.1 exiting from normal-low mode in normal mode (as well as doze mode ), if the plprcr[csrc] bit is set, the syst em toggles between low frequency (defined by plprcr[dfnl ]) and high frequency (defined by plprcr[dfnh]. the system switches from normal-low mode to normal-high mode if either of the following conditions is met: ? an interrupt is pending from the interrupt controller; or ? the msr[pow] bit is cleared ( power management is disabled). when neither of these conditions ar e met, the plprcr[csrc] bit is set, and the asynchronous interrupt status bits are reset, the syst em returns to normal-low mode. table 8-6. power mode wake-up operation operation mode wake-up method return time from wake-up event to normal-high normal-low (?gear?) software or interrupt asynchronous interrupts: 3-4 maximum system cycles synchronous interrupts: 3-4 actual system cycles doze-high interrupt doze-low interrupt sleep interrupt 3-4 maximum system clocks deep-sleep interrupt < 500 oscillator cycles 125 s ? 4 mhz 25 s ? 20 mhz power-down interrupt < 500 oscillator cycles + power supply wake-up iramstby external power-on sequence clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-19 8.7.3.2 exiting from doze mode the system changes from doze mode to normal-high mode whenever an interrupt is pending from the interrupt controller. 8.7.3.3 exiting from deep-sleep mode the system switches from deep-sleep mode to normal-high m ode if any of the foll owing conditions is met: ? an interrupt is pending from the interrupt controller ? an interrupt is requested by the rtc, pit, or time base ? a decrementer exception in deep-sleep mode the pll is disabled. the wa ke-up time from this mode is up to 500 pll input frequency clocks. in one-to-one mode the wake-up time may be up to 100 pll input frequency clocks. for a pll input frequency of 4 mhz, the wake-up time is less than 125 s. 8.7.3.4 exiting from power-down mode exit from power-down mode is accomplished through hard reset. external l ogic should assert hreset in response to the texps bit being set and texp pin bei ng asserted. the texps bit is set by an enabled rtc, pit, time base, or decrementer interrupt. the hard reset should be asserted for no longer than the time it takes for the power supply to wake-up in addition to the pll lock time. when the texps bit is cleared (and the texp signal is negated), assertion of ha rd reset sets the bit, causes the pin to be asserted, and causes an exit from power-down low-power mode. refer to section 8.8.3, ?keep-alive power ? for more information. 8.7.3.5 low-power modes flow figure 8-9 shows the flow among the different power modes. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-20 freescale semiconductor 1 software is active only in normal-high/low modes. 2 texps receives the zero value by writing one . writing of zero has no effect on texps. 3 the switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared. figure 8-9. low-power modes flow diagram normal high mode lpm = 00 csrc = 0/1 normal-low lpm = 00, csrc = 1 doze-low lpm = 01, csrc = 1 doze-high lpm = 01, csrc = 0/1 sleep mode lpm = 10, csrc = 0 deep-sleep mode lpm = 11, csrc = 0, power-down mode lpm = 11, csrc = 0, (msr[pow]+interrupt )+plprcr[csrc] ((msr[pow]+interrupt ))*csrc 3 interrupt software 1 software 1 software 1 software 1 software 1 async. wake-up or interrupt wake-up: frequency clocks wake-up: 3 - 4 sysfreq clocks 500 input software 1 rtc/pit/tb/dec interrupt hard reset asynchronous wake-up: 3 - 4 sys interrupts clocks texps = 1 texps = 0 2 software 1 rtc/pit/tb/dec freqmax followed by external hard reset clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-21 8.8 basic power structure 8.8.1 general power supply definitions kapwr and vss power the following clock unit modules: oscillator, pi trtclk and tmbclk generation logic, timebase, decremen ter, rtc, pit, system clock cont rol register (sccr), low-power and reset-control register (plprcr ), and reset status register (rsr). all other circuits are powered by the normal supply pins: vdd , qvddl, nvddl, vddf, vddsyn, vflash, vddh and vss. the power supply for each block is listed in table 8-7 . the following are the relations between different power supplies: ? vdd = qvddl = nvddl = vdd syn = vddf = 2.6 v 0.1 v ? kapwr = vdd 0.2 v ( during normal operation) ? vddh = vdda = vflash = 5.0 5% ? kapwr = 2.6 0.1 v (during standby operation) ? iramstby = current source > 50 a, < 1.75 ma (average) note the power supply inputs vdd, q vddl, nvddl, vddsyn, and vddf should all be connected to the same 2.6-v power supply. the kapwr power supply can be connected to a 2.6-v standby power supply. if kapwr is not connected to a standby power supply, it should be connected to the same power supply as vdd. iramstby is the input to an approximately 1.7 volt regulator. it must be connected thr ough a resistor to a standby power supply. the power supply inputs vddh and vflash should be connected to the same 5.0- v supply. vdda can be isolated from vddh, but should be the sa me approxima te voltage. table 8-7. power supplies circuit power supply clkout spll (digital), system low-power control internal logic clock drivers nvddl/qvddl spll (analog) vddsyn main oscillator reset machine limp mode mechanism register control sccr, pllrcr and rsr ppc rtc, pit, tb, and dec kapwr calram, dptram, decram iramstby/vdd 1 1 keep-alive power is supplied by iramstby, but run current is provided through vdd clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-22 freescale semiconductor 8.8.2 chip power structure the mpc561/mpc563 provides a wide range of possibilities for power supply connections. figure 8-11 illustrates the different power supply sources for each of the basic units on the chip. 8.8.2.1 nvddl this supplies the final output stag e of the 2.6-v pad output drivers. 8.8.2.2 qvddl this supplies all pad logic and pre-dr iver circuitry, except for the fina l output stage of the 2.6-v pad output drivers. 8.8.2.3 vdd vdd powers the internal logic of the mpc561/mpc563, nominally 2.6v. 8.8.2.4 vddsyn, vsssyn the charge pump and the vco of th e spll are fed by a separate 2.6- v power supply (vddsyn) in order to improve noise immunity and achieve a high stabil ity in its output frequency. vsssyn provides an isolated ground reference for the pll. 8.8.2.5 kapwr the oscillator, time base counter, decrementer, periodic interrupt time r and the real-time clock are fed by the kapwr rail. this allows the ex ternal power supply unit to disconnect all other sub-units of the mcu in low-power deep-sleep mode. the texp pin (fed by the same rail) can be used by the external power supply unit to switch between sources. the irq [6:7]/modck[2:3], irq5 /modck1, xtal, extal, extclk, poreset , hreset , sreset , and rstconf /texp input pins are powered by kapwr. circuits, including pull-up resi sters, driving these inputs should be powered by kapwr. 8.8.2.6 vdda, vssa vdda supplies power to the analog subsystems of the qadc64e_a and qadc64e_b modules; it is nominally 5.0 v. vssa is the ground reference for the analog subsystems. 8.8.2.7 vflash vflash supplies the uc3f normal operating voltage . it is nominally 5.0 v. the mpc561 has no vflash signal. 8.8.2.8 vddf, vssf vddf provides internal core voltage to the uc3f flash module; it should be a nominal 2.6v. vssf provides an isolated ground for the uc3f flash module. the mpc561 has no vddf or vssf signal. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-23 8.8.2.9 vddh vddh provides power for the 5-v i/o operations. it is a nominal 5.0 v. 8.8.2.10 iramstby iramstby is the data retenti on power supply for all on-board ram arrays (calram, dptram, decram). it has a shunt regulator circuit of approximately 1.7 volts that divert s excess current to ground in order to regulate voltage on the iramstby power supply pin. run current is supplied by normal vdd. iramstby must be connected to a positive power supply, via a register, and bypassed by a capacitor to ground (see figure 8-10 . the resistor should sized accord ing to the following equations: where v supplymin is the lowest supply voltage and v supplymax is the highest possible supply voltage. see note in the vsrmcr[zoreg] bit description. figure 8-10. iramstby regulator circuit 8.8.2.11 vss vss provides the ground reference for the mpc561/mpc563. (v supplymin ? 1.95 v) r supply > 50 a (v supplymax ? 1.35 v) r supply <1.75 ma (average) iramstby v supply r supply c supply clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-24 freescale semiconductor figure 8-11. basic power supply configuration 8.8.3 keep-alive power 8.8.3.1 keep-alive power configuration figure 8-12 is an example of a switchi ng scheme for an optim ized low-power system. sw1 and sw2 can be unified in only one switch if vddsyn and vdd/n vddl/qvddl are supplied by the same source. clock control pll pit, rtc, tb, and dec nvddl i / o vdd vddsyn kapwr texp oscillator, vdd vddh flash* vflash vddf qvddl dptram decram calram qadc vdda vssa vdd iramstby internal logic note: flash is not implemented on the mpc561. clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-25 figure 8-12. external power supply scheme the mpc561/mpc563 asserts the texp signal, if enabled, when the rtc or tb time value matches the value programmed in th e associated alarm register or when th e pit or dec value r eaches zero. the texp signal is negated when the texps status bit is written to one. the kapwr power supply feeds the ma in crystal oscillator (oscm). th e condition for the main crystal oscillator stability is that the pow er supply value changes slowly. the ma ximum slope must be less than 5 mv per oscillation cycle ( > 200-300/freq oscm ). 8.8.3.2 keep-alive power registers lock mechanism the usiu timer, clocks, reset, pow er, decrementer, and time base registers are powered by the kapwr supply. when the main po wer supply is disconnected after power-down mode is entered, the value stored in any of these registers is preserved. if power-dow n mode is not entered befo re power disconnect, there is a chance of data loss in these registers. to minimize the possi bility of data lo ss, the mpc561/mpc563 includes a key mechanism that ensures data retention as long as a register is locked. while a register is locked, writes to this register are ignored. each of the registers in the kapwr region have a key th at can be in one of two states: open or locked. at power-on reset the following keys are locked by defa ult: rtc, rtsec, rtcal, and rtcsc. all other registers are unlocked. each key has an addre ss associated with it in the internal map. main power backup vddsyn 2.6 v vdd kapwr supply switch logic texp 2.6-v sw1 sw2 power supply iramstby power supply iramstby o o o o mpc561/mpc563 clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-26 freescale semiconductor a write of 0x55ccaa33 to the associated key register changes the key to the open state. a write of any other data to this lo cation changes the key to the locked state. the key registers are write-only. a read of the key register has undefined side effects and may be interpreted as a write th at locks the associated register. table 8-8 lists the registers powered by kapw r and the associated key registers. table 8-8. kapwr registers and key registers kapwr register associated key register address or spr number register address register 0x2f c200 time base status and control (tbscr) see ta bl e 6 - 1 8 for bit descriptions. 0x2f c300 time base status and control key (tbscrk) 0x2f c204 time base reference 0 (tbref0) see section 6.2.2.4.3, ?time base reference registers (tbref0 and tbref1) ? for bit descriptions. 0x2f c304 time base reference 0 key (tbref0k) 0x2f c208 time base reference 1 (tbref1) see section 6.2.2.4.3, ?time base reference registers (tbref0 and tbref1) for bit descriptions. 0x2f c308 time base reference 1 key (tbref1k) 0x2f c220 real time clock status and control (rtcsc) see ta bl e 6 - 1 9 for bit descriptions. this register is locked after reset by default. 0x2f c320 real time clock status and control key (rtcsck) 0x2f c224 real time clock (rtc) see section 6.2.2.4.6, ?real-time clock register (rtc) ? for bit descriptions. this register is locked after reset by default. 0x2f c324 real time clock key (rtck) 0x2f c228 real time alarm seconds (rtsec) reserved. this register is locked after reset by default. 0x2f c328 real time alarm seconds key (rtseck) 0x2f c22c real time alarm (rtcal) see section 6.2.2.4.7, ?real-time clock alarm register (rtcal) ? for bit descriptions. this register is locked after reset by default. 0x2f c32c real time alarm key (rtcalk) 0x2f c240 pit status and control (piscr) see ta bl e 6 - 2 0 for bit descriptions. 0x2f c340 pit status and control key (piscrk) 0x2f c244 pit count (pitc) see ta bl e 6 - 2 1 for bit descriptions. 0x2f c344 pit count key (pitck) 0x2f c280 system clock control register (sccr) see ta bl e 8 - 9 for bit descriptions. 0x2f c380 system clock control key (sccrk) 0x2f c284 pll low-power and reset-control register (plprcr) see ta bl e 8 - 1 1 for bit descriptions. 0x2f c384 pll low-power and reset-control register key (plprcrk) clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-27 figure 8-13 illustrates the process of locking or unlocking a register powered by kapwr. figure 8-13. keep-alive register key state diagram 8.9 iramstby supply failure detection a special circuit for iramstby supply failure de tection is provided. in th e case of supply failure detection, the dedicated sticky bits lvsrs in the vsrm cr register are asserted. software can read or clear these bits. the user should enab le the detector and then clear these bits. if any of the lvsr bits are read as one, then a power failure of iramstby has occurred. the circui t is capable of detecting supply failure below a voltage level to be determined. also, enable/disab le control bit for the iramstby detector may be used to disconnect the circ uit and save the detector power consumption. 8.10 power-up/down sequencing figure 8-14 and figure 8-15 detail the power-up sequencing for mpc561/mpc563 during normal operation. note that for each of the conditions detailing the voltage rela tionships the absolute bounds of the minimum and maximum voltage s upply cannot be violated; that is , the value of vddl cannot fall below 2.5 v or exceed 2.7 v, and the value of vddh cannot fall below 4.75 v or exceed 5.25 v for normal operation. power consumption during power up se quencing will be below the operating power consumption. 0x2f c288 reset status register (rsr) see ta bl e 7 - 3 for bit descriptions. 0x2f c388 reset status register key (rsrk) spr 22 decrementer see section 3.9.5, ?decrementer register (dec) ? for bit descriptions. 0x2f c30c time base and decrementer key (tbk) spr 268, 269, 284, 285, time base see section 6.2.2.4.2, ?time base sprs (tb) ,? for bit descriptions. table 8-8. kapwr registers and key registers (continued) kapwr register associated key register address or spr number register address register open locked write to the key 0x55ccaa33 write to the ke y other value power on reset (valid for rtc, rtsec, rtcal and rtcsc) (valid for other registers) power-on reset clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-28 freescale semiconductor during the power down sequence poreset needs to be asserted whil e vdd, nvddl, and qvddl are at a voltage greater than or equal to 2.5 v. below th is voltage the power supply chip can be turned off. if the turn-off voltage of the power supply chip is greater than 0.74 v for the 2.6-v supply and greater than 0.8 v for the 5-v supply, then the ci rcuitry inside the mpc561/mpc563 will act as a load to the respective supply and will discharge the supply line down to these values. since the 2.6-v l ogic represents a larger load to the supply chip, the 2.6-v supply line will decay faster than the 5-v supply line. figure 8-14. no standby, no ka pwr, all system power-on/off power on power off operating see note 1. see note 2. vddh vdd, nvvl, kapwr iramstby vdda, vrh vddsyn vflash (5 v) poreset hreset qvddl 1 vddh qvddl - 0.5 v vdda can lag vddh, and vddsyn can lag qvddl, but both must be at a valid level before resets are negated. 2 if keep-alive functions are not used, then when system power is on: kapw r = qvddl 0.1 v; kapwr 2.7 v 3 if keep-alive functions are used, then kapwr = qvddl = nvddl = 2.6 v 0.1 v when system power is on kapwr = 2.6 v 0.1 v when system power is off. iram stby should be powered prior to the other supplies. if iramstby is powered at the same time as the other supplies, it should be allowed to stabilize before poreset is negated. normal system power is defined as qvddl = vdd = vddf = vddsyn = kapwr = 2.6 0.1 v and vdda = vddh = vflash = 5.0 0.25 v. flash progra mming requirements are the same as normal system power. vflash should always be 5.0 0.25 v. note: flash is not implemented on the mpc561. 4 do not hold the 2.6-v supplies at ground while vddh/vdda is ramping to 5 v. 5 if 5 v is applied before the 2.6-v supply, all 5-v output s will be in indeterminate states until the 2.6-v supply reaches a level that allows reset to be distributed througho ut the device if 5 v is applied before the 2.6-v supply, all 5-v outputs will be in indeterminate states until the 2.6-v supply reaches a level that allows reset to be distributed throughout the device clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-29 figure 8-15. standby and kapwr, other power-on/off note for more detailed informat ion on power sequencing see section f.8, ?power-up/down sequencing .? 8.11 clocks unit programming model 8.11.1 system clock control register (sccr) the spll has a 32-bit control register, sccr , which is powered by keep-alive power. power on power off operating vddh vdd, nvvl, kapwr iramstby vdda, vrh vddsyn vflash (5 v) poreset hreset no battery connect battery no battery qvddl 1 vddh qvddl - 0.5 v vdda can lag vddh, and vddsyn can lag qvddl, but both must be at a valid level before resets are negated. 2 if keep-alive functions are not used, then when system power is on: kapwr = qvddl 0.1 v; kapwr 2.7 v 3 if keep-alive functions are used, then kapwr = qvddl = nvddl = 2.6 v 0.1 v when system power is on kapwr = 2.6 v 0.1 v when system power is off. iram stby should be powered prior to the other supplies. if iramstby is powered at the same time as the other supplies, it should be allowed to stabilize before poreset is negated. normal system power is defined as qvddl = vdd = vddf = vddsyn = kapwr = 2.6 0.1 v and vdda = vddh = vflash = 5.0 0.25 v. flash programming requirements are the same as normal system power. vflash should always be 5.0 0.25 v. note: flash is not implemented on the mpc561. 4 do not hold the 2.6-v supplies at ground while vddh/vdda is ramping to 5 v. 5 if 5 v is applied before the 2.6-v supply, all 5-v output s will be in indeterminate states until the 2.6-v supply reaches a level that allows reset to be distributed througho ut the device if 5 v is applied before the 2.6-v supply, all 5-v outputs will be in indeterminate states until the 2.6-v supply reaches a level that allows reset to be distributed throughout the device clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-30 freescale semiconductor note com[1] bit default value is de termined during by bdrv reset configuration bit; see section 7.5.2, ?hard reset configuration word (rcw) .? msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field dbct com dcslr mfpdl lpml tbs rtdiv 4 stbuc cqds prqen rtsel bucs ebdf[0:1] lme poreset 10id2 1 0000 1 1 0 1 eq2 2 0 id[13:14] 1 eq3 3 hreset u0id2 1 unaffected 1 unaffected id[13:14] 1 u addr 0x2f c280 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 eeclk[0:1] engdiv[0:5] ? dfnl[0:2] ? dfnh[0:2] poreset 0 0 1 1 1 1 1 1 0000_0000 hreset unaffected 0000_0000 1 the hard reset value is a reset configuration word value, ex tracted from the indicated inte rnal data bus lines. refer to section 7.5.2, ?hard reset configuration word (rcw) .? 2 eq2 = modck1 3 eq3 = (modck1 and modck2 and modck3 ) | (modck1 and modck2 and modck3) | (modck1 and modck2 and modck3). see ta bl e 8 - 1 . 4 rtdiv will be 0 if modck[1:3] = 000. figure 8-16. system clock and reset control register (sccr) table 8-9. sccr bit descriptions bits name description 0 dbct disable backup clock for timers. the dbct bit controls the timers clock source while the chip is in limp mode. if dbct is set, the ti mers clock (tmblck, pitrclk) source will not be the backup clock, even if the system clock source is the backup clock ring oscillator. the real-time clock source will be extal or extclk according to rtsel bit (see description in bit 11 below), and the time base clocks source will be determined according to tbs bit and modck1. 0 if the chip is in limp mode, the timer clock source is the backup (limp) clock 1 the timer clock source is either the external clock or the crystal (depending on the current clock mode selected) 1:2 com clock output mode ? the com and cqds bits control the output buffer strength of the clkout and external bus pins. when both com bits are set the clkout pin is held in the high (1) state and external bus pins are driven at reduced drive. these bits can be dynamically changed without generating spikes on the clkout and external bus pins. if clkout pin is not connected to external circuits, set both bits (disabling clkout) to minimize noise and power dissipation. the def ault value for com[1] is determined by the bdrv bit in the reset configuration word. see ta bl e 7 - 5 . for clkout control see ta bl e 8 - 1 0 . clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-31 3 dcslr disable clock switching at loss of lock during reset. when dcslr is clear and limp mode is enabled, the chip will switch automatically to the backup clock if the pll losses lock during hreset . when dcslr is asserted, a pll loss-of-lock event does not cause clock switching. if hreset is asserted and dcslr is set, the chip will not negate hreset until the pll acquires lock. 0 enable clock switching if the pll loses lock during reset 1 disable clock switching if the pll loses lock during reset 4 mfpdl mf and pre-divider lock. setting this contro l bit disables writes to the mf and divf bits. this helps prevent runaway software from changing the vco frequency and causing the spll to lose lock. in addition, to protect against hardware interference, a hardware reset will be asserted if these fields are changed while lpml is asserted. this bit is writable once after power-on reset. 0 mf and divf fields are writable 1 mf and divf fields are locked 5 lpml lpm lock. setting this control bit disables writes to the lpm and csrc control bits. in addition, for added protection, a hardware reset is asserted if any mode is entered other than normal-high mode. this protects agains t runaway software causing the mcu to enter low-power modes. (the msr[pow] bit provides additional protection). lpml is writable once after power-on reset.) 0 lpm and csrc bits are writable 1 lpm and csrc bits are locked and hard reset will occur if the mcu is not in normal-high mode 6 tbs time base source. 0 source is oscclk divided by either 4 or 16 1 source is system clock divided by 16 7 rtdiv rtc (and pit) clock divider. at power-on reset this bit is cleared if modck[1:3] are all low; otherwise the bit is set. 0 rtc and pit clock divided by 4 1 rtc and pit clock divided by 256 8 stbuc switch to backup clock control. when softw are sets this bit, the system clock is switched to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. the stbuc bit is ignored if lme is cleared. 0 do not switch to the backup clock ring oscillator 1 switch to backup clock ring oscillator 9 cqds clock quarter drive strength ? the com and cq ds bits control the output buffer strength of the clkout, see ta bl e 8 - 1 0 . 10 prqen power management request enable 0 remains in the lower frequency (defined by dfnl) even if the power management bit in the msr is reset (normal operational mode) or if there is a pending interrupt from the interrupt controller 1 switches to high frequency (defined by df nh) when the power management bit in the msr is reset (normal operational mode) or ther e is a pending interrupt from the interrupt controller table 8-9. sccr bit descriptions (continued) bits name description clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-32 freescale semiconductor 11 rtsel rtc circuit input source select. at power-on reset rtsel receives the value of the modck1 signal. refer to ta b l e 8 - 1 . note that if the chip is operating in limp mode (bucs = 0), the rtsel bit is ignored, and the backup clock is the clock source for the rt and pit clocks 0 oscm clock is selected as input to rtc and pit 1 extclk clock is selected as the rtc and pit clock source 12 bucs backup clock status. this status bit indi cates the current system clock source. when loss of clock is detected and the lme bit is set, the clock source is the backup clock and this bit is set. when the stbuc bit and lme bit are se t, the system switches to the backup clock and bucs is set. 0 system clock is not the backup clock 1 system clock is the backup clock 13:14 ebdf[0:1] external bus division factor. thes e bits define the frequency division factor between (gclk1 and gclk2) and (gclk1_50 and gclk2_50). clkout is similar to gclk2_50. the gclk2_50 and gckl1_50 are used by the ex ternal bus interface and controller in order to interface to the ex ternal system. the ebdf bits ar e initialized dur ing hard reset using the hard reset configuration mechanism. 00 clkout is gckl2 divided by 1 01 clkout is gckl2 divided by 2 1x reserved note: if ebdf > 0, an external burst access with short setup timing will corrupt any usiu register load/store. refer to section 10.2.6, ?reduced data setup time .? 15 lme limp mode enable. when lme is set, the loss-of-clock monitor is enabled and any detection of loss of clock will switch the system clock automatically to backup clock. it is also possible to switch to the backup clock by setting the stbuc bit. if lme is cleared, the option of using limp mode is disabled. the loss of clock detector is not active, and any write to stbuc is ignored. the lme bit is writable once, by software, af ter power-on reset, when the system clock is not backup clock (bucs = 0). during power-on reset, the value of lme is determined by the modck[1:3] bits. (refer to ta bl e 8 - 1 .) 0 limp mode disabled 1 limp mode enabled 16:17 eeclk[0:1] enable engineering clock. this field c ontrols the output buffer voltage of the engclk pin. when both bits are set the engclk pin is held in the high state. these bits can be dynamically changed without generating spikes on the engclk pin. if engclk is not connected to external circuits, set both bits (disabling engclk) to minimize noise and power dissipation. for measurement purposes the backup clock (buclk) can be driven externally on the engclk pin. 00 engineering clock enabled, 2.6 v output buffer 01 engineering clock enabled (slew rate controlled), 5 v output buffer 10 buclk is the output on the engclk 2.6 v output buffer 11 engineering clock disabled 18:23 engdiv[0:5] engineering clock division factor. t hese bits define the frequency division factor between vco/2 and engclk. division factor can be from 1 (engdiv = 000000) to 64 (engdiv = 111111). these bits can be read and written at any time. they are not affected by hard reset but are cleared during power-on reset. note: if the engineering clock division factor is not a power of two, synchronization between the system and engclk is not guaranteed. table 8-9. sccr bit descriptions (continued) bits name description clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-33 8.11.2 pll, low-power, and rese t-control register (plprcr) the pll, low-power, and reset-cont rol register (plprcr) is a 32-bit re gister powered by the keep-alive power supply. 24 ? reserved 25:27 dfnl[0:2] division factor low frequency. the user can load these bits with the desired divide value and the csrc bit to change the frequency. changi ng the value of these bits does not result in a loss of lock condition. these bits are cleared by power-on or hard reset. refer to section 8.5.1, ?general system clocks ? and figure 8-5 for details on using these bits. 000 divide by 2 001 divide by 4 010 divide by 8 011 divide by 16 100 divide by 32 101 divide by 64 110 reserved 111 divide by 256 28 ? reserved 29:31 dfnh division factor high frequency. these bits determine the general system clock frequency during normal mode. changing the value of these bits does not result in a loss of lock condition. these bits are cleared by power-on or hard reset. the user can load these bits at any time to change the general syst em clock rate. note that the gclks generated by this division factor are not 50% duty cycle (i.e. clkout). 000 divide by 1 001 divide by 2 010 divide by 4 011 divide by 8 100 divide by 16 101 divide by 32 110 divide by 64 111 reserved table 8-10. com and cqds bits functionality com[0:1] cqds function 00 x clock output enabled full-strength output buffer, bus pins full drive 01 0 clock output enabled half-strength output buffer, bus pins reduced drive 01 1 clock output enabled quarter-strength output buffer, bus pins reduced drive 10 x clock output disabled, bus pins full drive 11 x clock output disabled, bus pins reduced drive table 8-9. sccr bit descriptions (continued) bits name description clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-34 freescale semiconductor msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field mf ? locs locss spls poreset 0000_0000_0000 or 0000_0000_1000 0000 hreset unaffected addr 0x2f c284 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field splss texps texp_inv tmist ? csrc lpm csr lolre ? divf poreset 01 00_0000_0000_0000 hreset u 1 u 0 u 000 unaffected ? unaffected figure 8-17. pll, low-power, and reset-control register (plprcr) table 8-11. plprcr bit descriptions bits name description 0:11 mf multiplication factor bits. t he output of the vco is divided to generate the feedback signal to the phase comparator. the mf bits control the value of the divider in the spll feedback loop. the phase comparator determines the phase shift between the feedback signal and the reference clock. this difference results in either an increase or decrease in the vco output frequency. the mf bits can be read and written at any ti me. however, this fiel d can be write-protected by setting the mf and pre-divider lock (mfp dl) bit in the sccr. changing the mf bits causes the spll to lose lock. also, the mf field should not be modified when entering or exiting from low power mode (lpm change) , or when back-up clock is active. the normal reset value for the dfnh bits is zero (divide by 1). when the pll is operating in one-to-one mode, the multiplication factor is set to x1 (mf = 0). 12 ? reserved 13 locs loss of clock status. when the oscillator or external clock source is not at the minimum frequency, the loss-of-clock circuit asserts th e locs bit. this bit is cleared when the oscillator or external clock source is functioning normally. this bit is reset only on power-on reset. writes to this bit have no effect. 0 no loss of oscillator is currently detected 1 loss of oscillator is currently detected 14 locss loss of clock sticky. if, after negation of poreset , the loss-of-clock circuit detects that the oscillator or external clock source is not at a minimum frequency, the locss bit is set. locss remains set until software clears it by writ ing a one to it. a write of zero has no effect on this bit. the reset value is determined during hard reset. the stbuc bit will be set provided the pll lock cond ition is not met when hreset is asserted, and cleared if the pll is locked when hreset is asserted. 0 no loss of oscillator has been detected 1 loss of oscillator has been detected 15 spls system pll lock status bit 0 spll is currently not locked 1 spll is currently locked clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-35 16 splss spll lock status sticky bit. an out-of-l ock sets the splss bit. the bit remains set until software clears it by writing a one to it. a write of zero has no effect on this bit. the bit is cleared at power-on reset. this bit is not affect ed due to a software initiated loss-of-lock (mf change and entering deep-sleep or power-down m ode). the splss bit is not affected by hard reset. 0 spll has remained in lock 1 spll has gone out of lock at least once (not due to software-initiated loss of lock) 17 texps timer expired status bit. this bit cont rols whether the chip negates the texp pin in deep-sleep mode, thus enabling external circuitry to switch off the vdd (power-down mode). when lpm = 11, csrc = 0, and texps is high, the texp pin remains asserted. when lpm = 11, csrc = 0, and texps is low, the texps pin is negated. to enable automatic wake-up texps is asse rted when one of the following occurs: the pit is expired the real-time clock alarm is set the time base clock alarm is set the decrementer exception occurs the bit remains set until software clears it by writing a one to it. a write of zero has no effect on this bit. texps is set by power-on or hard reset. 0 texp is negated in deep-sleep mode 1 texp pin remains asserted always 18 texp_invp timer expired pin inversed polarity ? t he tex_invp bit controls whether the polarity of the texp pin will be active high (normal default) or active low. 0 the texp pin is active high 1 the texp pin is active low 19 tmist timers interrupt status.tmist is set when an interrupt from the rtc, pit, tb or dec occurs. the tmist bit is cleared by writing a one to it. writing a zero has no effect on this bit. the system clock frequency remain s at its high frequency value ( defined by dfnh) if the tmist bit is set, even if the csrc bit in the plprcr is set (dfnl enabled) and conditions to switch to normal-low mode do not exist. this bit is cleared during power-on or hard reset. 0 no timer expired event was detected 1 a timer expire event was detected 20 ? reserved 21 csrc clock source. this bit is cleared at hard reset. 0 general system clock is de termined by th e dfnh value 1 general system clock is de termined by th e dfnl value 22:23 lpm low-power mode select. these bits are en coded to provide one normal operating mode and four low-power modes. in no rmal and doze modes, the syst em can be in high state (frequency determined by the dfnh bits) or low state (frequency defined by the dfnl bits). the lpm field can be write-protected by sett ing the lpm and csrc lock (lpml) bit in the sccr refer to ta b l e 8 - 4 and ta b l e 8 - 5 . 24 csr checkstop reset enable. if this bit is set, then an automatic reset is generated when the rcpu signals that it has entered checkstop mode, unless debug mode was enabled at reset. if the bit is clear and debug mode is not ena bled, then the usiu will not do anything upon receiving the checkstop signal from the rcpu. if debug mode is enabled, then the part enters debug mode upon entering checkstop mode. in this case, the rcpu will not assert the checkstop signal to the reset circuitry. this bit is writable once after soft reset. 0 no reset will occur when checkstop is asserted 1 reset will occur when checkstop is asserted table 8-11. plprcr bit descriptions (continued) bits name description clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-36 freescale semiconductor 8.11.3 change of lock inte rrupt register (colir) the colir is 16-bit read/write register . it controls the change of lock interrupt generation, and is used for reporting a loss of lock interrupt sour ce. it contains the interrupt request level and the interrupt status bit. this register is readable and writab le at any time. a status bit is cl eared by writing a one (writing a zero does not affect a status bit?s va lue). the colir is mapped into th e mpc561/mpc563 usiu register map. 25 lolre loss of lock reset enable 0 loss of lock does not cause hreset assertion 1 loss of lock causes hreset assertion note: if limp mode is enabled, use the colir feature instead of setting the lolre bit. see section 8.11.3, ?change of lock interrupt register (colir) .? 26 ? reserved 27:31 divf the divf bits c ontrol the value of the pre-divider in the spll circuit. the divf bits can be read and written at any time. however, the divf field can be write-protected by setting the mf and pre-divider lock (mfpdl) bit in the s ccr. changing the divf bits causes the spll to lose lock. msb 01234567 8 9 1011121314 lsb 15 field colirq colis ? colie ? sreset 0000_0000_00 unaffected addr 0x2f c28c figure 8-18. change of lock interrupt register (colir) table 8-12. colir bit descriptions bits name description 0:7 colirq change of lock interrupt request level. these bits determine the interrupt priority level of the change of lock. to specify a certain level, the appropriate one of these bits should be set. 8 colis if set (1), the bit indicates that a change in the pll lock status was detected. the pll was locked and lost lock, or the pll was unlocked and got locked. the bit should be cleared by writing a one. 9?reserved 10 colie change of lock interrupt enable. if colie bit is asserted, an interrupt will be generated when the colis bit is asserted. 0 change of lock interrupt disable 1 change of lock interrupt enable 11:15 ? reserved table 8-11. plprcr bit descriptions (continued) bits name description clocks and power control mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 8-37 8.11.4 iramstby control register (vsrmcr) this register contains c ontrol bits for enabling or disabling the iramstby suppl y detection circuit. there are also four bits that indicate th e failure detection. all four bits ha ve the same function and are required to improve the detection ca pability in extreme cases. msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field ? lvsrs vsrde 1 1 this bit is reserved on mask sets which implement bit 7 (zoreg) lvdrs zoreg ? poreset unaffected 0 u 0_0000_0000 addr 0x2f c290 u = unaffected by reset figure 8-19. iramstby control register (vsrmcr) table 8-13. vsrmcr bit descriptions bits name description 0 ? reserved 1:4 lvsrs loss of iramstby sticky. these status bi ts indicate whether a iramstby supply failure occurred. in addition, when the power is tur ned on for the first time, iramstby rises and these bits are set. the lvsrs bits are cleared by writing them to ones. a write of zero has no effect on these bits. 0 no iramstby supply failure was detected 1 iramstby supply failure was detected 5 vsrde 1 1 removed on all parts that have the zoreg bit. iramstby detector disable. 0 iramstby detection circuit is enabled 1 iramstby detection circuit is disabled 6 lvdrs loss of iramstby for decram sticky ? the status bit, dedicated especially for the bbc decram, which indicates if there was iramstby supply failure. when the power is turned on for the first time, iramstby rises also and the bits will be asserted. the lvdecram bit can be cleared by writing ones to lvdecram. a write of zero has no effect on this bit. the bit may be used by application software, to decide if there is need to load decompression vocabularies during reset routine. 0 iramstby supply failure was not detected 1 iramstby supply failure was detected note: the lvdrs bit is provided as a convenie nce for indicating that the decram has lost power. it requires that the iramstby pins are connected to the same power supply. it actually only monitors the iramstby supply. 7 zoreg 2 this bit indicates the status of the internal iramstby supply. this bit is cleared by writing a 1 to it. 0 internal iramstby zener regulator has not gone out of regulation 1 internal iramstby zener regulator has gone out of regulation. note: zoreg may get set in advertently if iramst by is not supplied wit h at least 150 a. 8:15 ? reserved clocks and power control mpc561/mpc563 reference manual, rev. 1.2 8-38 freescale semiconductor 2 zoreg is not in rev 0 of the mpc561 but is in all later revisions. it is not in rev 0 or 0a of the mpc563, but is in rev a and later revisions. mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-1 chapter 9 external bus interface the mpc561/mpc563 external bus is a synchronous, burstable bus. signals driven on this bus must adhere to the setup and hold time re lative to the bus clock?s rising edge . the bus has the ability to support multiple masters. the mpc561/mpc5 63 external bus interface architec ture supports byte, half-word, and word operands allowing access to 8- , 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (tsiz0, tsiz1). for accesses to 16- and 8-bit ports, the slave must be controlled by the memory controller. for more information, refer to appendix f, ?electrical characteristics .? 9.1 features the external bus interface features are listed below: ? 32-bit address bus with transfer size indication (only 24 available on pins) ? 32-bit data bus ? bus arbitration logic on-chip with external master support ? chip-select and wait state gene ration to support peripheral or st atic memory devices through the memory controller ? supports various memory (sram, eeprom) t ypes: synchronous and asynchronous, burstable and non-burstable ? supports non-wrap bursts with up to four data beats ? flash rom programming support ? implements the powerpc isaarchitecture ? easy to interface to slave devices ? bus is synchronous (all signals are re ferenced to rising edge of bus clock) ? bus can operate at the same fr equency as the intern al rcpu core of mpc 561/mpc563 or half the frequency. 9.2 bus transfer signals the bus transfers information betw een the mpc561/mpc563 and external memory of a peripheral device. external devices can accept or provi de 8, 16, and 32 data bits in parall el and must follow the handshake protocol described in this section. the maximum numbe r of bits accepted or provi ded during a bus transfer is defined as the port width. the mpc561/mpc563 has non-multiplexed address a nd data buses. control signals indicate the beginning and type of the cycle, as well as the address space and size of the transfer. the selected device external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-2 freescale semiconductor then controls the length of the cycle with the signal(s) used to terminate the cycle. a strobe signal for the address lines indicates th e validity of the address. the mpc561/mpc563 bus is synchronou s with a synchronous support. the bus and control input signals must be timed to setup and hold time s relative to the rising edge of th e clock. bus cycles can be completed in two clock cycles. for all inputs, the mpc561/mpc563 latches the leve l of the input during a sample window around the rising edge of the clock signal. this window is illustrated in figure 9-1 , where t su and t ho are the input setup and hold times, respectively. to ensure that an input signal is recognized on a specific rising edge of the clock, that input must be stable during the sa mple window. if an input ma kes a transition during the window time period, the level recognized by the mp c561/mpc563 is not predictable; however, the mpc561/mpc563 always resolves the latched level to either a logic high or low before using it. in addition to meeting input setup and hold times for deterministic operati on, all input signals must obey the protocols described in this section. figure 9-1. input sample window 9.3 bus control signals the mpc561/mpc563 initiates a bus cycle by driving th e address, size, address type, cycle type, and read/write outputs. at the beginning of a bus cycle, tsiz[0:1] are driv en with the address type signals. tsiz0 and tsiz1 indicate the number of bytes remaining to be tran sferred during an operand cycle (consisting of one or more bus cycles). these signals ar e valid at the rising edge of the clock in which the transfer start (ts ) signal is asserted. the read/write (rd/wr ) signal determines the direction of the tr ansfer during a bus cycle. driven at the beginning of a bus cycle, rd/wr is valid at the rising edge of the clock in which ts is asserted. the logic level of rd/wr only changes when a write cycl e is preceded by a read cycle or vice versa. the signal may remain low for consecutive write cycles. clock signal t ho t su sample window external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-3 figure 9-2. mpc561/mpc563 bus signals 9.4 bus interface signal descriptions table 9-1 describes each signal in the bus interface unit. more detailed descriptions can be found in subsequent subsections. the buses are described in big endian manner, which means that bit 0 is the most significant bit in a bus (msb), and bi t 31 is the least significant bit (lsb). addr[8:31] rd/ wr burst tsiz[0:1] at[0:3] ts bi / sts kr data[0:31] ta tea bdip br bg bb cr 24 1 1 2 4 1 1 1 1 1 32 1 1 1 1 1 1 address and transfer attributes transfer start arbitration data transfer termination reservation protocol cycle rsv ptr 1 retry 1 bus interface external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-4 freescale semiconductor . table 9-1. mpc561/mpc563 biu signals signal name pins active i/o description address and transfer attributes addr[8:31] address bus 24 [8:31] high o specifies the physical address of the bus transaction. i driven by an external bus master when it owns the external bus. an input for testing purposes only. rd/wr read/write 1high o driven by the mpc561/mpc563 along with the address when it owns the external bus. driven high indicates that a read access is in progress. driven low indicates that a write access is in progress. i driven by an external master when it owns the external bus. driven high indicates that a read access is in progress. driven low indicates that a write access is in progress. burst burst transfer 1low o driven by the mpc561/mpc563 along with the address when it owns the external bus. driven low indicates that a burst transfer is in progress. driven high indicates that the current transfer is not a burst. i driven by an external master when it owns the external bus. driven low indicates that a burst transfer is in progress. driven high indicates that the current transfer is not a burst. the mpc561/mpc563 does not support burst accesses to internal slaves. tsiz[0:1] transfer size 2 high o driven by the mpc561/mpc563 along with the address when it owns the external bus. specifies the data transfer size for the transaction. i driven by an external master when it owns the external bus. specifies the data transfer size for the transaction. at[0:3] address type 3 high o driven by the mpc561/mpc563 along with the address when it owns the external bus. indicates additional type on the current transaction. i only for testing purposes. rsv reservation transfer 1low o driven by the mpc561/mpc563 along with the address when it owns the external bus. indicates additional information about the address on the current transaction. i only for testing purposes. ptr program trace 1 high o driven by the mpc561/mpc563 along with the address when it owns the external bus. indicates additional information about the address on the current transaction. i only for testing purposes. external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-5 bdip burst data in progress 1low o driven by the mpc561/mpc563 when it owns the external bus. it is part of the burst protocol. when bdip is asserted, the second beat in front of the current one is requested by the master. this signal is negated prior to the end of a burst to terminate the burst data phase early. i driven by an external master when it owns the external bus. when bdip is asserted, the second beat in front of the current one is requested by the master. this signal is negated prior to the end of a burst to terminate the burst data phase early. the mpc561/mpc563 does not support burst accesses to internal slaves. transfer start ts transfer start 1low o driven by the mpc561/mpc563 when it owns the external bus. indicates the start of a transaction on the external bus. i driven by an external master when it owns the external bus. it indicates the start of a transaction on the external bus or (in show cycle mode) signals the beginning of an internal transaction. reservation protocol cr cancel reservation 1lowi each mpc500 cpu has its own cr signal. assertion of cr instructs the bus master to clear its reservation; some other master has touched its reserved space. this is a pulsed signal. kr kill reservation 1lowi in case of a bus cycle initiated by a stwcx instruction issued by the rcpu to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. refer to section 9.5.10, ?storage reservation ? for details. table 9-1. mpc561/mpc563 biu signals (continued) signal name pins active i/o description external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-6 freescale semiconductor data data[0:31] data bus 32 high o the data bus has the following byte lane assignments: data byte byte lane data[0:7] 0 data[8:15] 1 data[16:23] 2 data[24:31] 3 driven by the mpc561/mpc563 when it owns the external bus and it initiated a write transaction to a slave device. for single beat transactions, the byte lanes not selected for the transfer by addr[30:31] and tsiz[0:1] do not supply valid data. in addition, the mpc561/mpc563 drives the data[0:31] when an external master owns the external bus and initiated a read transaction to an internal slave module. i driven by the slave in a read transaction. for single beat transactions, the mpc561/mpc563 does not sample byte lanes that are not selected for the transfer by addr[30:31] and tsiz[0:1]. in addition, an external master that owns the bus and initiated a write transaction to an internal slave module drives data[0:31]. transfer cycle termination ta transfer acknowledge 1low i driven by the slave device to which the current transaction was addressed. indicates that the slave has received the data on the write cycle or returned data on the read cycle. if the transaction is a burst, ta should be asserted for each one of the transaction beats. o driven by the mpc561/mpc563 when the slave device is controlled by the on-chip memory controller or when an external master initiated a transaction to an internal slave module. tea transfer error acknowledge 1low i driven by the slave device to which the current transaction was addressed. indicates that an error condition has occurred during the bus cycle. o driven by the mpc561/mpc563 when the internal bus monitor detected an erroneous bus condition, or when an external master initiated a transaction to an internal slave module and an internal error was detected. table 9-1. mpc561/mpc563 biu signals (continued) signal name pins active i/o description external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-7 bi / sts burst inhibit/ special transfer start 1low i burst inhibit: driven by the slave device to which the current transaction was addre ssed. indicates that the current slave does not support burst mode. o burst inhibit: driven by the mpc561/mpc563 when the slave device is controlled by the on-chip memory controller. the mpc561/mpc563 also asserts bi for any external master burst access to internal mpc561/mpc563 memory space. special transfer start: driven by the mpc561/mpc563 when it owns the external bus. indicates the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode. arbitration br bus request 1low i when the internal arbiter is enabled, br assertion indicates that an external master is requesting the bus. o driven by the mpc561/mpc563 when the internal arbiter is disabled and the chip is not parked. bg bus grant 1low o when the internal arbiter is enabled, the mpc561/mpc563 asserts this signal to indicate that an external master may assume ownership of the bus and begin a bus transaction. the bg signal should be qualified by the master requesting the bus in order to ensure it is the bus owner: qualified bus grant = bg & ~ bb i when the internal arbiter is disabled, bg is sampled and properly qualified by the mpc561/mpc563 when an external bus transaction is to be executed by the chip. bb bus busy 1low o when the internal arbiter is enabled, the mpc561/mpc563 asserts this signal to indicate that it is the current owner of the bus. when the internal arbiter is disabled, the mpc561/mpc563 asserts this signal after the external arbiter has granted the ownership of the bus to the chip and it is ready to start the transaction. i when the internal arbiter is enabled, the mpc561/mpc563 samples this signal to get indication of when the external master ended its bus tenure (bb negated). when the internal arbiter is disabled, the bb is sampled to properly qualify the bg line when an external bus transaction is to be executed by the chip. table 9-1. mpc561/mpc563 biu signals (continued) signal name pins active i/o description external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-8 freescale semiconductor 9.5 bus operations this section provides a functional desc ription of the system bus, the si gnals that control it, and the bus cycles provided for data transfer operations. it also describes the error conditions , bus arbitration, and reset operation. the mpc561/mpc563 generates a system clock output (clkout). this output sets the frequency of operation for the bus interface dir ectly. internally, the mpc561/mpc 563 uses a phase-lock loop (pll) circuit to generate a master clock for all of the mpc561/mpc563 circuitry (inc luding the bus interface) which is phase-locked to th e clkout output signal. all signals for the mpc561/mpc563 bus interface are sp ecified with respect to the rising edge of the external clkout and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. since the same clock edge is referenced for dr iving or sampling the bus si gnals, the possibility of clock skew could exist between vari ous modules in a system due to r outing or the use of multiple clock lines. it is the responsibility of the system to handle any such clock skew problems that could occur. 9.5.1 basic transfer protocol the basic transfer protocol defi nes the sequence of actions that must occur on the mpc561/mpc563 bus to perform a complete bus transaction. a simplified scheme of the basic tr ansfer protocol is illustrated in figure 9-3 . figure 9-3. basic transfer protocol the basic transfer protocol provides for an arbitration phase and an a ddress and data transfer phase. the address phase specifies the address for the transacti on and the transfer attributes that describe the transaction. the data phase performs th e transfer of data (if any is to be transf erred). the data phase may transfer a single beat of da ta (four bytes or le ss) for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes). retry retry 1low i in the case of regular transaction, this signal is driven by the slave device to indicate that the mpc561/mpc563 must relinquish the ownership of the bus and retry the cycle. o when an external master owns the bus and the internal mpc561/mpc563 bus initiates access to the external bus at the same time, this signal is used to cause the external master to relinquish the bus for one clock to solve the contention. table 9-1. mpc561/mpc563 biu signals (continued) signal name pins active i/o description arbitration address transfer data transfer termination external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-9 9.5.2 single beat transfer during the data transfer phase, the da ta is transferred from master to sl ave (in write cycles) or from slave to master (on read cycles). during a write cycle, the mast er drives the data as soon as it can, bu t never earlier than the cycle following the address transfer phase. the master has to take into consideration th e ?one dead clock cycle? switching between drivers to avoid electrical contentions. the master can stop driving the data bus as soon as it samples the ta line asserted on the rising edge of the clkout. during a read cycle, the master accepts the data bus contents as valid at the rising edge of the clkout in which the ta signal is sampled/asserted. 9.5.2.1 single beat read flow the basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer. the handshakes illustrated in the fo llowing flow and timing figures ( figure 9-4 , figure 9-5 , and figure 9-6 ) are applicable to the fi xed transaction protocol. figure 9-4. basic flow diagram of a single beat read cycle 3. assert bus busy ( bb ) if no other master is driving bus 4. assert transfer start ( ts ) 5. drive address and attributes 1. receive address 2. return data 3. assert transfer acknowledge ( ta ) slave master 2. receive bus grant ( bg ) from arbiter 1. request bus ( br ) external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-10 freescale semiconductor figure 9-5. single beat read cycle ? basic timing ? zero wait states clkout addr[8:31] ts br bg bb data ta rd/ wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst , bdip tsiz[0:1] o o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-11 figure 9-6. single beat read cycle ? basic timing ? one wait state 9.5.2.2 single beat write flow the basic write cycle begins with a bus arbitration, foll owed by the address transfer , then the data transfer. the handshakes are illustrated in th e following flow and timing diagra ms as applicable to the fixed transaction protocol. clkout addr[8:31] ts br bg bb data ta rd/ wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst , bdip tsiz[0:1] wait state o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-12 freescale semiconductor figure 9-7. basic flow diagram of a single beat write cycle master slave 1. request bus ( br ) 2. receive bus grant ( bg ) from arbiter 3. assert bus busy ( bb ) if no other master is driving bus 4. assert transfer start ( ts ) 5. drive address and attributes 1. drive data 1. assert transfer acknowledge ( ta ) 1. interrupt data driving external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-13 figure 9-8. single beat basic write cycle timing ? zero wait states clkout addr[8:31] ts br bg bb data ta rd/ wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled by slave burst , bdip tsiz[0:1] o o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-14 freescale semiconductor figure 9-9. single beat basic write cycle timing ? one wait state 9.5.2.3 single beat flow with small port size the general case of single beat tr ansfers assumes that the external memory has a 32-bit port size. the mpc561/mpc563 provides an effective mechanism fo r interfacing with 16-bit and 8-bit port size memories, allowing transfers to thes e devices when they are controlled by the internal memory controller. in this case, the mpc561/mpc563 attemp ts to initiate a transfer as in the normal case. if the bus interface receives a small port size ( 16 or 8 bits) indication before the transf er acknowledge to the first beat (through the internal memory controller), the mcu initiates su ccessive transactions until th e completion of the data transfer. note that all the transactions initiated to complete the data transf er are considered to be part of an atomic transaction, so the mcu does not allow other unrelated master accesses or bus arbitration to intervene between the transfers. if a ny of the transactions except the firs t is re-tried during an access to a small port, then a machine-check ex ception is generated to the rcpu. clkout addr[8:31] ts br bg bb data ta rd/ wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst , bdip tsiz[0:1] wait state o o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-15 1. for an illustration of device connections on the data bus, see figure 9-23 . figure 9-10. single beat 32-bit data write cycle timing ? 16-bit port size 9.5.3 data bus pre-discharge mode pre-discharge mode is provided fo r applications that use 3.3-v/5- v external memories while the mpc561/mpc563 data bus pads are op timized to 2.6-v memories, and ca nnot tolerate more than 3.1 v. when connecting 3.3-v devices to the e-bus, and perf orming read and write operations, this mode should be invoked in order to avoid long term reliability issues of the data pads. when the pdmcr2[predis_en] bit is set, the mpc561/mpc563 will discharge the bus during the address phase of any write cycle prio r to the data phase. the data bus will be discha rged from up to 5 v to a level which is suitable to the low voltage drivers. in most cases, the orx[ehtr] bit of the relevant memory bank, should be set along with the predis_en bi t in order to reserve sufficient time for the clkout addr[0:1] ts br bg bb data 1 ta rd/ wr burst , bdip tsiz[0:1] 00 10 addr addr + 2 abcdefgh efghefgh sts external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-16 freescale semiconductor memory to three-state the bus before the bus disc harge is initiated. ehtr has a slight performance reduction impact since it adds a clock ga p between some read and write cycles. note ehtr also adds one idle clock for two consecutive read cycles from different memory banks. note the pre-disharge will not occur, when using multiple processors with a common bus accessing an external device , if the processor that initiates a read is different from the processor that initiated th e previous write. perform a write to the external device to discha rge the external bus, or read a value of 0x0 from the external device, pr ior to accessing another mcu on the same bus. 9.5.3.1 operating conditions pre-discharge mode should be enabled in the following cases: ? when external devices can charge the data bus to a higher voltage level than 3.1 volts ? and when one or more of the following occurs: ? the mpc561/mpc563 uses write acc esses to any external memory ? data show cycles are enabled ? instruction show cycles are enabled in code compression mode (mpc562/mpc564 only) note in the case of code compression pr ogram tracking (3rd case above), the predis_en bit should only be set when program tracking is not required since pre-discharge mode overwrites the compression show cycles data. the user should not set predis_en bit when program tracking is required on development system, and set predis _en bit on the production version. ehtr can always be set to keep the same system performance during development, and production phases. 9.5.3.2 initialization sequence systems that require pre-discharge opera tion should include the following steps: ? execute boot sequence ? set ehtr bit in all relevant memory banks dur ing the memory controller initialization phase (configure orx, and brx) if it is required to extend the time between read cycles, and pre-discharge phase of write cycles. ? set predis_en in pdmcr2 register ? start to write data to external devices external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-17 refer to section 2.4, ?pad module configuration register (pdmcr2) ,? and section 10.9.4, ?memory controller option registers (or0?or3) ,? for more information on predis_en, and ehtr configuration bits. figure 9-11. read followed by write when pre-discharge mode is enabled, and ehtr is set 9.5.4 burst transfer the mpc561/mpc563 uses non-wrapping burst transfer s to access operands of up to 32 bytes (eight words). a non-wrapping burst access st ops accessing the external device when the word address is modulo four/eight. burst configuration is determined by the value of burs t_en in the siumcr register. see chapter 5, ?unified system in terface unit (usiu) overview ? for further details. the mpc561/mpc563 begins the access by supplying a star ting address that points to one of the words in the array and requires the memory to sequentially drive or sample each word on the data bus. the selected slave device must internally increment addr28 and addr29 (and addr30 in the case of a 16-bit port slave device, and also addr31 in the case of an 8- bit port slave device) of the supplie d address for each transfer, causing the address to reach a four/eight word boundary, and then stop. the addre ss and transfer at tributes supplied by the mpc561/mpc563 remain stable during the transfer s. the selected device terminates each transfer by driving or sampling the word on the data bus and asserting ta . clkout data ta rd/ wr pre-discharge addr[8:31] ts read cycle write cycle write data oe read data ehtr provides 1 clock gap to three-state data bus to low voltage external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-18 freescale semiconductor the mpc561/mpc563 also supports burst-inhibited transf ers for slave devices th at are unable to support bursting. for this type of bus cycl e, the selected slave device suppl ies or samples the first word the mpc561/mpc563 points to and assert s the burst-inhibit signal with ta for the first transfer of the burst access. the mpc561/mpc563 responds by terminating the burst and accessing the remainder of the 16-byte block. these remaining accesses use up to three read/write bus cycl es (each one for a word) in the case of a 32-bit port width sl ave, up to seven read/write bus cycles in the case of a 16-bi t port width slave, or up to fifteen read/write bus cycles in the case of a 8-bit port width slave. the general case of burst transfers assumes that the external memory has a 32-bit port size. the mpc561/mpc563 provides an effective mechanism fo r interfacing with 16-bit and 8-bit port size memories, allowing bursts transfers to these devices when they are controlled by the internal memory controller. in this case, the mpc561/mpc563 attemp ts to initiate a burst transfer as in the normal case. if the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words. eight words requires 32 or 16 beats. each beat of the burst tr ansfers only one or two bytes effectively. note that this burst of 8 or 16 beats is considered an atom ic transaction, so the mp c561/mpc563 does not allow other unrelated master accesses or bus arbitr ation to intervene between the transfers. 9.5.5 burst mechanism in addition to the standard bus signals, the mpc561/mpc563 burst mech anism uses the following signals: ? the burst signal indicates that the cycle is a burst cycle. ? the burst data in progress (bdip ) signal indicates the duration of the burst data. ? the burst inhibit (bi ) signal indicates whether the slave is burstable. at the start of the burst transfer, the master drives the address, the address attributes, and the burst signal to indicate that a burst transfer is being initiated, and asserts ts . if the slave is burstable, it negates the burst-inhibit (bi ) signal. if the slave cannot burst, it asserts bi . for additional details, refer to section 10.2.5, ?burst support .? during the data phase of a burst- write cycle, the master drives the data. it also asserts bdip if it intends to drive the data beat following the current data beat. when the slave has received the data, it asserts ta to indicate to the master that it is r eady for the next data transfer. the ma ster again drives the next data and asserts or negates the bdip signal. if the master does not intend to drive another data beat following the current one, it negates bdip to indicate to the slave that the next da ta beat transfer is the last data of the burst-write transfer. bdip has two basic timings: normal and late (see figure 9-14 and figure 9-15 ). in the late timing mode, assertion of bdip is delayed by the number of wait states in the first data beat. this implies that for zero-wait-state cycles, bdip assertion time is identical in normal and late modes. cycles with late bdip generation can occur only during cycles for which the memory controller generates ta internally. refer to chapter 10, ?memory controller ? for more information. external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-19 in the mpc561/mpc563, no internal master initiate s write bursts. the mpc 561/mpc563 is designed to perform this kind of transaction in order to support an external master that is us ing the memory controller services. refer to section 10.8, ?memory controller external master support .? during the data phase of a burst-read cy cle, the master receives data from the addressed slave. if the master needs more than one data beat, it asserts bdip . upon receiving the second-to-l ast data beat, the master negates bdip . the slave stops driving new data afte r it receives the negation of the bdip signal at the rising edge of the clock. burst inputs (reads) in the mpc561/mp c563 are used only for instruction cy cles. data load cycles are not supported. figures 9-12 through 9-21 are examples of various burst cycles, including illustra tions of burst-read and burst-write cycles for both the 16- and 32-bit port sizes. external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-20 freescale semiconductor master slave 1. request bus ( br ) 2. receive bus grant ( bg ) from arbiter 3. assert bus busy ( bb ) if no other master is driving 4. assert transfer start ( ts ) 5. drive address and attributes receive address return data assert transfer acknowledge ( ta ) receive data 6. drive burst asserted assert bdip bdip asserted yes return data assert transfer acknowledge ( ta ) receive data bdip asserted yes return data assert transfer acknowledge ( ta ) receive data bdip asserted yes return data assert transfer acknowledge ( ta ) receive data bdip asserted yes negate burst data in progress ( bdip ) no drive last data & assert ta no drive last data & assert ta no drive last data & assert ta no drive last data & assert ta addr[28:29] mod 4 =? assert bdip assert bdip = 2 = 1 = 3 = 0 = 4 external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-21 figure 9-12. basic flow diag ram of a burst-read cycle figure 9-13. burst-read cycle ? 32-bit port size ? zero wait state clkout addr[8:31] ts br bg bb data ta rd/ wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 addr[28:31] = 0000 o o o o o o oo no data expected external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-22 freescale semiconductor figure 9-14. burst-read cycle ? 32-bit port size ? one wait state clkout addr[8:31] ts br bg bb data ta rd/ wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state addr[28:31] = 0000 normal late o o o o o o o o no data expected external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-23 figure 9-15. burst-read cycle ? 32-bit port size ? wait states between beats clkout addr[8:31] ts br bg bb data ta rd/ wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state addr[28:31] = 0000 normal or late o o o o o o o o no data expected external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-24 freescale semiconductor figure 9-16. burst-read cycle ? 16-bit port size clkout addr[8:31] ts br bg bb data[0:15] ta rd/wr burst tsiz[0:1] bdip 00 addr[28:31] = 0000 external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-25 external master slave 1. request bus ( br ) 2. receive bus grant ( bg ) from arbiter 3. assert bus busy ( bb ) if no other master is driving 4. assert transfer start ( ts ) 5. drive address and attributes receive address sample data assert transfer acknowledge ( ta ) drive data 6. drive burst asserted assert bdip bdip asserted yes sample data assert transfer acknowledge ( ta ) drive data bdip asserted yes sample data assert transfer acknowledge ( ta ) drive data bdip asserted yes sample data assert transfer acknowledge ( ta ) stop driving data bdip asserted yes negate burst data in progress ( bdip ) no don?t sample next data no don?t sample next data no don?t sample next data no don?t sample next data addr[28:29] mod 4 =? assert bdip assert bdip = 2 = 1 = 3 = 0 drive data 7. mts asserted (from mpc500 device) external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-26 freescale semiconductor figure 9-17. basic flow diagram of a burst-write cycle 1 from external master figure 9-18. burst-write cycle, 32-bit port size, zero wait states (only for external master memory controller service support) addr[8:31] mts br 1 bg 1 bb 1 rd/ wr 1 burst 1 tsiz[0:1] bdip 1 data data data data is sampled is sampled is sampled is sampled last beat will drive another data addr[28:29] = 00 o o o o o o o o clkout data ta 00 ts 1 no data expected external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-27 1 burst and bdip will be asserted for one cycle if the rcpu core requests a burst, but the usiu splits it in to a sequence of normal cycles. figure 9-19. burst-inhibit read cycle, 32-bit port size (emulated burst) clkout addr[0:27] ts br bg bb data ta rd/ wr burst 1 tsiz[0:1] bdip 1 00 bi addr[28:29] addr[30:31] 0 12 3 external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-28 freescale semiconductor figure 9-20. non-wrap burst with three beats clkout addr(0:29) ts br bg bb data ta rd/ wr burst tsiz[0:1] bdip 00 bi addr[30:31] n (n modulo 4 = 1) expects another data o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-29 figure 9-21. non-wrap burst with one data beat 9.5.6 alignment and packaging of transfers the mpc561/mpc563 external bus re quires natural address alignment: ? byte accesses allow any address alignment ? half-word accesses require a ddress bit 31 to equal zero clkout addr[0:29] ts br bg bb data ta rd/ wr burst tsiz[0:1] bdip data is sampled first and last beat 00 addr[30:31] 00 n (n modulo 4 = 3) is never asserted o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-30 freescale semiconductor ? word accesses require addre ss bits 30 ? 31 to equal zero ? burst accesses require addre ss bits 30 ? 31 to equal zero the mpc561/mpc563 performs operand tran sfers through its 32-bit data port. if the transfer is controlled by the internal memory controller, the mpc561/mp c563 can support 8- and 16- bit data port sizes. the bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 32-bit port resides on data[0:31], a 16-bit port must reside on data[0:15], and an 8-bit port must reside on data[0:7]. the mpc561/mpc563 always trie s to transfer the maximum amount of data on all bus cycles. for a word operation, it always assumes th at the port is 32 bits wide when beginning the bus cycle. in figure 9-22 , figure 9-23 , table 9-2 , and table 9-3 , the following conventions are used: ? op0 is the most-significant byte of a word operand and op3 is the least-significant byte. ? the two bytes of a half-wor d operand are either op0 (most- significant) and op1 or op2 (most-significant) and op3, depe nding on the address of the access. ? the single byte of a byte-le ngth operand is op0, op1, op2, or op3, depending on the address of the access. figure 9-22. internal operand representation op0 op1 op2 031 word half-word byte op0 op1 op2 op3 op0 op1 op2 op3 op3 external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-31 figure 9-23 illustrates the device c onnections on the data bus. figure 9-23. interface to different port size devices table 9-2 lists the bytes required on the data bus for read cycles. note: ??? denotes a byte not requir ed during that read cycle. table 9-2. data bus requirements for read cycles transfer size tsize [0:1] address 32-bit port size 16-bit port size 8-bit port size addr [30:31] data [0:7] data [8:15] data [16:23] data [24:31] data [0:7] data [8:15] data [0:7] byte 01 00 op0 ? ? ? op0 ? op0 01 01 ? op1 ? ? ? op1 op1 01 10 ? ? op2 ? op2 ? op2 01 11 ? ? ? op3 ? op3 op3 half-word 10 00 op0 op1 ? ? op0 op1 op0 10 10 ? ? op2 op3 op2 op3 op2 word 00 00 op0 op1 op2 op3 op0 op1 op0 031 32-bit port size op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 16-bit port size 8-bit port size data[0:7] data[8:15] data[16:23] data[24:31] interface output register external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-32 freescale semiconductor table 9-3 lists the patterns of the data transfer for write cycles when the mpc561/mpc563 initiates an access. note: ??? denotes a byte not driv en during that write cycle. 9.5.7 arbitration phase the external bus design provides fo r a single bus master at any one time, either the mpc561/mpc563 or an external device. one or more of the external devices on the bus can have the capability of becoming bus master for the external bus. bus arbitration may be ha ndled either by an external central bus arbiter or by the internal on-chip arbiter. in the latter case, the system is optimized for one external bus master besides the mpc561/mpc563. the arbitration configuration (e xternal or internal) is set at system reset. each bus master must have bus request (br ), bus grant (bg ), and bus busy (bb ) signals. the device that needs the bus asserts br . the device then waits for the arbiter to assert bg . in addition, the new master must look at bb to ensure that no other master is dr iving the bus before it can assert bb to assume ownership of the bus. any time the arbiter has taken the bus grant away from the master and the master wants to execute a new cycle, the master must re -arbitrate before a new cycle can be executed. the mpc561/mpc563, however, guarantees da ta coherency for access to a smal l port size and for decomposed bursts. this means that the mpc 561/mpc563 will not release the bus before the completion of the transactions that are considered atomic. figure 9-24 describes the basic protocol for bus arbitration. table 9-3. data bus contents for write cycles transfer size tsize[0:1] address external data bus pattern addr [30:31] data [0:7] data [8:15] data [16:23] data [24:31] byte 01 00 op0 ? ? ? 01 01 op1 op1 ? ? 01 10 op2 ? op2 ? 01 11 op3 op3 ? op3 half-word 10 00 op0 op1 ? ? 10 10 op2 op3 op2 op3 word 00 00 op0 op1 op2 op3 external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-33 figure 9-24. bus arbi tration flowchart 9.5.7.1 bus request the potential bus master asserts br to request bus mastership. br should be negated as soon as the bus is granted, the bus is not busy, and the new master can drive the bus. if more requests are pending, the master can keep asserting its bus request as long as needed. when configured fo r external central arbitration, the mpc561/mpc563 drives this signal wh en it requires bus mastership. when the internal on-chip arbiter is used, this signal is an input to the internal arbiter and should be driven by the external bus master. 9.5.7.2 bus grant the arbiter asserts bg to indicate that the bus is granted to the requesting device. this signal can be negated following the negation of br or kept asserted for the current master to park the bus. when configured for external central arbitration, bg is an input signal to the mpc561/mpc563 from the external arbiter. when the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master. requesting device arbiter request the bus 1. assert br terminate arbitration 1. negate bg (or keep asserted to park 1. wait for bb to be negated. 3. negate br bus master operate as bus master 1. perform data transfer release bus mastership 1. negate bb acknowledge bus mastership 2. assert bb to become next master grant bus arbitration 1. assert bg external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-34 freescale semiconductor 9.5.7.3 bus busy bb assertion indicates that the curren t bus master is using the bus. ne w masters should not begin transfer until this signal is negated. the bus owner should not relinquish or negate this signal until the transfer is complete. to avoid contention on the bb line, the master should three-state this signal when it gets a logical one value. this requires the connection of an ex ternal pull-up resistor to ensure that a master that acquires the bus is able to recognize the bb line negated, regard less of how many cycles have passed since the previous master relinquished the bus. refer to figure 9-25 . figure 9-25. master signals basic connection external bus slave 2 master ts bb mpc500 device (slave 1) external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-35 figure 9-26. bus arbitration timing diagram 9.5.7.4 internal bus arbiter the mpc561/mpc563 can be configured at system reset to use the internal bus arbiter. in this case, the mpc561/mpc563 will be parked on the bus. the parking feature allows the mpc561/mpc563 to skip the bus request phase, and if bb is negated, assert bb and initiate the transact ion without waiting for bg from the arbiter. the priority of the external device relative to the internal mpc561/mpc563 bus masters is programmed in the siu module configuration re gister. if the external device re quests the bus and the mpc561/mpc563 does not require it, or if the extern al device has higher priority than the current internal bus master, the mpc561/mpc563 grants the bus to the external device. table 9-4 describes the priority mechanis m used by the internal arbiter. clkout br0 bg1 addr[8:31] bg0 br1 master 0 ?turns on? and drives signals master 0 negates bb and ?turns off? (three-state controls) bb ts ta master 1 ?turns on? and drives signals and attributes external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-36 freescale semiconductor figure 9-27 illustrates the internal finite-state mach ine that implements the arbiter protocol. figure 9-27. internal bus arbitration state machine table 9-4. priority between internal and external masters over external bus 1 1 external master will be granted external bus ownership if earp is greater than the internal access priority. type direction priority parked access 2 2 parked access is instruction or data access from the rcpu which is initiated on the internal bus without requesting it first in order to improve performance. internal external 0 instruction access internal external 3 data access internal external 4 external access external external/internal earp (could be programmed to 0 ? 7) idle bg = 1 bb = three external bg = 0 external master br = 0 external master release bus bg = 1 bb = three bb = three bb = 0 bg = 1 bb = 0 bb = 1 b b = 1, b r =1 br = 0 requests bus br = 1 external device with higher priority than the current internal bus master re quests the bus internal master with higher priority than the external device requires the bus mcu needs no longer the bus needs the bus still needs the bus wait device owner owner bus mpc500 mpc500 device mpc500 device mpc500 device state state state mpc500 device external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-37 9.5.8 address transfer phase signals address transfer phase signa ls include the following: ? transfer start ? address bus ? transfer attributes transfer attributes signals include rd/wr , burst , tsiz[0:1], at[0:3], sts , and bdip . with the exception of the bdip , these signals are available at th e same time as the address bus. 9.5.8.1 transfer start this signal (ts ) indicates the beginning of a tr ansaction on the bus addressi ng a slave device. this signal should be asserted by a mast er only after the ownership of the bus was granted by the arbitration protocol. this signal is asserted for the first cycle of the tran saction only and is negated in successive clock cycles until the end of the transaction. the master should th ree-state this signal when it relinquishes the bus to avoid contention between two or more masters in this line. th is situation indicates th at an external pull-up resistor should be connected to the ts signal to avoid having a slave recogni ze this signal as asserted when no master drives it. refer to figure 9-25 . 9.5.8.2 address bus the address bus consists of 32 bits , with addr0 the most significant bit and addr 31 the least significant bit. only 24 bits (addr[8:31]) are availabl e external to the mpc561/mpc563. the bus is byte-addressable, so each a ddress can address one or more bytes. the address and its attr ibutes are driven on the bus with the transfer star t signal and kept valid until the bus master receives the transfer acknowledge signal from the slave. to distinguish the individual byte, th e slave device must observe the tsiz signals. 9.5.8.3 read/write a high value on the rd/wr line indicates a read access. a low value indicates a write access. 9.5.8.4 burst indicator burst is driven by the bus master at the beginning of the bus cycle along with the addr ess to indicate that the transfer is a burst transfer. the mpc561/mpc563 supports a non-wrapping, 8-beat ma ximum (with 32-bit port), critical word first burst type. the maximum burst size is 32 bytes. for a 16-bit port, the bur st includes 16 beat s. for an 8-bit port, the burst includes 32 beats at most. note 8- and 16-bit ports must be cont rolled by the memory controller. the actual size of the burst is determined by the a ddress of the starting word of the burst. refer to table 9-5 and table 9-6 . external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-38 freescale semiconductor 9.5.8.5 transfer size the transfer size signals (tsiz[0:1] ) indicate the size of the requested data transfer. during each transfer, the tsiz signals indicate how many bytes are remaining to be transf erred by the transaction. the tsiz signals can be used with burst and addr[30:31] to determine whic h byte lanes of the data bus are involved in the transfer. fo r non-burst transfers, the ts iz signals specify the numbe r of bytes starting from the byte location addressed by addr[30:31]. in burs t transfers, the value of tsiz is always 00. 9.5.8.6 address types the address type (at[0: 3]), program trace (ptr ), and reservation transfer (rsv ) signals are outputs that indicate one of 16 address types. these types are designated as eith er a normal or alternate master cycle, user or supervisor, and instruction or data type. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) signal is asserted. a special use of the ptr and rsv signals is for the reserva tion protocol described in section 9.5.10, ?storage reservation .? refer to section 9.5.14, ?show cycle transactions ? for information on show cycles. table 9-7 summarizes the pins used to define the address type. table 9-8 lists all the definitions achieved by combining these pins. table 9-5. 4 word burst length and order starting address addr[28:29] burst order (assuming 32-bit port size) burst length in words (beats) burst length in bytes comments 00 word 0 word 1 word 2 word 3 416 01 word 1 word 2 word 3 3 12 10 word 2 word 3 2 8 11 word 3 1 4 bdip never asserted table 9-6. burst /tsize encoding burst tsiz[0:1] transfer size negated 01 byte negated 10 half-word negated 11 x negated 00 word asserted 00 burst (16 or 32 bytes) external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-39 : table 9-7. address type pins pin function sts 0 special transfer 1 normal transfer ts 0 start of transfer 1 no transfer at0 must equal zero on mpc561/mpc563 at1 0 supervisor mode 1 user mode at2 0 instruction 1data at3 reservation/program trace ptr 0 program trace 1 no program trace rsv 0 reservation data 1 no reservation table 9-8. address types definition sts ts at0 at1 at2 at3 ptr rsv address space definitions 1xxxxx11no transfer 00 1 000001rcpu, normal instruction, program trace, supervisor mode 1 1 1 rcpu, normal instruction, supervisor mode 1 0 1 0 rcpu, reservation data, supervisor mode 1 1 1 rcpu, normal data, supervisor mode 1 0 0 0 1 rcpu, normal instruction, program trace, user mode 1 1 1 rcpu, normal instruction, user mode 1 0 1 0 rcpu, reservation data, user mode 1 1 1 rcpu, normal data, user mode 1???11reserved 1000001rcpu, show cycle address instruction, program trace, supervisor mode 1 1 1 rcpu, show cycle address instruction, supervisor mode 1 0 1 0 rcpu, reservation show cycle data, supervisor mode 1 1 1 rcpu, show cycle data, supervisor mode 1 0 0 0 1 rcpu, show cycle address inst ruction, program trace, user mode 1 1 1 rcpu, show cycle address instruction, user mode 1 0 1 0 rcpu, reservation show cycle data, user mode 1 1 1 rcpu, show cycle data, user mode 1???11reserved external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-40 freescale semiconductor 9.5.8.7 burst data in progress this signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. the master uses this signal to give the sl ave advance warning of the re maining data in the burst. bdip can also be used to terminate the burst cycle early. refer to section 9.5.4, ?burst transfer ? and section 9.5.5, ?burst mechanism ? for more information. refer to section 10.9.3, ?memory controller base registers (br0?br3) ? for memory controller bdip options. 9.5.9 termination signals the ebi uses three termination signals: ? transfer acknowledge (ta ) ? burst inhibit (bi ) ? transfer error acknowledge (tea ) 9.5.9.1 transfer acknowledge transfer acknowledge (ta ) indicates normal completion of the bus transfer. during a burst cycle, the slave asserts this signal with every da ta beat returned or accepted. 9.5.9.2 burst inhibit a slave sends the bi signal to the master to indicate that the addressed device does not have burst capability. if this signal is asserted, the master must transfer in multiple cycles and increment the address for the slave to complete the burst transfer. for a system that does not use the burst mode at all, this signal can be tied low permanently. refer to section 10.9.3, ?memory controller base registers (br0?br3) ? for bi options. 9.5.9.3 transfer error acknowledge the tea signal terminates a bus cycle unde r one or more bus error conditi ons. the current bus cycle must be aborted. this signal overrides a ny other cycle termination signals, such as transfer acknowledge. 9.5.9.4 termination signals protocol the transfer protocol was defined to avoid electric al contention on lines that can be driven by various sources. to this end, a slave must not drive signals associated with the data tr ansfer until the address phase is completed and it recognizes the address as its ow n. the slave must disconnect from signals immediately after it has acknowledged the cycle and no later than the termination of th e next address phase cycle. this means that the termination signals must be connected to power through a pull-up resistor to avoid the situation in which a master sample s an undefined value in any of thes e signals when no real slave is addressed. refer to figure 9-28 and figure 9-29 . 1 cases in which both ts and sts are asserted indicate normal cy cles with the show cycle attribute. external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-41 figure 9-28. termination signal s protocol basic connection figure 9-29. termination signal s protocol timing diagram external bus mcu slave 2 slave 1 acknowledge signals ta tea clkout addr[8:31] ts ta , bi , tea rd/ wr tsiz[0:1] slave 1 slave 2 slave 1 allowed to drive acknowledge signals slave 1 negates acknowledge signals and turns off slave 2 allowed to drive acknowledge signals slave 2 negates acknowledge signals and turns off data external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-42 freescale semiconductor 9.5.10 storage reservation reservation occurs when a master loads data from memory. the memory location must not be overwritten until the master finishes processi ng the data and writing the results back to the reserved location. the mpc561/mpc563 storage reservation protocol supports a multi-level bus structure. for each local bus, storage reservation is handled by the local reservation logic. the protocol tries to op timize reservation cancellation such that an mpc500 processo r is notified of storage reservation loss on a remote bus only when it has issued a condi tional storeword (stwcx) cycle to that address. that is, the reservat ion loss indication comes as part of the stwcx cycle. this method avoids the need to have very fast storag e reservation loss indication signals r outed from every remote bus to every mpc500 master. the storage reservation protocol makes the following assumptions: ? each processor has, at most, one reservation flag ? lwarx sets the reservation flag ? lwarx by the same processor clears the reservation flag related to a previ ous lwarx instruction and again sets the reservation flag ? stwcx by the same processor clears the reservation flag ? store by the same processor does not clear the reservation flag ? some other processor (or other mechanism) store to the same address as an existing reservation clears the reservation flag ? in case the storage reservation is lost, it is gua ranteed that stwcx will not modify the storage the reservation protocol for a single- level (local) bus is illustrated in figure 9-30 . the protocol assumes that an external logic on the bus carries out the following functions: ? snoops accesses to all local bus slaves ? holds one reservation for each local ma ster capable of storage reservations ? sets the reservation when that master issues a load and reserve request ? clears the reservation when some other master issues a store to the reservation address external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-43 figure 9-30. reservation on local bus the mpc561/mpc563 samples the cr line at the rising e dge of clkout. when th is signal is asserted, the reservation flag is reset (negated). the external bus interface (ebi) samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the rc pu stwcx instruction. if the reservat ion flag is set, the ebi begins with the bus cycle. if the reservation flag is reset, no bus cycle is initiat ed externally, and this situation is reported to the rcpu. the reservation protocol for a multi- level (local) bus is illustrated in figure 9-31 . the system describes the situation in which the reserved location is sited in the remote bus. s r reservation logic external bus interface lwarx q enable external stwcx access cr external bus bus addr[0:29] cr clkout at[0:3], rsv, r/w, ts mpc500 device master external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-44 freescale semiconductor figure 9-31. reservation on multi-level bus hierarchy in this case, the bus interface block implements a reservation flag for th e local bus master. the reservation flag is set by the bus interface when a load with re servation is issued by the local bus master and the reservation address is located on the remote bus. the fl ag is reset (negated) when an alternative master on the remote bus accesses the same location in a write cycle. if the mpc561/mpc563 begins a memory cycle to the previously reserved address (located in the remote bus) as a re sult of an stwcx instruction, the following two cases can occur: ? if the reservation flag is se t, the buses interface acknowle dges the cycle in a normal way ? if the reservation flag is reset, th e bus interface should assert the kr . however, the bus interface should not perform the remote bus write-access or abort it if the remote bus supports aborted cycles. in this case the failure of the stwcx instruction is reported to the rcpu. s r bus interface external bus interface q kr external bus (local bus) at[0:3], rsv, r/w , ts addr[0:29] remote bus a master in the remote bus write to the reserved location local master accesses with to remove bus address lwarx mpc500 device external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-45 9.5.11 bus exception control cycles the mpc561/mpc563 bus architect ure requires assertion of ta from an external devi ce to signal that the bus cycle is complete. ta is not asserted in the following cases: ? the external device does not respond ? various other applicati on-dependent errors occur external circuitry can provide tea when no device responds by asserting ta within an appropriate period of time after the mpc561/mp c563 initiates the bus cycle (it can be th e internal bus monitor). this allows the cycle to terminate and the proc essor to enter exception-processing for the error condition (each one of the internal masters causes an intern al interrupt under this situation). to properly control termination of a bus cycle for a bus error, tea must be asserted at the same time or before ta is asserted. tea should be negated before the second rising edge af ter it was sampled as asserted to avoid the detection of an error for the next initiated bus cycle. tea is an open drain pin that allows th e ?wired-or? of any different sources of error generation. 9.5.11.1 retrying a bus cycle when an external device asserts the retry signal during a bus cycle, the mpc561/mpc563 enters a sequence in which it termin ates the current transaction, relinquishe s the ownership of the bus, and retries the cycle using the same address, address attri butes, and data (in the ca se of a write cycle). figure 9-32 illustrates the behavior of the mpc561/mpc563 when the retry signal is detected as a termination of a transfer. as seen in this fi gure, in the case when the internal arbiter is enabled, the mpc561/mpc563 negates bb and asserts bg in the clock cycle following th e retry detection. this allows any external master to gain bus ow nership. in the next clock cycle, a normal arbitration procedure occurs again. as shown in the figure, the external master did not use the bus, so the mpc561/mpc563 initiates a new transfer with the same addr ess and attribut es as before. in figure 9-33 , the same situation is shown except that the mpc561/mpc 563 is working with an external arbiter. in this case, in th e clock cycle after the retry signal is detected asserted, br is negated together with bb . one clock cycle later, the normal arbitration procedure occurs again. external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-46 freescale semiconductor figure 9-32. retry transfer timing ? internal arbiter clkout addr[8:31] ts br bg (output) bb data ta rd/ wr burst tsiz[0:1] retry (input) addr addr allow external master to gain the bus o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-47 figure 9-33. retry transfer timing ? external arbiter when the mpc561/mpc563 initiates a burst ac cess, the bus interface recognizes the retry assertion as a retry termination only if it dete cts it before the first data beat was acknowledged by the slave device. when the retry signal is asserted as a ter mination signal on any data beat of the access after the first (being the first data beat acknowledged by a normal ta assertion), the mpc561/mpc563 recognizes retry as a transfer error acknowledge. clkout addr[8:31] ts br (output) bg bb data ta rd/ wr burst tsiz[0:1] retry (input) addr addr allow external master to gain the bus o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-48 freescale semiconductor figure 9-34. retry on burst cycle if a burst access is acknowledged on its first beat with a normal ta but with the bi signal asserted, the following single-beat transfers initiated by the mpc561/mpc563 to complete the 16-byte transfer recognizes the retry signal assertion as a transfer error acknowledge. in the case in which a small port size causes the mpc561/mpc563 to break a bus transaction into several small transactions, terminati ng any transaction with retry causes a transfer error acknowledge. see section 9.5.2.3, ?single beat flow with small port size .? clkout addr[8:31] ts br bg (output) bb data ta rd/ wr burst tsiz[0:1] retry addr addr allow external master to gain the bus bi if asserted will cause transfer error o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-49 9.5.11.2 termination sign als protocol summary table 9-9 summarizes how the mpc561/mp c563 recognizes the te rmination signals pr ovided by the slave device that is addressed by the initiated transfer. 9.5.12 bus operation in external master modes when an external master takes ownership of the external bus and the mpc561/mpc563 is programmed for external master mode operation, the external master can access the internal space of the mpc561/mpc563 (see section 6.1.2, ?external master modes ?). in external master mode, the external master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when the mpc561/mpc563 owns the bus. the external master gets owne rship of the bus and asserts ts in order to initiate an external master access. the access is directed to the internal bus only if the input address matc hes the internal address space. the access is terminated with one of the followings outputs: ta , tea , or retry . if the access completes successfully, the mpc561/mpc563 asserts ta , and the external master can proceed with another external master access or relinquish the bus. if an address or data error is det ected internally, the mpc561/mpc563 asserts tea for one clock. tea should be negated before the second ri sing edge after it is sampled asserted in order to avoid the detection of an er ror for the next bus cycle initiated. tea is an open drain pin, and the negation timing depends on the attached pull-up. the mpc5 61/mpc563 asserts the retry signal for one clock in order to retry the external master access. if the address of the external access does not match the internal memory space, the internal memory controller can provide the chip-select and control signa ls for accesses that belong to one of the memory controller regions. this feature is explained in chapter 10, ?memory controller .? figure 9-35 and figure 9-36 illustrate the basic flow of read and write external master accesses. table 9-9. termination signals protocol tea ta retry action asserted x x transfer error termination negated asserted x normal transfer termination negated negated asserted retry transfer termination external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-50 freescale semiconductor figure 9-35. basic flow of an external master read access external master 1. request bus ( br ) 2. receives bus grant ( bg ) from arbiter 3. asserts bus busy ( bb ) if no other master is driving 4. assert transfer start ( ts ) 1. receives address 1. returns data 1. asserts transfer acknowledge ( ta ) 1. receives data address in internal memory map no yes asserts csx if in range memory controller mpc500 device 5. drives address and attributes external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-51 figure 9-36. basic flow of an external master write access figure 9-37 , figure 9-38 , and figure 9-39 describe read and write cycl es from an external master accessing internal space in the mpc561/mpc563. note the minimum number of wait states fo r such access is two clocks. the accesses in these figures are valid for both periphera l mode and slave mode. external master 1. asserts transfer acknowledge (ta ) address in internal memory map no yes asserts csx if in range memory controller 1. drives data 1. receives address 1. receives data mpc500 device 1. request bus ( br ) 2. receives bus grant ( bg ) from arbiter 3. asserts bus busy ( bb ) if no other master is driving 4. assert transfer start ( ts ) 5. drives address and attributes external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-52 freescale semiconductor figure 9-37. peripheral mode: external master reads from mpc561/mpc563 (two wait states) clkout addr[8:31] ts (input) br (input) bg bb data ta (output) rd/ wr receive bus grant an d bus busy negated assert bb , drive address and assert ts data is valid burst tsiz[0:1] minimum 2 wait states bdip use the internal arbiter o o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-53 figure 9-38. peripheral mode: external master writes to mpc561/mpc563 (two wait states) 9.5.13 contention resolution on external bus when the mpc561/mpc563 is in slave mode, extern al master access to the mpc561/mpc563 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to- external access to be executed. the retry signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock. figure 9-39 describes the flow of an ex ternal master retried access. figure 9-40 shows the timing when an external access is retried and a pendi ng internal-to-external access follows. clkout addr[8:31] ts (input) br (input) bg bb data ta (output) rd/ wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst tsiz[0:1] minimum 2 wait states bdip use the internal arbiter o o o o o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-54 freescale semiconductor figure 9-39. flow of retry of external master read access external master 1. request bus ( br ) 2. receives bus grant ( bg ) from arbiter 3. asserts bus busy ( bb ) if no other master is driving 4. assert transfer start ( ts ) 5. drives address and attributes 1. receives address 1. returns data 1. asserts transfer acknowledge ( ta ) 1. receives data address in internal memory map no yes asserts csx if in range memory controller 1. assert retry 1. release bus request ( br ) for one clock and request bus ( br ) again 2. wait until bus busy negated (no other master is driving) 4. assert transfer start ( ts ) 5. drives address and attributes 3. assert bus busy ( bb ) mpc500 device external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-55 note: the delay for the internal to external cycle may be one clock or greater. figure 9-40. retry of external master access (internal arbiter) 9.5.14 show cycle transactions show cycles are representations of rcpu accesses to internal devices of the mpc561/mpc563. these accesses are driven externally fo r emulation, visibility, and debugging purposes. a show cycle can have one address phase and one data phase, or just an address phase in the ca se of instruction show cycles. the cycle can be a write or a read access. the data for both the read and write acces ses should be driven by the bus master. (this is different from normal bus read and write accesses.) the address and data of the show cycle must each be valid on the bus for one clock. the data phase must not require a transfer acknowledge to terminate the bus show cycle. clkout addr[8:31] ts br bg (output) bb data ta rd/ wr burst tsiz[0:1] retry (output) addr (external) addr (internal) allow internal access to gain the bus o external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-56 freescale semiconductor show cycles are activated by properly se tting the siumcr register bits. refer to section 6.2.2.1.1, ?siu module configuration register (siumcr) .? construction visibility is c ontrolled by the isct_ser bits in the ictrl register. refer to table 23-26 . data visibility is controlled by the lshow bits of the l2u_mcr register. refer to table 11-7 . in a burst show cycle only the first data beat is shown externally. refer to table 9-8 for show cycle transaction encodings. instruction show cycle bus transactions have the following characteristics (see figure 9-41 ): ? one clock cycle ? address phase only; in decompression on mode part of the compressed address is driven on data lines together with address lines. the external bus interface adds one cl ock delay between a read cycle and such show cycle. ?sts assertion only (no ta assertion) the compressed address is driven on the external bus in the following manner: ? addr[0:29] = the word base address; ? data[0] = operating mode: ? 0 = decompression off mode; ? 1 = decompression on mode; ? data[1:4] = bit pointer see chapter 4, ?burst buffer controller 2 module ? and appendix a, ?mpc562/mpc564 compression features ? for more details about decompression mode. external bus interface mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 9-57 i figure 9-41. instruction show cycle transaction both read and write data show cycles have the following characteristics: (see figure 9-42 ) ? two clock cycle duration ? address valid for two clock cycles ? data is valid only in the second clock cycle ?sts signal only is asserted (no ta or ts ) clkout addr[8:31] ptr bb (three-state) ta rd/ wr burst tsiz[0:1] addr1 addr2 sts ts ?normal? non-show cycle bus transaction instruction show cycle bus transaction ?compressed? address on data lines data external bus interface mpc561/mpc563 reference manual, rev. 1.2 9-58 freescale semiconductor figure 9-42. data show cycle transaction clkout addr[8:31] br (in) bg (out) bb data ta rd/ wr burst tsiz[0:1] addr1 addr2 sts ts data1 data2 read data show cycle bus transaction write data show cycle bus transaction mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-1 chapter 10 memory controller the memory controller generates interface signals to support a glueless interface to external memory and peripheral devices. it supports four regions, each with its own program med attributes. the four regions are controlled by four chip-sel ect signals. read and write strobes are also provided. the memory controller operates in parallel with the external bus interf ace to support external cycles. when an access to one of the memory regi ons is initiated, the memory controll er takes ownership of the external signals and controls the access until its termination. refer to figure 10-1 . figure 10-1. memory controller function within the usiu 10.1 overview the memory controller provides a glueless interf ace to external eprom, static ram (sram), flash (eeprom), and other peripherals. the general-pur pose chip-selects are available on lines cs0 through cs3 . cs0 also functions as the global (boot) chip-selec t for accessing the boot flash eeprom. the chip select allows zero to 30 wait states. figure 10-2 is a block diagram of the mp c561/mpc563 memory controller. internal bus ebi bus memory controller u-bus interface external bus interface memory controller addr[0:31] data[0:31] control bus we [0:3]/ be [0:3] oe cs [0:3] bus memory controller mpc561/mpc563 reference manual, rev. 1.2 10-2 freescale semiconductor figure 10-2. memory controller block diagram most memory controller features are common to all four banks. (for feat ures unique to the cs0 bank, refer to section 10.7, ?global (boot) chip-select operation.? ) a full 32-bit address decode for each memory bank is possible with 17 bits having address masking. th e full 32-bit decode is av ailable, even if all 32 address bits are not mpc561/mpc563 signal s connected to the external device. each memory bank includes a variable block size of 32 kbytes, 64 kbytes and up to four gbytes. each memory bank can be selected for re ad-only or read/write operation. the access to a memory bank can be restricted to certain addr ess type codes for system protection. the address type comparison occurs with a mask option as well. from 0 to 30 wait states can be programmed with ta generation. four write- enable and byte-enable signals (we /be [0:3]) are available for each byte that is written to memory. an output enable (oe ) signal is provided to eliminate external glue logic. a memory transfer start (mts ) strobe permits one master on a bus to access external memory through the chip selects on another. the memory controller functionality allows mpc561/mpc563-based systems to be built with little or no glue logic. a minima l system using no glue logic is shown in figure 10-3 . in this example cs 0 is used for internal addresses [0:16], at[0:2] attributes wait state counter expired load cs [0:3] we /be [0:3] oe base register option register dual mapping base register (dmbr) dual mapping option register (dmor) base register 3 (br3) option register 3 (or3) 0 (or0) 1 (or1) 2 (or2) 0 (br0) 1 (br1) 2 (br2) region match logic general-purpose chip-select machine (gpcm) memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-3 a 16-bit boot eprom and cs1 is used for a 32-bit sram. the we /be [0:3] signals are used both to program the eprom and to enable writ e access to various bytes in the ram. figure 10-3. mpc561/mpc563 simple system configuration 10.2 memory controller architecture the memory controller consists of a basic machine that handles the memory access cycle: the general-purpose chip-select machine (gpcm). when any of the internal masters request a new access to external memory, the address of the transfer (with 17 bits having a mask) and the addres s type (with three bits having a ma sk) are compared to each one of the valid banks defined in the memory controller. refer to figure 10-4 . eprom address data[0:15] sram address ce we /be [0:3] data cs1 oe address data cs0 we /be [0:3] ce oe oe [0:15] [0:31] we /be [0:1] mpc500 memory controller mpc561/mpc563 reference manual, rev. 1.2 10-4 freescale semiconductor figure 10-4. bank base address and match structure when a match is found on one of the memory banks, its attributes are se lected for the functional operation of the external memory access: ? read-only or read /write operations ? number of wait states for a single memory access, and for any beat in a burst access ? burst-inhibit indication. internal burst requests are still possible during burst-inhibited cycles; the memory controller emulates the burst cycles ? port size of the external device note that if more than one region matches the inte rnal address supplied, then the lowest numbered region is selected to provide the attribut es and the chip select. if the dual mapping region is ma tched, it has the highest priority (refer to section 10.5, ?dual mapping of the internal flash eeprom array ?). 10.2.1 associated registers status bits for each memory bank are found in the me mory control status register (mstat). the mstat reports write-protect viol ations for all the banks. each of the four memory banks has a base regi ster (br) and an opti on register (or). the br x and or x registers contain the attri butes specific to memory bank x. the base register contains a valid bit (v) that indicates the register information for th at particular chip select is valid. 10.2.2 port size configuration the memory controller supports dynamic bus sizing. de fined 8-bit ports can be accessed as odd or even bytes. defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even bytes, or even half-words. define d 32-bit ports can be acc essed as odd bytes, even bytes, odd half-words, even half-words, or words on word boundaries. the port size is specified by the ps bits in the base register. m0 m1 m2 m3 m4 m5 rba2 cmp cmp cmp cmp cmp cmp cmp cmp cmp cmp m[0:16] a[0:16] base address address mask match . . . . . . . . . . . . . m16 . . . . cmp rba15 rba3 rba4 rba1 rba0 m6 m7 memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-5 10.2.3 write-protect configuration the wp bit in each base register ca n restrict write access to its range of addresses. any attempt to write this area results in the associated wper bit being set in the mstat. if an attempt to access an extern al device results in a write-protect violation, the memory controller considers the access to be no match. no chip-select line is asserted externally, and the memory controller does not terminate the cycle. the external bus interf ace generates a normal cycle on the external bus. since the memory controller does not acknowledge the cycle in ternally, the cycle may be terminated by external logic asserting ta or by the on-chip bus monitor asserting tea . 10.2.4 address and address space checking the base address is written to the brx. the address ma sk bits for the address are written to the or. the address type access value, if desired, is written to the at bits in the br x . the atm bits in the orx can be used to mask this value. if a ddress type checking is not desire d, program the atm bits to zero. each time an external bus cycle access is requested, the address and a ddress type are compared with each one of the banks. if a match is found, the a ttributes defined for this bank in its br x and or x are used to control the memory access. if a match is found in mo re than one bank, the lowest bank matched handles the memory access (e.g., bank zero is selected over bank one). note when an external master accesses a slave on the bus, the internal at[0:2] lines reaching the memory controller are forced to 100. 10.2.5 burst support the memory controller supports burst accesses of exte rnal burstable memory. to enable bursts, clear the burst inhibit (bi) bit in the appropriate base register. burst support is for read only. bursts can be four or eight beat s depending on the value of the burs t_en bit in the siumcr register and the bl bit in the brx register. th at is, the memory controller execut es up to eight one-word accesses, but when a modulo eight limit is reached, the burst is te rminated (even if fewer th an eight words have been accessed). when the siu initiates a bur st access, if no match is found in any of the memory controller?s regions then a burst access is initiated to the external bus. the term ination of each beat for this access is externally controlled. to support different types of memory devices, the memory controller su pports two types of timing for the bdip signal: normal and late. note the bdip signal itself is controlled by the external bus interface logic. refer to figure 9-13 and figure 9-14 in chapter 9, ?external bus interface ." if the memory controller is used to support an external master accessing an external device with bursts, the bdip input signal is used to indicate to the me mory controller when the burst is terminated. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-6 freescale semiconductor for addition details, refer to section 9.5.4, ?burst transfer ." 10.2.6 reduced data setup time in order to meet timing requirements when interfaci ng to external memories, th e data setup time can be reduced. this mode can be selected by programming the br x registers. thus there is flexibility in how each region can be config ured to operate. the opera tion mode will be determ ined dynamically according to a particular access type. this m eans that for a memory region with th e reduced setup time mode enabled, the mode will automatically switch to disabled when there is no requirement for the reduced setup time, (e.g., a back-to-back load/store access). for a new access with burst length more than 1, the operation mode will be automatically switched back to the reduced setup time mode. reduced setup time can be sele cted via the sst bit in br[0 : 3]. see section 10.9.3, ?memory controller base registers (br0?br3) ? for more details. if sccr[ebdf] is gr eater than 0, however, an external burst access with reduced data setup time will co rrupt a load/store to any usiu register. the reduced setup time mode may or may not have a performance impa ct, depending on the properties of the memory. namely, there is always an additional em pty cycle between two burst sequences. on the other hand, this additional cycle, under certain conditions, may be comp ensated for by reducing the number of cycles in initial data access and sequential burst beats. 10.2.6.1 case 1: normal setup time initial access: to derive the number of clocks required, divide by the system clock cycle time: therefore 4 cycles are required burst access: the number of clocks required th erefore 2 clocks are required. this case is illustrated in figure 10-5 . table 10-1. timing requirements for reduced setup time cpu specification memory device requirements cycle time at 56 mhz = 17.9 ns initial access time = 49 ns short setup time = 3 ns burst access time = 13 ns normal setup time = 6 ns additional delay arising from on-board wires and clock skew between internal clock and clkout initial access time of memory data setup time of cpu delays + + 496156ns = ++ = 56 17.9 ---------- 3.13 = burst access time of memory data setup time of cpu delays 13 6 1 20ns = ++ = ++ 20 17.9 ---------- =1.11 = memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-7 10.2.6.2 case 2: short setup time initial access: enabling short setup time requires one clock cycle: the number of clocks require d therefore 4 clocks are required. initial access time of memory data setup time of cpu delays + + 493153ns = ++ = 53 17.9 ---------- 2 . 9 6 1 ( s s t e n a b l e c l o c k ) 3.96 = + = = memory controller mpc561/mpc563 reference manual, rev. 1.2 10-8 freescale semiconductor burst access: the number of clocks required therefore 1 clock is required. this case is illustrated in figure 10-6 . 10.2.6.3 summary of short setup time with normal setup time and a 4-beat burst, a 4-2-2-2 burst cycle is requi red which is reduced to a 4-1-1-1 burst cycle with a short setup time. short setup time creates a saving of three clock cycles with a 4-beat burst and can result in even better performance with an 8-beat burst, sa ving seven clock cycles. burst access time of memory data setup time of cpu delays + + 13 3 1 17ns = ++ = 17 17.9 ---------- = 0.95 = memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-9 figure 10-5. a 4-2-2-2 burst read cycle (one wait state between bursts) clkout addr[0:31] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 00 addr[28:31] = 0b0000 normal late last beat no data expected expects another data 123456 78910 1st data is valid 3rd data is valid 4th data is valid 2nd data is valid memory controller mpc561/mpc563 reference manual, rev. 1.2 10-10 freescale semiconductor figure 10-6. 4 beat burst read with short setup time (zero wait state) note an extra clock cycle is required to en able short set-up time, resulting in a 4-1-1-1 cycle. 10.3 chip-select timing the general-purpose chip-select mach ine (gpcm) allows a glueless and flexible interface between the mpc561/mpc563 and external sram, eprom, eep rom, rom peripherals. when an address and clkout addr ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 2nd data 3rd data 4th data is valid is valid is valid is valid last beat expects another data 00 addr[28:31] = 0000 no data expected 1234 567 1st data [0:31] memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-11 address type match the values progr ammed in the br and or for one of the memory controller banks, the attributes for the memory cycle ar e taken from the or and br regist ers. these attributes include the following fields: csnt, acs, scy, bscy, wp, trlx, bi, ps, and seta. table 10-2 summarizes the chip-select timing options. byte write and read -enable signals (we /be [0:3]) are available for each byte th at is written to or read from memory. an output enable (oe ) signal is provided to eliminate extern al glue logic for read cycles. upon system reset, a global (boot) chip select is available. (refer to section 10.7, ?global (boot) chip-select operation ? for more information on the gl obal chip select.) this provides a boot rom chip select before the system is fully configured. note when a bank is configured for ta to be generated externally (seta bit is set) and the trlx is set, the memory controller requires the external device to provide at least one wa it state before asserting ta to complete the transfer. in this case, the minimum transfer time is three clock cycles. the internal ta generation mode is enabled if the seta bit in the or register is cleared. however, if the ta signal is asserted externally at least two clock cycles be fore the wait states c ounter has expired, this assertion terminates the memory cycle. when seta is cleared, it is forbidden to assert external ta less than two clocks before the wait states counter expires. table 10-2. timing attributes summary timing attribute bits/fields description access speed trlx the trlx (timing relaxed) bit determines strobe timing to be fast or relaxed. intercycle space time ehtr the ehtr (extended hold time on read accesses) bit is provided for devices that have long disconnect times from the data bus on read accesses. ehtr specifies whether the next cycle is delayed one clock cycle following a read cycle, to av oid data bus c ontentions. ehtr applies to all cycles fo llowing a read cycle except for another read cycle to the same region. synchronous or asynchronous device acs, csnt the acs (address-to-chip-sele ct setup) and csnt (chip-select negation time) bits cause the timing of the strobes to be the same as the address bus timing, or cause the strobes to have setup and hold times relative to the address bus. wait states scy, bscy, seta, trlx from zero to 15 wait states can be programmed for any cycle that the memory controller generates. the transfer is then terminated internally. in simplest case, the cycle length equals (2 + scy) clock cycles, where scy represents the programmed number of wait states (cycle length in clocks). the number of wait states is doubled if the trlx bit is set (2 + (scy x 2)). when the seta (external transfer acknowledge) bit is set, ta must be generated externally, so that external hardware determines the number of wait states. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-12 freescale semiconductor 10.3.1 memory devices interface example figure 10-7 describes the basic connecti on between the mpc561/mpc563 and a static memory device. in this case cs x is connected directly to the chip enable (ce ) of the memory device. the we /be [0:3] lines are connected to the respective we in the memory device where each we /be line corresponds to a different data byte. figure 10-7. gpcm?memory devices interface in figure 10-8 , the csx timing is the same as that of the address lines output. the strobes for the transaction are supplied by the oe and the we /be lines (if programmed as we /be ). when the acs bits in the corresponding orx register = 00, cs is asserted at the same time that the address lines are valid. note if csnt is set, the we signal is negated a quarter of a clock earlier than normal. memory address ce oe we data address csx oe we /be data mpc5xx memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-13 note: in this and subsequent timing diagrams in this section, the data bus refers to a read cycle. in a write cycle, the data immediately follows ts . figure 10-8. memory devices interface basic timing (acs = 00, trlx = 0) 10.3.2 peripheral devices interface example figure 10-9 illustrates the basic connect ion between the mpc561/mpc563 and an external peripheral device. in this case csx is connected directly to the chip enable (ce ) of the memory de vice and the r/w line is connected to the r/w in the peripheral device. the csx line is the strobe output for the memory access. figure 10-9. peripheral devices interface clock address cs we /be oe data ts ta csnt = 1, acs = 00 peripheral address ce data address cs x rd/wr data mpc5xx rd/wr memory controller mpc561/mpc563 reference manual, rev. 1.2 10-14 freescale semiconductor the cs x timing is defined by the setup time requi red between the address lines and the ce line. the memory controller allows specification of the cs timing to meet th e setup time required by the peripheral device. this is accomplished through the acs field in the base register. in figure 10-10 , the acs bits are set to 0b11, so csx is asserted half a clock cycle after the address lines are valid. figure 10-10. peripheral devices basic timing (acs = 11, trlx = 0) 10.3.3 relaxed timing examples the trlx field is provided for memo ry systems that need a more re laxed timing between signals. when trlx is set and acs = 0b00, the memory controller inserts an additional cycle between address and strobes (cs line and we /oe ). when trlx and csnt are both set in a write to memory, the strobe lines (we /be [0:3] and cs , if acs = 0b00) are negated one clock earli er than in the regular case. note in the case of a bank selected to wo rk with external transfer acknowledge (seta = 1) and trlx = 1, the memory controller does not support external devices that provide ta to complete the transfer with zero wait states. the minimum access duration in this cas e equals three clock cycles. figure 10-11 shows a read access with rela xed timing. note the following: ? strobes (oe and cs ) assertion time is delayed one clock relative to addr ess (trlx bit set effect). ? strobe (cs ) is further delayed (half-clock) relative to address due to acs field being set to 11. clock address ts ta cs rd/wr data acs = 11 csnt = 1 memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-15 ? total cycle length = 5, is determined as follows: ? two clocks for basic cycle ? scy = 1 determines 1 wait state, which is mult iplied by two due to trlx being set (2 + (scy x 2)). ? extra clock is added due to trlx effect on the strobes. figure 10-11. relaxed timing ? read access (acs = 11, scy = 1, trlx = 1) figure 10-12 through figure 10-14 are examples of write acces ses using relaxed timing. in figure 10-12 , note the following points: ? because trlx is set, assertion of the cs and we strobes is delayed by one clock cycle. ?cs assertion is delayed an additional one quarter clock cycle because acs = 10. ? the total cycle length = three cloc k cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? an extra clock cycle is required due to the effect of trlx on the strobes. clock address ts ta cs rd/wr we /be data oe acs = ?11? & trlx = ?1? acs = ?00? & trlx = ?1? webs = ?1?,line acts as be in read. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-16 freescale semiconductor figure 10-12. relaxed timing ? write access (acs = 10, scy = 0, csnt = 0, trlx = 1) in figure 10-13 , note the following: ? because the trlx bit is se t, the assertion of the cs and we strobes is delayed by one clock cycle. ? because acs = 11, the assertion of cs is delayed an additional half clock cycle. ? because csnt = 1, we is negated one clock cycle ear lier than normal. (refer to figure 10-8 .) the total cycle length is four clock cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? two extra clock cycles are requi red due to the effect of trlx on the assertion and negation of the cs and we strobes. clock address ts ta cs rd/ wr we / be data oe acs = 10 acs = 00 memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-17 figure 10-13. relaxed timing ? write access (acs = 11, scy = 0, csnt = 1, trlx = 1) in figure 10-14 , notice the following: ? because acs = 0, trlx being set does not delay the assertion of the cs and we strobes. ? because csnt = 1, we /be is negated one clock cycle ear lier than normal. (refer to figure 10-8 ). ?cs is not negated one clock cycle earlier, since acs = 00. ? the total cycle length is three cl ock cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? one extra clock cycle is required due to th e effect of trlx on the negation of the we /be strobes. clock address ts ta cs rd/ wr we / be data oe acs =11 acs=00 & csnt = 1 csnt = 1 memory controller mpc561/mpc563 reference manual, rev. 1.2 10-18 freescale semiconductor figure 10-14. relaxed timing ? write access (acs = 00, scy = 0, csnt = 1, trlx = 1 10.3.4 extended hold time on read accesses for devices that require a long disc onnection time from the data bus on read accesses, the bit ehtr in the corresponding or register can be set. in this case any mpc561/mpc563 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank. figure 10-15 through figure 10-18 show the effect of the ehtr bit on memory controller timing. figure 10-15 shows a write access fo llowing a read access. because ehtr = 0, no extra clock cycle is inserted between memory cycles. clock address ts ta cs rd/ wr we / be data oe csnt = 1 no effect, acs = 00 memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-19 figure 10-15. consecutive accesses (write after read, ehtr = 0) figure 10-16 shows a write access foll owing a read access when ehtr = 1. an extra clock is inserted between the cycles. for a write cycle following a read, this is true regardless of whether both accesses are to the same region. clock address ts ta csx csy rd/ wr data oe tdt memory controller mpc561/mpc563 reference manual, rev. 1.2 10-20 freescale semiconductor figure 10-16. consecutive accesses (write after read, ehtr = 1) figure 10-17 shows consecutive accesses from different ba nks. because ehtr = 1 (and the accesses are to different banks), an extra clock cycle is inserted. clock address ts ta csx csy rd/ wr data oe tdt long tdt allowed extra clock before next cycle starts. memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-21 figure 10-17. consecutive accesses (read after read from different banks, ehtr = 1) figure 10-18 shows two consecutive read cycl es from the same bank. even though ehtr = 1, no extra clock cycle is inserted between th e memory cycles. (in the case of two consecutive read cycles to the same region, data contention is not a concern.) clock address ts ta csx csy rd/ wr data oe tdt long tdt allowed extra clock before next cycle starts memory controller mpc561/mpc563 reference manual, rev. 1.2 10-22 freescale semiconductor figure 10-18. consecutive accesses (read after read from same bank, ehtr = 1) 10.3.5 summary of gpcm timing options table 10-3 summarizes the different co mbinations of timing options. table 10-3. programming rules for timing strobes trlx access type acs csnt address to cs asserted cs negated to add/data invalid address to we /be or oe asserted we /be negated to add/data invalid oe negated to add/data invalid total number of cycles 0 read 00 x 0 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 read 10 x 1/4 * clock 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 read 11 x 1/2 * clock 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 write 00 0 0 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy 0 write 10 0 1/4 * clock 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy 0 write 11 0 1/2 * clock 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy 0 write 00 1 0 1/4 * clock 3/4 * clock 1/2 * clock x 2 + scy 0 write 10 1 1/4 * clock 1/2 * clock 3/4 * clock 1/2 * clock x 2 + scy clock address ts ta csx csy data oe tdt rd/wr memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-23 note: timing in this table refers to the typica l timing only. consult the electrical char acteristics for exact worst-case timing valu es. 1/4 clock actually means 0 to 1/4 cloc k, 1/2 clock means 1/4 to 1/2 clock. additional timing rules not covered in table 10-3 include the following: ? if seta = 1, an external ta signal is required to terminate the cycle. ? if trlx = 1 and seta = 1, the minimum cy cle length = 3 clock cycles (even if scy = 0000) ? if trlx = 1, the number of wait states = 2 ? scy & 2 ? bscy ? acs = 01 is not defined (reserved). ? if ehtr = 1, an extra (idle) cloc k cycle is inserted be tween a read cycle and a following read cycle to another region, or between a read cycl e and a following write cycle to any region. ? if lbdip = 1 (late bdip assertion), the bdip signal is asserted only afte r the number of wait states for the first beat in a burst have elapsed. see figure 9-13 in chapter 9, ?external bus interface ,? as well as section 9.5.5, ?burst mechanism .? note the lbdip/tbdip function can operate only when the cycle termination is internal, using the number of wait states programmed in one of the or x registers. the lbdip/tbdip function cannot be activated at the same time?results are unknown. 0 write 11 1 1/2 * clock 1/2 * clock 3/4 * clock 1/2 * clock x 2 + scy 1 read 00 x 0 1/4 * clock 3/4 clock x 1/4 * clock 2 + 2 * scy 1 read 10 x (1 + 1/4) * clock 1/4 * clock (1 + 3/4) * clock x1/4 * clock3 + 2 * scy 1 read 11 x (1 + 1/2) * clock 1/4 * clock (1 + 3/4) * clock x1/4 * clock3 + 2 * scy 1 write 00 0 0 1/4 * clock 3/4 clock 1/4 * clock x 2 + 2 * scy 1 write 10 0 (1 + 1/4) * clock 1/4 * clock (1 + 3/4) * clock 1/4 * clock x 3 + 2 * scy 1 write 11 0 (1 + 1/2) * clock 1/4 * clock (1 + 3/4) clock 1/4 * clock x 3 + 2 * scy 1 write 00 1 0 1/4 * clock 3/4 clock (1 + 1/2) * clock x3 + 2 * scy 1 write 10 1 (1 + 1/4) * clock (1 + 1/2) * clock (1 + 3/4) clock (1 + 1/2) * clock x4 + 2 * scy 1 write 11 1 (1 + 1/2) * clock (1 + 1/2) * clock (1 + 3/4) clock (1 + 1/2) * clock x4 + 2 * scy table 10-3. programming rules for timing strobes (continued) trlx access type acs csnt address to cs asserted cs negated to add/data invalid address to we /be or oe asserted we /be negated to add/data invalid oe negated to add/data invalid total number of cycles memory controller mpc561/mpc563 reference manual, rev. 1.2 10-24 freescale semiconductor 10.4 write and byte enable signals the gpcm determines the timing and value of the we /be signals if allowed by the port size of the accessed bank, the transfer size of th e transaction and the address accessed. the functionality of the we /be [0:3] signals depends upon the value of the write enable/byte select (webs) bit in the corresponding br register. setti ng webs to 1 will enable these signals as be , while clearing it to zero will enable them as we . we is asserted only duri ng write access, while be is asserted for both read and write acce sses. the timing of the we /be signals remains the same in either case, and is determined by the trlx, acs and csnt bits. the upper we /be (we 0/be0 ) indicates that the upper eight bits of the data bus (d0?d7) contains valid data during a write/read cycle. th e upper-middle write byte enable (we 1/be 1) indicates that the upper-middle eight bits of the data bus (d8?d15) contains valid data during a write/read cycle. the lower-middle write byte enable (we 2/be 2) indicates that the lower-middl e eight bits of the data bus (d16?d23) contains valid data during a write/re ad cycle. the lower write/read enable (we 3/be 3) indicates that the lower eight bits of the data bus contains valid data during a write cycle. the write/byte enable lines affected in a transact ion for 32-bit port (ps = 00) , a 16-bit port (ps = 10) and a 8-bit port (ps = 01) are shown in table 10-4 . 10.5 dual mapping of the internal flash eeprom array the internal flash eeprom (uc3f) module can be mapped to an extern al memory region controlled by the memory controller. only one region can be programmed to be dual-mapped. when dual mapping is enabled (dme bit is set in the dmbr register) a nd when an internal address matches the dual-mapped address range (as programmed in the dmbr) with the cycle type matching the at/atm field in dmbr/dmor registers, the following occurs: ? the internal flash memory doe s not respond to that address ? the memory controller takes control of the external access table 10-4. write enable/byte enable signals function 1 1 this table shows which write enables are asserted (indicated wi th an ?x?) for different combinations of port size and transfer size. transfer size tsiz address 32-bit port size 16-bit port size 8-bit port size a30 a31 we 0/ be 0 we 1/ be 1 we 2 be 2 we 3/ be 3 we 0/ be 0 we 1/ be 1 we 2/ be 2 we 3/ be 3 we 0 / be 0 we 1 /be 1 we 2 be 2 we 3/ be 3 byte 01 0 0 x x x 01 0 1 x x x 01 1 0 x x x 01 1 1 x x x half- word 10 0 0 x x x x x 1010 xxxx x word 0000xxxxxx x memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-25 ? the attributes for the access are taken from one of the base and opt ion registers of the appropriate chip select ? the chip-select region selected is determined by the cs line select bit field ( section 10.9.5, ?dual-mapping base register (dmbr) ?). with dual mapping, aliasing of addr ess spaces may occur. this happe ns when the region is dual-mapped into a region which is also mapped into one of the four regions available in the memory controller. if code or data is written to th e dual-mapped region, care must be taken to avoid overwriti ng this code or data by normal accesses of the chip-select region. there is a match if: bus_address[0:16] == {0000000,isb[0:2],0,ba[1:6]} eqn. 10-1 where ba represents the bit field in the dmbr register. eqn. 10-2 care must also be taken to a void overwriting ?normal? csx data with dual-mapped code or data. one way to avoid this situation is by disabling th e chip-select region and en abling only the dual-mapped region (dmbr[dme] = 1, but brx[v] = 0). figure 10-19 illustrates the phenomenon. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-26 freescale semiconductor figure 10-19. aliasing phenomenon illustration note the default state is to allow dual- mapping data accesses only; this means that dual mapping is possible only for data accesses on the internal bus. also, the default state takes the lowe r 2 mbytes of the mpc563 internal flash memory. hence, caution should be taken to change the dual-mapping setup before the first da ta access. dual mapping is not supported for an external master when the memory controller serves the access; in such a case, the mpc561/mpc563 terminat es the cycle by asserting tea . 10.6 dual mapping of an external flash region the dual mapping feature also enables mapping of external memory to alternative memory regions controlled by the memory controller. when dual mappi ng is enabled and an external address matches a cs x physical external memory mpc5xx memory map external cs x flash dual mapping dual-map region memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-27 dual mapped address, and the cycl e type matches at/atm field in dmbr/dmor register, then the following occur: ? the chip-select that is mapped to the access does not respond to th at address (it remains negated) ? the chip-select region selected is determined by the dmcs bit field in the dmbr register ? the attributes for the access are taken from the corresponding chip select region dual mapping can only be enabled over memory addresses in the range 0x0000 0000 through 0x000f ffff. note internal flash must be disabled to use dual mapping over an external memory. 10.7 global (boot) chip-select operation global (boot) chip-select operation al lows address decoding for a boot rom before system initialization. if the global chip-select feature is enabled then the memory controller is enabled from reset. the global chip select port size is programmable at system reset using rc w[bps]. the global chip select does not provide write prot ection and responds to all address type s, allowing a boot rom to be located anywhere in the address space. the memory controller wi ll operate in this boot mode until the first write to any chip select option register (orx).the chip select signal can be programmed to continue decoding a range of addresses after this write, provided the preferred address range is first loaded into the chip sel ect base register (brx). after the first write to orx, the global chip select can only be restarted with a system reset. which chip-select line is used as the global chip se lect, and how it operates, is determined by the reset configuration parameters: ? flen ? internal flash enable (bit 20) ? bdis ? boot disable (bit 3) ? dme ? dual mapping enable (bit 31) table 10-6 summarizes global chip select operations fo r all combinations of values on these reset configuration word lines.in case 1, where flen , bdis, dme = 0b000 (all cleared) at reset, cs 0 is the global chip-select output. when the rcpu begi ns accessing memory after system reset, cs 0 is asserted for every address, for accesses to both internal and external instructions and data. in case 2, where flen, bdis, dme = 0b001 at reset, cs 0 is asserted for all external address accesses (instructions and data) and for intern al instruction accesses. however, cs 3 is asserted for all internal data accesses. cs 3 is used in this case to allow dual mapping of loads/stores to/from an alternative bank which is not the memory bank normally used for instructions/data. in this way cs 3 can be used to allow load/store from a different memory bank from reset. dme can then be disabled as required. the global chip select feature is disabled by dr iving only the bdis line of the rcw (flen, bdis, dme = 0b010). this is shown in case 3 of table 10-6 . table 10-5 shows the initial values of the ? boot bank? in the memory controller. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-28 freescale semiconductor 10.8 memory controller external master support the memory controller in the mp c561/mpc563 supports acce sses initiated by both internal and external bus masters to external memories. if the addre ss of any master is mapped within the internal mpc561/mpc563 address space , the access will be directed to the in ternal device, and will be ignored by the memory controller. if the addres s is not mapped internally, but rather mapped to one of the memory controller regions, the memory cont roller will provide the appropria te chip select and strobes as programmed in the corresponding region (see section 6.2.2.1.3, ?external ma ster control register (emcr) ?). the mpc561/mpc563 supports only sync hronous external bus masters. th is means that the external master works with clkout and implements the mp c561/mpc563 bus protocol to access a slave device. a synchronous master initiate s a transfer by asserting ts . the addr[0:31] signals must be stable from the rising edge of clkout during which ts is sampled, until the last ta acknowledges the transfer. since the external master works synchronously with th e mpc561/mpc563, only setup and hold times around the rising edge of clkou t are important. once the ts is detected/asserted, the memory controller compares the address with each one of its defined valid banks to fi nd a possible match. but, since the external address space is shorter than the internal space, the actual address that is used for comparing against the memory controller regions is in the format of: {00000000, bits [8:16] of the external address}. in the case where a match is found, the controls to the memory devices are generated and the transfer acknowledge indication (ta ) is supplied to the master. table 10-5. boot bank fields values after hard reset field value (binary) ps rcw[4:5] bps sst 0 bl 0 wp 0 seta 0 bi 0b1 v cs 0 = id 3 cs 3 = id 20 & id31 am[0:16] 0 0000 0000 0000 0000 atm[0:2] 000 csnt 0 acs[0:1] 00 ehtr 0 scy[0:3] 0b1111 bscy[0:2] 0b011 trlx 0 memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-29 because it takes two clocks for the external a ddress to be recognized and handled by the memory controller, the ts which is generated by the external master is ahead of the corresponding cs and strobes which are asserted by the memory controller. this 2-clock delay might cause problems in some synchronous memories. to overcome this, th e memory controller generates the mts (memory transfer start) strobe which can be used in the slave?s memory instead of the external master?s ts signal. as seen in figure 10-20 , the mts strobe is synchronized to the assertion of cs by the memory controller so that the external memory can latch the external master?s address correctly. to activat e this feature, the mtsc bit must be set in the siumcr register. use external logic to control devices th at can have burst accesses from an external master. on the mpc563, when the external master accesses the internal flash when it is disabled, the access is terminated with the transfer error acknowledge (tea ) signal asserted, and the memory controller does not support this access in any way. when the memory controller serves an external master, the bdip signal becomes an input signal. this signal is watched by the memory controller to detect when the burst is terminated. figure 10-20. synchronous external master configuration for gpcm-handled memory devices memory address ce oe w data address csx oe we /be data synchronous external master ts ta ta ts addr data bdip bdip bdip burst note: the memory controller?s bdip lin e is used as a burst_in_progress signal. burst burst mts ts mpc5xx memory controller mpc561/mpc563 reference manual, rev. 1.2 10-30 freescale semiconductor figure 10-21. synchronous external master basic access (gpcm controlled) note because the mpc561/mpc 563 has only 24 address si gnals, the eight most significant internal address li nes are driven as 0b0000_0000, and so compared in the memory controller?s regions. clock addr[0:31] cs we / be oe data ts ta address match & compare memory device access rd/ wr burst tsize mts memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-31 10.9 programming model the registers in table 10-6 are used to control the memory controller. 10.9.1 general memory cont roller programming notes 1. in the case of an external master that acce sses an internal mpc561/mpc563 module (in slave or peripheral mode), if that slave device address also matches one of the memo ry controller?s regions, the memory controller will not issue any cs for this access, nor will it terminate the cycle. thus, this practice should be avoided. be aware also th at any internal slave access prevents memory controller operation. 2. if the memory controller serves an external master, then it can suppor t accesses to 32-bit port devices only. this is because the mpc561/mpc 563 external bus interface cannot initiate extra cycles to complete an access to a smaller port-s ize device as it does not own the external bus. 3. when the seta bit in the base register is set, then the timing programmi ng for the various strobes (cs , oe and we /be ) may become meaningless. 4. when configuring a chip select for a memory region with the intent to access that region immediately after configur ation, then an isync instruction should be executed in order to ensure that the configuration takes effect before any accesses are initiated. table 10-6. memory controller address map address register 0x2f c100 base register bank 0 (br0) 0x2f c104 option register bank 0 (or0) 0x2f c108 base register bank 1 (br1) 0x2f c10c option register bank 1 (or1) 0x2f c110 base register bank 2 (br2) 0x2f c114 option register bank 2 (or2) 0x2f c118 base register bank 3 (br3) 0x2f c11c option register bank 3 (or3) 0x2f c120 ? 0x13f reserved 0x2f c140 dual-mapping base register (dmbr) 0x2f c144 dual-mapping option register (dmor) 0x2f c148 ? 0x2f c174 reserved 0x2f c178 memory status register (mstat) memory controller mpc561/mpc563 reference manual, rev. 1.2 10-32 freescale semiconductor 10.9.2 memory controller status registers (mstat) , 10.9.3 memory controller base registers (br0?br3) , msb 01234567 8 9 10 11 121314 lsb 15 field ? wper0 wper1 wper2 wper3 ? hreset 0000_0000_0000_0000 addr 0x2f c178 figure 10-22. memory controller status register (mstat) table 10-7. mstat bit descriptions bits name description 0:7 ? reserved 8:11 wper0 ? wper3 write protection error for bank x. this bit is asserted when a write-protect error occurs for the associated memory bank. a bus monitor (responding to tea assertion) will, if enabled, prompt the read of this register if ta is not asserted during a write cycle. wperx is cleared by writing one to the bit or by performing a system re set. writing a zero has no effect on wper. 12:15 ? reserved msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ba hreset (br0) unchanged hreset (br[1:3]) unchanged addr 0x2f c100 (br0); 0x2f c108 (br1); 0x2f c110 (br2); 0x2f c118 (br3) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 ba at ps sst wp ? bl webs tbdip lbdip seta bi v hreset (br0) unchanged id[4:5] 00 undefined 0 undefined 1 id3 hreset (br[1:3]) unchanged x 2 1 the reset value is determined by the value on the internal data bus during reset (reset-configuration word). 2 see table 10-9 for reset value. figure 10-23. memory controller base registers 0?3 (br0?br3) memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-33 table 10-8. br0?br3 bit descriptions bits name description 0:16 ba base address. these bits are compared to the corresponding unmasked address signals among addr[0:16] to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. (the address types are also compared.) these bits are used in conjunction with the am [0:16] bits in the or. 17:19 at address type. this field can be used to require accesses of the memory bank to be limited to a certain address space type. these bits are used in conjunction with the atm bits in the or. note that the address type field uses only at[0:2] and does not need at3 to define the memory type space. for a full definition of address types, refer to section 9.5.8.6, ?address types .? 20:21 ps port size 00 32-bit port 01 8-bit port 10 16-bit port 11 reserved 22 sst short setup time ? this field specifies the setup time required for this memory region. 0 normal setup time (like the mpc555) 1 short setup time selected note that an external burst access with short setup timing will corrupt any usiu register load/store if sccr[ebdf] is not 0b00. refer to ta b l e 8 - 9 . 23 wp write protect. an attempt to write to the ran ge of addresses specified in a base address register that has this bit set can cause the tea signal to be asserted by the bus-monitor logic (if enabled), causing terminati on of this cycle. 0 both read and write accesses are allowed 1 only read accesses are allowed. the csx signal and ta are not asserted by the memory controller on write cycles to this memory bank. wper is set in t he mstat register if a write to this memory bank is attempted 24 ? reserved 25 bl burst length ? this field spec ifies the maximum number of wo rds that may comprise a burst access for this memory region. this field has an effect only in the case when the burst accesses are initiated by the usiu (siumcr[burst_en] =1). 0 burst access of up to 4 words 1 burst access of up to 8 words 26 webs write-enable/byte-select. this bi t controls the func tionality of the we /be pads. 0the we /be pads operate as we 1the we /be pads operate as be 27 tbdip toggle-burst data in progress . tbdip determines how long the bdip strobe will be asserted for each data beat in the burst cycles. 28 lbdip late-burst-data-in-progress (lbd ip). this bit determines the timi ng of the first assertion of the bdip signal in burst cycles. note: do not set both lbdip and tbdip bits in a region?s base registers; behavior in such cases is unpredictable. 0 normal timing for bdip assertion (asserts one clock after negation of ts ) 1 late timing for bdip assertion (asserts after the prog rammed number of wait states) 29 seta external transfer acknowledge 0ta generated internally by memory controller 1ta generated by external logic. note that programming the timing of cs /we /oe strobes may have no meaning when this bit is set memory controller mpc561/mpc563 reference manual, rev. 1.2 10-34 freescale semiconductor 10.9.4 memory controller option registers (or0?or3) 1, 30 bi burst inhibit 0 memory controller drives bi negated (high). the bank supports burst accesses. 1 memory controller drives bi asserted (low). the bank does not support burst accesses. note: following a system reset, the bi bit is set. 31 v valid bit. when set, this bit indicates that th e contents of the base-register and option-register pair are valid. the cs signal does not assert until the v-bit is set. note: an access to a region that has no v-bit set may cause a bus monitor timeout. see ta b l e 1 0 - 9 for the reset value of this bit in br 0. table 10-9. br x [v] reset value branch register br x [v] reset value br0 id3 br1 0 br2 0 br3 id20 & id31 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field am 1 hreset 0000_0000_0000_0000 addr 0x2f c104 (or0); 0x2f c10c (or1 ); 0x2f c114 (or2), 0x2f c11c (or3) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 am atm csnt acs ehtr scy bscy trlx hreset 0000_0000 1111 0 1 1 0 1 it is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 3 - 1 = 7 [0b111]). figure 10-24. memory controller option registers 1?3 (or0?or3) table 10-8. br0?br3 bit descriptions (continued) bits name description memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-35 table 10-10. or0?or3 bit descriptions bits name description 0:16 am address mask. this field allows masking of any corresponding bits in the associated base register. masking the address bits independently allo ws external devices of different size address ranges to be used. any clear bit masks the corresponding address bit. any set bit causes the corresponding address bit to be used in comparison with the address signals. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this field can be read or written at anytime. following a system reset, the am bits are cleared in or0. 17:19 atm address type mask. this field masks selected address type bits, allowing more than one address space type to be assigned to a chip-select. any set bit causes the corresponding address type code bits to be used as part of the address comparison. any cleared bit masks the corresponding address type code bit. clear the atm bits to igno re address type codes as part of the address comparison. note that the address type field us es only at[0:2] and does not need at3 to define the memory type space. following a system reset, the at m bits are cleared in or0. 20 csnt chip-select negation time. following a system reset, the csnt bit is reset in or0. 0cs /we are negated normally. 1cs /we are negated a quarter of a clock earlier than normal following a system reset, the cs nt bit is cleared in or0. 21:22 acs address to chip-select setup. following a system reset, the acs bits are reset in or0. 00 cs is asserted at the same time that the address lines are valid. 01 reserved 10 cs is asserted a quarter of a clock after the address lines are valid. 11 cs is asserted half a clock after the address lines are valid following a system reset, the ac s bits are cleared in or0. 23 ehtr extended hold time on read accesses. this bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any mp c561/mpc563 write accesses or read accesses to a different bank. 0 memory controller generates normal timing 1 memory controller generates extended hold timing following a system reset, the eh tr bits are cleared in or0. 24:27 scy cycle length in clocks. this four-bit value repr esents the number of wait states inserted in the single cycle, or in the first beat of a burst, when the gpcm handles the external memory access. values range from 0 (0b0000) to 15 (0b1111). this is the main parameter for determining the length of the cycle. the total cycle length may vary depending on the sett ings of other timing attributes. the total memory access length is (2 + scy) x clocks. if an external ta response is selected for this memory bank (by setting the seta bit), then the scy field is not used. following a system reset, the scy bits are set to 0b1111 in or0. memory controller mpc561/mpc563 reference manual, rev. 1.2 10-36 freescale semiconductor 10.9.5 dual-mapping base register (dmbr) , 28:30 bscy burst beats length in clocks. this field determin es the number of wait states inserted in all burst beats except the first, when the gpcm starts handling the external memory access and thus using scy[0:3] as the main parameter for determining the length of that cycle. the total cycle length may vary depending on the sett ings of other timing attributes. the total memory access length for the beat is (1 + bscy) x clocks. if an external ta response has been selected for this memory bank (by setting the seta bit) then bscy[0:3] are not used. 000 0-clock-cycle (1 clock per data beat) 001 1-clock-cycle wait states (2 clocks per data beat) 010 2-clock-cycle wait states (3 clocks per data beat) 011 3-clock-cycle wait states (4 clocks per data beat) 1xx reserved following a system reset, the bscy bits are set to 0b011 in or0. 31 trlx timing relaxed. this bit, when set, modifies the timing of the signals that control the memory devices during a memory access to this memory region. relaxed timing multiplies by two the number of wait states determined by the scy and bscy fields. refer to section 10.3.5, ?summary of gpcm timing options ,? for a full list of the effects of this bit on signals timing. 0 normal timing is generated by the gpcm. 1 relaxed timing is generated by the gpcm following a system reset, th e trlx bit is set in or0. msb 0123456789101112131415 field ? ba ? at ? hreset 0 undefined 000 001 000 addr 0x2f c140 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? dmcs dme hreset 0000_0000_0000_0 id 20 1 id31 1 1 the reset value is a reset configuration word value extracted from the indicated internal data bus lines. refer to section 7.5.2, ?hard reset configuration word (rcw) .? figure 10-25. dual-mapping base register (dmbr) table 10-11. dmbr bit descriptions bits name description 0?reserved 1:6 ba base address. ba field corresponds to address bits [11:16]. the base address field is compared (along with the address type field) to the address of the address bus to determine whether an address should be dual-mapped by one of the memory banks controlled by the memory controller. these bits are used in co njunction with the am[11:16] bits in the dmor. table 10-10. or0?or3 bit descriptions (continued) bits name description memory controller mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 10-37 10.9.6 dual-mapping op tion register (dmor) , 7:9 ? reserved 10:12 at address type. this field can be used to spec ify that accesses involving the memory bank are limited to a certain address space type. these bi ts are used in conjunction with the atm bits in the or. the default value at reset is to map data only. for a full definition of address types, refer to section 9.5.8.6, ?address types .? 13:27 ? reserved 28:30 dmcs dual-mapping chip select. this field determines which chip-select signal is assigned for dual mapping. 000 cs 0 001 cs 1 010 cs 2 011 cs 3 1xx reserved 31 dme dual mapping enabled. this bit indicates th at the contents of the dual-mapping registers and associated base and option registers are valid and enables the dual-mapping operation. the default value at reset comes from the internal data bus that reflects the reset configuration word. see section 10.5, ?dual mapping of the internal flash eeprom array ,? for more information. 0 dual mapping is not active 1 dual mapping is active msb 0123456789101112131415 field ? am 1 ?atm? hreset 0000_0000_00 001 000 addr 0x2f c144 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? hreset 0000_0000_0000_0000 1 it is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 3 - 1 = 7 [0b111]). figure 10-26. dual-mapping option register (dmor) table 10-11. dmbr bit descriptions bits name description memory controller mpc561/mpc563 reference manual, rev. 1.2 10-38 freescale semiconductor table 10-12. dmor bit descriptions bits name description 0?reserved 1:6 am address mask. the address mask field of each opt ion register provides for masking any of the corresponding bits in the associated base register. by masking the address bits independently, external devices of different size address ranges can be used. any clear bit masks the corresponding address bit. any set causes the corresponding address bit to be used in the comparison with the address signals. address ma sk bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this field can be read or written at any time. 7:9 ? reserved 10:12 atm address type mask. this field can be used to mask certain address type bits, allowing more than one address space type to be assigned to a chip select. any set bit causes the corresponding address type code bits to be used as part of the address comparison. any cleared bit masks the corresponding address type code bit. to instruct the memory controller to ignore address type codes as part of the address comparison, clear the atm bits. note: following a system reset, the atm bits ar e cleared in dmor, except the atm2 bit. this means that only data accesses are dual mapped. refer to the address types definition in ta bl e 9 - 8 . 13:31 ? reserved mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-1 chapter 11 l-bus to u-bus interface (l2u) the l-bus to u-bus interfa ce unit (l2u) provides an in terface between the load/s tore bus (l-bus) and the unified bus (u-bus). the l2u modul e includes the data memory prot ection unit (dmpu) , which provides protection for data memory accesses. the l2u is bidirectional. it allows load/store acce sses not intended for the l-bus data ram to go to the u-bus. it also allows code executi on from the l-bus data ram and read/w rite accesses from the u-bus to the l-bus. the l2u directs bus traffic between the l-bus and the u-bus. when transactions start concurrently on both buses, the l2u interface arbitrates to select which transaction is handle d. the top priority is assigned to u-bus to l-bus accesses; lower priority is assigned to the load/store accesses by the rcpu. 11.1 general features ? non-pipelined master and slave on u-bus ? does not start two back-to-back accesses on the u-bus ? supports u-bus pipelining ? retries back-to-back accesses from u-bus masters ? non-pipelined master and slave on the l-bus ? generates module selects for l-bus memory -mapped resources within a programmable, contiguous block of storage ? programmable data memo ry protection unit (dmpu) ? l-bus and u-bus snoop logic for the reservati on protocol compatible with the powerpc isa architecture ? show cycles for rcpu accesses to the calram (none, all, writes) ? protection for calram accesses from the u-bus side (all accesses to th e calram from the u-bus side are blocked once the calram protection bit is set) 11.2 data memory protection unit features ? supports four memory regions whose base address and size can be programmed ? available sizes are 4 kbytes, 8 kbytes, 16 kbytes, 32 kbytes, 64 k bytes, 128 kbytes, 256 kbytes, 512 kbytes, 1 mbyte, 2 mbytes, 4 mbytes, 8 mbytes, and 16 mybtes ? region must start on the specified region size boundary (modulo addressing) ? overlap between regions is allowed ? each of the four regions suppor ts the following attributes: l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-2 freescale semiconductor ? access protection: us er or supervisor ? guarded attribute: spec ulative or non-speculative ? enable/disable option ? read only option ? supports a default global entry for memo ry space not covered by other regions: ? default access protection ? default guarded attribute ? interrupt generated upon: ? access violation ? load from guarded region ? write to read-only region ? the msr[dr] bit (data relocate) cont rols dmpu protection on/off operation ? programming is done using the mt spr/mfspr instructions to/from implementation-specific special purpose registers. ? no protection for accesses to the calram module on the l-bus (calram has its own protection options) 11.3 l2u block diagram figure 11-1 shows a block diagram of the l-bus to u- bus interface as implemented in the overall mpc561/mpc563 bus architecture. l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-3 figure 11-1. l2u bus interface block diagram 11.4 modes of operation the l2u module can operate in the following modes: ? normal mode ? reset operation ? peripheral mode ? factory test mode 11.4.1 normal mode in normal mode (master or slave) the l2u modul e acts as a bidirectional protocol translator. ? in master mode the rcpu is full y operational, and there is no exte rnal master access to the u-bus. ? slave mode enables an external master to access any internal bus slave while the rcpu is fully operational. the l2u transfers load/store accesse s from the rcpu to the u-bus and the read/write accesses by the u-bus master to the l-bus. in addition to the bus protocol translation, the l2u supports other functions such as show cycles, data memory protection, and mpc500 reservation protocol. e-bus mpc500 core l-bus u-bus + fp usiu burst buffer controller dmpu reservation control address decode u-bus interface l-bus interface uimb interface l-bus to u-bus interface imb3 l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-4 freescale semiconductor when a load to or store from the u-bus resource is issued by the rcpu, it is compared against the dmpu region access (address and attr ibute) comparators. if none of the a ccess attributes are violated, the access is directed to the u-bus by the l2u module. if the dmpu detects an access violation, it informs the error status to the master initiating the cycle. when show cycles are enabled, accesses to all of th e l-bus resources by the rcpu are made visible on the u-bus side by the l2u. the l2u is responsible for handling the effects of reservations on th e l-bus and the u- bus. for the l-bus and the u-bus, the l2u detects rese rvation losses and updates the rcpu co re with the reservation status. 11.4.2 reset operation while hard or soft reset is asserted on the u-bus , the l2u asserts the corre sponding l-bus reset signals. upon soft reset assertion, the l2u goe s to an idle state and all pending accesses are ignored. additionally, the l2u module control registers are not initialized on soft reset, keeping the system configuration unchanged. upon assertion of hard reset, the l2u control register s are initialized to their reset states. the l2u also drives the reset configuration word from the u-bus to the l-bus upon hard reset. 11.4.3 peripheral mode in the peripheral mode of operation the rcpu is shut down and an al ternative master on the external bus can perform accesses to any intern al bus (u-bus and l-bus) slave. the external master can also access the internal mp c500 special registers that are located in the l2u module. in order to access one of these mpc500 regi sters the emcr[cont] bit in the usiu must be cleared. 11.4.4 factory test mode factory test mode is a speci al mode of operation that allows access to the internal modules for testing. this mode is not intended for general use a nd is not supported for normal applications. 11.5 data memory protection the data memory protection unit (dmpu) in the l2u module provides access protection for the memory regions on the u-bus side from lo ad/store accesses by the rcpu. (onl y u-bus space is protected.) the dmpu does not protect mpc500 regi ster accesses initiated by the rcpu on the l-bus. the user can assign up to four regions of acces s protection attributes and can assign global attributes to any space not included in the active regions. when it det ects an access violation, the l2u gene rates an exception request to the cpu. a functional diagram of the dmpu is shown in figure 11-2 . l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-5 figure 11-2. dmpu basic functional diagram 11.5.1 functional description data memory protection is assigned on a regional basis. default mani pulation of the dmpu is done on a global region. the dmpu has control registers that contain the follow ing information: region protection on/off, region base address, region size, and th e region?s access permissions. each region?s protection attributes can be turned on or off by configuring the global region attribut e register?s enable attribute bit (l2u_gra[enrx]). during each load or store access from the rcpu to the u-bus, the address is compared to the value in the region base address register of eac h enabled region. any acces s that matches the specific region within its appropriate size, as defined by the region attribute register ?s region size field (l2u_rax[rs]), sets a match indication. when more than one match indication occurs, the eff ective region is the region with the highest priority. priority is determined by region num ber; highest priority corresponds to the lowest region number, e.g. region 0 is highest priority, while region 3 is lowest. when no match occurs, the effective region is th e global region, which has the lowest priority. the region attribute register also c ontains the region?s protection fields . the protection field (pp) of the effective region is compared to the access attributes. if the attributes match, the access is permitted. when the access is permitted, a u-bus acce ss may be generated according to the specific attribute of the effective region. region0 protection/attribute exception logic specific error interrupts to core address access attribute region1 protection/attribute region2 protection/attribute region3 protection/attribute global protection/attribute access region0 address and size region1 address and size region2 address and size region3 address and size granted match select msr[dr] region protection/attribute l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-6 freescale semiconductor when the access by the rcpu is not permitted, the l2u modul e asserts a data memory storage exception to the rcpu. for speculative load/store accesses from the rcpu to a region marked as guarded (g bit of region attribute register is set), the l2u asks the rcpu to retry the l- bus cycle until either the access is not speculative, or is canceled by the rcpu. in the case of attempted accesses to a guarded region togeth er with any other pr otection violation (no access), the l2u retries the access. the l2u handles this event as a da ta storage violation only when the access becomes non-speculative. note that access protection is active only when the mpc500?s msr[ dr] = 1. when msr[dr] = 0, dmpu exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative accesses are allowed. in this case, if the l-bus master [rcpu] initiates a non-calram cycle (access through the l2u) that is marked speculative, the l2u asks the rcpu to retry th e l-bus cycle until either the access is not speculative, or it is canceled by the rcpu core. note the programmer must not overlap th e calram memory space with any enabled region. overlapping an enab led region with calram memory space disables the l2u data me mory protection for that region. if an enabled region overlaps with th e l-bus space, the dmpu ignores all accesses to addresses within the l-bus space. if an enable d region overlaps with mpc500 register addr esses, the dmpu ignores any access marked as an mpc500 access. 11.5.2 associated registers table 11-1 shows registers that are used to control the dmpu of the l2u module. all the registers are special purpose registers that are accessed via the mpc500 mtspr/mfspr instructions. the re gisters are also accessed by an external master when emcr[cont] = 0. see section 11.8, ?l2u programming model ,? for register diagrams and bit descriptions. . table 11-1. dmpu registers name description l2u_rba0 region base address register 0 l2u_rba1 region base address register 1 l2u_rba2 region base address register 2 l2u_rba3 region base address register 3 l2u_ra0 region attribute register 0 l2u_ra1 region attribute register 1 l2u_ra2 region attribute register 2 l2u_ra3 region attribute register 3 l2u_gra global region attribute l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-7 note the appropriate dmpu registers must be programmed before the msr[dr] bit is set. otherwise, dmpu operation is not guaranteed. program the region base address in the l2u_rbax regi sters to the lower boundary of the region specified by the corresponding l2u_rax[rs] fi eld. if the region base addre ss does not correspond to the boundary of the block size programmed in the l2u_rax, the dm pu snaps the region base to the lower boundary of that block. for example, if the block size is programmed to 16 kbytes for region zero (i.e., l2u_ra0[rs] = 0x3) and the region base address is programmed to 0x1fff(i.e., l2u_rba0[rba] = 0x1), then the effective base a ddress of region zero is 0x0. see figure 11-3 . figure 11-3. region base address example external action is required to pr ogram only legal region sizes. the l2 u does not check whether the value is legal. if an illegal region size is programm ed, the region calculation may not be successful. 11.5.3 l-bus memory access violations all l-bus slaves have their own acce ss protection logic. for consistency, all storage access violations have the same termination result. thus access violations for load/store accesses started by the rcpu always have the same termination from all slaves: assertion of the data stor age exception. all other l-bus masters cause machine check exceptions. 11.6 reservation support in general terms, a reservation activity is the pr ocess whereby a load and store instruction pair is accompanied by a reservation of the data, the goal bein g to achieve an atomic operation. if a bus master other than the one holding the reservation accesses the data (or some other specific condition occurs as described in section 11.6.1, ?reservation protocol ?) the reservation is lost and is indicated accordingly. the rcpu storage reservation protocol supports a mult i-level bus structure. fo r each local bus, storage reservation is handled by the local reservation logic. the protocol tries to optim ize reservation cancellation such that an mpc500 processor (rcpu) is notified of storage reservation lo ss on a remote bus (u-bus, imb or external bus) only when it has issued a stwcx cy cle to that address. that is, the reservation loss indication comes as part of the stwcx cycle. region 0 (16 kbytes) actual programmed region resulting region 0x0000 0000 0x0000 1fff 0x0000 3fff 0x0000 5fff l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-8 freescale semiconductor 11.6.1 reservation protocol the reservation protocol operate s under the following assumptions: ? each processor has at most 1 reservation flag ? a lwarx instruction sets the reservation flag ? another lwarx instruction by same processor clears the reservati on flag related to a previous lwarx instruction and sets again the reservation flag ? a stwcx instruction by the same pr ocessor clears the reservation flag ? a store instruction by the same proces sor does not clear the reservation flag ? some other processor (or other mech anism) store to an address with an existing reservation clears the reservation flag ? in case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage 11.6.2 l2u reservation support the l2u is responsible for handling the effects of reservations on th e l-bus and the u- bus. for the l-bus and the u-bus, the l2u detects reservation losses. the reservation logic in the l2u performs the foll owing functions: ? snoops accesses to all l-bus and u-bus slaves ? holds one reservation (address) for the core ? sets the reservation flag when the rpcu issues a load-with-reservation request the unit for reservation is one word. a byte or half-w ord store request by anothe r master will clear the reservation flag. a load-with-reservation request by the rpcu updates the reservation address related to a previous load-with-reservation request and sets the reservati on flag for the new location. a store-with-reservation request by the rpcu clears the reservation flag. a store request by the rpcu does not clear the flag. a store request by some other mast er to the reservation address clears the reservation flag. if the storage reservation is lost, it is guaranteed that a store-with-reservation re quest by the rpcu will not modify the storage. the l2u does not start a store-with-reservation cycle on the u-bus if the reserved location on the u-bus has been touched by another master. the l2u driv es the reservation status back to the core. when the reserved location in the calram on the l-bus is touched by an alternate master, on the following clock the l2u indicates to the rpcu that the reservation has been touched. on assertion of the cancel-reservation signal, th e rcpu clears the internal reservation bit. if an stwcx cycle has been issued at the same time, the rcpu aborts the cycle. software must check the cr0[eq] bit to determine if the stwcx instruction completed successfully. storage reservation is set re gardless of the termination status (address or data ph ase) of the lwarx access. storage reservation is cleared regardless of the data phase termination status of the stwcx access if the address phase is terminated normally. l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-9 storage reservation will be cleared regardless of the data phase termin ation status of th e write requests by another master to the reserved address if the addres s phase of the write access is terminated normally on the destination (u-bus/l-bus) bus. if the programmable memory map of the part is m odified between a lwarx and a stwcx instruction, the reservation is not guaranteed. 11.6.3 reserved location (bus) and possible actions once the rpcu core reserves a memory location, th e l2u module is responsible for snooping the l-bus and u-bus for possible intrusion of the reserved lo cation. under certain circumstances, the l2u depends on the usiu or the uimb to provide status of rese rvation on external bus and the imb3 respectively. table 11-2 lists all reservation protocol cases supported by the l2u snooping logic. 11.7 l-bus show cycle support the l2u module provides support for l-bus show cycles. l-bus show cycl es are external vi sibility cycles that reflect activity on the l-bus that would otherwise not be visible to the external bus. l-bus show cycles are software controlled. table 11-2. reservation snoop support reserved location on intr uding alternate master action taken on stwcx cycle l-bus l-master request to cancel the reservation. 1 1 if the rcpu tries to modify (stwcx) that location, the l2u does not have enough time to stop the write access from completing. in this case, the l2u will drive cancel-reservation signal back to the core as soon as it comes to know that the alternate master on the u-bus has touched the reserved location. u-master request to cancel the reservation. u-bus l-master block stwcx 2 2 if the rcpu tries to modify (stwcx) that location, the l2u does not start the cycle on the u-bus and it communicates to the core that the current write ha s been aborted by the slave with no side effects. u-master block stwcx external bus l-master block stwcx u-master block stwcx ext-master transfer status 3 3 if the rcpu tries to modify (stwcx) that location, th e l2u runs a write-cycle-with -reservation r equest on the u-bus. the l2u samples the status of the reservati on along with the u-bus cycle termination signals and it communicates to the core if the current write ha s been aborted by the slave with no side effects. imb3 l-master block stwcx u-master block stwcx imb3-master transfer status l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-10 freescale semiconductor 11.7.1 programming show cycles l-bus show cycles are disa bled during reset and must be configured by setting the lshow[0:1] bits in the l2u_mcr. table 11-3 shows the configurations of the lshow[0:1] bits. 11.7.2 performance impact when show cycles are enabled in the l2u module, there is a performance penalty on the l-bus. this occurs because the l2u module does not support more than one access being proc essed at any time. to ensure that only one access at a time is processed, and not lose an l-bus access that would have been show cycled, the l2u module will arbitrate for the l-bus whenever it is processing any access. this l-bus arbitration will prevent any other l-bus master from star ting a cycle that might turn out to be a qualifiable l-bus show cycle. for l-bus show cycles, the minimu m performance impact on the l-bus will be three clocks. this minimum impact assumes that the l-bus slave access is a 1- clock access, and the l2u module acquires immediate bus grant on the u-bus. the l2u has to wait two cloc ks before completing the show cycle on the u-bus, thus using up five clocks for the complete process. a retried access on the l-bus (no addr ess acknowledge) that qualifies to be show cycled, will be accepted when it is actually acknowledged. this will cause a 1- clock delay before an l-bus master can retry the access on the l-bus, because the l2u modul e will release l-bus one clock later. l2u asserts the internal bus request signal on the u-bus for a minimum of two clocks when starting a show cycle on the u-bus. 11.7.3 show cycle protocol the l2u module behaves as both a master and a slav e on the u-bus during show cycles. the l2u starts the u-bus transfer as a bus master and then complete s the address phase and data phase of the cycle as a slave. the l2u follows u-bus protocol of in-order termination of the data phase. the usiu can control the start of s how cycles on the u-bus by asserting the no-show cycle indicator. this will cause the l2u module to release the u-bus for at least one clock before retrying the show cycle. 11.7.4 l-bus write show cycle flow the l2u performs the following sequence of actions for an l-bus-write show cycle. 1. arbitrates for the l-bus to prevent any other l-bus cycles from starting table 11-3. l2u_mcr lshow modes lshow action 00 disable l-bus show cycles 01 show address and data of all l-bu s space write cycles 10 reserved (disable l-bus show cycles) 11 show address and data of all l-bus space read and write cycles l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-11 2. latches the address and the data of the l- bus access, along with all address attributes 3. waits for the termination of the l-bus access an d latches the termination status (data error) 4. arbitrate for the u-bus, and when granted, starts the u- bus access, asserting show cycle request on the u-bus, along with address, attributes and th e write data. the l2u m odule provides address recognition and acknowledgment for the address phase . if the no-show cycle indicator from the u-bus is asserted, the l2u does not start the show cycle. the l2 u module releases the u-bus until the no-show cycle indicator is negated and then arbitrates for the u-bus again. 5. when the l2u module has u-bus data bus grant, it drives the data phase termination handshakes on the u-bus. 6. releases the l-bus 11.7.5 l-bus read show cycle flow the l2u performs the following sequence of actions for an l-bus read show cycle. 1. arbitrates for the l-bus to preven t any other l-bus cycle from starting 2. latches the address of the l-bus acce ss, along with all address attributes 3. waits for the data phase termination on the l-bus and latches the read da ta, and the termination status from the l-bus 4. arbitrates for the u-bus, and when granted, star ts the u-bus access, a sserting the show cycle request on the u-bus, along with address a ttributes. the l2u module provides address recognition/acknowledgment for the ad dress phase. if the no-show cy cle indicator from the u-bus is asserted, the l2u does not start the show cy cle. the l2u module releases the u-bus until the no-show cycle indicator is negated and then arbitrates for the u-bus again. 5. when the l2u module has u-bus data bus grant, it drives the read da ta and the data phase termination handshakes on the u-bus 6. release the l-bus. 11.7.6 show cycle support guidelines the following are the guidelines for l2u show cycle support: ? the l2u module provides address and data for al l qualifying l-bus cycles when the appropriate mode bits are set in the l2u_mcr. ? the l2u-module-only provides show cy cles l-bus activity that is not targeted for the u-bus or the l2u module internal registers, regardless of the termination status of such activity. ? the l2u module does not provide show cycle access to any mpc500 special purpose register. ? the l2u does not start a show cycle for an l-bus access that is retried. this decision to not start the show cycle causes a clock dela y before the cycle can be retrie d, since the l2u module will have arbitrated away the l-bus immediat ely on detecting the show cycle, before the retry information is available. ? the l2u module does not show cycle any l-bus activity that is aborted. ? the l2u module does not access the u-bus if the usiu inhibits show cycle activity on the u-bus. l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-12 freescale semiconductor ? the l2u does not provide show cycle for any l- bus addresses that fall in the l-bus calram address space if the calram protecti on [sp] bit is set in the l2u_mcr. table 11-4 summarizes the l2u show cycle support. 11.8 l2u programming model the l2u control registers control the l2u bus interf ace and the dmpu. they are accessible via the mtspr and mfspr instructions. they are al so accessible by an external master when emcr[cont] bit is cleared. l2u control registers are accessible from both the l-bus side and the u-bus side in one clock cycle. as with all sprs, l2u registers are acc essible in supervisor mode only. any unimplemented bits in l2u registers return 0?s on a read, and the writes to those register bits are ignored. table 11-5 shows l2u registers along with their spr numbers and hexadecimal addre sses that are used to access l2u registers during a peripheral mode access. . table 11-4. l2u show cycle support chart case destination lb aack lb abort comments 1l-bus slave 1 1 l-bus slave includes all address in the l-bus address space. no x 2 2 x indicates don?t care conditions. not show cycled [cycle will be retried one clock later] 3 3 there will be a 1-clock turnaround because the l-bus retry information is not available in time to negate the l-bus arbitration. 2l2u 4 4 l2u indicates l2u registers. x x not show cycled 3 u-bus/e-bus 5 5 u-bus/e-bus refers to all destinations through the l2u interface. x x not show cycled 4 l-bus slave 1 yes no show cycled 5 l-bus slave 1 yes yes not show cycled [l-bus will be released next clock] table 11-5. l2u (ppc) register decode name spr # spr[5:9] spr[0:4] address for external master access 1 access description l2u_mcr 568 10001 11000 0x0000_3110 supr l2u module configuration register l2u_rba0 792 11000 11000 0x0000_3180 supr region base address register 0 l2u_rba1 793 11000 11001 0x0000_3380 supr region base address register 1 l2u_rba2 794 11000 11010 0x0000_3580 supr region base address register 2 l2u_rba3 795 11000 11011 0x0000_3780 supr region base address register 3 l2u_ra0 824 11001 11000 0x0000_3190 supr region attribute register 0 l2u_ra1 825 11001 11001 0x0000_3390 supr region attribute register 1 l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-13 for these registers a bus cycle will be performed on the l-bus and the u- bus with the address as shown in table 11-6 . . 11.8.1 u-bus access the l2u registers are accessible from th e u-bus side only if it is a supervisor mode data access and the register address is correct and it is indicated on the u-bus that it is a ppc register access. a user mode access, or an access mark ed as instruction, to l2u register s from the u-bus side will cause a data error on the u-bus. 11.8.2 transaction size all l2u registers are defined by mp c500 architecture as bei ng 32-bit registers in normal mode. there is no mpc500 instruction to access either a half word or a byte of the special purpose register. all l2u registers are only word accessible (read and wr ite) in peripheral mode. a half-word or byte access in peripheral mode will resu lt in a word transaction. 11.8.3 l2u module configur ation register (l2u_mcr) the l2u module configuration register (l2u_mcr) is used to control th e l2u module operation. l2u_ra2 826 11001 11010 0x0000_3590 supr region attribute register 2 l2u_ra3 827 11001 11011 0x0000_3790 supr region attribute register 3 l2u_gra 536 10000 11000 0x0000_3100 supr global region attribute 1 when emcr[cont] = 0, for external master access only. table 11-6. hex address for spr cycles a[0:17] a[18:22] a[23:27] a[28:31] 0 spr[5:9] spr[0:4] 0 table 11-5. l2u (ppc) register decode (continued) name spr # spr[5:9] spr[0:4] address for external master access 1 access description l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-14 freescale semiconductor 11.8.4 region base address registers (l2u_rbax) the l2u region base address register (l2u_rbax) defines the base addr ess of a specific region protected by the data memory protection unit. there are four registers (x = 0...3), one for each supported region. msb 0123456789101112131415 field sp lshow ? reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? reset 0000_0000_0000_0000 addr spr 568 figure 11-4. l2u module configuration register (l2u_mcr) table 11-7. l2u_mcr bit descriptions bits name description 0 sp calram protection (sp) bit is used to protec t the calram on the l-bus from u-bus accesses. any attempt to set or clear the sp bit from the u-bus side has no affect. once this bit is set, the l2u blocks all calram accesses initiated by the u-bus masters and the access is terminated with a data error on the u-bus. if l-bus show cycles are enable d, setting this bit will disable l-bus calram show cycles. 1:2 lshow lshow bits are used to configure the show cycle mode for cycles accessing the l-bus slave e.g. calram 00 disable show cycles 01 show address and data of all l-bus space write cycles 10 reserved 11 show address and data of all l-bus space read and write cycles 3:31 ? reserved msb 0123456789101112131415 field rba reset undefined 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field rba ? reset undefined 0000_0000_0000 addr spr 792?795 figure 11-5. l2u region x base address register (l2u_rbax) l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-15 11.8.5 region attribute registers (l2u_rax) each l2u region attribute register defines the protection attributes associated with a specific region protected by the data memory protection unit. ther e are four registers (x = 0...3), one for each supported region. table 11-8. l2u_rbax bit descriptions bits name description 0:19 rba region base address. the rba field provides the base address of the region. the region base address should start on the block boundary for the corresponding block size attribute specified in the region attribute register (l2u_rax). 20:31 ? reserved msb 0123456789101112131415 field ? rs reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field rs pp ? g ? reset 0000_0000_0000_0000 addr spr 824?827 figure 11-6. l2u region x attribute register (l2u_rax) table 11-9. l2u_rax bit descriptions bits name description 0:7 ? reserved 8:19 rs region size 0000_0000_0000 = 4 kbytes 0000_0000_0001 = 8 kbytes 0000_0000_0011 = 16 kbytes 0000_0000_0111 = 32 kbytes 0000_0000_1111 = 64 kbytes 0000_0001_1111 = 128 kbytes 0000_0011_1111 = 256 kbytes 0000_0111_1111 = 512 kbytes 0000_1111_1111 = 1 mbyte 0001_1111_1111 = 2 mbytes 0011_1111_1111 = 4 mbytes 0111_1111_1111 = 8 mbytes 1111_1111_1111 = 16 mbytes l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-16 freescale semiconductor 11.8.6 global region attribute register (l2u_gra) the l2u global region attribut e register (l2u_gra ) defines the protection attri butes associated with the memory region which is not protect ed under the four dmpu regions. this register also provides enable/disable control fo r the four dmpu regions. 20:21 pp protection bits 00 no supervisor access, no user access 01 supervisor read/write access, no user access 10 supervisor read/write access, user read-only access 11 supervisor read/write access, user read/write access 22:24 ? reserved 25 g guarded attribute 0 not guarded from speculative accesses 1 guarded from speculative accesses 26:31 ? reserved msb 0 1 2 3 4 5 6 7 8 9 101112131415 field enr0 enr1 enr2 enr3 ? reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? pp ? g ? reset 0000_0000_0000_0000 addr spr 536 figure 11-7. l2u global region attribute register (l2u_gra) table 11-10. l2u_gra bit descriptions bits name description 0 enr0 enable attribute for region 0 0 region attribute is off 1 region attribute is on 1 enr1 enable attribute for region 1 0 region attribute is off 1 region attribute is on 2 enr2 enable attribute for region 2 0 region attribute is off 1 region attribute is on table 11-9. l2u_rax bit descriptions (continued) bits name description l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 11-17 3 enr3 enable attribute for region 3 0 region attribute is off 1 region attribute is on 4:19 ? reserved 20:21 pp protection bits 00 no supervisor access, no user access 01 supervisor read/write access, no user access 10 supervisor read/write access, user read-only access 11 supervisor read/write access, user read/write access 22:24 ? reserved 25 g guarded attribute 0 not guarded from speculative accesses 1 guarded from speculative accesses 26:31 ? reserved table 11-10. l2u_gra bit descriptions (continued) bits name description l-bus to u-bus interface (l2u) mpc561/mpc563 reference manual, rev. 1.2 11-18 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 12-1 chapter 12 u-bus to imb3 bus interface (uimb) the u-bus to imb3 bus interface (uimb) structure is used to connect th e cpu internal unified bus (u-bus) to the intermodule bus 3 (imb3). it controls bus communication between the u-bus and the imb3. the uimb interface (see figure 12-1 ) consists of seven submodules that control bus interface timing, address decode, data multiplexing, intrasystem communicati on (interrupts), and clock generation to allow communication between u-bus and th e imb3. the seven submodules are: ? u-bus interface ? imb3 interface ? address decoder ? data multiplexer ? interrupt synchronizer ? clock control ? scan control 12.1 features ? provides complete interfacing between the u-bus and the imb3: ? 15 bits (32 kbytes) of address decode on imb3 ? 32-bit data bus ? read/write access to imb3 module registers ? interrupt synchronizer ? monitoring of accesses to unimplemented addr esses within uimb in terface address range ? burst-inhibited accesses to the modules on imb3 ? support of 32-bit and 16-bit bus interface units (bius) for imb3 modules ? half and full speed operation of imb3 bus with respect to u-bus ? simple ?slave only? u-bus interface implementation ? transparent mode operation not supported ? relinquish and retry not supported ? supports scan control for modules on the imb3 and on the u-bus note modules on the imb3 bus can only be reset by sreset . some modules may have a module reset, as well. u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 12-2 freescale semiconductor warning the user should not perform instructi on fetches from modules on the imb3. 12.2 uimb block diagram figure 12-1. uimb interface module block diagram 12.3 clock module the clock module within the uimb interface generate s the imb3 clock. the imb3 clock is the main timing reference used within the imb3 modules. the imb3 clock is generated based on the stop an d hspeed bits in the ui mb module configuration register (umcr). if the stop = 1, the imb3 clock is not generated. if the st op = 0 and the hspeed = 0, the imb3 clock is generated as the inversion of the internal system clock. this is the same frequency as the clkout if sccr[ebdf] = 0b00 ? full speed external bus. (see figure 12-2 .) if the hspeed = 1, then the imb3 clock is one-half of th e internal system frequency. (see figure 12-3 .) table 12-1. stop and hspeed bit functionality stop hspeed functionality 0 0 imb3 bus frequency is the same as u-bus frequency. 0 1 imb3 bus frequency is half that of the u-bus frequency. 1 x imb3 clock is not generated. address decode data mux interrupt synchronizer scan control u-bus interface imb3 interface clock control u-bus imb3 u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 12-3 figure 12-2. imb3 clock ? full-speed imb3 bus figure 12-3. imb3 clock ? half-speed imb3 bus table 12-2 shows the number of syst em clock cycles that the uimb re quires to perform each type of bus cycle. it is assumed that the imb3 is available to the uimb at all times (fastest possible case). note the uimb interface dynamically interpre ts the port size of the addressed module during each bus cycle, allowing bus transfers to and from 16-bit and 32-bit imb3 modules. during a bus transaction, the slave module on the imb3 signals its port size (16- or 32- bit) via an internal port size signal. 12.4 interrupt operation the interrupts from the modules on the imb3 are propa gated to the interrupt controller in the usiu through the uimb interface. the uimb interrupt synchronizer latches the interrupt s from the modules on the imb3 and drives them onto the u-bus, where th ey are latched by the usiu interrupt controller. 12.4.1 interrupt sources and levels on imb3 the imb3 has eight interrupt lines. there can be a ma ximum of 32 levels of in terrupts from the modules on imb3 bus. a single module can be a source for more than one interrupt. for example, the qsmcm can generate two interrupts (one for qs ci1/qsci2 and another for qspi). in this case, the qsmcm has two interrupt sources. each of these two sources ca n assert the interrupt on any of the 32 levels. table 12-2. bus cycles and system clock cycles bus cycle (from u-bus transfer start to u-bus transfer acknowledge) number of system clock cycles full speed half speed normal write 4 6 normal read 4 6 dynamically-sized write 6 10 dynamically-sized read 6 10 imb3 clock clkout imb3 clock clkout u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 12-4 freescale semiconductor it is possible for multiple interrupt s ources to assert the same interrupt level. to reduce the latency, it is a good practice for each interrupt source to assert an interrupt on a level on which no othe r interrupt source is mapped. 12.4.2 imb3 interrupt multiplexing the imb3 has 10 lines for interrupt support. eight li nes are for interrupts and two are for interrupt level byte select (ilbs). these lines will transfer the 32 interrupt levels to the interrupt synchronizer. a diagram of the interrupt flow is shown in figure 12-4 . figure 12-4. interrupt synchronizer signal flow latching 32 interrupt levels using eight imb3 interrupt lines is accomp lished with a 4: 1 time-multiplexing scheme. the uimb drives tw o signals (ilbs[0:1]) with a multiplexer select code that tells all interrupting modules on the imb3 about which group of si gnals to drive during the next clock. see figure 12-5 . 12.4.3 ilbs sequencing the imb3 interface drives the ilbs signals c ontinuously, incrementing through a code sequence (0b00, 0b01, 0b10, 0b11) once every clock. the umcr[irqmux] bits in the imb3 module configuration register select which type of multiplexing the inte rrupt synchronizer will perform. the irqmux field can select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources . these protocols would take one, two, three or four clocks, respectively. table 12-4 shows ilbs sequenci ng. programming irqmux[0:1] to 0b00 di sables time multiplexing. in this case the ilbs lines remain at 0b00 at all times. in this mode, no interrupts from imb3 modules which assert on levels 8 through 31 are ever latc hed by the interrupt synchronizer. sreset will not clear the irqmux bits, so time multiplexing will be en abled with the previous setup after sreset is released. the timing for the scheme and the valu es of ilbs and the interrupt leve ls driven onto th e imb3 irq lines are shown in figure 12-5 . this scheme causes a maximum latency of four clocks and an average latency of two clocks before the interrupt reque st can reach the interrupt synchronizer. uipend imb3 interrupt 8 block byte count byte-enables [24:31] [16:23] [8:15] [0:7] 8 to imb3 byte-enable 2 4 u-bus interrupt u-bus level[0:7] register data[0:31] u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 12-5 note: this diagram represents the ilbs behavior when irqmux[0:1] = 11 figure 12-5. time-multiplexi ng protocol for irq signals the irqmux bits determine how many levels of imb3 inte rrupts are sampled. refer to table 12-4 . 12.4.4 interrupt synchronizer the interrupt synchronizer latches the 32 levels of interrupts from the imb3 bus into a register which can be read by the cpu or ot her u-bus master. since there are only ei ght lines for interrupts on the imb3 and 32 levels of interrupts are possible, the 32 interrupt levels are multiplexe d onto eight imb3 interrupt lines. apart from latching these interrupts in the register (uipend), the interrupt synchronizer drives the interrupts onto the u-bus, where they are latc hed by the interrupt controller in the usiu. if imb3 modules drive interrupts on any of the 24 levels (levels eight through 31), th ey will be latched in uipend in the uimb. if any of the register bits 7 to 31 are set, then bit 7 will be set as well. table 12-3. ilbs signal functionality ilbs[0:1] description 00 imb3 interrupt sources mapped onto 0:7 levels will drive interrupts onto imb3 lvl[0:7] 01 imb3 interrupt sources mapped onto 8:15 levels will drive interrupts onto imb3 lvl[0:7] 10 imb3 interrupt sources mapped onto 16:23 levels will drive interrupts onto imb3 lvl[0:7] 11 imb3 interrupt sources mapped onto 24:31 levels will drive interrupts onto imb3 lvl[0:7] table 12-4. irqmux functionality irqmux[0:1] ilbs sequence description 00 00, 00, 00..... latch 0: 7 imb3 interrupt levels 01 00, 01, 00, 01.... latch 0: 15 imb3 interrupt levels 10 00, 01, 10, 00, 01, 10,..... latch 0:23 imb3 interrupt levels 11 00, 01, 10, 11, 00, 01, 10, 11,.... latch 0:31 imb3 interrupt levels imb3 clock ilbs [0:1] imb3 lvl[0:7] 00 01 11 10 00 01 11 10 lvl [0:7] lvl [8:15] lvl 16:23 lvl 24:31 lvl 0:7 u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 12-6 freescale semiconductor note software must poll this register to fi nd out which of the le vels 7 to 31 are asserted. the uipend register contains a status bit for each of the 32 interrupt leve ls. each bit of the register is a read-only status bit, reflecting th e current state of the corresponding in terrupt signal. for each of the 32 interrupt levels, a corresponding bi t of the uipend register is set. figure 12-4 shows how the eight interrupt lines are connect ed to the uipend regi ster to represent 32 levels of interrupts. figure 12-6 shows the implementation of the interrupt synchronizer. figure 12-6. interrupt synchronizer block diagram 12.5 programming model table 12-5 lists the registers used for c onfiguring and testing the uimb module. the address offset shown in this table is from the start of the block reserved for uimb registers. as shown in figure 1-2 , this block begins at offset 0x30 7f80 from the start of the mpc561/mpc563 intern al memory map (the last 128-byte sub-block of the uimb interface memory map). table 12-5. uimb interface register map access 1 base address register s 0x30 7f80 uimb module conf iguration register (umcr) see table 12-6 for bit descriptions. ? 0x30 7f84 ? 0x30 7f8f reserved lvl [8:31] lvl[0:7] ilbs [0:1] state 4 imbclock uipend reset imb3 lvl [0:7] machine u-bus interrupt level[0:7] or 24 7 lvl7 8 u-bus 32 data[0:31] register u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 12-7 any word, half-word or byte access to a 32-bit location within the uimb interface register decode block that is unimplemented (defined as reserved) causes the uimb interface to assert a data error exception on the u-bus.the entire 32-bit location must be defined as reserved in order for a data error exception to be asserted. unimplemented bits in a regist er return zero when read. 12.5.1 uimb module config uration register (umcr) the uimb module configuration register (umcr) is accessible in supervisor mode only. s/t 0x30 7f90 uimb test c ontrol register (utstcreg) reserved ? 0x30 7f94 ? 0x30 7f9f reserved s 0x30 7fa0 pending interrupt request register (uipend) see section 12.5.3, ?pending interrupt request register (uipend) ? for bit descriptions. 1 s = supervisor mode only; t = test mode only msb 0 12 3 456789101112131415 field stop irqmux hspeed ? hreset 0 00 1 0000_0000_0000 addr 0x30 7f80 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? hreset 0000_0000_0000_0000 figure 12-7. uimb module configuration register (umcr) table 12-5. uimb interface register map (continued) access 1 base address register u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 12-8 freescale semiconductor 12.5.2 test control register (utstcreg) the utstcreg register is used for factory testing only. 12.5.3 pending interrupt re quest register (uipend) the uipend register is a read-only st atus register which reflects the st ate of the 32 interrupt levels. the state of irq0 is shown in bit 0, the state of irq1 is shown in bit 1 and so on. this register is accessible only in supervisor mode. table 12-6. umcr bit descriptions bits name description 0 stop stop enable. 0 enable system clock for imb3 bus 1 disable imb3 system clock to avoid complications at restart and data corrup tion, system software must stop each slave on the imb3 before setting the stop bit. software must also ensure that all imb3 interrupts have been serviced before setting this bit. 1:2 irqmux interrupt request multiplexing. these bits control the multiplexing of the 32 possible interrupt requests onto the eight imb3 interrupt request lines. 00 disables the multiplexing scheme on the interrupt controller within this interface. what this means is that the imb3 irq [0:7] signals are n on-multiplexed, only providing 8 [0:7] interrupt request lines to the interrupt controller 01 enables the imb3 irq control logic to perform a 2-to-1 multiplexing to allow transferring of 16 [0:15] interrupt sources 10 enables the imb3 irq control logic to perform a 3-to-1 multiplexing to allow transferring of 24 [0:23]interrupt sources 11 enables the imb3 irq control logic to perform a 4-to-1 multiplexing to allow transferring of 32 [0:31] interrupt sources 3 hspeed half speed. the hspeed bit co ntrols the frequency at which the imb3 runs with respect to the u-bus. this is a modify-once bit. software can write the reset value of this bit any number of times. however, once logic 0 is written to this loca tion, any attempt to rewrite this bit to a logic 1 will have no effect. 0 imb3 frequency is the same as that of the u-bus 1 imb3 frequency is one half that of the u-bus 4:31 ? reserved u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 12-9 msb 012345678 9101112131415 field lvl0 lvl1 lvl2 lvl3 lvl4 lvl5 lvl6 lvl7 lvl8 lvl9 lvl 10 lv l 11 lv l 12 lv l 13 lv l 14 lv l 15 hreset 0000_0000_0000_0000 addr 0x30 7fa0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field lvl 16 lv l 17 lv l 18 lv l 19 lv l 20 lv l 21 lv l 22 lv l 23 lv l 24 lv l 25 lv l 26 lv l 27 lv l 28 lv l 29 lv l 30 lv l 31 hreset 0000_0000_0000_0000 figure 12-8. pending interrupt request register (uipend) table 12-7. uipend bit descriptions bits name description 0:31 lvl x pending interrupt request level. accessible only in supervisor mode. lvl x identifies the interrupt source as uimb lvl x , where x is the interrupt number. u-bus to imb3 bus interface (uimb) mpc561/mpc563 reference manual, rev. 1.2 12-10 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-1 chapter 13 qadc64e legacy mode operation the two queued analog-to-digital converter (qadc) modules on mp c561/mpc563 devices are 10-bit, unipolar, successive approximation conve rters. the modules can be confi gured to operate in one of two modes, legacy mode (mpc555 compat ible) and enhanced mode. this ch apter describes how the modules operate in legacy mode, which is the default mode of operation. refer to chapter 14, ?qadc64e enhanced mode operation ,? for information regarding the qadc 64e functionality in enhanced mode. for this revision of the qadc, the name qadc64e implies the enhanced version of the qadc module, not just enhanced mode of ope ration. for simplicity, the names qadc and qadc64e may be used interchangeably throughout this document. 13.1 qadc64e block diagram figure 13-1 displays the major components of th e qadc64e modules on the mpc561/mpc563. figure 13-1. qadc64e block diagram queues of 10-bit conversion command words (ccw ), 64 entries bus interface unit digital control 10-bit result table, 64 entries 10-bit to 16-bit result alignment 10-bit analog to digital converter analog input multiplexor and digital signal functions external triggers external mux address up to 16 analog input signals reference inputs analog power inputs imb3 (biu) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-2 freescale semiconductor 13.2 key features and quick reference diagrams this section gives an overview of the im plementation of the two qadc64e modules on mpc561/mpc563. it can also be used as a quick reference guide while programming the modules. 13.2.1 features of the qadc 64e legacy mode operation ? internal sample and hold ? directly supports up to four external multiplexers (for example the mc14051) ? up to 41 analog input channels us ing qadc64e external multiplexing ? programmable input sample time for various source impedances ? minimum conversion time of 7 s (w ith typical qclk frequency, 2 mhz) ? two conversion command queues with a total of 64 entries ? sub-queues possible using pause mechanism ? queue complete and pause software interrupts available on both queues ? queue pointers indicate cu rrent location for each queue ? automated queue modes initiated by ? external edge trigger ? periodic/interval timer, within qadc64e module ? software command ? external gated trigger (queue 1 only) ? single-scan or continuous-scan of queues ? 64 result registers in each qadc64e module ? output readable in three formats ? right-justified unsigned ? left-justified signed ? left-justified unsigned ? unused analog channels on port a can be used as digital input/output signals, unused analog channels on port b can be us ed as digital input signals. the analog section includes input signals, an analog mu ltiplexer, and the sample and hold circuits. the analog conversion is performed by th e digital-to-analog converter (dac ) resistor-capacitor array and a high-gain comparator. the digital control section contains queue control logic to sequence th e conversion process and interrupt generation logic. also included are th e periodic/interval timer, control a nd status registers, the conversion command word (ccw) table ram, and the result table ram. the bus interface unit (biu) allows the qadc64e to operate with the applicat ions software through the imb3 environment. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-3 13.2.2 memory map the qadc64e occupies 1 kbyte, or 512 16-bit entries, of address space. ten 16-b it registers are control, port, and status registers, 64 16-bit entries are the ccw table, and 64 16-bit entries are the result table, and occupy 192 16-bit address locations because the result da ta is readable in three data alignment formats. each qadc64e module on the mpc561/mp c563 has its own memory space. table 13-1 shows the memory map for qadc64e module a, it occupies 0x30 4800 to 0x30 4bff. table 13-2 displays the memory map for module b. module b has the same offset scheme starting at 0x30 4c00. qadc64e b occupies 0x30 4c00 to 0x30 4fff. z table 13-1. qadc64e_a address map address msb lsb register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4800 stop frz loc k fli p supv module config. 1 1 registers are accessible only as supervisor data space 0x30 4802 test mode te s t 1 0x30 4804 irl1 irl2 interrupt 1 0x30 4806 portqa portqb port data 0x30 4808 ddrqa port direction 0x30 480a emu x tr g psh psa psl control 0 0x30 480c cie1 pie 1 sse 1 mq1 control 1 0x30 480e cie2 pie 2 sse 2 mq2 resum e bq2 control 2 0x30 4810 cf1 pf1 cf2 pf2 tor 1 tor 2 qs cwp status 0 0x30 4812 cwpq1 cwpq2 status 1 0x30 4814- 0x30 49ff reserved 0x30 4a00- 0x30 4a7f pby p ist chan ccws 0x30 4a80- 0x30 4aff 0000 00 unsigned right justified results 0x30 4b00- 0x30 4b7f sign signed left justified 00 0000 results 0x30 4b80 0x30 4bff unsigned left justified 00 0000 results qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-4 freescale semiconductor accesses to supervisor-only data space is permitted onl y when the bus master is operating in supervisor access mode. assignable data space can be either restricted to supervis or-only access or unrestricted to both supervisor and user data space addresses. see section 13.3.1.4, ?supervisor /unrestricted address space .? 13.2.3 legacy and enhan ced modes of operation the qadc64e modules can be configured to operate in legacy or enhanced mode. legacy mode is the default state out of reset. conf iguring bits in the qadc64e modul e configuration register enables table 13-2. qadc64e_b address map address msb lsb register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4c00 sto p frz loc k fli p supv module config. 1 1 registers are accessible only as supervisor data space 0x30 4c02 test mode te s t 1 0x30 4c04 irl1 irl2 interrupt 1 0x30 4c06 portqa portqb port data 0x30 4c08 ddrqa port direction 0x30 4c0a emu x trg psh ps a psl control 0 0x30 4c0c cie1 pie 1 sse 1 mq1 control 1 0x30 4c0e cie2 pie 2 sse 2 mq2 resum e bq2 control 2 0x30 4c10 cf1 pf1 cf2 pf2 tor 1 tor 2 qs cwp status 0 0x30 4c12 cwpq1 cwpq2 status 1 0x30 4c14- 0x30 4dff reserved 0x30 4e00- 0x30 4e7f p byp ist chan ccws 0x30 4e80- 0x30 4eff 0000 00 unsigned right justified results 0x30 4f00- 0x30 4f7f sign signed left justified 00 0000 results 0x30 4f80 0x30 4fff unsigned left justified 00 0000 results qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-5 enhanced mode. this will be described in section 13.3.1.3, ?switching between legacy and enhanced modes of operation .? 13.2.4 using the queue and result word table the heart of the qadc is its c onversion command word (ccw) queues. this is where the module is programmed to convert a pa rticular channel according to a particular requireme nt. the queues are created by writing ccws into the ccw table in the regist er memory. the queues are controlled by the three control registers, and their status can be read from the two status regi sters. as conversions are completed the digital value is written into the result word table. figure 13-2 shows the ccw queue and the result word table. figure 13-2. qadc64e conversion queue operation 13.2.5 external multiplexing the qadc can use from one to four 8-input external multiplexer chips to expand the number of analog signals that may be converted. the externally multip lexed channels are automatically selected from the conversion command word (ccw) table 00 bq2 a/d converter result word table 00 channel select, sample, hold, and analog to digital conversion begin queue 1 begin queue 2 end of queue 1 end of queue 2 p byp ist chan 10-bit conversion command word (ccw) format 10-bit result is software readable in three different 16-bit formats p = pause until next trigger byp = bypass buffer amplifier ist = input sample time chan = channel number and end_of_queue code result s result 0 right justified, unsigned result format left justified, unsigned result format left justified, signed result format 15 0 15 0 result 15 0 00 00 0 000 00 0 000 00 0 msb 5 6 msb lsb lsb 8 6 9 10 15 7 9 10 9 10 1 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-6 freescale semiconductor channel field of the conversion command word (ccw ) table. external multiplex mode is software selectable, by setting the emux bi t of control register 0, qacr0. figure 13-3 shows the maximum configurati on of four external multiplexe r chips connected to the qadc. the qadc provides three multiplexer address signals ? ma[0], ma[1], ma[2] ? to select one of the multiplexer chips. these outputs are the multiplexer c ontrol lines and they are connected to all external multiplexer chips. the analog output of each of the four multiplexer chips is connected to four se parate qadc inputs ? anw, anx, any, anz. these signals are the first four signals of port b and each one can represent eight analog input channels. the qadc converts the proper input channel (anw, an x, any, anz) by interpreting the channel number in the ccw. refer to table 13-3 . figure 13-3. example of external multiplexing in the external multiplexed mode, four of the port b signals are redefined to each represent eight input channels. refer to table 13-3 for more information. an[52]/ma[0]/pqa[0] an[53]/ma[1]/pqa[1] an[54]/ma[2]/pqa[2] an[55]/pqa[3] an[56]/pqa[4] an[57]pqa[5] an[58]/pqa[6] an[59]/pqa[7] an[0]/anw/pqb[0] an[1]/anx/pqb[1 ] an[2]/any/pqb[2 ] an[3]/anz/pqb[3] an[48]/pqb[4] an[49]/pqb[5] an[50]/pqb[6] an[51]/pqb[7] v dda v ssa v rl v rh mux an[0] an[2] an[6] an[8] an[10] an[12] an[14] mux mux mux analog power analog references port b port a qadc digital control analog converter analog multiplexer port logic and etrig1 etrig2 external triggers: an[4] an[1] an[3] an[7] an[9] an[11] an[13] an[15] an[5] an[16] an[18] an[22] an[24] an[26] an[28] an[30] an[20] an[17] an[19] an[23] an[25] an[27] an[29] an[31] an[21] qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-7 i table 13-4 shows the total number of analog input channe ls supported with zero to four external multiplexer chips using one qadc module. note: qadc64e external mux users if either qadc64e_a or qadc64e_b is in external multiplexing (emux) mode then the multiplexer address signal channels, an[52:54] should not be programmed into queues. 13.3 programming the qadc64e registers the qadc64e has three global register s for configuring module operation: ? module configuration register ( section 13.3.1, ?qadc64e module configuration register (qadmcr) ?) ? interrupt register ( section 13.3.2, ?qadc64e interrupt register (qadcint) ? ? test register (qadctes t) for factory tests. the global registers are always defined to be in supervisor-only data space. refer to table 13-1 for the qadc64e_a address map and table 13-2 for the qadc64e_b address map. see section 13.3.1.4, ?supervisor/unrestricted address space ? for access modes of these registers. the remaining five registers in th e control register block control th e operation of the queuing mechanism, and provide a means of monito ring the operation of the qadc64e. ? control register 0 (qacr0 ) contains hardware configuration information ( section 13.3.5, ?control register 0 (qacr0) ?) ? control register 1 (qacr1) is associated with queue 1 ( section 13.3.6, ?control register 1 (qacr1) ?) ? control register 2 (qacr2) is associated with queue 2 ( section 13.3.7, ?control register 2 (qacr2) ?) table 13-3. multiplexed analog input channels multiplexed analog input channels anw (an[0]) 0, 2, 4, 6, 8, 10, 12, 14 anx (an[1]) 1, 3, 5, 7, 9, 11, 13, 15 any (an[2]) 16, 18, 20, 22, 24, 26, 28, 30 anz (an[3]) 17, 19, 21, 23, 25, 27, 29, 31 table 13-4. analog input channels number of analog inpu t channels available directly connected + external multiplexed = total channels no external mux chips one external mux chip two external mux chips three external mux chips four external mux chips 16 20 27 34 41 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-8 freescale semiconductor ? status registers (qasr0 and qasr1) provide vi sibility on the status of each queue and the particular conversion th at is in progress ( section 13.3.8, ?status registers (qasr0 and qasr1) ?) the ccw table follows the register block in the addr ess map. there are 64 table entries to hold the desired analog conversion sequences. each ccw table entry is 16-bits, with ten im plemented bits in four fields. the final block of address space belongs to the result word table, which appears in three places in the memory map. each result word table lo cation holds one 10-bi t conversion value. 13.3.1 qadc64e module config uration register (qadmcr) the qadcmcr contains five implem ented bits that control the operating modes of the qadc64e module. the configurable modes ar e freeze, stop and supervisor. the qadcmcr also imp lements a pair of bits that together sel ect either legacy or enhanced mode for the qadc module, and lock that operating mode. . msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field stop frz ? lock flip supv ? sreset 0000_0000 1 000_0000 addr 0x30 4800 (qadcmcr_a); 0x30 4c00 (qadcmcr_b) figure 13-4. module confi guration regist er (qadcmcr) table 13-5. qadcmcr bit descriptions bits name description 0 stop stop enable. refer to section 13.3.1.1, ?low power stop mode ,? for more information. 0 = disable stop mode 1 = enable stop mode 1 frz freeze enable. refer to section 13.3.1.2, ?freeze mode ,? for more information. 0 = ignores the imb3 internal freeze signal 1 = finish any conversion in progress, then freeze 2:5 ? reserved 6 lock lock/unlock qadc mode of operation as defined by flip bit. refer to section 13.3.1.3, ?switching between legacy and enhanced modes of operation ,? for more information. 0 = qadc mode is locked 1 = qadc mode is unlocked and changeable using flip bit 7 flip qadc mode of operation ? the flip bit allows selection of the mode of operation of the qadc module, either legacy mode (default) or enhanced mode. this bit can only be written when the lock is set (unlocked). refer to section 13.3.1.3, ?switchin g between legacy and enhanced modes of operation ,? for more information. 0 = legacy mode enabled 1 = enhanced mode enabled qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-9 13.3.1.1 low power stop mode when the stop bit in the qadcmcr is set, th e qadc64e clock (qclk) which clocks the a/d converter, is disabled and the an alog circuitry is powered down. this results in a static, low power consumption, idle condition. the stop mode aborts any convers ion sequence in progre ss. because the bias currents to the analog circuits are turned off in st op mode, the qadc64e require s some recovery time (t sr in appendix f, ?electri cal characteristics ?) to stabilize the analog circuits after the stop enable bit is cleared. in stop mode: ? biu state machine and logic do not shut down ? the ccw and result is not reset and is not accessible ? the module configuratio n register (qadcmcr), the interrupt register (qadcint ), and the test register (qadctest) are fully accessible and are not reset ? the data direction register (d drqa), port data register (portq a/portqb), and control register 0 (qacr0) are not reset a nd are read-only accessible ? control register 1 (qacr1), cont rol register 2 (qacr2), and th e status registers (qasr0 and qasr1) are reset and ar e read-only accessible ? in addition, the periodic/interval time r is held in reset during stop mode if the stop bit is clear, stop mode is disabled. 13.3.1.2 freeze mode freeze mode occurs when the bac kground debug mode is enabled in the usiu and a breakpoint is encountered. this is indicated by th e assertion of the internal freeze line on the imb3. the frz bit in the qadcmcr determines whether or not the qadc 64e responds to an imb3 internal freeze signal assertion. freeze is very useful when debugging an application. when the internal freeze signal is asserted and the frz bit is set, the qadc64e finish es any conversion in progress and then freezes. depending on when the freeze signal is asserted, th ere are three possible que ue "freeze" scenarios: ? when a queue is not executing, the qadc64e freezes immediately ? when a queue is executing, the qadc64e completes the conversion in progress and then freezes 8 supv supervisor/unrestricted data space. refer to section 13.3.1.4, ?supervisor/unrestricted address space ,? and table 13-6 for more information. 0 = only the module configuration register, test register, and interrupt register are designated as supervisor-only data space. access to all other locations is unrestricted. 1 = all qadc64e registers and ccw/result tables are designated as supervisor-only data space. 9:15 ? reserved. write as zeros. table 13-5. qadcmcr bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-10 freescale semiconductor ? if, during the execution of the current conversi on, the queue operating mode for the active queue is changed, or a queue 2 abort occu rs, the qadc64e fr eezes immediately during freeze mode, both the analog clock, qclk, and peri odic/interval timer are he ld in reset. when the qadc64e enters the freeze mode while a queue is act ive, the current ccw location of the queue pointer is saved. during freeze, the analog clock, qclk, is held in reset and the periodic/in terval timer is held in reset. external trigger events that occur during the fre eze mode are not captured. the biu remains active to allow imb3 access to all qadc64e registers and ra m. although the qadc64e saves a pointer to the next ccw in the current queue, the software can force the qadc64e to execute a different ccw by writing new queue operating modes for normal ope ration. the qadc64e looks at the queue operating modes, the current queue pointer, a nd any pending trigger events to d ecide which ccw to execute when exiting freeze. if the frz bit is clear, the internal freeze signal is ignored. 13.3.1.3 switching between legacy and enhanced mode s of operation the lock and flip bits of the qadcmcr regist er control the operating mode of the qadc64e modules. out of reset, the qadc64e modules are in le gacy mode (flip = 0) and the lock bit is clear, indicating that the module is locked in legacy mode. in order to change the value of the flip bit, the operating mode must first be unlocke d, by setting the lock bit. only then can the fl ip bit be changed. finally, the lock bit must be cleared again to prot ect the state of the flip bit from future writes. 1. write lock = 1 to unl ock operating mode bit. 2. modify the value of flip as required. ? flip = 0 legacy mode enabled ? flip = 1 enhanced mode enabled 3. write lock = 0 and new flip bit valu e to preserve the value of flip bit ? example 1 switching from legacy mode to enhanced mode ? qadcmcr = 0x280; lo ck =1, supv = 1 ? qadcmcr = 0x380; lock =1, write flip = 1, supv = 1 ? qadcmcr = 0x180; lock = 0, flip = 1, supv = 1 subsequent writes to the flip bit wi ll have no effect while lock = 0. ? example 2 switching from e nhanced mode to legacy mode ? qadcmcr = 0x280 or 0x380; lock = 1, supv =1 (can write flip = x because value will not change) ? qadcmcr = 0x280; lock = 1, flip = 0, supv = 1 ? qadcmcr = 0x080; lock = 0, flip = 0, supv =1 13.3.1.4 supervisor/unrest ricted address space the qadc64e memory map is divided into two segments: supervisor-onl y data space and assignable data space. access to supervisor-only data space is permitted only when the software is operating in supervisor qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-11 access mode. assignable data space can be either restricted to supervis or-only access or unrestricted to both supervisor and user data sp ace accesses. the supv bit in th e qadcmcr designates the assignable space as supervisor or unrestricted. the following information applies to accesses to address space located within the module?s 16-bit boundaries and where the res ponse is a bus error. see table 13-6 for more information. ? attempts to read a supervisor-only data space when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus er ror condition. no data is returned. if supv = 0, the qadc64e asserts a bus error c ondition and no data is returned. ? attempts to write to s upervisor-only data space when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus error condition. no data is written. if supv = 0, the qadc64e asserts a bus error conditi on and the register is not written. ? attempts to read unimplemented data space in the unrestricted access mode and supv = 1, causes the bus master to assert a bus error condition and no data is returned. in all other attempts to read unimplemented data space, the qadc64e causes a bus error condition and no data is returned. ? attempts to write unimple mented data space in the unrestric ted access mode and supv = 1, causes the bus master to assert a bus error condition and no data is written. in all other attempts to write unimplemented data space, the qadc64e causes a bus error condition a nd no data is written. ? attempts to read assignable data space in the unrestricted access mode when the space is programmed as supervisor space caus es the bus master to assert a bus error condition and no data is returned. ? attempts to write assignable data space in th e unrestricted access mode when the space is programmed as supervisor space causes the bus master to assert a bus error condition and the register is not written. the bus master indicates the supervisor and user spa ce access with the function c ode bits (fc[2:0]) on the imb3. for privilege violations, refer to the chapter 9, ?external bus interface ? to determine the consequence of a bus er ror cycle termination. table 13-6. qadc64e bus error response s/u 1 mode 1 s/u = supervisor/unrestricted supv bit supervisor-only register supervisor/ unrestricted register reserved/ unimplemented register u 0 qadc64e bus error 2 2 qadc64e bus error = caused by qadc64e valid access 4 qadc64e bus error 2 u 1 master bus error 3 3 master bus error = caused by bus master 4 access to qadctest register will act as a rese rved/unimplemented register unless in factory test mode master bus error 3 master bus error 3 s 0 valid access valid access qadc64e bus error 2 s 1 valid access valid access qadc64e bus error 2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-12 freescale semiconductor the supervisor-only data space se gment contains the qadc64e globa l registers, which include the qadcmcr, the qadctest, and the qadcint. the s upervisor/unrestricted sp ace designation for the ccw table, the result word table, and the remaining qadc64e regi sters is programmable. 13.3.2 qadc64e interrupt register (qadcint) qadcint specifies the priority leve l of qadc64e interrupt requests. th e interrupt level for queue 1 and queue 2 may be different. th e interrupt register is read/write accessi ble in supervisor da ta space only. the implemented interrupt register fields can be read and written, reserved bits read zero and writes have no effect. they are typically written once when the software init ializes the qadc64e, and not changed afterwards. the qadc64e conditionally generates interrupts to the bus master via the imb3 irq signals. when the qadc64e sets a status bit assigned to generate an interrupt, the qadc64e drives the irq bus. the value driven onto irq[7:0] represents th e interrupt level assigned to the inte rrupt source. under the control of ilbs, each interrupt request level is driven during th e time multiplexed bus during one of four different time slots, with eight levels comm unicated per time slot. no hardware pr iority is assigned to interrupts. furthermore, if more than one source on a module re quests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 13-6 displays the interrupt levels on irq with ilbs. refer to chapter 12, ?u-bus to imb3 bus interface (uimb) ,? for more information. msb 01234567891011121314 lsb 15 field irl1 irl2 ? sreset 0000_0000_0000_0000 addr 0x30 4804 (qadcint_a ); 0x30 4c04 (qadcint_b) figure 13-5. qadc interr upt register (qadcint) table 13-7. qadcint bit descriptions bit(s) name description 0:4 irl1 queue 1 interrupt request level. the irl1 fiel d establishes the queue 1 interrupt request level. the 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. all interrupts are presented on the imb3. interrupt leve l priority software determines which level has the highest priority request. 5:9 irl2 queue 2 interrupt request level. the irl2 fiel d establishes the queue 2 interrupt request level. the 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. all interrupts are presented on the imb3. interrupt leve l priority software determines which level has the highest priority request. 10:15 ? reserved. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-13 figure 13-6. interrupt levels on irq with ilbs 13.3.3 port data regist er (portqa and portqb) qadc64e ports a and b are accesse d through two 8-bit port data registers (portqa and portqb) in each qadc64e. port a signals are referred to as pqa[7:0] when used as 8-bit general-purpos e digital input or output signals. it is configured as a digital input or digita l output using the data dire ction register, ddrqa. when port a is configured as an input, a read of the po rtqa register returns the act ual pqa[7:0] signal values. when port a is configured as an output, the contents of port register pqa are driven on the port a signals. port a can also be used as analog inputs an[59:52] and external multiplexer address outputs ma[2:0]. port b signals are referred to as pqb[7:0] when us ed as 8-bit general-purpose digital input-only signals. digital input signal states are read from the 8-bit portqb register. port b can also be used as non-multiplexed analog inputs an[51:48] and an[3:0] , and external multiplexer analog inputs, anw, anx, any, anz. during a port data register read, the actual value of the signal is repor ted when its corr esponding bit in the data direction register defines the signal to be an input. when th e data direction bit sp ecifies the signal to be an output, the content of the port data register is read. portqa and portqb are not initialized by reset. msb 0 1234567 891011121314lsb 15 field pqa 7 pqa 6 pqa 5 pqa 4 pqa 3 pqa 2 pqa 1 pqa 0 pqb 7 pqb 6 pqb 5 pqb 4 pqb 3 pqb 2 pqb 1 pqb 0 sreset unaffected unaffected addr (portqa) 0x30 4806 ; 0x30 4c06 (portqb) 0x30 4807, 0x30 4c07 analog channel: an5 9 an5 8 an5 7 an5 6 an5 5 an5 4 an5 3 an5 2 an5 1 an5 0 an4 9 an4 8 an3 an2 an1 an0 multiplexed address outputs: ma2 ma1 ma0 figure 13-7. port x data register (portqa and portqb) imb3 clock ilbs [1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-14 freescale semiconductor 13.3.4 port data direction register (ddrqa) the port data direction register, ddr qa, is associated with port a digi tal input/output signals only. any bit set in this register configures the corresponding si gnal as an output. any bit cl eared in this register configures the corresponding signal as an input. the software is responsib le for ensuring that ddr bits are not set on signals used for analog inputs. when the ddr bit is set, thereby selecting the signal for analog conversion, the voltage sampled is that of the out put digital driver as influenced by the load. note caution should be exercised when mix ing digital and analog inputs. this should be isolated as much as possible. rise and fall times should be as large as possible to minimize ac coupling effects. there are two special cases to consider for the di gital i/o port operation. when qacr0[emux] is set, enabling external multiplexing, the data direction regi ster settings are ignored for the bits corresponding to portqa[2:0], which are the three multiplexed a ddress (ma[2:0]) output signa ls. the ma[2:0] signals are forced to be digital outputs, regardless of the da ta direction setting, and th e multiplexed address outputs are driven. the data returned during a port data register read is the valu e of the multiplexed address latches which drive ma[2:0], regardless of the data direction setting. 13.3.5 control register 0 (qacr0) control register 0 is used to define whether external multiplexing is enabled, assign external triggers to the conversion queues and to sets up the qclk presca ler parameter field. all of the implemented control multiplexed analog inputs: anz any anx anw table 13-8. portqa, portqb bit descriptions bits name description 0:7 pqa[7:0] port a signals are referred to as pqa when used as an 8-bit input/output port. port a can also be used for analog inputs (an[59:52]), and ex ternal multiplexer address outputs (ma[2:0]). 8:15 pqb[7:0] port b signals are referred to as pqb when used as an 8 input-only port. port b can also be used for non-multiplexed (an[51:48]/an[3:0]) and multiplexed (anz, any, anx, anw) analog inputs. msb 01234567891011121314 lsb 15 field ddq a7 ddq a6 ddq a5 ddq a4 ddq a3 ddq a2 ddq a1 ddq a0 ? sreset 0000_0000_0000_0000 addr 0x30 4808 (ddrqa_a); 0x30 4c08 (ddrqa_b) figure 13-8. port a data direction register (ddrqa) figure 13-7. port x data register (portqa and portqb) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-15 register fields can be read or written but reserved fields read zero and writes have no effect. typically, they are written once when software initializes the qadc64e and are not changed afterwards. note details of how to calculate values for psh, psa, and psl, as well as examples, are given in section 13.5.5, ?qadc64e clock (qclk) generation .? 13.3.6 control register 1 (qacr1) control register 1 is the mode co ntrol register for the operation of queue 1. the application software defines the queue operating mode for the queue, and may enable a completion a nd/or pause interrupt. all of the control register fields are read/write data. however, the sse1 bi t always reads as zero. most of the bits are typically written once when the software initializes the qa dc64e, and not changed afterwards. msb 0 1 2 34567891011121314 lsb 15 field emux ? trg ? psh psa psl sreset 0 00 0 000 0_0001 0 011 addr 0x30 480a (qacr0_a); 0x30 4c0a (qacr0_b) figure 13-9. control register 0 (qacr0) table 13-9. qacr0 bit descriptions bits name description 0 emux externally multiplexed mode. the emux bit c onfigures the qadc64e for externally multiplexed mode, which affects the interpreta tion of the channel numbers and forces the ma[2:0] signals to be outputs. see table 13-7 for more information. 0 internally multiplexed, 16 possible channels 1 externally multiplexed, 41 possible channels 1:2 ? reserved 3 trg trigger assignment. trg allows the software to assign the etrig[2:1] signals to queue 1 and queue 2. 0 etrig1 triggers queue 1; etrig2 triggers queue 2 1 etrig1 triggers queue 2; etrig2 triggers queue 1 refer to section 13.7.2, ?external trigger input signals .? 4:6 ? reserved 7:11 psh prescaler clock high time. the psh field selects the qclk high time in the prescaler. psh value plus 1 represents the high time in imb3 clocks 12 psa note that this bit lo cation is maintained for soft ware compatibility with pr evious versions of the qadc64e. it serves no functional benefit in the mpc561/mpc563 and is not operational. 13:15 psl prescaler clock low time. the psl field selects the qclk low time in the prescaler. psl value plus 1 represents the low time in imb3 clocks qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-16 freescale semiconductor msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field cie1 pie1 sse1 mq1 ? sreset 0000_0000_0000_0000 addr 0x30 480c (qacr1_a); 0x30 4c0c (qacr1_b) figure 13-10. control register 1 (qacr1) table 13-10. qacr1 bit descriptions bits name description 0 cie1 queue 1 completion interrupt enable. cie1 enables an interrupt upon completion of queue 1. the interrupt request is initiated when the conversion is complete for the ccw in queue 1. 0 disable the queue completion interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 1 1 pie1 queue 1 pause interrupt enable. pie1 enables an interrupt when queue 1 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 1 which has the pause bit set 2 sse1 queue 1 single-scan enable bit. sse1 enab les a single-scan of queue 1 to start after a trigger event occurs. the sse1 bit may be se t to a one during th e same write cycle when the mq1 bits are set for one of the single-scan queue operating modes . the single-scan enable bit can be written as a one or a zero, but is always read as a zero. the sse1 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 1. the qadc64e clears the sse1 bit when the singl e-scan is complete. refer to table 13-11 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 1 in a single-scan mode 3:7 mq1 queue 1 operating mode. the mq1 field se lects the queue operating mode for queue 1. table 13-11 shows the bits in the mq1 field which enable different queue 1 operating mode 8:15 ? reserved table 13-11. queue 1 operating modes mq1[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse1) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-17 13.3.7 control register 2 (qacr2) control register 2 is the mode cont rol register for the operation of que ue 2. software specifies the queue operating mode of queue 2, and may enable a completio n and/or a pause interrupt . all control register fields are read/write data, except the sse2 bit, which is readable only when the test m ode is enabled. most of the bits are typically written once when the software initializes the qadc64e, and not changed afterwards. 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 external gated single-sc an mode (started with sse1) 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 1 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 external gated continuous-scan mode table 13-11. queue 1 operating modes (continued) mq1[3:7] operating modes qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-18 freescale semiconductor msb 0 1 2 34567 8 91011121314 lsb 15 field cie2 pie2 sse2 mq2 resume bq2 sreset 0 0 0 0_0000 0 111_1111 addr 0x30 480e (qacr2_a), 0x30 4c0e (qacr2_b) figure 13-11. control register 2 (qacr2) table 13-12. qacr2 bit descriptions bits name description 0 cie2 queue 2 completion software interrupt enable. cie2 enables an interrupt upon completion of queue 2. the interrupt request is initiated w hen the conversion is complete for the ccw in queue 2. 0 disable the queue completion interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 2 1 pie2 queue 2 pause software interrupt enable. pie2 enables an interrupt when queue 2 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 2 which has the pause bit set 2 sse2 queue 2 single-scan enable bit. sse2 enables a single-scan of queue 2 to start after a trigger event occurs. the sse2 bit may be set to a one during the same write cycle when the mq2 bits are set for one of the single-scan queue operating modes. the single-scan enable bit can be written as a one or a zero, but is always read as a zero. the sse2 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 2. the qadc64e clears the sse2 bit when the single-scan is complete. refer to table 13-13 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 2 in a single-scan mode 3:7 mq2 queue 2 operating mode. the mq2 field sele cts the queue operating mode for queue 2. refer to table 13-13 for more information. 8 resume 0 after suspension, begin executing with the first ccw in queue 2 or the current sub-queue 1 after suspension, begin executing with the aborted ccw in queue 2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-19 table 13-13 shows the bits in the mq2 field that enable different queue 2 operating modes. 9:15 bq2 beginning of queue 2. the bq2 field indicates the ccw location where queue 2 begins. to allow the length of queue 1 and queue 2 to vary, a programmable pointer identifies the ccw table location where queue 2 begins. the bq2 field also serves as an end-of-queue condition for queue 1. setting bq2 beyond physical ccw table memory space allows queue 1 all 64 entries. software defines the beginning of queue 2 by programming the bq2 field in qacr2. bq2 is usually programmed before or at the same time as the queue operating mode for queue 2 is selected. if bq2 is 64 or greater, queue 2 has no entries, and the entire ccw table is dedicated to queue 1 and ccw63 is the end-of-queue 1. if bq2 is zero, the entire ccw table is dedicated to queue 2. as a special case, when a queue operating mode for queue 1 is selected and a trigger event occurs for queue 1 with bq2 set to zero, queue 1 execution is terminated after ccw0 is read. conversions do not occur. the bq2 pointer may be changed dynamically, to alternate between queue 2 scan sequences. a change in bq2 after queue 2 has begun or if queue 2 has a trigger pending does not affect queue 2 until queue 2 is started again.for example, two scan sequences could be defined as follows: the first sequence starts at ccw10, with a pause after ccw11 and an eoq programmed in ccw15; the second sequence starts at ccw16, with a pause after ccw17 and an eoq programmed in ccw39. with bq2 set to ccw10 and the continuous-scan mode selected, queue execution begins. when the pause is encountered in ccw11, a soft ware interrupt routine can redefine bq2 to be ccw16. therefore, after the end- of-queue is recognized in ccw15, an internal retrigger event is generated and execution restarts at ccw16. when the pause software interrupt occurs again, software can change bq2 back to ccw10. after the end-of-queue is recognized in ccw39, an internal retrigger event is created and execution now restarts at ccw10. if bq2 is changed while queue 1 is active, the ef fect of bq2 as an end-of-queue indication for queue 1 is immediate. however, beware of the risk of losing the end-of-queue 1 through moving bq2. recommend use of eoq (chan63) to end queue 1. note: be sure to do a mode change when changi ng bq2 and setting sse2. setting bq2 first is recommended. table 13-13. queue 2 operating modes mq2[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse2) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 01010 interval timer single-scan mode: time = qclk period x 2 13 table 13-12. qacr2 bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-20 freescale semiconductor note if bq2 was assigned to the ccw that queue 1 is currently working on, then that conversion is completed before bq2 takes effect. each time a ccw is read for queue 1, the ccw locati on is compared with the current value of the bq2 pointer to detect a possibl e end-of-queue condition. for example, if bq2 is changed to ccw3 while queue 1 is converting ccw2, queue 1 is terminated after the conversion is completed. however, if bq2 is changed to ccw1 while queue 1 is converting ccw2, the qadc64e would not recognize a bq2 end-of-queue condition until queue 1 execution r eached ccw1 again, presumably on the next pass through the queue. 13.3.8 status register s (qasr0 and qasr1) the status registers contains info rmation about the state of each que ue and the current a/d conversion. except for the four flag bits (cf1, pf1, cf2, and pf2 ) and the two trigger overr un bits (tor1 and tor2), 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 reserved mode 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 13 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 reserved mode table 13-13. queue 2 operating modes (continued) mq2[3:7] operating modes qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-21 all of the status register fields c ontain read-only data. the four flag bits and the two tr igger overrun bits are cleared by writing a zero to the bit after the bit was previously read as a one. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field cf1 pf1 cf2 pf2 tor1 tor2 qs cwp sreset 0000_0000_0000_0000 addr 0x30 4810 (qasr0_a); 0x30 4c10 (qasr0_b) figure 13-12. status register 0 (qasr0) table 13-14. qasr0 bit descriptions bits name description 0 cf1 queue 1 completion flag. cf1 indicates that a queue 1 scan has been completed. the scan completion flag is set by the qadc64e when the input channel sample requested by the last ccw in queue 1 is converted, and the result is stored in the result table. the end-of-queue 1 is i dentified when execution is complete on the ccw in the location prior to that pointed to by bq2, when the current ccw cont ains an end-of-queue code instead of a valid channel number, or when t he currently completed ccw is in the last location of the ccw ram. when cf1 is set and interrupts are enabled for that queue completion flag, the qadc64e asserts an interrupt request at the level specified by irl1 in the interrupt register (qadcint). the software reads the completion flag during an interrupt service routine to identify the interrupt request. the interrupt re quest is cleared when t he software writes a zero to the completion flag bit, when the bit was previously read as a one. once set, only software or reset can clear cf1. cf1 is maintained by the qadc64e regardless of whether the corresponding interrupt is enabled. the software polls for cf1 bit to see if it is set. this allows the software to recognize that the qadc64e is finished with a queue 1 scan. the software acknowledges that it has detected the comple tion flag being set by writing a zero to the completion flag after the bit was read as a one. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-22 freescale semiconductor 1 pf1 queue 1 pause flag. pf1 indicates that a queue 1 scan has reached a pause. pf1 is set by the qadc64e when the current queue 1 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf1 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, if th e ccw with the pause bit set is the last ccw in a queue, the queue execution is complete. the queue status becom es idle, not paused, and both the pause and completion flags are se t. another exception occurs in software controlled mode, where the pf1 can be set bu t queue 1 never enters the pause state since queue 1 continues without pausing. when pf1 is set and interrupts are enabled for the corresponding queue, the qadc64e asserts an interrupt request at the level spec ified by irl1 in the interrupt register. the software may read pf1 during an interrupt serv ice routine to identify the interrupt request. the interrupt request is cleared when the softwa re writes a zero to pf1, when the bit was previously read as a one. once set, only software or reset can clear pf1. in external gated single-scan and continuou s-scan mode the definition of pf1 has been redefined. when the gate closes before the end-of-queue 1 is reached, pf1 becomes set to indicate that an incomple te scan has occurred.in single-scan mode, setting pf1 can be used to cause an interrupt and software can then determine if queue 1 should be enabled again. in either external gated mode, setting pf1 indicates that the results for queue 1 have not been collected during one scan (coherently). note: if a pause in a ccw is encountered in external gated mode for either single-scan and continuous-scan mode, the pause flag will not set, and execution continues without pausing. this has allowed for the added definition of pf1 in the external gated modes. pf1 is maintained by the qadc64e regardle ss of whether the corresponding interrupts are enabled. the software may poll pf1 to find out when the qadc64e has reached a pause in scanning a queue.the software ackn owledges that it has detected a pause flag being set by writing a zero to pf1 after the bit was last read as a one. 0 = queue 1 has not reached a pause (or gate has not closed before end-of-queue in gated mode) 1 = queue 1 has reached a pause (or gate cl osed before end-of-queue in gated mode) refer to table 13-15 for a summary of pause response in all scan modes. 2 cf2 queue 2 completion flag. cf2 indicates that a queue 2 scan has been completed. cf2 is set by the qadc64e when the input channel sample requested by the last ccw in queue 2 is converted, and the result is stored in the result table. the end-of-queue 2 is identif ied when the current ccw contains an end-of-queue code instead of a valid channel number, or when t he currently completed ccw is in the last location of the ccw ram. when cf2 is set and interrupts are enabled for that queue completion flag, the qadc64e asserts an interrupt request at the level specified by irl2 in the interrupt register (qadcint). the software reads cf2 during an interrupt service rout ine to identify the interrupt request. the interrupt request is clear ed when the software writes a zero to the cf2 bit, when the bit was previously read as a one. once set, only software or reset can clear cf2. cf2 is maintained by the qadc64e regardless of whether the corresponding interrupts are enabled. the software polls for cf2 to see if it is set. this allows the software to recognize that the qadc64e is finished with a queue 2 scan. the software acknowledges that it has detected the comple tion flag being set by writing a zero to the completion flag after the bit was read as a one. table 13-14. qasr0 bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-23 3 pf2 queue 2 pause flag. pf2 indicates that a queue 2 scan has reached a pause. pf2 is set by the qadc64e when the current queue 2 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf2 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, if th e ccw with the pause bit set is the last ccw in a queue, the queue execution is complete. the queue status becom es idle, not paused, and both the pause and completion flags are se t. another exception occurs in software controlled mode, where the pf2 can be set but queue 2 never enters the pause state. when pf2 is set and interrupts are enabled for the corresponding queue, the qadc64e asserts an interrupt request at the level spec ified by irl2 in the interrupt register. the software reads pf2 during an interrupt service routine to identify the interrupt request. the interrupt request is cleared when the software writes a zero to pf2, when the bit was previously read as a one. once set, only software or reset can clear pf2. pf2 is maintained by the qadc64e regardle ss of whether the corresponding interrupts are enabled. the software may poll pf2 to find out when the qadc64e has reached a pause in scanning a queue. the software ackno wledges that it has detected a pause flag being set by writing a zero to pf2 after the bit was last read as a one. 0 queue 2 has not reached a pause 1 queue 2 has reached a pause refer to table 13-15 for a summary of pause response in all scan modes. 4 tor1 queue 1 trigger overrun. tor1 indicates that an unexpected trigger event has occurred for queue 1. tor1 can be set only while queue 1 is in the active state. a trigger event generated by a transition on the external trigger signal or by the periodic/interval timer may be captured as a trigger overrun. tor1 cannot occur when the software initiated single-scan mode or the so ftware initiated cont inuous-scan mode are selected. tor1 occurs when a trigger event is received while a queue is executing and before the scan has completed or paused. tor1 has no effect on the queue execution. after a trigger event has occurred for queue 1, and before the scan has completed or paused, additional queue 1 trigger events ar e not retained. such trigger events are considered unexpected, and the qadc64e sets the tor1 error status bit. an unexpected trigger event may be a system overrun situation, indicating a system loading mismatch. in external gated continuous-scan mode the de finition of tor1 has been redefined. in the case when queue 1 reaches an end-of-queue condition for the second time during an open gate, tor1 becomes set. this is considered an overrun condition. in this case cf1 has been set for the first end-of-queue 1 condition and then tor1 becomes set for the second end-of-queue 1 condition. for tor1 to be se t, software must not clear cf1 before the second end-of-queue 1. the software acknowledges that it has detect ed a trigger overrun being set by writing a zero to the trigger overrun, after the bit was read as a one. once set, only software or reset can clear tor1. 0 no unexpected queue 1 trigger events have occurred 1 at least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an end-of-queue condition for the second time in gated mode) table 13-14. qasr0 bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-24 freescale semiconductor 5 tor2 queue 2 trigger overrun. tor2 indicates that an unexpected trigger event has occurred for queue 2. tor2 can be set when queue 2 is in the active, suspended, and trigger pending states. the tor2 trigger overrun can only occur when using an external trigger mode or a periodic/interval timer mode. trigger overruns cannot occur when the software initiated single-scan mode and the software initiated continuous-scan mode are selected. tor2 occurs when a trigger event is received while queue 2 is executing, suspended, or a trigger is pending. tor2 has no effect on the queue execution. a trigger event that causes a trigger overrun is not retained since it is considered unexpected. an unexpected trigger event may be a system overrun sit uation, indicating a system loading mismatch. the software acknowledges that it has detected a trigger overrun being set by writing a zero to the trigger overrun, after the bit was read as a one. once set, only software or reset can clear tor2. 0 no unexpected queue 2 trigger events have occurred 1 at least one unexpected queue 2 trigger event has occurred 6:9 qs queue status. the 4-bit read-only qs field indicates the current condition of queue 1 and queue 2. the following are the five queue status conditions: idle active paused suspended trigger pending the two most significant bits are associated primarily with qu eue 1, and the remaining two bits are associated with queue 2. since th e priority scheme between the two queues causes the status to be interlinked, the status bits are considered as one 4-bit field. table 13-16 shows the bits in the qs field and ho w they affect the status of queue 1 and queue 2. refer to section 13.6, ?trigger and queue interaction examples ,? which shows the 4-bit queue status field trans itions in typical situations. 10:15 cwp command word pointer. the cwp allows the software to know which ccw is executing at present, or was last completed. the comma nd word pointer is a software read-only field, and write operations have no effect. the cw p allows software to monitor the progress of the qadc64e scan sequence. the cwp field is a ccw word pointer with a valid range of 0 to 63. when a queue enters the paused state, the cwp points to the ccw with the pause bit set. while in pause, the cwp value is maintained until a trigger event occurs on the same queue or the other queue. usua lly, the cwp is updated a few clock cycles before the queue status field shows that the queue has become active. for example, software may read a cwp pointing to a ccw in queue 2, and the status field shows queue 1 paused, queue 2 trigger pending. when the qadc64e finishes the scan of the queue, the cwp points to the ccw where the end-of-queue (eoq) condition was dete cted. therefore, when the end-of-queue condition is a ccw with the eoq code (c hannel 63), the cwp points to the ccw containing the eoq. when the last ccw in a queue is in the last ccw table location (ccw63), and it does not contain the eoq code, the end-of-queue is de tected when the following ccw is read, so the cwp points to word ccw0. finally, when queue 1 operation is terminated after a ccw is read that is defined as bq2, the cwp points to the same ccw as bq2. during the stop mode, the cwp is reset to zero, since the control registers and the analog logic are reset. when the freeze mode is enter ed, the cwp is unchanged; it points to the last executed ccw. table 13-14. qasr0 bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-25 one or both queues may be in the id le state. when a queue is idle, ccws are not being executed for that queue, the queue is not in the pause st ate, and there is not a trigger pending. the idle state occurs when a queue is disabled, when a queue is in a rese rved mode, or when a queue is in a valid queue operating mode awaiting a tri gger event to initiate queue execution. table 13-15. pause response scan mode q operation pf asserts? external trigger single-scan pauses yes external trigger continuous-scan pauses yes periodic/interval timer trigger single-scan pauses yes periodic/interval timer continuous-scan pauses yes software initiated single-scan continues yes software initiated continuous-scan continues yes external gated single-scan continues no external gated continuous-scan continues no table 13-16. queue status qs[9:6] queue 1/queue 2 states 0000 queue 1 idle, queue 2 idle 0001 queue 1 idle, queue 2 paused 0010 queue 1 idle, queue 2 active 0011 queue 1 idle, queue 2 trigger pending 0100 queue 1 paused, queue 2 idle 0101 queue 1 paused, queue 2 paused 0110 queue 1 paused, queue 2 active 0111 queue 1 paused, queue 2 trigger pending 1000 queue 1 active, queue 2 idle 1001 queue 1 active, queue 2 paused 1010 queue 1 active, queue 2 suspended 1011 queue 1 active, queue 2 trigger pending 1100 reserved 1101 reserved 1110 reserved 1111 reserved qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-26 freescale semiconductor a queue is in the active state when a valid queue ope rating mode is selected, wh en the selected trigger event has occurred, or when the qadc64e is pe rforming a conversion spec ified by a ccw from that queue. only one queue can be active at a time. either or both queues can be in the paused state. a queue is paused when the previous ccw executed fr om that queue had the pause bit set. the qadc64e does not execute any ccws from the paused queue until a trigger event occurs. cons equently, the qadc64e can service queue 2 while queue 1 is paused. only queue 2 can be in the suspended state. when a trigger event occurs on queue 1 while queue 2 is executing, the current queue 2 convers ion is aborted. the queue 2 status is reported as suspended. queue 2 transitions back to the active state when queue 1 becomes idle or paused. a trigger pending state is required since both queues cannot be active at the same time. the status of queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. in the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, que ue 2 is aborted and the status is reported as queue 1 activ e, queue 2 suspended. so due to the priority scheme, only queue 2 can be in the trigger pending state. there are two transition cases which cause the queue 2 st atus to be trigger pending before queue 2 is shown to be in the active state. when queue 1 is active and there is a tr igger pending on queue 2, after queue 1 completes or pauses, queue 2 conti nues to be in the trigger pending state for a few clock cycles. the following are fleeti ng status conditions: ? queue 1 idle with queue 2 trigger pending ? queue 1 paused with queue 2 trigger pending figure 13-13 displays the status conditions of the queue status field as the qadc64e goes through the transition from queue 1 ac tive to queue 2 active. figure 13-13. qadc64e queue status transition the queue status field is affected by the stop mode. because all of th e analog logic and control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle. queue 1 queue 2 trigger pending trigger pending active idle active active idle (paused) idle (paused) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-27 during the freeze mode, the queue status field is not modified. the queue st atus field retains the status it held prior to freezing. as a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. 13.3.9 conversion command word table the conversion command word (ccw ) table is a ram, 64 words long on 16-bit address boundaries where 10-bits of each entry are implemented. a ccw can be programmed by the software to request a conversion of one analog input channel. the ccw table is writ ten by software and is not modified by the qadc64e. each ccw requests the conve rsion of an analog channel to a digita l result. the ccw specifies the analog channel number, the input sample t ime, and whether the queue is to pause after th e current ccw. the ten implemented bits of the ccw word are read/write data, where they may be written when the software initializes the qadc64e. the remaining 6-bits are unimplemented so these read as zeros, and write msb 0 1 234567 8 91011121314 lsb 15 field ? cwpq1 ? cwpq2 sreset 00 11_1111 00 11_1111 addr 0x30 4812 (qasr1_a); 0x30 4c12 (qasr1_b) figure 13-14. status register 1 (qasr1) table 13-17. qasr1 bit descriptions bits name description 0:1 ? reserved 2:7 cwpq1 command word pointer for q1 . cwpq1 a llows the software to know what ccw was last completed for queue 1 . this field is a software read-only field, and write operations have no effect. cwpq1 allows software to read t he last executed ccw in queue 1, regardless of which queue is active . the cwpq1 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq1 is updated wh en the conversion result is written . when the qadc64e finishes a conversion in queue 1, both the result register is written and the cwpq1 are updated . finally, when queue 1 operation is terminated after a ccw is read that is defined as bq2, cwp points to bq2 while cwpq1 points to the last ccw queue 1 . during the stop mode, the cwpq1 is reset to 63, since the control registers and the analog logic are reset. when the freeze mode is entered, the cwpq1 is unchanged; it points to the last executed ccw in queue 1. 8:9 ? reserved 10:15 cwpq2 command word pointer for q2. cwpq2 allows the software to know what ccw was last completed for queue 2 . this field is a software read-only field, and write operations have no effect. cwpq2 allows software to read t he last executed ccw in queue 2, regardless which queue is active . the cwpq2 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq2 is updated wh en the conversion result is written . when the qadc64e finishes a conversion in queue 2, both the result register is written and the cwpq2 are updated . during the stop mode, the cwpq2 is reset to 63, since the control registers and the analog logic are reset . when the freeze mode is entered, the cwp is unchanged; it points to the last executed ccw in queue 2 . qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-28 freescale semiconductor operations have no effect. each location in the ccw table corresponds to a location in the result word table. when a conversion is completed for a ccw entr y, the 10-bit result is written in the corresponding result word entry. the qadc64 e provides 64 ccw table entries. the beginning of queue 1 is the first location in the ccw table. the first locati on of queue 2 is specified by the beginning of queue 2 pointer (bq2) in qacr2. to dedicate the entire ccw table to queue 1, queue 2 is programmed to be in the disabled mode, and bq 2 is programmed to 64 or greater. to dedicate the entire ccw table to que ue 2, queue 1 is programmed to be in the disabled mode, and bq 2 is specified as the first location in the ccw table. figure 13-15 illustrates the operation of the queue structure. figure 13-15. qadc64e conversion queue operation to prepare the qadc64e for a scan se quence, the software writes to th e ccw table to specify the desired channel conversions. the software also establishes the criteria fo r initiating the queue execution by programming the queue operating mode. the queue operating mode determines what type of trigger event causes queue execution to begin. a ?trigger event? is used to refer to any of the ways to cause the qadc64e to begin executing the ccws in a queue or sub-queue. an ?exter nal trigger? is only one of the possible ?trigger events.? conversion command word (ccw) table 0x200 (ccw0) 1 bq2 0x27e (ccw63) 1 a/d converter result word table result 0 result 63 channel select, sample, hold, and analog to digital conversion begin queue 1 begin queue 2 end of queue 1 end of queue 2 p byp ist chan 10-bit conversion command word (ccw) format 10-bit result is software readable in 3 different 16-bit formats p = pause after conversion byp = bypass buffer amplifier ist = input sample time chan = channel number and end_of_queue code s = sign bit address offsets 0x280-0x2ff 1 0x380-0x3ff 1 0x300-0x37f 1 note 1: these offsets must be added to the module base address: a = 0x30 4800 or b = 0x30 4c00. result s result 0 right justified, unsigned result format left justified, unsigned result format left justified, signed result format 15 0 15 0 result 15 0 00 00 0 000 00 0 000 00 0 9 10 9 10 5 6 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-29 a scan sequence may be initiated by the following: ? a software command ? expiration of the peri odic/interval timer ? external trigger signal ? external gated signal (queue 1 only) the software also specifies whethe r the qadc64e is to perform a singl e pass through the queue or is to scan continuously. when a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. when a continuous-scan mode is sel ected, the queue remains active in the selected queue operating mode after the qadc64e completes each queue scan sequence. during queue execution, the qadc64e reads each ccw from the activ e queue and executes conversions in three stages: ? initial sample - during initial sa mple, a buffered version of the sel ected input channe l is connected to the sample capacitor at the input of the sample buffer amplifier. ? final sample - during the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the samp le capacitor directly. each ccw specifies a final input sample time of 2, 4, 8, or 16 cycles. ? resolution - when an analog-to-digital conversi on is complete, the result is written to the corresponding location in the result word table. the qadc64e continues to sequentially execute each ccw in the queue until the end of the queue is detected or a pause bit is found in a ccw. when the pause bit is set in the current ccw, the qadc64e stops execution of the queue until a new trigger event occurs. the pause status flag bit is set, which may cause an interrupt to notify the software that the queue has reached the pause state. after the trigger event occurs, the pa used state ends and the qadc64e continues to execute each ccw in the queue until another paus e is encountered or the end of the queue is detected. the following indicate the end-of-queue condition: ? the ccw channel field is programmed with 63 (0x3f) to specify the end of the queue ? the end-of-queue 1 is implied by the beginning of queue 2, which is specifie d in the bq2 field in qacr2 ? the physical end of the queue ram sp ace defines the end of either queue when any of the end-of-queue conditi ons is recognized, a queue completion flag is set, a nd if enabled, an interrupt is issued to the software. the following situations premat urely terminate queue execution: ? because queue 1 is higher in prio rity than queue 2, when a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is su spended by aborting the execution of the ccw in progress, and the queue 1 execution begins. wh en queue 1 execution is completed, queue 2 conversions restart with the first ccw entry in que ue 2 or the first ccw of the queue 2 sub-queue being executed when queue 2 was suspended. altern ately, conversions can restart with the aborted queue 2 ccw entry. the resume bit in qacr2 al lows the software to select where queue 2 begins after suspension. by choosing to re-ex ecute all of the suspended queue 2 queue and qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-30 freescale semiconductor sub-queue ccws, all of the sample s are guaranteed to have been ta ken during the same scan pass. however, a high trigger event rate for queue 1 can prohibit the completion of queue 2. if this occurs, the software may choose to begin exec ution of queue 2 with the aborted ccw entry. ? software can change the queue operating mode to disabled mode . any conversion in progress for that queue is aborted. putting a queue into the disabled mode does not power down the converter. ? software can change the queue operating mode to anot her valid mode. any conversion in progress for that queue is aborted. the queue restarts at the beginning of the que ue, once an appropriate trigger event occurs. ? for low power operation, software can set the st op mode bit to prepare the module for a loss of clocks. the qadc64e aborts any conversion in progress when the stop mode is entered. ? when the freeze enable bi t is set by software and the imb3 in ternal freeze line is asserted, the qadc64e freezes at the end of th e conversion in progress. when internal freeze is negated, the qadc64e resumes queue execution beginning with the next ccw entry. refer to section 13.5.7, ?configuration and control using the imb3 interface ? for more information. msb 01234567891011121314 lsb 15 field ? p byp ist chan[5:0] reset unaffected addr 0x30 4a00 ? 0x30 4a7f, 0x30 4e00 ? 0x30 4e7f figure 13-16. conversion command word table (ccw) table 13-18. ccw bit descriptions bits name description 0:5 ? reserved 6 p pause. the pause bit allows the creation of sub-queues within queue 1 and queue 2. the qadc64e performs the conversion specified by the ccw with the pause bit set, and then the queue enters the pause state. another trigger event causes execution to continue from the pause to the next ccw. 0 do not enter the pause state after execution of the current ccw. 1 enter the pause state after execution of the current ccw. 7 byp sample amplifier bypass. setting byp enables t he amplifier bypass mode for a conversion, and subsequently changes the timing. refer to section 13.4.1.2, ?amplifie r bypass mode conversion timing ,? for more information. 0 amplifier bypass mode disabled. 1 amplifier bypass mode enabled. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-31 8:9 ist input sample time. the ist fi eld specifies the length of the samp le window. longer sample times permit more accurate a/d conversions of signals with higher source impedances, especially if byp = 1. 00 qckl period x 2 01 qckl period x 4 10 qckl period x 8 11 qckl period x 16 10:15 chan channel number. the chan field selects the input channel number corresponding to the analog input signal to be sampled and converted. the analog input signal channel number assignments and the signal definitions vary depending on whether the qadc64e is operating in multiplexed or non-multiplexed mode. the queue scan mechanism sees no distinction between an internally or externally multiplexed analog input. if chan specifies a reserved channel number (c hannels 32 to 47) or an invalid channel number (channels 4 to 31 in non-multiplexed mode), the low reference level (vrl) is converted. programming the channel field to channel 63 indica tes the end of the queue. channels 60 to 62 are special internal channels. when one of these channels is selected, the sample amplifier is not used. the value of vrl, vrh, or (v rh ? v rl )/2 is placed directly into the converter. programming the input sample time to any value other than two for one of the internal channels has no benefit except to lengthen the overall conversion time. ta b l e 1 3 - 1 9 shows the channel number assignments for non-multiplexed mode. table 13-20 shows the channel number assignments for multiplexed mode. table 13-19. non-multiplexed channel assignments and signal designations non-multiplexed input sign als channel nu mber in chan port signal name analog signal name other functions signal type (i/o) binary decimal pqb0 pqb1 pqb2 pqb3 an0 an1 an2 an3 ? ? ? ? i i i i 000000 000001 000010 000011 0 1 2 3 ? ? pqb4 pqb5 ? ? an48 an49 invalid reserved ? ? ? ? i i 000100 to 011111 10xxxx 110000 110001 4 to 31 32 to 47 48 49 port signal name analog signal name other functions signal type (i/o) binary decimal pqb6 pqb7 pqa0 pqa1 an50 an51 an52 an53 ? ? ? ? i i i/o i/o 110010 110011 110100 110101 50 51 52 53 pqa2 pqa3 pqa4 pqa5 an54 an55 an56 an57 ? ? ? ? i/o i/o i/o i/o 110110 110111 111000 111001 54 55 56 57 table 13-18. ccw bit descriptions (continued) bits name description qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-32 freescale semiconductor the channel field is programmed for channel 63 to i ndicate the end of the queue. channels 60 to 62 are special internal channels. when one of the special cha nnels is selected, the samp ling amplifier is not used. the value of vrl, vrh, or (vrh - vrl)/2 is placed directly onto th e converter. also for the internal special channels, programming any input sample time other than two has no benefit except to lengthen the overall conversion time. 13.3.10 result word table the result word table is a ram, 64 words long and 10 bits wide. an entry is written by the qadc64e after completing an analog conversion specified by the corresponding ccw table en try. software can read pqa6 pqa7 ? ? an58 an59 v rl v rh ? ? ? ? i/o i/o i i 111010 111011 111100 111101 58 59 60 61 ? ? ? ? (v rh ? v rl )/2 end of queue code ? ? 111110 111111 62 63 table 13-20. multiplexed channel assignments and signal designations multiplexed input signals channel number in chan port signal name analog signal name other functions signal type (i/o) binary decimal pqb0 pqb1 pqb2 pqb3 anw anx any anz ? ? ? ? i i i i 00xxx0 00xxx1 01xxx0 01xxx1 0 to 14 even 1 to 15 odd 16 to 30 even 17 to 31 odd ? pqb4 pqb5 pqb6 ? an48 an49 an50 reserved ? ? ? ? i i i 10xxxx 110000 110001 110010 32 to 47 48 49 50 pqb7 pqa0 pqa1 pqa2 an51 ? ? ? ? ma0 ma1 ma2 i i/o i/o i/o 110011 110100 110101 110110 51 52 53 54 pqa3 pqa4 pqa5 pqa6 an55 an56 an57 an58 ? ? ? ? i/o i/o i/o i/o 110111 111000 111001 111010 55 56 57 58 pqa7 ? ? ? an59 v rl v rh ? ? ? ? (v rh -v rl )/2 i/o i i ? 111011 111100 111101 111110 59 60 61 62 ? ? end of queue code ? 111111 63 table 13-19. non-multiplexed channel assignments and signal designations (continued) non-multiplexed input sign als channel nu mber in chan qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-33 or write the result word table, but in normal operation, the software re ads the result word table to obtain analog conversions from the qadc64e . unimplemented bits are read as zeros, and write operations do not have any effect. see figure 13-17 for a diagram of the result word table while there is only one result word table, the data can be accessed in three different data formats: ? right justified in the 16- bit word, with zeros in the higher order unused bits ? left justified, with the most signifi cant bit inverted to form a sign bit, and zeros in the unused lower order bits ? left justified, with zeros in the lower order unused bits the left justified, signed format corr esponds to a half-scale, offset binary, two?s complement data format. the data is routed onto the imb3 according to the se lected format. the address used to access the table determines the data alignment format. all write opera tions to the result word table are right justified. the three result data formats ar e produced by routing the ram bits onto the data bus. the software chooses among the three formats by r eading the result at the memory address which produces the desired data alignment. the result word table is read/write accessible by software. during normal operation, appl ication software only needs to read the result table. write operations to the table may occur during test or debug breakpoint operation. when locations in the ccw table are not used by an application, software could use the msb 01234567891011121314 lsb 15 field ? result sreset 0000_00 undefined addr 0x30 4a80?4aff (rjurr_a); 0x30 4e80?4eff (rjurr_b) figure 13-17. right justified, unsigned result format (rjurr) msb 01234567891011121314 lsb 15 field s 1 1 s = sign bit. result ? sreset undefined 00_0000 addr 0x30 4b00?4b7f (ljsrr_a); 0x30 4f00?4f7f (ljsrr_b) figure 13-18. left justified, signed result format (ljsrr) msb 01234567891011121314 lsb 15 field result ? sreset undefined 00_0000 addr 0x30 4b80?4bff (ljurr_a ); 0x30 4f80?4fff (ljurr_b) figure 13-19. left justified, unsigned result register (ljurr) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-34 freescale semiconductor corresponding locations in the result word table as scratch pad ram, remembering that only 10 bits are implemented. the result alignment is only implemented for software read operations. since write operations are not the normal use for the result register s, only one write data fo rmat is supported, which is right justified data. note some write operations, like bit manipul ation, may not operate as expected because the hardware cannot access a true 16-bit value. 13.4 analog subsystem this section describes the qadc64e analog subsystem, which includes the front-end analog multiplexer and analog-to-dig ital converter. 13.4.1 analog-to-digital converter operation the analog subsystem consists of the path from the input si gnals to the a/d convert er block. signals from the queue control logic are fed to the multiplexer and state machine. the end of convert (eoc) signal and the successive-approximation register (s ar) are the result of the conversion. figure 13-20 shows a block diagram of the qadc64e analog subsystem. figure 13-20. qadc64e analog subsystem block diagram stop state mach, sar and sar buffer an44 an59 + - final sample buffer chan decoder + - comp. 2 v rh v rl cdac (4 bit) rdac (7 bit) conv. crh crl 4 (one is offset) 7 ccw buffer data bus 10 result ist ref wccw eos/eoc standard converter interface clk zero 6 buffer amp bias cap array equals cdac sample . . . qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-35 13.4.1.1 conversion cycle times total conversion time is made up of initial sample time, final sample time, and resolution time. initial sample time refers to the time during which the selected input ch annel is coupled through the buffer amplifier to the sample capacitor. this buffer is us ed to quickly reproduce its input signal on the sample capacitor and minimize charge sharing errors. duri ng the final sampling period the amplifier is bypassed, and the multiplexer input charges the sample capaci tor array directly for improved accuracy. during the resolution period, the voltage in the sa mple capacitor is converted to a di gital value and stored in the sar. initial sample time is fixed at tw o qclk cycles. final sample time can be 2, 4, 6, 8, or 16 qclk cycles, depending on the value of the ist field in th e ccw. resolution time is ten qclk cycles. therefore, conversion time requires a minimum of 14 qclk clocks (7 s with a 2.0-mhz qclk). if the maximum final sample time period of 16 qclks is selected, the total conversion time is 28 qclks or 14 s (with a 2.0-mhz qclk) figure 13-21 illustrates the timing for conversions. figure 13-21. conversion timing 13.4.1.2 amplifier bypass mode conversion timing if the amplifier bypass mode is enabled for a conve rsion by setting the amplifier bypass (byp) bit in the ccw, the timing changes to that shown in figure 13-22 . the buffered sample time is eliminated, reducing the potential conversion time by two qclks. however, due to internal rc effects, a minimum final sample time of four qclks must be allowed. this re sults in no savings of qc lks. when using the bypass mode, the external circuit should be of lo w source impedance, t ypically less than 10 k ? . also, the loading effects of the external circuitry by the qadc64e need to be considered, since th e benefits of the sample amplifier are not present. note because of internal rc time constant s, a sample time of two qclks in bypass mode for high frequency operation is not recommended. buffer sample time final sample time resolution time sample time successive approximation resolution sequence 2 cycles n cycles: 10 cycles qclk (2, 4, 8, 16) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-36 freescale semiconductor figure 13-22. bypass mode conversion timing 13.4.2 channel decode and multiplexer the internal multiplexer selects one of the 16 analog input signals for conversion. the selected input is connected to the sample buffer amplifier. the mult iplexer also includes positive and negative stress protection circuitry, which prevents deselected channe ls from affecting the selected channel when current is injected into the deselected channels. refer to appendix f, ?electri cal characteristics ,? for specific current levels. 13.4.3 sample buffer amplifier the sample buffer is used to raise the effective inpu t impedance of the a/d converter, so that external components (higher bandwidth or higher impedance) ar e less critical to accuracy. the input voltage is buffered onto the sample capacitor to reduce crosstalk between channels. 13.4.4 digital-to-analog converter (dac) array the digital to analog converter (dac) array consists of binary-weighted capacitors and a resistor-divider chain. the reference voltages, v rh and v rl , are used by the dac to perfor m ratiometric conversions. the dac also converts the followi ng three internal channels: ?v rh ? reference voltage high ?v rl ? reference voltage low ?(v rh ? v rl )/2 ? reference voltage the dac array serves to provide a mechanism for the successive approximation a/d conversion. resolution begins with the most si gnificant bit (msb) and works down to the least significant bit (lsb). the switching sequence is controlled by the comp arator and successive-appr oximation register (sar) logic. ? sample capacitor ? the sample capacitor is employed to sample and hold the voltage to be converted. sample time resolution time sample time successive approximation resolution sequence n cycles: 10 cycles qclk (2, 4, 8, 16) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-37 13.4.5 comparator the comparator is used during the approximation pr ocess to sense whether the digitally selected arrangement of the dac array produces a voltage le vel higher or lower than the sampled input. the comparator output feeds into the sar which accumu lates the a/d conversion result sequentially, beginning with the msb. 13.4.6 bias the bias circuit is controlled by the stop signal to power-up and power-down al l the analog circuits. 13.4.7 successive approximation register the input of the successive approxi mation register (sar) is connected to the comparator output. the sar sequentially receives the c onversion value one bit at a time, starting with the ms b. after accumulating the 10 bits of the conversion result, the sar data is transferred to the appr opriate result lo cation, where it may be read from the imb3 by user software. 13.4.8 state machine the state machine receives the qclk, rst, stop, byp, ist, chan[5:0], and start conv signals, from which it generates all timing to perform an a/d conversion. the start c onvert (start conv) signal indicates to the a/d converter that the desired channel has been sent to the mux. ist indicates the desired sample time. byp indicates whether to bypass the sample amplifier. th e end of conversion (eoc) signal, notifies the queue control logic that a result is available for storage in the result ram. 13.5 digital subsystem the digital control subsystem includes the control logi c to sequence the conversi on activity, the clock and periodic/interval timer, c ontrol and status register s, the conversion command word table ram, and the result word table ram. the central element for control of the qadc64e co nversions is the 64-entry ccw table. each ccw specifies the conversion of one i nput channel. depending on the appl ication, one or two queues can be established in the ccw tabl e. a queue is a scan seque nce of one or more input channels. by using a pause mechanism, sub-queues can be created in the two queues. each queue can be operated usi ng one of several different scan modes. the scan modes for queue 1 and queue 2 are programmed in qacr1 and qacr2 (control registers 1 and 2). once a queue has been star ted by a trigger event (any of the ways to cause the qadc64e to begin executing the cc ws in a queue or sub-queue), the qadc64e performs a sequence of conversions and places the results in the result word table. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-38 freescale semiconductor 13.5.1 queue priority queue 1 has priority over queue 2 execution. the following cases show the conditions under which queue 1 asserts its priority: ? when a queue is not active, a tr igger event for queue 1 or queue 2 causes the corresponding queue execution to begin. ? when queue 1 is active and a tr igger event occurs for queue 2, que ue 2 cannot begin execution until queue 1 reaches completion or the paused state. the status register records the trigger event by reporting the queue 2 stat us as trigger pending. additional tri gger events for queue 2, which occur before execution can begin, are captured as trigger overruns. ? when queue 2 is active and a trigger event occu rs for queue 1, the curren t queue 2 conversion is aborted. the status register repor ts the queue 2 status as suspe nded. any trigger events occurring for queue 2 while queue 2 is susp ended are captured as trigger ov erruns. once queue 1 reaches the completion or the paused state, queue 2 begins executing again. the pr ogramming of the resume bit in qacr2 determines which ccw is executed in queue 2. refer to section 13.3.7, ?control register 2 (qacr2) ? for more information. ? when simultaneous trigger events occur for que ue 1 and queue 2, queue 1 begins execution and the queue 2 status is ch anged to trigger pending. 13.5.2 paused sub-queues the pause feature can be us ed to divide queue 1 and/ or queue 2 into multiple sub-queues. a sub-queue is defined by setting the pause bit in the last ccw of the sub-queue. figure 13-23 shows the ccw format and an example of us ing pause to create s ub-queues. queue 1 is shown with four ccws in each sub-queue and queue 2 has two ccws in each sub-queue. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-39 figure 13-23. qadc64e queue operation with pause the queue operating mode selected fo r queue 1 determines what type of trigger event causes the execution of each of the sub-queues within queue 1. similarly, the queue operati ng mode for queue 2 determines the type of trigger event required to execut e each of the sub-queues within queue 2. for example, when the external trig ger rising edge continuous-scan mode is selected for queue 1, and there are six sub-queues within queue 1, a separate rising edge is required on the external trigger signal after every pause to begin the execution of each sub-queue (refer to figure 13-23 ). refer to section 13.5.4, ?scan modes ,? for information on different scan modes. the choice of single-scan or c ontinuous-scan applies to the full queue, and is not applied to each sub-queue. once a sub-queue is initiated, each ccw is executed sequentially until the last ccw in the sub-queue is executed and the paus e state is entered. execution can onl y continue with the next ccw, which is the beginning of the next sub-queue. a s ub-queue cannot be executed a second time before the overall queue execution has been completed. refer to section 13.3.7, ?control register 2 (qacr2) ,? for more information. trigger events which occur during th e execution of a sub-queue are ignor ed, except that the trigger overrun flag is set. when a continuous-scan mode is selected, a trigger event oc curring after the completion of the qadc64e cqp 00 begin queue 1 bq2 63 end of queue 1 begin queue 2 end of queue 2 00 63 conversion command word (ccw) table result word table 0 p 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 p 1 p 0 pause pause pause pause pause pause channel select, sample, hold, and a/d conversion qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-40 freescale semiconductor last sub-queue (after the queue comp letion flag is set), causes the ex ecution to continue with the first sub-queue, starting with th e first ccw in the queue. when the qadc64e encounters a ccw with the pause bit set, the queue enters the paused state after completing the conversion specified in the ccw with the pause bit. the pause flag is set and a pause software interrupt may optionally be issued. the status of the queue is shown to be paused, indicating completion of a sub-queue. the qadc 64e then waits for another trigge r event to again begin execution of the next sub-queue. 13.5.3 boundary conditions the following are queue operation boundary conditions: ? the first ccw in a queue contai ns channel 63, the end-of-queue (eoq) code. the queue becomes active and the first ccw is rea d. the end-of-queue is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. ? bq2 (beginning of queue 2) is set at the end of the ccw table (63) and a trigger event occurs on queue 2. refer to section 13.3.7, ?control register 2 (qacr2) ,? for more information on bq2. the end-of-queue condition is recognized, a convers ion is performed, the completion flag is set, and the queue becomes idle. ? bq2 is set to ccw0 and a trigger event occurs on queue 1. after readi ng ccw0, the end-of-queue condition is recognized, the completi on flag is set, and the queue b ecomes idle. a conversion is not performed. ? bq2 is set beyond the end of the ccw table (64 ? 127) and a trigge r event occurs on queue 2. the end-of-queue condition is recogni zed immediately, the completion flag is set, and the queue becomes idle. a conversion is not performed. note multiple end-of-queue conditions ma y be recognized simultaneously, although there is no change in the qad c64e behavior. for example, if bq2 is set to ccw0, ccw0 contains the eo q code, and a trigger event occurs on queue 1, the qadc64e reads ccw0 and detects both end-of-queue conditions. the completion flag is set and queue 1 becomes idle. boundary conditions also exist for combinations of pa use and end-of-queue. one ca se is when a pause bit is in one ccw and an end-of-queue condition is in the next ccw. the conversion specified by the ccw with the pause bit set completes norma lly. the pause flag is set. howeve r, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. examples of this situation include: ? the pause bit is set in ccw5 and the eoq code is in ccw6 ? the pause is set in ccw63 ? during queue 1 operation, the pause bit is set in ccw20 and bq2 points to ccw21 another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same ccw. both the pa use and end-of-queue co nditions are recognized simultaneously. the end-of-queue condition has precedence so a conversion is not performed for the ccw qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-41 and the pause flag is not set. th e qadc64e sets the completion flag and the queue status becomes idle. examples of this situation are: ? the pause bit is set in ccw10 and eoq is programmed into ccw10 ? during queue 1 operation, the pause bi t set in ccw32, which is also bq2 13.5.4 scan modes the qadc64e queuing mechanism al lows the application to util ize different requirements for automatically scanning input channels. in single-scan mode, a single pass through a sequence of conversions de fined by a queue is performed. in continuous-scan mode, mu ltiple passes through a sequence of c onversions define d by a queue are executed. the possible modes are: ? disabled and reserved mode ? single-scan modes ? software initiated single-scan mode ? external trigger single-scan mode ? external gated single-scan mode ? periodic/interval ti mer single-scan mode ? continuous-scan modes ? software initiated continuous-scan mode ? external trigger continuous-scan mode ? external gated continuous-scan mode ? periodic/interval time r continuous-scan mode the following paragraphs describe singl e-scan and continuous-scan operations. 13.5.4.1 disabled mode when the disabled mode is selecte d, the queue is not active. trigger ev ents cannot initiate queue execution. when both queue 1 and queue 2 are disabled, wait st ates are not encountered for imb3 accesses of the ram. when both queues are disa bled, it is safe to change the qclk prescaler values. 13.5.4.2 reserved mode reserved mode allows for future mode definitions. wh en the reserved mode is selected, the queue is not active. it functions the same as disabled mode. caution do not use a reserved mode. un specified operations may result. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-42 freescale semiconductor 13.5.4.3 single-scan modes when the application software wants to execute a single pass through a sequenc e of conversions defined by a queue, a single-scan queue operating mode is sel ected. by programming the mq field in qacr1 or qacr2, the following modes can be selected: ? software initiated single-scan mode ? external trigger single-scan mode ? external gated single-scan mode ? periodic/interval ti mer single-scan mode note queue 2 cannot be programmed for external gated single-scan mode. in all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queue?s control register. the single-scan enable bits, sse1 and sse2, are provided for queue 1 and queue 2 respectively. until the single-scan enable bit is set, any trigger events for that queue are ignored. the single-scan enable bit may be set to a one during the write cycle, wh ich selects the single-scan queue operating mode. the single-scan enable bit is set through software, but will always read as a zero. once set, writing the single-scan enable bit to zero has no effect. only th e qadc64e can clear the single-scan enable bit. the completion flag, completion interrupt , or queue status are used to determine when the queue has completed. after the single-scan enable bit is set, a trigger ev ent causes the qadc64e to begin execution with the first ccw in the queue. the single-scan enable bit remains set until the queue is completed. after the queue reaches completion, the qadc64e resets the si ngle-scan enable bit to zero. if the single-scan enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not affected. however, if the software changes the queue operating mode, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. the conversi on in progress is aborted and the new queue operati ng mode takes effect. in the software-initiated single-scan mode, the writing of a one to th e single-scan enable bit causes the qadc64e to internally generate a trigger event and the queue execution begins immediatel y. in the other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. the single-scan enable bit allows the entire queue to be scanned once. a trigger overrun is captured if a trigger event occurs during queue executi on in an edge-sensitive external trigger mode or a periodic/interval timer mode. in the periodic/interval time r single-scan mode, the next expiration of the timer is the trigger event for the queue. after the queue execution is complete, the queue status is shown as idle. the software can restart the queue by setting the single-scan enable bit to a one. queue execution begins with the first ccw in the queue. 13.5.4.3.1 software init iated single-scan mode software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enab le bit in qacr1 or qacr2. a trigger event is qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-43 generated internally and the qadc64e immediately begins execution of the first ccw in the queue. if a pause occurs, another trigger event is generated internally, and then execution continues without pausing. the qadc64e automatically performs the conversions in the queue until an e nd-of-queue condition is encountered. the queue remains idle unt il the software again sets the singl e-scan enable bit. while the time to internally generate and act on a trigger event is ve ry short, software can momentarily read the status conditions, indicating that the queue is paused. the trig ger overrun flag is never se t while in the software initiated single-scan mode. the software initiated single-scan mode is useful in the following applications: ? allows software complete control of the queue execution ? allows the software to easily altern ate between severa l queue sequences. 13.5.4.3.2 external trigger single-scan mode the external trigger single-scan mode is availabl e on both queue 1 and queue 2. the software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. the software must enable the scan to occur by setting the single-scan enable bit for the queue. the first external trigger edge causes the queue to be executed one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. after the queue is completed, the qadc64e clears the single-scan enable bit. software may set the single-scan enable bit again to allow another scan of the queue to be initiated by the next external trigger edge. the external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. analog samples can be taken in sync with an external event, even though the software is not interested in data taken from every edge. the software can start the external tri gger single-scan mode and get one set of data, and at a later ti me, start the queue again for the next set of samples. when a pause bit is encount ered during external trigger single-scan mode, another trigger event is required for queue execution to continue. soft ware involvement is not needed to enable queue execution to continue from the paused state. 13.5.4.3.3 external ga ted single-scan mode the qadc64e provides external gating for queue 1 onl y. when external gated single-scan mode is selected, the input level on the associ ated external trigger signal enable s and disables queue execution. the polarity of the external gated signal is fixed so only a high le vel opens the gate and a low level closes the gate. once the gate is ope n, each ccw is read and th e indicated conversions are performed until the gate is closed. software must enable the scan to occur by setting the single-scan enable bit for queue 1. if a pause in a ccw is encountered, the pause flag will not set, and ex ecution continues without pausing. while the gate is open, queue 1 executes one time. e ach ccw is read and the indicated conversions are performed until an end-of -queue condition is encountered. when queue 1 completes, the qadc64e sets the completion flag (cf1) and clears the single-scan en able bit. software may set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. if the gate closes before queue 1 completes execution, the current ccw completes, execution of queue 1 stops, the single-scan enable bit is cleared, and th e pf1 bit is set. software can read the cwpq1 to qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-44 freescale semiconductor determine the last valid conversion in the queue. soft ware must set the single-sc an enable bit again and should clear the pf1 bit before anothe r scan of queue 1 is in itiated during the next open gate. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conve rsion time interval does not guarant ee the closure will be captured. 13.5.4.3.4 periodic/interv al timer single-scan mode both queues can use the periodic/inte rval timer in a single- scan queue operating mode . the timer interval can range from 128- to 128-kbyte qclk cycles in binary multiples. when the periodic/ interval timer single-scan mode is selected and the software sets the single-scan enable bit in qacr1 or qacr2, the timer begins counting. when th e time interval elapses, an internal trigger event is created to start the queue and the qadc64e begins execution with the first ccw. the qadc64e automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. wh en a pause occurs, queue execution stops until the timer interval elapses again, and then queue execution continues. when the queue execution reaches an end-of-queue situation, the single-scan enable bit is clea red. software may set the single-scan enable bit again, allowing another scan of the queue to be initia ted by the periodic/interval timer. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. once the queue execution is completed, the single-scan enab le bit must be set again to enable the timer to count again. normally only one queue will be en abled for periodic/inter val timer single-scan mode and the timer will reset at the end-of-queue. however, if both queues are enabled for either single-scan or continuous periodic/interval timer mode , the end-of-queue condition will not reset the timer while the othe r queue is active. in this case, the time r will reset when both queues ha ve reached end-of-queue. see section 13.5.6, ?periodic / interval timer ? for a definition of periodic/in terval timer reset conditions. the periodic/interval timer si ngle-scan mode can be used in applica tions which need coherent results, for example: ? when it is necessary that all samp les are guaranteed to be taken during the same scan of the analog signals ? when the interrupt rate in the periodic/interv al timer continuous-scan mode would be too high ? in sensitive battery applications, where the single- scan mode uses less power than the software initiated continuous-scan mode 13.5.4.4 continuous-scan modes when the application software want s to execute multiple passes through a sequence of conve rsions defined by a queue, a continuous-scan queu e operating mode is selected. by programming the mq1 fiel d in qacr1 or the mq2 field in qacr 2, the following software initiated modes can be selected: ? software initiated continuous-scan mode qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-45 ? external trigger continuous-scan mode ? external gated continuous-scan mode ? periodic/interval time r continuous-scan mode when a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meani ng or effect. as soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. in the case of the software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. in the other continuous-scan queue operati ng modes, the selected trigger event must occur before the queue can start. a trigger overrun is captured if a trigger event occurs during queue execution in the external trigger c ontinuous-scan mode and the periodic/interval timer continuous-scan mode. after the queue execution is complete, the queue status is shown as idle. since the continuous-scan queue operating modes allow the entire queue to be scanned mu ltiple times, software i nvolvement is not needed to enable queue execution to continue from the idle state. the next trigger event causes queue execution to begin again, starting with the first ccw in the queue. note coherent samples are guaranteed. the time between consecutive conversions has been designed to be consistent. however, there is one exception. for queues that end with a ccw containing e oq code (channel 63), the last queue conversion to th e first queue conversion requires 1 additional ccw fetch cycle. therefore continuous sa mples are not coherent at this boundary. in addition, the time from trigger to first conversion cannot be guaranteed since it is a function of clock synchronization, programmable trigger ev ents, queue priorities, and so on. 13.5.4.4.1 software initia ted continuous-scan mode when the software initiated con tinuous-scan mode is programmed, the trigger event is generated automatically by the qadc64e. queue execution begins immediately. if a pause is encountered, another trigger event is generated internally, and then execution continues without pausing. when the end-of-queue is reached, another in ternal trigger event is generated, and queue execution begins again from the beginning of the queue. while the time to internally generate and act on a tr igger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. the trigger overrun flag is never set while in the software-initiated continuous-scan mode. the software initiated cont inuous-scan mode keeps the result regist ers updated more frequently than any of the other queue operating modes. the software can always read the result table to get the latest converted value for each channel. the channels sc anned are kept up to date by the qadc64e without software involvement. software can read a result value at any time. the software initiated continuous-scan mode may be c hosen for either queue, but is normally used only with queue 2. when the software in itiated continuous-scan m ode is chosen for queue 1, that queue operates qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-46 freescale semiconductor continuously and queue 2, be ing lower in priority, never gets execut ed. the short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. the software initiated con tinuous-scan mode is a usef ul choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-to-cha nge analog channels. interrupts are normally not used with the software initiated continuou s-scan mode. rather, the so ftware reads the latest conversion result from the re sult table at any time. once initiated, so ftware action is not needed to sustain conversions of channel. 13.5.4.4.2 external trig ger continuous-scan mode the qadc64e provides external trigger signals for both queues. when the external trigger software initiated continuous-scan mode is se lected, a transition on the associated external trigger signal initiates queue execution. the polarity of the ex ternal trigger signal is programmable, so that the software can select a mode which begins queue execution on the rising or falling edge. each ccw is read and the indicated conversions are performed unt il an end-of-queue condition is encount ered. when the next external trigger edge is detected, the queue executi on begins again automatically. soft ware initialization is not needed between trigger events. when a pause bit is encountered in external trigger continuous-scan mode , another trigger event is required for queue execution to continue. soft ware involvement is not needed to enable queue execution to continue from the paused state. some applications need to synchroni ze the sampling of analog channels to external events. there are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. 13.5.4.4.3 external gate d continuous-scan mode the qadc64e provides external gating for queue 1 onl y. when external gated continuous-scan mode is selected, the input level on the associ ated external trigger signal enable s and disables queue execution. the polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. when the gate opens agai n, the queue execution automatically begins again from the beginning of the queue. software initializ ation is not needed between trigger events. if a paus e in a ccw is encountered, the pause flag will not set , and execution conti nues without pausing. the purpose of external gated cont inuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples availa ble. it is up to the progr ammer to ensure that the queue is large enough so that a maximum gate open tim e will not reach an end- of-queue. however it is useful to take advantage of a smaller queue in the manner described in the next paragraph. in the event that the queue completes before the gate closes, a completion flag will be set and the queue will roll over to the beginning and continue conversions until the gate closes. if the gate remains open and the completion flag is not cleared, when the queue co mpletes a second time the trigger overrun flag will be set and the queue will roll-over again. the queue will continue to execute until the gate closes or the mode is disabled. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-47 if the gate closes before queue 1 completes execut ion, the current ccw comple tes execution of queue 1 stops and qadc64e sets the pf1 bit to indicate an incomplete queue. software can read the cwpq1 to determine the last valid conversion in the queue. in this mode, if the ga te opens again, execution of queue 1 begins again. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time inte rval does not guarantee the closure will be captured. 13.5.4.4.4 periodic/interval timer continuous-scan mode the qadc64e includes a dedicated periodic/interval timer for initiating a scan sequence on queue 1 and/or queue 2. software selects a programmable timer interval ranging from 128 to 128 kbytes times the qclk period in binary multiples. the qclk pe riod is prescaled down from the imb3 mcu clock. when a periodic/interval timer cont inuous-scan mode is selected for queue 1 and/or queue 2, the timer begins counting. after the programmed interval elapse s, the timer generated trigger event starts the appropriate queue. meanwhile , the qadc64e automatically performs the conversi ons in the queue until an end-of-queue condition or a pa use is encountered. when a pause occurs, the qadc64e waits for the periodic interval to expire again, then continues wi th the queue. once end-of-que ue has been detected, the next trigger event causes queu e execution to begin again with the first ccw in the queue. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue executi on to continue following a pause or queue completi on, or may be considered a trigger overrun. as with all cont inuous-scan queue operating modes, software action is not needed between trigger events. si nce both queues may be triggered by the periodic/interval timer, see section 13.5.6, ?periodic / interval timer ? for a summary of periodic/in terval timer reset conditions. software enables the completion interrupt when usi ng the periodic/interval timer continuous-scan mode. when the interrupt occurs, the softwa re knows that the periodically collec ted analog results have just been taken. the software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. 13.5.5 qadc64e clock (qclk) generation figure 13-24 is a block diagram of the clock subsyste m. the qclk provides the timing for the a/d converter state machine wh ich controls the timing of the conversion. the qclk is also the input to a 17-stage binary divider which implem ents the periodic/interval timer. to retain the specified analog conversion accuracy, th e qclk frequency (f qclk ) must be within the tolerance specified in appendix f, ?electrical characteristics .? before using the qadc64e, the software must initiali ze the prescaler with values that put the qclk within the specified range. though most software applications init ialize the prescaler once and do not change it, write operations to th e prescaler fields are permitted. for software compatibility with earlier versions of qadc64e, the definition of psl, psh, and psa have been maintained. however, the requirements on minimum time and minimum low time no longer exist. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-48 freescale semiconductor note a change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. therefore, any prescaler write operation should be done only wh en both queues are in the disabled modes. figure 13-24. qadc64e clock subsystem functions to accommodate wide variations of the main mcu clock frequency (imb3 clock ? f sys ), qclk is generated by a programmable prescaler which divides the mcu imb3 cl ock to a frequency within the specified qclk tolerance range. to allow the a/d conversion time to be maximized across the spectrum of imb3 clock frequencies, the qadc64e prescaler permits the frequency of qclk to be software selectable. it also allows the duty cycle of the qclk waveform to be programmable. the software establishes the basic high phase of the qclk waveform with the psh (prescaler clock high time) field in qacr0, and selects th e basic low phase of qclk with th e prescaler clock low time (psl) field. the combination of the psh and psl parame ters establishes the frequency of the qclk. prescaler rate selection (from control register 0): binary counter periodic/interval timer select 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 16 2 17 one?s complement compare clock generate 5-bit down counter zero detect reset qclk load psh set qclk qclk qadc64e clock (f sys / 2 to f sys //40 ) low time high time input sample time queue 1 & 2 timer sar control sar periodic / interval trigger event 53 3 5 imb3 clock a/d converter state machine for q1 and q2 2 8 10 mode rate selection from (ccw) cycles (psl) cycles (psh) (f sys ) 2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-49 note the guideline for selecting psh and psl is select is to maintain approximately 50% duty cycl e. so for prescaler valu es less then 16, or psh ~= psl. for prescaler values greater than 16 keep psl as large as possible. figure 13-24 shows that the prescaler is es sentially a variable pulse widt h signal generator. a 5-bit down counter, clocked at the imb3 clock rate, is used to create both the high phase and the low phase of the qclk signal. at the beginning of the high phase, the 5- bit counter is loaded wi th the 5-bit psh value. when the zero detector finds that the high phase is finished, the qclk is reset. a 3-bit comparator looks for a one?s complement match with the 3-bit psl valu e, which is the end of the low phase of the qclk. the psa bit was maintained for software co mpatibility, but has no effect on qadc64e. the following equations define qclk frequency: high qclk time = (psh + 1) f sys low qclk time = (psl + 1) f sys fqclk= 1 (high qclk time + low qclk time) where: ? psh = 0 to 31, the prescaler qclk high cycles in qacr0 ? psl = 0 to 7, the prescaler qclk low cycles in qacr0 ?f sys = imb3 clock frequency ? fqclk = qclk frequency the following are equations for calculating the qclk high/ low phases in example 1: high qclk time = (19 + 1) 56 x 10 6 = 357 ns low qclk time = (7 + 1) 56 x 10 6 = 143 ns fqclk = 1/(357 + 143) = 2 mhz the following are equations for calculating the qclk high/ low phases in example 2: high qclk time = (11 + 1) 40 x 10 6 = 300 ns low qclk time = (7 + 1) 40 x 10 6 = 200 ns fqclk = 1/(300 + 200) = 2 mhz the following are equations for calculating the qclk high/ low phases in example 3: high qclk time = (7 + 1) 32 x 10 6 = 250 ns low qclk time = (7 + 1) 32 x 10 6 = 250 ns fqclk = 1/(250 + 250) = 2 mhz figure 13-25 and table 13-21 show examples of qclk program mability. the examples include conversion times based on the following assumption: ? input sample time is as fast as possible (ist = 0, 2 qclk cycles). figure 13-25 and table 13-21 also show the conversion time calcula ted for a single conversion in a queue. for other mcu imb3 clock fr equencies and other input sample times, the same calculat ions can be made. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-50 freescale semiconductor figure 13-25. qadc64e clock programmability examples note psa is maintained for software comp atibility but has no functional benefit to this version of the module. the mcu imb3 clock frequency is the basis of th e qadc64e timing. the qadc64e requires that the imb3 clock frequency be at least twice the qclk frequency. the qclk frequency is established by the combination of the psh a nd psl parameters in qacr0. the 5-bit psh field selects the number of imb3 clock cycles in the high pha se of the qclk wave. th e 3-bit psl field selects the number of imb3 clock cycles in the low phase of the qclk wave. example 1 in table 13-21 shows that when the psh = 19, the qclk remains high for 20 cycles if the imb3 clock and with psl = 7 the qclk remains lo w for 8 imb3 clock cycles. example 2 shows that when psh = 11, qclk is high for 12 imb3 clock cy cles and with psl = 7, qclk is low for 8 imb3 clock cycles. finally, example 3 sh ows that with psh = 7 and psl = 7, qclk alternates between high and low every 8 imb3 cycles. table 13-21. qadc64e clock programmability control register 0 information input sample time (ist) =0b00 example number frequency psh psa psl qclk (mhz) conversion time ( s) 1 56 mhz 19 0 7 2.0 7.0 2 40 mhz 11 0 7 2.0 7.0 3 32 mhz 7 0 7 2.0 7.0 qclk examples f sys 56 mhz ex1 40 mhz ex2 imb3 clock qadc64e qclk ex 32 mhz ex3 30 cycles qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-51 13.5.6 periodic / interval timer the on-chip periodic/interval timer can be used to generate trigger events at a programmable interval, initiating execution of queue 1 and/ or queue 2. the periodic /interval timer stays re set under the following conditions: ? both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer ? imb3 system reset or the master reset is asserted ? stop mode is selected ? freeze mode is selected note interval timer single-scan mode does not use the periodic/interval timer until the single-scan enable bit is set. the following two conditions will cause a pulsed reset of the periodic/in terval timer during use: ? a queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer ? a queue 2 operating mode change to a mode whic h uses the periodic/interv al timer, provided queue 1 is not in a mode which uses the periodic/interval timer ? roll over of the timer during the low power stop mode, the periodic timer is held in reset. since low power stop mode causes qacr1 and qacr2 to be reset to zero, a valid periodic or interval timer mode mu st be written after stop mode is exited to rel ease the timer from reset. when the imb3 internal freeze line is asserted and a periodic or interval time r mode is selected, the timer counter is reset after the conve rsion in progress completes. when the periodic or inte rval timer mode has been enabled (the timer is counting), but a tri gger event has not been issued, the freeze mode takes effect immediately, and th e timer is held in reset. when the in ternal freeze line is negated, the timer counter starts counting fr om the beginning. refer to section 13.5.7, ?configuration and control using the imb3 interface ,? for more information. 13.5.7 configuration and cont rol using the imb3 interface the qadc64e module communicates wi th other microcontroller modul es via the imb3. the qadc64e bus interface unit (biu) coordinates imb3 activity with internal qadc 64e bus activity. this section describes the operation of the biu, imb3 read/wri te accesses to qadc64e memory locations, module configuration, and genera l-purpose i/o operation. 13.5.7.1 qadc64e bus interface unit the biu is designed to act as a slave device on the imb3. the biu has the following functions: ? respond with the appropria te bus cycle termination ? supply imb3 interface timing to all internal module signals qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-52 freescale semiconductor biu components consist of: ? imb3 buffers ? address match and module select logic ? the biu state machine ? clock prescaler logic ? data bus routing logic ? interface to the internal module data bus note normal accesses from the imb3 to the qadc64e require two clocks. however, if the cpu tries to access table locations while the qadc64e is accessing them, the qadc64e produces imb3 wait states. from one to four imb3 wait states may be insert ed by the qadc64e in the process of reading and writing. 13.5.7.2 qadc64e bus accessing the qadc64e supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. coherency of results read (ensuring that all results read were taken consecutively in one sc an) is not guaranteed. for example, if a read of two consecut ive 16-bit locations in a result area is made, the qadc64e could change one 16-bit location in the result ar ea between the bus cycles. there is no holding register for the second 16-bit location. all read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. depending on bus master protocol, thes e accesses could include misaligned and 32-bit accesses. figure 13-26 shows the three bus cycles which are im plemented by the qadc64e. the following paragraphs describe how the thr ee types of accesses are used, incl uding misaligned 16-bit and 32-bit accesses. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-53 figure 13-26. bus cycle accesses byte access to an even addre ss of a qadc64e location is show n in the top illustration of figure 13-26 . in the case of write cycles, by te 1 of the register is not disturbed. in the case of a read cycle, the qadc64e provides both byte 0 and byte 1. byte access to an odd address of a qadc64e location is shown in the center illustration of figure 13-26 . in the case of write cycles, byte 0 of the register is not disturbed. in th e case of read cy cles, the qadc64e provides both byte 0 and byte 1. 16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of figure 13-26 . the full 16 bits of data is written to and read from the qad c64e location with each access. 16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit qadc64e locations is accessed. the first bus cycle is treated by the qadc64e as an 8-bit read or write of an odd address. the second cycle is an 8-bit read or write of an even address. the qadc64e address space is organized into 16-bit even address lo cations, so a 16-bit read or write of an odd addr ess obtains or provides the lower half of one qadc64e location, and th e upper half of the foll owing qadc64e location. qadc64e bus cyc acc intermodule bus 8-bit access of an even address (isiz = 01, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 8-bit access of an odd address (isiz = 01, a0 = 1; or isiz = 10, a0 = 1) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 16-bit aligned access (isiz = 10, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-54 freescale semiconductor 32-bit accesses to an even address require two bus cy cles to complete the access, and two full 16-bit qadc64e locations are accessed. the first bus cycle reads or writes the addressed 16-bit qadc64e location and the second cycle reads or writes the follow ing 16-bit location. 32-bit accesses to an odd addr ess require three bus cycl es. portions of three di fferent qadc64e locations are accessed. the first bus cycle is treated by the qad c64e as an 8-bit access of an odd address, the second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. the qadc64e address space is organized into 16-bit even a ddress locations, so a 32-bit read or write of an odd address provides the lower half of one qadc64e location, the full 16-bit content of the following qadc64e location, and the upper half of the third qadc64e location. 13.6 trigger and queue interaction examples this section contains exampl es describing queue priority and conversion timing schemes. 13.6.1 queue priority schemes since there are two conversion command queues and only one a/d converter, there is a priority scheme to determine which conversion is to occur. each queue has a variety of trigger events that are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress. for example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting another trigger event to continue the queue, and so on. the following paragraphs and figures outline the prioritizing criteria used to determine which conversion occurs in each overlap situation. note the situations in figure 13-27 through figure 13-45 are labeled s1 through s19. in each diagram, time is shown increasing from left to right. the execution of queue 1 and queue 2 (q 1 and q2) is shown as a string of rectangles representing the execution ti me of each ccw in the queue. in most of the situations, th ere are four ccws (labeled c1 to c4) in both queue 1 and queue 2. in some of the situati ons, ccw c2 is pres umed to have the pause bit set, to show the similari ties of pause and end-of-queue as terminations of queue execution. trigger events are described in table 13-22 . table 13-22. trigger events trigger events t1 events that trigger queue 1 execution (external trigger, software initiated single-scan enable bit, or completion of the previous continuous loop) t2 events that trigger queue 2 execution (external trigger, software initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-55 when a trigger event causes a ccw execution in progress to be aborte d, the aborted conversion is shown as a ragged end of a shortened ccw rectangle. the situation diagrams also show when key status bits are set. table 13-23 describes the status bits. below the queue execution flows are three sets of bloc ks that show the status information that is made available to the software. the first two rows of status blocks show the condition of each queue as: ? idle ?active ?pause ? suspended (queue 2 only) ? trigger pending the third row of status blocks shows the 4-bit qs status register field that encodes the condition of the two queues. two transition status cases, qs = 0011 and qs = 0111, are not s hown because they exist only very briefly between stable status conditions. the first three examples in figure 13-27 through figure 13-29 (s1, s2, and s3) show what happens when a new trigger event is recognized be fore the queue has completed servic ing the previous trigger event on the same queue. in situation s1 ( figure 13-27 ), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event. the trigger overrun error status bit is set, and otherwise, the premature trigger even t is ignored. a trigger event that occurs before the servicing of the previous trigger event is completed does no t disturb the queue execution in progress. table 13-23. status bits bit function cf flag set when the end of the queue is reached pf flag set when a queue completes execution up through a pause bit trigger overrun error (tor) set when a new trigger event occurs before the queue is finished serving the previous trigger event qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-56 freescale semiconductor figure 13-27. ccw priority situation 1 in situation s2 ( figure 13-27 ), more than one trigger event is rec ognized before servicing of a previous trigger event is complete, the trigger overrun bit is ag ain set, but otherwise, the additional trigger events are ignored. after the queue is complete, the first newly detected tr igger event causes queue execution to begin again. when the trigger event ra te is high, a new trigger event can be seen very soon after completion of the previous queue, leaving software little time to retrieve the prev ious results. also, when trigger events are occurring at a high rate for queue 1, the lower prio rity queue 2 channels may not get serviced at all. figure 13-28. ccw priority situation 2 situation s3 ( figure 13-28 ) shows that when the pause feature is in use, the tri gger overrun error status bit is set the same way, and that queue execution continues unchanged. q1 q2 qs idle idle active idle 0000 1000 0000 0010 0000 tor1 t1 t1 q1: c1 c2 c3 c4 cf1 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle qadc s1 active qadc s2 active idle q1 q2 qs idle active idle active idle 1000 1000 0000 0010 0000 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle c1 c2 c3 c4 t1 cf1 c1 c2 c3 c4 tor1 t1 t1 q1: cf1 tor1 t1 tor1 t1 tor2 t2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-57 figure 13-29. ccw priority situation 3 the next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced. situation s4 ( figure 13-30 ) shows that a queue 2 trigger event that is recognized while queue 1 is active is saved, and as soon as queue 1 is finished, queue 2 servicing begins. figure 13-30. ccw priority situation 4 situation s5 ( figure 13-31 ) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. situation s5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue. qadc s3 pause q1 q2 qs idle active idle active idle 1000 0110 0001 0010 active 0000 idle c1 c2 t1 t1 q1: tor1 pf1 c1 c2 0000 q2: 0100 tor2 pf2 t2 t2 0101 c3 c4 t1 t1 tor1 cf1 active pause 1001 c3 c4 cf2 t2 t2 tor2 qadc s4 q1 q2 qs idle idle active idle 0000 1000 0010 active 0000 c1 c2 c3 c4 t1 q1: cf1 q2: c1 c2 c3 c4 t2 cf2 idle 1011 triggered qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-58 freescale semiconductor figure 13-31. ccw priority situation 5 the remaining situations, s6 through s11, show the impact of a queue 1 trig ger event occurring during queue 2 execution. queue 1 is higher in priority the c onversion taking place in queue 2 is aborted, so that there is not a variable latency time in responding to queue 1 trigger events. in situation s6 ( figure 13-32 ), the conversion initiated by the sec ond ccw in queue 2 is aborted just before the conversion is complete, so that queue 1 execution can begi n. queue 2 is considered suspended. after queue 1 is finished, queue 2 st arts over with the first ccw, when the res (resume) control bit is set to 0. situation s7 ( figure 13-33 ) shows that when pause operation is not in use with queue 2, queue 2 suspension works the same way. figure 13-32. ccw priority situation 6 qadc s5 q1 q2 qs idle idle idle 0000 1000 0010 active 0000 c1 c2 t1 q1: c1 c2 pf2 c3 c4 c3 c4 cf2 idle 1011 trig q2: t2 t2 pf1 pause active pause tor2 t2 t2 cf1 tor2 t1 active trig 0110 active active 0101 1001 1011 qadc s6 idle q1 q2 qs idle idle 0000 1000 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c1 c2 c3 c4 cf2 t2 0010 0000 resume=0 c2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-59 figure 13-33. ccw priority situation 7 situations s8 and s9 ( figure 13-34 and figure 13-35 ) repeat the same two situat ions with the resume bit set to a one. when the res bit is set, following su spension, queue 2 resumes ex ecution with the aborted ccw, not the first ccw in the queue. figure 13-34. ccw priority situation 8 qadc s7 t1 t1 pause q1 q2 qs idle idle idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 c1 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active act active resume=0 c2 active suspend suspend qadc s8 idle q1 q2 qs idle idle 0000 1000 0010 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c2 c3 c4 cf2 t2 0000 resume=1 c2 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-60 freescale semiconductor figure 13-35. ccw priority situation 9 situations s10 and s11 ( figure 13-36 and figure 13-37 ) show that when an a dditional trigger event is detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue 2 were being executed when a new trigger event occurs. trigger overrun on queue 2 thus permits the software to know that queue 1 is taking up so much qadc64e time that queue 2 trigge r events are being lost. figure 13-36. ccw priority situation 10 qadc s9 t1 pause q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 pause 0110 c1 q2: t2 c2 pf2 t1 c3 c4 cf1 c4 cf2 suspend act active suspend t2 c3 c1 resume=1 c2 c4 active active qadc s10 t1 t1 pause q1 q2 qs idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active 0110 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active c1 act t2 tor2 t2 tor2 resume=0 c2 active active suspend suspend paus qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-61 figure 13-37. ccw priority situation 11 the above situations cover normal overlap conditions that arise with asynchronous trigger events on the two queues. an additional conflict to consider is that the freeze c ondition can arise while the qadc64e is actively executing ccws. the conventional us e for the freeze mode is for software/hardware debugging. when the cpu background debug mode is enab led and a breakpoint occurs, the freeze signal is issued, which can cause periphe ral modules to stop operation. when freeze is detected, the qadc64e completes the conversion in progress, unlike queue 1 suspending queue 2. after the freeze condition is removed, the qadc64e continues queue exec ution with the next ccw in sequence. trigger events that occur during fre eze are not captured. when a trigger event is pe nding for queue 2 before freeze begins, that trigger event is remembered when the freeze is pa ssed. similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 re sumes execution as soon as queue 1 is finished. situations 12 through 19 ( figure 13-38 to figure 13-45 ) show examples of all of the freeze situations. figure 13-38. ccw freeze situation 12 qadc s11 t1 t1 c3 c4 cf1 pause q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 suspend act c1 active suspend t2 tor2 t2 tor2 c2 pf2 c4 cf2 t2 c3 c2 c4 resume=1 active qadc s12 c3 c4 cf1 c1 c2 t1 q1: freeze qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-62 freescale semiconductor figure 13-39. ccw freeze situation 13 figure 13-40. ccw freeze situation 14 figure 13-41. ccw freeze situation 15 figure 13-42. ccw freeze situation 16 qadc s13 c1 c2 t2 q2: cf2 c3 c4 freeze qadc s14 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 t2 t2 (triggers ignored) qadc s15 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 t1 t1 (triggers ignored) qadc s16 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 pf1 (triggers ignored) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-63 figure 13-43. ccw freeze situation 17 figure 13-44. ccw freeze situation 18 figure 13-45. ccw freeze situation 19 13.6.2 conversion timing schemes this section contains some conve rsion timing examples. example 1 below shows the timing for basic conversions where the following is assumed: ? q1 begins with ccw0 and ends with ccw3 ? ccw0 has pause bit set ? ccw1 does not have pause bit set ? external trigger rise-edge for q1 ? ccw4 = bq2 and q2 is disabled qadc s17 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 pf2 (triggers ignored) qadc s18 c1 c2 t1 q1: cf1 c3 c4 freeze t2 c1 c2 q2: c3 cf2 c4 (trigger captured, response delayed after freeze) qadc s19 c1 c2 t1 q1: cf1 c4 freeze cf2 c4 c1 c2 t2 q2: c3 c3 c4 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-64 freescale semiconductor ? q1 res shows relative result register updates figure 13-46. external trigger mode (positive edge) timing with pause recall qs = 0 => queues disabled; qs = 8 => q1 active, q2 disabled; qs= 4 => q1 paused, q2 disabled. a time separator was provided betw een the triggers and end of conve rsion (eoc). the relationship to qclk displayed is not guaranteed. cwpq1 and cwpq2 typically lag cwp and only match cwp when the associated queue is inactive. another way to view cwpq1 and cwpq2 is that thes e registers update when eoc triggers the result register to be written. when the pause bit is set (ccw0), please note that cwp does not increment unt il triggered. when the pause is not set (ccw1), the cwp increments with eoc. the conversion results q1 res(x) show the result as sociated with ccw(x). so that r0 represents the result associated with ccw0. example 2 below shows the timing for conversi ons in gated mode single-scan with the same assumptions as example 1 except: ? no pause bits set in any ccw ? external trigger gated single-scan mode for q1 ? single-scan bit is set when the gate closes and opens again the c onversions start with the first ccw in q1. when the gate closes the active conversi on completes before the queue goes idle. when q1 completes both the cf1 bit sets and the sse bit clears. qclk trig1 eoc qs cwp cwpq1 q1 res ccw1 04 ccw0 last ccw1 ccw2 84 8 r0 r1 conversion time is >= 14 qclks ccw0 last time between triggers qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-65 figure 13-47. gated mode , single-scan timing example 3 below shows the timing for conversions in gated continuous-scan mode with the same assumptions in the amended de finition for the pf bit in th is mode to reflect the c ondition that a gate closing occurred before the queue completed is a proposal under consideration at th is time as example 2. note at the end of q1,the completion flag cf1 sets and the queue restarts. also, note that if the queue starts a second time and completes, the trigger overrun flag tor1 sets. trig1 eoc qs cwp cwpq1 q1 res ccw1 0 8 ccw1 last ccw1 ccw2 last 08 r0 r1 ccw0 last ccw1 ccw0 ccw0 r1 ccw0 r0 ccw2 ccw3 r2 sse ccw3 r3 cf1 software must set sse pf1 software must clear pf1 0 (gate) qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-66 freescale semiconductor figure 13-48. gated mode, continuous scan timing 13.7 qadc64e integration requirements the qadc64e requires accurate, noise -free input signals for proper opera tion. this secti on discusses the design of external circuitry to maximize qadc64e performance. the qadc64e uses the exte rnal signals shown in figure 13-1 . there are 16 channel si gnals that can also be used as general-purpose digital input signals, 8 of which can be configured as either digital input or output signals. 13.7.1 port digital input/output signals the 16 port signals on the qadc64e module can be used as analog i nputs. port a signals can be configured as digital input or digi tal output signals and port b signals can be used as 8-bit digital input signals. port a signals are referred to as pqa[7:0] when us ed as a bidirectional 8-bi t digital input/output port. these eight signals may be used for general-purpose digital input si gnals or push-pull digital output signals. port b signals are referred to as pq b[7:0] when used as digital input signals. port a and b signals are connected to a digital input synchr onizer during reads and ma y be used as general purpose digital inputs when the applie d voltages meet high voltage input (v ih ) and low voltage input (v il ) requirements. refer to appendix f, ?electrical characteristics ,? for more information on voltage requirements. trig1 eoc qs cwp cwpq1 q1 res 0 8 last ccw0 ccw1 r1 ccw3 r3 cf1 tor1 ccw0 last xx ccw2 r2 ccw2 ccw1 ccw0 r0 ccw0 ccw3 r3 ccw3 ccw2 r2 ccw3 q restart (gate) q restart qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-67 port a signals are configured as inputs or out puts by programming the port da ta direction register, ddrqa. the digital input signal states are read from the port data regi ster, portqa, when the port data direction register specifies that the si gnals are inputs. the digital data in the port data register is driven onto the port a signals when the corresponding bit in the port data direction register sp ecifies that the signals are outputs. refer to appendix b, ?internal memory map ,? for more information. since the outputs are configured as push-pull drivers, ex ternal pull-up provisions are not nece ssary when the output is used to drive another integrated circuit. 13.7.2 external trigger input signals the qadc64e uses two external trigger signals (etr ig[2:1]). each of the tw o input external trigger signals is associated with one of the scan queues, queue 1 or queue 2 the assignment of etrig[2:1] to a queue is made in the qacr0 register by the trg bit. when trg=0, etrig[1] triggers queue 1 and etrig[2] triggers queue 2. when trg=1, etrig[1] tr iggers queue 2 and etrig [2] triggers queue 1. note the etrig[2:1] pins on the mpc561/mpc563 are multiplexed with the pcs[7:6] pins. 13.7.3 analog power signals v dda and v ssa signals supply power to the analog subs ystems of the qadc64e module. dedicated power is required to isolate the sensitive analog circ uitry from the normal levels of noise present on the digital power supply. refer to appendix f, ?electrical characteristics ,? for more information. the analog supply signals (v dda and v ssa ) define the limits of the analog reference voltages (v rh and v rl ) and of the analog multiplexer inputs. figure 13-49 is a diagram of the analog input circuitry. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-68 freescale semiconductor figure 13-49. equivalent analog input circuitry since the sample amplifier is powered by v dda and v ssa , it can accurately transf er input signal levels up to but not exceeding v dda and down to but not below v ssa. if the input signal is outsi de of this range, the output from the sample amplifier is clipped. in addition, v rh and v rl must be within the range defined by v dda and v ssa . as long as v rh is less than or equal to v dda and v rl is greater than or equal to v ssa and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by v rl and v rh . if v rh is greater than v dda , the sample amplifier can never transfer a fu ll-scale value. if v rl is less than v ssa , the sample amplifier can never transfer a zero value. figure 13-50 shows the results of reference vol tages outside the range defined by v dda and v ssa . at the top of the input signal range, v dda is 10 mv lower than v rh . this results in a ma ximum obtainable 10-bit conversion value of 0x3fe. at th e bottom of the signal range, v ssa is 15 mv higher than v rl , resulting in a minimum obtainable 10-bit conversion value of three. sample amp 16 channels v ssa v rl vdda qadc64e 16ch sample amp vrh s/h rc dac comparator cp qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-69 figure 13-50. errors resulting from clipping 13.7.3.1 analog supply filtering and grounding two important factors influencing performance in an alog integrated circuits are supply filtering and grounding. generally, digital circuits use bypass capacitors on every vdd/vss signal pair. this applies to analog sub-modules also. the distribution of power and ground is equally important. analog supplies should be isolated fr om digital supplies as much as pos sible. this necessity stems from the higher performance requirements of ten associated with analog circuits . therefore, deriving an analog supply from a local digital supply is not recomme nded. however, if for econom ic reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of th e supplies already mentioned. for example, an rc low pass filter could be used to isolat e the digital and analog supplies when generated by a common regulator. if multiple high precision an alog circuits are locally employed (i.e., two a/d converters), the analog supplies should be isolated from each other as sharing supplies introduces the potential for interference between analog circuits. grounding is the most importa nt factor influencing an alog circuit performance in mixed signal systems (or in stand-alone analog systems). care must be taken to not introduce a dditional sources of noise into the analog circuitry. common sources of noise incl ude ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. qadc64e clipping 0 .020 5.100 5.110 input in volts (v rh = 5.120, = 0 v) 1 2 3 4 5 6 7 8 3fa 3fb 3fc 3fd 3fe 3ff .010 .030 5.120 5.130 10-bit result (hexadecimal) v rl qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-70 freescale semiconductor the problem of how and when to combine digital a nd analog grounds arises from the large transients which the digital ground must handle. if the digital gr ound is not able to handle the large transients, the current from the large transients can return to gr ound through the analog ground. it is the excess current overflowing into the analog ground wh ich causes performance degradat ion by developing a differential voltage between the true analog ground and the microcontroller?s ground signa l. the end result is that the ground observed by the analog circuit is no longer tr ue ground and often ends in skewed results. two similar approaches designed to improve or eliminate the problem s associated with grounding excess transient currents involve st ar-point ground systems. one approach is to star-point the different grounds at the power supply origin, thus keep ing the ground isolated. refer to figure 13-51 . another approach is to star-point the diff erent grounds near the analog ground signal on the microcontroller by using small tr aces for connecting the non-analog grounds to the analog ground. the small traces are mean t only to accommodate dc diff erences, not ac transients. note this star-point scheme still require s adequate grounding for digital and analog subsystems in additi on to the star-point ground. other suggestions for pcb layout in wh ich the qadc64e is employed include: ? analog ground must be low impedance to all analog ground points in the circuit. ? bypass capacitors should be as close to the power signals as possible. the analog ground should be isolated from the digita l ground. this can be done by cutting a separate ground plane for the analog ground ? non-minimum traces should be utilized for conn ecting bypass capacitors and filters to their corresponding ground/power points. ? distance for trace runs should be minimized where possible qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-71 figure 13-51. star-ground at the point of power supply origin 13.7.4 analog reference signals v rh and v rl are the dedicated input signals for the hi gh and low reference voltages. separating the reference inputs from the power suppl y signals allows for additional ex ternal filtering, which increases reference voltage precision and stability, and subseque ntly contributes to a higher degree of conversion accuracy. no a/d converter can be more accurat e than its analog reference. any noise in the reference can result in at least that much error in a conversion. the reference for th e qadc64e, supplied by signals v rh , and v rl , should be low-pass filtered from it s source to obtain a noise-free, cl ean signal. in many cases, simple capacitive bypassing may sufficed. in extreme cases, i nductors or ferrite beads ma y be necessary if noise or rf energy is present. series resistance is not advi sable since there is an effective dc current requirement from the reference volta ge by the internal resi stor string in the rc dac array. external resistance may introduce error in this architecture under certain conditions. any series devices in the filter network should contain a mini mum amount of dc resistance. 13.7.5 analog input signals analog inputs should have low ac impedance at the signals. low ac impedance can be realized by placing a capacitor with good high frequenc y characteristics at the input sign al of the part. ideally, that capacitor should be as large as possi ble (within the practical range of capacitors that still have good high frequency characteristics). this capacitor has two effects: ? it helps attenuate any noise that may exist on the input. qadc64e vrh vrl vssa vdda vdd vss analog power supply +5v +5v agnd digital power +5v pgnd pcb supply qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-72 freescale semiconductor ? it sources charge during the sample period when the analog signal source is a high-impedance source. series resistance can be used with the capacitor on an input signal to implement a simple rc filter. the maximum level of filtering at the input signals is application depe ndent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input . simple rc filtering at the signal may be limited by the source impedance of the transducer or circuit supplyi ng the analog signal to be measured. refer to section 13.7.5.3, ?error re sulting from leakage ,? for more information. in some cases, the size of the capacitor at the signal may be very small. figure 13-52 is a simplified model of an input channel. re fer to this model in the following discussion of the interaction between the external circui try and the circuitry inside the qadc64e. figure 13-52. electrical model of an a/d input signal in figure 13-52 , r f , r src and c f comprise the external filter circuit. c p is the internal parasitic capacitor. c samp is the capacitor array used to sa mple and hold the input voltage. v i is an internal vol tage source used to provide charge to c samp during sample phase. the following paragraphs provide a simplified description of the in teraction between the qadc64e and the external circuitry. this circuitry is assumed to be a simple rc low-pass fi lter passing a signal from a source to the qadc64e input signal. the fo llowing simplifying assumptions are made: ? the external capacitor is perfect (no leakage, no significant dielectric ab sorption characteristics, etc.) ? all parasitic capacitance associated with the input signal is in cluded in the value of the external capacitor ? inductance is ignored qadc64e sample amp model s1 amp r f s3 s2 c samp vi c p c f v src internal circuit model external filter = source voltage = internal parasitic capacitance v src r f c f c p c samp = sample capacitor v i = filter impedance = filter capacitor = internal voltage source during sample and hold source r src r src = source impedance qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-73 ? the ?on? resistance of th e internal switches is 0 ? and the ?off? resistance is infinite 13.7.5.1 analog input considerations the source impedance of the analog signal to be m easured and any intermedia te filtering should be considered whether external multiplexing is used or not. figure 13-53 shows the connection of eight typical analog signal sources to one qadc64e analog input signal through a separate multiplexer chip. also, an example of an analog signal source connected directly to a qadc64e analog input channel is displayed. qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-74 freescale semiconductor 1 typical value 2 rfilter typically 10kw?20kw figure 13-53. external multiplexing of analog signal sources ~ ~ ~ ~ ~ ~ ~ ~ c p c samp c p c sa m p c in = c p + c samp r muxout r source 2 typical mux chip qadc64e qadc64e ext mux ex ~ c filter c source r filter 2 c muxin c muxout (mc54hc4051, mc74hc4051, mc54hc4052, mc74hc4052, mc54hc4053, etc.) r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin c filter r filter 2 r source 2 c source c pcb c pcb analog signal source filtering and interconnect 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 interconnect qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-75 13.7.5.2 settling time fo r the external circuit the values for r src , r f and c f in the external circuitry determine the length of time required to charge c f to the source voltage level (v src ). at time t = 0, v src changes in figure 13-52 while s1 is open, disconnecting the internal ci rcuitry from the external circuitry. assume that th e initial voltage across c f is zero. as c f charges, the voltage across it is determined by the following equation, where t is the total charge time: eqn. 13-1 as t approaches infinity, v cf will equal v src . (this assumes no internal leak age.) with 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. assuming worst case (v src = full scale), table 13-24 shows the require d time for c f to charge to within 1/ 2 of a count of the actual source voltage during 10-bit conversions. table 13-24 is based on the rc network in figure 13-52 . note the following times are completely independent of the a/d converter architecture (assuming the qadc64e is not affecting the charging). the external circuit described in table 13-24 is a low-pass filter. a user in terested in measuring an ac component of the external signal must take the characteristics of this filter into account. 13.7.5.3 error resulting from leakage a series resistor limits the current to a signal, therefore input leakage acting through a large source impedance can degrade a/d accuracy. the maxi mum input leakage current is specified in appendix f, ?electrical characteristics .? input leakage is greate r at higher operating temper atures. in the temperature range from 125 c to 50 c, the leakage current is halved for every 8 ? 12 c reduction in temperature. assuming v rh ? v rl = 5.12 v, one count (assuming 10-bit reso lution) corresponds to 5 mv of input voltage. a typical input leakag e of 200 na acting through 10 k ? of external series resistance results in an error of 0.4 count (2.0 mv). if the source impedance is 100 k ? and a typical leakage of 100 na is present, an error of two counts (10 mv) is introduced. table 13-24. external circuit settling time to 1/2 lsb (10-bit conversions) filter capacitor (cf) source resistance (r f + r src ) 100 ? 1 k ? 10 k ? 100 k ? 1 f 760 s 7.6 ms 76 ms 760 ms .1 f76 s 760 s 7.6 ms 76 ms .01 f7.6 s76 s 760 s 7.6 ms .001 f 760 ns 7.6 s76 s 760 s 100 pf 76 ns 760 ns 7.6 s76 s v cf v src 1e ? t ? r f r src + () c f ---------------------------------------------------------- - ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-76 freescale semiconductor in addition to internal junction leakage, external leakage (e.g., if external cl amping diodes are used) and charge sharing effects with internal capacitors also contribute to the total leakage current. table 13-25 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. the error is listed in terms of 10-bit counts. caution leakage from the part below 200 na is obtainable only within a limited temperature range. 13.7.5.4 accommodating positive /negative stress conditions positive or negative stress refers to conditions which exceed nominally defined operating limits. examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ranges) or causing currents into or out of the signal which exceed normal limits. qadc64e specific considerat ions are voltages greater than v dda , v rh or less than v ssa applied to an analog input which cause excessive currents into or out of the input. refer to appendix f, ?electrical characteristics ,? to for more information on exact magnitudes. either stress condition can potentially disrupt conversion results on neighboring inputs. parasitic devices, associated with cmos processes, can cause an im mediate disruptive influen ce on neighboring signals. common examples of parasitic device s are diodes to substrate and bipolar devices with the base terminal tied to substrate (v ssi /v ssa ground). under stress conditions, curren t injected on an adjacent signal can cause errors on the selected channel by devel oping a voltage drop across the selected channel?s impedances. figure 13-54 shows an active parasitic bipolar npn transistor when an input signal is subjected to negative stress conditions. figure 13-55 shows positive stress conditions ca n activate a similar pnp transistor. figure 13-54. input signal subj ected to negative stress table 13-25. error resulting from input leakage (ioff) source impedance leakage value (10-bit conversions) 100 na 200 na 500 na 1000 na 1 k ? ? ? 0.1 counts 0.2 counts 10 k ? 0.2 counts 0.4 counts 1 counts 2 counts 100 k ? 2 counts 4 count 10 counts 20 counts qadc64e par r stress r selected adjacent 10k signal under parasitic i injn i in + stress v stress device signal v in an n an n+1 qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 13-77 figure 13-55. input signal subj ected to positive stress the current into the signal (i injn or i injp ) under negative or positive stress is determined by the following equations: eqn. 13-2 eqn. 13-3 where: v stress = adjustable voltage source v eb = parasitic pnp emitter/base voltage (refer to v negclamp in appendix f, ?electrical characteristics ?) v be = parasitic npn base/emitter voltage (refer to v negclamp in appendix f, ?electrical characteristics ?) r stress = source impedance (10- k ? resistor in figure 13-54 and figure 13-55 on stressed channel) r selected = source impedance on chan nel selected for conversion the current into (i in ) the neighboring signal is determined by the k n (current couplin g ratio) of the parasitic bipolar transistor (k n << 1). the i in can be expressed by the following equation: i in = - k n * i inj where i inj is either i injn or i injp . a method for minimizing the impact of stress conditi ons on the qadc64e is to strategically allocate qadc64e inputs so that the lower a ccuracy inputs are adjacent to the inputs most likely to see stress conditions. also, suitable source impedances shoul d be selected to meet design goals and minimize the effect of stress conditions. qadc64e par r stress r selected adjacent 10k signal under parasitic i injp i in + stress v stress device signal v in v dda an n an n+1 i injn v stress v be ? () ? r stress ------------------------------------------------------ = i injp v stress v eb ? v dda ? r stress --------------------------------------------------------------------- - = qadc64e legacy mode operation mpc561/mpc563 reference manual, rev. 1.2 13-78 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-1 chapter 14 qadc64e enhanced mode operation the two queued analog-to-digital converter ( qadc) modules on the mpc561/mpc563 devices are 10-bit, unipolar, successive approxima tion converters. the modules can be configured to operate in one of two modes, legacy mode (for mpc 555 compatibility) and e nhanced mode. this chap ter describes how the module operates in enha nced mode. refer to chapter 13, ?qadc64e legacy mode operation ,? for information regarding the qadc64e functionality in legacy mode. for this revision of the qadc, the name qadc64e implies the en hanced version of the qadc64 module, not just enhanced mode of operation. for simplicity, the names q adc and qadc64e may be used interchangeably throughout this document. 14.1 qadc64e block diagram figure 14-1 displays the major components of th e qadc64e modules on the mpc561/mpc563. figure 14-1. qadc64e block diagram queues of 10-bit conversion command words (ccw ), 64 entries bus interface unit digital control 10-bit result table, 64 entries 10-bit to 16-bit result alignment 10-bit analog to digital converter analog input multiplexor and digital signal functions external triggers external mux address up to 16 analog input signals reference inputs analog power inputs imb3 (biu) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-2 freescale semiconductor 14.2 key features and quick reference diagrams this section gives an overview of the impl ementation of the two qadc64e modules on the mpc561/mpc563. it can also be used for a quick reference while programming the modules. 14.2.1 features of the qadc64 e enhanced mode operation ? internal sample and hold ? directly supports up to four external multiplexers (for example, the mc14051) ? up to 41 analog input channels using qadc64 external multiplexing ? programmable input sample time for various source impedances ? minimum conversion time of 7s (w ith typical qclk frequency, 2 mhz) ? two conversion command queues with a total of 64 entries ? sub-queues possible using pause mechanism ? queue complete and pause software interrupts available on both queues ? queue pointers indicate cu rrent location for each queue ? automated queue modes initiated by ? external edge trigger ? periodic/interval timer, within qadc64e module ? software command ? external gated trigger (queue 1 only) ? single-scan or continuous-scan of queues ? 64 result registers in each qadc64e module ? output readable in three formats ? right-justified unsigned ? left-justified signed ? left-justified unsigned ? unused analog channels can be us ed as digital input/output signals ? modulus prescaler can divide the syst em clock for the converter by two to 128 ? alternate reference input, with contro l in the conversion command word (ccw) the analog section includes input signals, an analog mu ltiplexer, and the sample and hold circuits. the analog conversion is performed by th e digital-to-analog converter (dac ) resistor-capacitor array and a high-gain comparator. the digital control section contains queue control logic to sequence th e conversion process and interrupt generation logic. also included are th e periodic/interval timer, control a nd status registers, the conversion command word (ccw) table ram, and the result table ram. the bus interface unit (biu) allows the qadc64e to operate with the applicat ions software through the imb3 environment. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-3 14.2.2 memory map the qadc64e occupies one kbyte, or 512 16-bit entr ies, of address space. ten 16-bit registers are control, port, and status registers, 64 16-bit entries are th e ccw table, and 64 16-bit entries are the result table, and occupy 192 16-bit address loca tions because the result data is readable in three data alignment formats. each qadc64e module on mpc561/mpc 563 has its own memory space. table 14-1 shows the memory map for qadc64e module a, it occupies 0x30 4800 to 0x30 4bff. table 14-2 shows the memory map for qadc64e module b. module b has the same offset scheme startin g at 0x30 4c00. qadc64e_b occupies 0x30 4c00 to 0x30 4fff. table 14-1. qadc64e_a address map address msb lsb register 0 1 2 3 4 5 6 7 8 9 10 11121314 15 0x30 4800 stop frz loc k fli p sup v module config. 1 1 registers are accessible only as supervisor data space. 0x30 4802 test mode te s t 1 0x30 4804 irl1 irl2 interrupt 1 0x30 4806 portqa portqb port data 0x30 4808 ddrqa ddrqb port direction 0x30 480a emu x trg qclk prescaler control 0 0x30 480c cie1 pie 1 sse 1 mq1 control 1 0x30 480e cie2 pie 2 sse 2 mq2 res ume bq2 control 2 0x30 4810 cf1 pf1 cf2 pf2 tor1 tor2 qs cwp status 0 0x30 4812 cwpq1 cwpq2 status 1 0x30 4814- 0x30 49ff reserved reserved 0x30 4a00- 0x30 4a7f pre f ist chan ccws 0x30 4a80- 0x30 4aff 0000 00 unsigned right justified results 0x30 4b00- 0x30 4b7f sign signed left justified 00 0000 results 0x30 4b80 0x30 4bff unsigned left justified 00 0000 results qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-4 freescale semiconductor accesses to supervisor-only data space is permitted onl y when the bus master is operating in supervisor access mode. assignable data space can be either restricted to supervis or-only access or unrestricted to both supervisor and user data space addresses. see section 14.3.1.4, ?supervisor /unrestricted address space .? 14.2.3 legacy and enhan ced modes of operation the qadc64e modules can be configured to operate in legacy or enhanced mode. legacy mode is the default state out of reset. the qadc 64e modules are configured for enha nced mode by a se ries of writes table 14-2. qadc64e_b address map address msb lsb register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4c00 stop frz loc k fli p supv module config. 1 1 registers are accessible only as supervisor data space 0x30 4c02 test mode te s t 0x30 4c04 irl1 irl2 interrupt 0x30 4c06 portqa portqb port data 0x30 4c08 ddrqa ddrqb port direction 0x30 4c0a emux tr g qclk prescaler control 0 0x30 4c0c cie1 pie 1 sse1 mq1 control 1 0x30 4c0e cie2 pie 2 sse2 mq2 resu me bq2 control 2 0x30 4c10 cf1 pf1 cf2 pf2 tor 1 tor2 qs cwp status 0 0x30 4c12 cwpq1 cwpq2 status 1 0x30 4c14- 0x30 4dff reserved reserved 0x30 4e00- 0x30 4e7f pre f ist chan ccws 0x30 4e80- 0x30 4eff 0000 00 unsigned right justified results 0x30 4f00- 0x30 4f7f sign signed left justified 00 0000 results 0x30 4f80 0x30 4fff unsigned left justified 00 0000 results qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-5 to the lock and flip bits of the module configurati on register. this will be described in section 14.3.1.3, ?switching between legacy and enhanced modes of operation .? 14.2.4 using the queue and result word table the heart of the qadc is its c onversion command word (ccw) queues. this is where the module is programmed to convert a pa rticular channel according to a particular requireme nt. the queues are created by writing ccws into the ccw table in the regist er memory. the queues are controlled by the three control registers, and their status can be read from the two status regi sters. as conversions are completed the digital value is written into the result word table. figure 14-2 shows the ccw queue and the result word table. figure 14-2. ccw queue and result table block diagram 14.2.5 external multiplexing the qadc can use from one to four 8-input external multiplexer chips to expand the number of analog signals that may be converted. the externally multip lexed channels are automatically selected from the conversion command word (ccw) table 0x200 (ccw0) bq2 0x27e (ccw63) a/d converter result word table result 0 result 63 channel select, sample, hold, and analog to digital conversion begin queue 1 begin queue 2 end of queue 1 end of queue 2 pref ist chan 10-bit conversion command word (ccw) format 10-bit result is software readable in three different 16-bit formats p = pause until next trigger ref = use alternate reference voltage ist = input sample time chan = channel number and end_of_queue code result s result 0 right justified, unsigned result format left justified, unsigned result format left justified, signed result format 15 0 15 0 s = sign bit result 15 0 00 00 0 000 00 0 000 00 0 address offsets: 0x280-0x2ff 1 0x380-0x3ff 1 0x300-0x37f 1 msb msb lsb lsb 8 6 9 15 7 7 8 1 7 8 7 8 note 1: these offsets must be added to the modu le base address: a = 0x30 4800 or b = 0x30 4c00 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-6 freescale semiconductor channel field of the conversion command word (ccw ) table. external multiplex mode is software selectable, by setting the emux bi t of control register 0 (qacr0). figure 14-3 shows the maximum configurati on of four external multiplexe r chips connected to the qadc. the qadc provides three multiple xer address signals ? ma0, ma1, ma2 ? to select one of the multiplexer chips. these outputs are the multiplexer c ontrol lines and they are connected to all external multiplexer chips. the analog output of each of the four multiplexer chips is connected to four se parate qadc inputs ? anw, anx, any, anz. these signals are the first four signals of port b and each one can represent eight analog input channels. the qadc converts the proper input channel (anw, an x, any, anz) by interpreting the channel number in the ccw. refer to table 14-3 . figure 14-3. example of external multiplexing i table 14-3. multiplexed analog input channels multiplexed analog input channels anw (an44) 0 through 7 anx (an45) 8 through 15 any (an46) 16 through 23 anz (an47) 24 through 31 an52/ma0/pqa0 an53/ma1/pqa1 an54/ma2/pqa2 an55/pqa3 an56/pqa4 an57/pqa5 an58/pqa6 an59/pqa7 an44/anw/pqb0 an45/anx/pqb1 an46/any/pqb2 an47/anz/pqb3 an48/pqb4 an49/pqb5 an50/pqb6 an51/pqb7 v dda v ssa v rl v rh mux an0 an1 an2 an3 an4 an5 an6 an7 mux an8 an9 an10 an11 an12 an13 an14 an15 mux an16 an17 an18 an19 an20 an21 an22 an23 mux an24 an25 an26 an27 an28 an29 an30 an31 analog power analog references port b port a qadc digital control analog converter analog multiplexer port logic and etrig1 etrig2 external triggers: altref qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-7 table 14-4 shows the total number of analog input channe ls supported with zero to four external multiplexer chips using one qadc module. note: qadc64e external mux users if a qadc64e module is in external multiplexing (emux) mode then the multiplexer address signal channels an[52:54] should not be programmed into queues. 14.3 programming the qadc64e registers the qadc64e has three global regist ers for configuring module operation. ? the module configuration register, qadcmcr ( section 14.3.1, ?qadc64e module configuration register ?) ? the interrupt register, qadcint ( section 14.3.2, ?qadc64e interrupt register ?) ? the test register, qadctest. this re gister is used for factory test only. these global registers are always defined to be in supervisor -only data space. refer to table 14-1 for the qadc64e_a address map and table 14-2 for qadc64e_b address map. see section 14.3.1.4, ?supervisor/unrestricted address space ? for access modes for these registers. the remaining five registers in th e control register block control th e operation of the queuing mechanism, and provide a means of monito ring the operation of the qadc64e. ? control register 0 (qacr0 ) contains hardware configuration information ( section 14.3.5, ?control register 0 ?) ? control register 1 (qacr1) is associated with queue 1 ( section 14.3.6, ?control register 1 ?) ? control register 2 (qacr2) is associated with queue 2 ( section 14.3.7, ?control register 2 ?) ? status registers (qasr0 and qasr1) provide vi sibility on the status of each queue and the particular conversion th at is in progress ( section 14.3.8, ?status registers (qasr0 and qasr1) ?) the conversion command word (ccw) table contains 64 entries to hold the software programmable analog conversion sequences. each ccw table entry is a 16-bit entry, though only 10 bits are used. the final block of address space belongs to the result word table, which appears in three places in the memory map. each result word table lo cation holds one 10-bi t conversion value. table 14-4. analog input channels number of analog inpu t channels available directly connected + external multiplexed = total channels no external mux chips one external mux chip two external mux chips three external mux chips four external mux chips 16 20 27 34 41 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-8 freescale semiconductor 14.3.1 qadc64e module configuration register the qadcmcr contains fields and bits that control freeze and stop modes, operating mode of the qadc64e module, determine the privilege level requi red to access most registers and master/slave operation. . 14.3.1.1 low power stop mode when the stop bit in the qadcmcr is set, th e qadc64e clock (qclk) which clocks the a/d converter, is disabled and the an alog circuitry is powered down. this results in a static, low power consumption, idle condition. the stop mode aborts any convers ion sequence in progre ss. because the bias currents to the analog circuits are turned off in st op mode, the qadc64e require s some recovery time (t sr in appendix f: electricl characteristic s) to stabilize the anal og circuits after the stop enable bit is cleared. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field stop frz ? lock flip supv ? sreset 0000_0000 1 000_0000 addr 0x30 4800 (qadcmcr_a); 0x30 4c00 (qadcmcr_b) figure 14-4. module confi guration regist er (qadcmcr) table 14-5. qadcmcr bit descriptions bits name description 0 stop stop enable. refer to section 14.3.1.1, ?low power stop mode ? for more information. 0 disable stop mode 1 enable stop mode 1 frz freeze enable. refer to section 14.3.1.2, ?freeze mode ? for more information. 0 ignores the imb3 internal freeze signal 1 finish any conversion in progress, then freeze 2:5 ? reserved 6 lock lock/unlock qadc mode of operation as defined by flip bit. refer to section 14.3.1.3, ?switching between legacy and enhanced modes of operation ? for more information. 0 qadc mode is locked 1 qadc mode is unlocked and changeable using flip bit 7 flip qadc mode of operation. the flip bit allows selection of the mode of operation of the qadc module, either legacy mode (default) or enhanc ed mode. this bit can only be written when the lock is set (unlocked). refer to section 14.3.1.3, ?switchin g between legacy and enhanced modes of operation ? for more information. 0 legacy mode enabled 1 enhanced mode enabled 8 supv supervisor/unrestricted data space. refer to section 14.3.1.4, ?supervisor/unrestricted address space ? and ta b l e 1 4 - 6 for more information. 0 only the module configuration register, test register, and interrupt register are designated as supervisor-only data space. access to all other locations is unrestricted. 1 all qadc64e registers and ccw/result tables ar e designated as supervisor-only data space. 9:15 ? reserved. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-9 in stop mode: ? biu state machine and logic do not shut down ? the ccw and result ram is not reset and is not accessible ? the module configuratio n register (qadcmcr), the interrupt register (qadcint ), and the test register (qadctest) are fully accessible and are not reset ? the data direction register (d drqa), port data register (portq a/portqb), and control register 0 (qacr0) are not reset a nd are read-only accessible ? control register 1 (qacr1), cont rol register 2 (qacr2), and th e status registers (qasr0 and qasr1) are reset and ar e read-only accessible ? in addition, the periodic/interval time r is held in reset during stop mode if the stop bit is clear, stop mode is disabled. 14.3.1.2 freeze mode freeze mode occurs when backgr ound debug mode is enabled in the usiu and a breakpoint is encountered. this is indicated by th e assertion of the internal freeze line on the imb3. the frz bit in the qadcmcr determines whether or not the qadc 64e responds to an imb3 internal freeze signal assertion. freeze is very useful when debugging an application. when the internal freeze signal is asserted and the frz bit is set, the qadc64e finish es any conversion in progress and then freezes. depending on when the freeze signal is asserted, th ere are three possible que ue "freeze" scenarios: ? when a queue is not executing, the qadc64e freezes immediately ? when a queue is executing, the qadc64e completes the conversion in progress and then freezes ? if, during the execution of the current conversi on, the queue operating mode for the active queue is changed, or a queue 2 abort occu rs, the qadc64e fr eezes immediately during freeze mode, both the analog clock, qclk, and peri odic/interval timer are he ld in reset. when the qadc64e enters the freeze mode while a queue is act ive, the current ccw location of the queue pointer is saved. during freeze, the analog clock, qclk, is held in reset and the periodic/in terval timer is held in reset. external trigger events that occur during the fre eze mode are not captured. the biu remains active to allow imb3 access to all qadc64e registers and ra m. although the qadc64e saves a pointer to the next ccw in the current queue, the software can force the qadc64e to execute a different ccw by writing new queue operating modes for normal ope ration. the qadc64e looks at the queue operating modes, the current queue pointer, a nd any pending trigger events to d ecide which ccw to execute when exiting freeze. if the frz bit is clear, the internal freeze signal is ignored. 14.3.1.3 switching between legacy and enhanced mode s of operation the lock and flip bits of the qadcmcr regist er control the operating mode of the qadc64e modules. out of reset, the qadc64e modules are in legacy mode (flip = 0) a nd the lock bit is clear, qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-10 freescale semiconductor indicating that the module is locked in legacy mode. in order to change the value of the flip bit, the operating mode must first be unlocked by setting the lo ck bit. only then can the flip bit be changed. finally, the lock bit must be cleared again to prot ect the state of the flip bit from future writes. 1. write lock = 1 to unl ock operating mode bit. 2. modify the value of flip as required. ? flip = 0 legacy mode enabled ? flip = 1 enhanced mode enabled 3. write lock = 0 and new flip bit valu e to preserve the value of flip bit ? example 1: switching from le gacy mode to enhanced mode ? qadcmcr = 0x280; lock =1, supv = 1 ? qadcmcr = 0x380; lock =1, write flip = 1, supv = 1 ? qadcmcr = 0x180; lock = 0, flip = 1, supv = 1 subsequent writes to the flip bit wi ll have no effect while lock = 0. ? example 2: switching from e nhanced mode to legacy mode ? qadcmcr = 0x280 or 0x380; lock = 1, supv =1 (can write flip = x since va lue will not change) ? qadcmcr = 0x280; lock = 1, flip = 0, supv = 1 ? qadcmcr = 0x080; lock = 0, flip = 0, supv =1 14.3.1.4 supervisor/unrest ricted address space the qadc64e memory map is divided into two segments: supervisor-onl y data space and assignable data space. access to supervisor-only data space is permitted only when the software is operating in supervisor access mode. assignable data space can be either restri cted to supervisor-only access or unrestricted to both supervisor and user data sp ace accesses. the supv bit in th e qadcmcr designates the assignable space as supervisor or unrestricted. the following information applies to accesses to address space located within the module?s 16-bit boundaries and where the res ponse is a bus error. see table 14-6 for more information. ? attempts to read a supervisor- only data space when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus error condition. no data is returned. if supv = 0, the qadc64e asserts a bus error cond ition and no data is returned. ? attempts to write to supervisor- only data space when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus error condition. no data is wr itten. if supv = 0, the qadc64e asserts a bus error condition and the register is not written. ? attempts to read unimplemented data space in the unrestricted access mode and supv = 1, causes the bus master to assert a bus e rror condition and no data is returned. in all other attempts to read unimp lemented data space, the qadc64e cau ses a bus error c ondition and no data is returned. ? attempts to write unimplemented data sp ace in the unrestricted access mode and supv= 1, causes the bus master to assert a bus error condition and no data is written. in all other qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-11 attempts to write unimplemente d data space, the qadc64e caus es a bus error condition and no data is written. ? attempts to read assignable data space in the unrestricted access mode when the space is programmed as supervisor space caus es the bus master to assert a bus error condition and no data is returned. ? attempts to write assignable data space in th e unrestricted access mode when the space is programmed as supervisor space causes the bus master to assert a bus error condition and the register is not written. the bus master indicates the supervisor and user spa ce access with the function c ode bits (fc[2:0]) on the imb3. for privilege vi olations, refer to chapter 9, ?external bus interface ? to determine the consequence of a bus error cycle termination. the supervisor-only data space se gment contains the qadc64e globa l registers, which include the qadcmcr, qadcint and qadctest. the supervisor/unrestricted space designation for the ccw table, the result word table and the re maining qadc64e registers is programmable. 14.3.2 qadc64e interrupt register qadcint specifies the priority leve l of qadc64e interrupt requests. th e interrupt level for queue 1 and queue 2 may be different. th e interrupt register is read/write accessi ble in supervisor da ta space only. the implemented interrupt register fields can be read and written, reserved bits read zero and writes have no effect. they are typically written once when the software init ializes the qadc64e, and not changed afterwards. table 14-6. qadc64e bus error response s/u 1 mode 1 s/u = supervisor/unrestricted supv bit supervisor-only register supervisor/ unrestricted register reserved/ unimplemented register u 0 qadc64e bus error 2 2 qadc64e bus error = caused by qadc64e valid access 4 qadc64e bus error 2 u 1 master bus error 3 3 master bus error = caused by bus master 4 access to qadctest register will act as a rese rved/unimplemented register unless in factory test mode master bus error 3 master bus error 3 s 0 valid access valid access qadc64e bus error 2 s 1 valid access valid access qadc64e bus error 2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-12 freescale semiconductor the qadc64e conditionally generates interrupts to the bus master via the imb3 irq signals. when the qadc64e sets a status bit assigned to generate an interrupt, the qadc64e drives the irq bus. the value driven onto irq[7:0] represents th e interrupt level assigned to the inte rrupt source. under the control of ilbs, each interrupt request level is driven during th e time multiplexed bus during one of four different time slots, with eight levels comm unicated per time slot. no hardware pr iority is assigned to interrupts. furthermore, if more than one source on a module re quests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 14-6 displays the interrupt levels on irq with ilbs. refer to chapter 12, ?u-bus to imb3 bus interface (uimb) ? for more information. figure 14-6. interrupt levels on irq with ilbs 14.3.3 port data register qadc64e ports a and b are accessed through two 8- bit port data registers, portqa and portqb. msb 01234567891011121314 lsb 15 field irl1 irl2 ? sreset 0000_0000_0000_0000 addr 0x30 4804 (qadcint_a ); 0x30 4c04 (qadcint_b) figure 14-5. qadc interr upt register (qadcint) table 14-7. qadcint bit descriptions bits name description 0:4 irl1 queue 1 interrupt request level. the irl1 fiel d establishes the queue 1 interrupt request level. the 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. all interrupts are presented on the imb3. interrupt leve l priority software determines which level has the highest priority request. 5:9 irl2 queue 2 interrupt request level. the irl2 fiel d establishes the queue 2 interrupt request level. the 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. all interrupts are presented on the imb3. interrupt leve l priority software determines which level has the highest priority request. 10:15 ? reserved. imb3 clock ilbs [1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-13 port a signals are referred to as pqa[7:0] when used as 8-bit general-purpos e digital input or output signals. it is configured as a digital input or digita l output using the data dire ction register, ddrqa. when port a is configured as an input, a read of the po rtqa register returns the act ual pqa[7:0] signal values. when port a is configured as an output, the contents of port register pqa are driven on the port a signals. port a can also be used as analog inputs an[59:52] and external multiplexer address outputs ma[2:0]. port b signals are referred to as pqb[7:0] when used as 8-bit general-purpos e digital input or output signals. it is configured as a digita l input or digital output using the da ta direction register, ddrqb. when port b is configured as an input, a read of the portqb register retu rns the actual pqb[7:0] signal values. when port b is configured as an output, the contents of por t register pqb are driven on the port b signals. port b can also be used as non-multiplexed analog i nputs an[51:44]. in external multiplexed mode four signals can be used as multiplexer analog inputs, anw, anx, any, anz. during a port data register read, the actual value of the signal is repor ted when its corr esponding bit in the data direction register defines the signal to be an input. when th e data direction bit sp ecifies the signal to be an output, the content of the port data register is read. portqa and portqb are not initialized by reset.. 14.3.4 port data direction register the port data direction registers (d drqa and ddrqb) are associated with the port a and port b digital i/o signals. refer to appendix f, ?electrical characteristics ,? for more information. any bit set to one in this register configures the corr esponding signal as an output. any bit cl eared to zero in this register msb 01234567 891011121314 lsb 15 field pqa7 pqa6 pqa5 pqa4 pqa3 pqa2 pqa1 pqa0 pqb7 pqb6 pqb5 pqb4 pqb3 pqb2 pqb1 pqb0 sreset undefined undefined addr (portqa) 0x30 4806; 0x30 4c 06 (portqb) 0x30 4807; 0x30 4c07 analog channel: an59 an58 an57 an56 an55 an54 an53 an52 an51 an50 an49 an48 an47 an46 an45 an44 multiplexed address outputs: ma2 ma1 ma0 multiplexed analog inputs: anz any anx anw figure 14-7. port a data register (portqa), port b data register (portqb) table 14-8. portqa, portqb bit descriptions bits name description 0:7 pqa[7:0] port a signals are referred to as pqa when used as an 8-bit input/output port. port a can also be used for analog inputs (an[59:52]), and ex ternal multiplexer address outputs (ma[2:0]). 8:15 pqb[7:0] port b signals are referred to as pqb when used as an 8-bit input/output port. port b can also be used for non-mulitplexed (an[51:44]) and mult iplexed (anz, any, anx, anw) analog inputs. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-14 freescale semiconductor configures the corresponding signal as an input. the software is responsib le for ensuring that ddr bits are not set to one on signals used for an alog inputs. when the ddr bit is set to one and the signal is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. note caution should be exercised when mix ing digital and analog inputs. this should be isolated as much as possible. rise and fall times should be as large as possible to minimize ac coupling effects. there are two special cases to cons ider for the digital i/ o port operation. when qacr0 [emux] bit is set, enabling external multiplexing, the data direction regi ster settings are ignored for the bits corresponding to portqa[2:0], which are the thre e multiplexed address output signals , ma[2:0]. the ma[2:0] signals are forced to be digital outputs, regardless of the da ta direction setting, and th e multiplexed address outputs are driven. the data returned during a port data register read is the valu e of the multiplexed address latches which drive ma[2:0], regardless of the data direction setting. 14.3.5 control register 0 control register 0 defines whether external multiple xing is enabled, assigns external triggers to the conversion queues and sets up the qclk prescaler parameter field. all of the implemented control register fields can be read or written but re served fields read zero and writes have no effect. typically, they are written once when software initializes th e qadc64e and are not changed afterwards. msb 01234567891011121314 lsb 15 field ddq a7 ddq a6 ddq a5 ddq a4 ddq a3 ddq a2 ddq a1 ddq a0 ddq b7 ddq b6 ddq b5 ddq b4 ddq b3 ddq b2 ddq b1 ddq b0 sreset 0000_0000_0000_0000 addr 0x30 4808 (ddrqa_a); 0x30 4c08 (ddrqa_b); 0x 30 4809 (ddrqb_a); 0x30 4c09 (ddrqb_b) figure 14-8. port x data direction register (ddrqa and ddrqb) msb 0 1 2 34567891011121314 lsb 15 field emux ? trg ? prescaler sreset 0 000000000010011 addr 0x30 480a (qacr0_a); 0x30 4c0a (qacr0_b) figure 14-9. control register 0 (qacr0) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-15 table 14-10 displays the bits in prescaler field wh ich enable a range of qclk frequencies table 14-9. qacr0 bit descriptions bits name description 0 emux externally multiplexed mode. the emux bit allows the software to select the externally multiplexed mode, which affects the interpreta tion of the channel nu mbers and forces the ma0, ma1 and ma2 signals to be outputs. 0 internally multiplexed, 16 possible channels 1 externally multiplexed, up to 41 possible channels see ta bl e 1 4 - 4 for more information. 1:2 ? reserved 3 trg trigger assignment. the trg bit allows the so ftware to assign the etrig[2:1] signals to queue 1 and queue 2. 0 etrig1 triggers queue 1, etrig2 triggers queue 2 1 etrig1 triggers queue 2, etrig2 triggers queue 1 refer to section 14.6.2, ?external trigger input signals .? 4:8 ? reserved 9:15 prescaler prescaler value. the prescaler value determines the qclk frequency (f qclk ). refer to appendix f, ?electrical characteristics ,? for more information on the qadc64e operating clock frequency (f qclk ) values. f qclk can range from 2-to-128 system clock cycles (f sysclk ). to keep f qclk within the specified range, the value of prescaler+1 is the f sysclk divisor. refer to section 14.4.5, ?qadc64e clock (qclk) generation ? for more information on selecting a prescaler value. table 14-10. prescaler f sysclk divide-by values prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div 0000000 2 0100000 33 1000000 65 1100000 97 0000001 2 0100001 34 1000001 66 1100001 98 0000010 3 0100010 35 1000010 67 1100010 99 0000011 4 0100011 36 1000011 68 1100011 100 0000100 5 0100100 37 1000100 69 1100100 101 0000101 6 0100101 38 1000101 70 1100101 102 0000110 7 0100110 39 1000110 71 1100110 103 0000111 8 0100111 40 1000111 72 1100111 104 0001000 9 0101000 41 1001000 73 1101000 105 0001001 10 0101001 42 1001001 74 1101001 106 0001010 11 0101010 43 1001010 75 1101010 107 0001011 12 0101011 44 1001011 76 1101011 108 0001100 13 0101100 45 1001100 77 1101100 109 0001101 14 0101101 46 1001101 78 1101101 110 0001110 15 0101110 47 1001110 79 1101110 111 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-16 freescale semiconductor 14.3.6 control register 1 control register 1 is the mode co ntrol register for the operation of queue 1. the applications software defines the queue operating mode for the queue, and may enable a completion a nd/or pause interrupt. all of the control register fields are re ad/write data. however, the sse1 bit al ways reads as zero unless the test mode is enabled. most of the bits are typically written once when th e software initializes the qadc64e, and not changed afterwards. 0001111 16 0101111 48 1001111 80 1101111 112 0010000 17 0110000 49 1010000 81 1110000 113 0010001 18 0110001 50 1010001 82 1110001 114 0010010 19 0110010 51 1010010 83 1110010 115 0010011 20 0110011 52 1010011 84 1110011 116 0010100 21 0110100 53 1010100 85 1110100 117 0010101 22 0110101 54 1010101 86 1110101 118 0010110 23 0110110 55 1010110 87 1110110 119 0010111 24 0110111 56 1010111 88 1110111 120 0011000 25 0111000 57 1011000 89 1111000 121 0011001 26 0111001 58 1011001 90 1111001 122 0011010 27 0111010 59 1011010 91 1111010 123 0011011 28 0111011 60 1011011 92 1111011 124 0011100 29 0111100 61 1011100 93 1111100 125 0011101 30 0111101 62 1011101 94 1111101 126 0011110 31 0111110 63 1011110 95 1111110 127 0011111 32 0111111 64 1011111 96 1111111 128 msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field cie1 pie1 sse1 mq1 ? sreset 0000_0000_0000_0000 addr 0x30 480c (qacr1_a); 0x30 4c0c (qacr1_b) figure 14-10. control register 1 (qacr1) table 14-10. prescaler f sysclk divide-by values (continued) prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-17 table 14-11. qacr1 bit descriptions bits name description 0 cie1 queue 1 completion interrupt enable. cie1 enables an interrupt upon completion of queue 1. the interrupt request is initiated when the conversion is complete for the ccw in queue 1. 0 disable the queue completion interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 1 1 pie1 queue 1 pause interrupt enable. pie1 enables an interrupt when queue 1 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 1 which has the pause bit set 2 sse1 queue 1 single-scan enable bit. sse1 enab les a single-scan of queue 1 to start after a trigger event occurs. the sse1 bit may be se t to a one during th e same write cycle when the mq1 bits are set for one of the single-scan queue operating modes. the single-scan enable bit can be written as a one or a zero, but is always read as a zero. the sse1 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 1. the qadc64e clears the sse1 bit when the singl e-scan is complete. refer to table 14-12 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 1 in a single-scan mode 3:7 mq1 queue 1 operating mode. the mq1 field se lects the queue operating mode for queue 1. table 14-12 shows the bits in the mq1 field which enable different queue 1 operating mode 8:15 ? reserved table 14-12. queue 1 operating modes mq1[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse1) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-18 freescale semiconductor 14.3.7 control register 2 control register 2 is the mode cont rol register for the operation of que ue 2. software specifies the queue operating mode of queue 2, and may enable a completio n and/or a pause interrupt . all control register fields are read/write data, except the sse2 bit, which is readable only when the test m ode is enabled. most of the bits are typically written once when the software initializes the qadc64e, and not changed afterwards. 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 external gated single-sc an mode (started with sse1) 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 1 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 external gated continuous-scan mode msb 0 1 2 34567 8 91011121314 lsb 15 field cie2 pie2 sse2 mq2 resume bq2 sreset 0 0 0 0_0000 0 111_1111 addr 0x30 480e (qacr2_a), 0x30 4c0e (qacr2_b) figure 14-11. control register 2 (qacr2) table 14-12. queue 1 operating modes (continued) mq1[3:7] operating modes qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-19 table 14-13. qacr2 bit descriptions bits name description 0 cie2 queue 2 completion software interrupt enable. cie2 enables an interrupt upon completion of queue 2. the interrupt request is initiated wh en the conversion is complete for the ccw in queue 2. 0 disable the queue completion interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 2 1 pie2 queue 2 pause software interrupt enable. pie2 enables an interrupt when queue 2 enters the pause state. the interrupt r equest is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 2 which has the pause bit set 2 sse2 queue 2 single-scan enable bit. sse2 enables a single-scan of queue 2 to start after a trigger event occurs. the sse2 bit may be set to a one during the same write cycle when the mq2 bits are set for one of the single-scan queue operating modes. the single-scan enable bit can be written as a one or a zero, but is always read as a zero. the sse2 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 2. the qadc64e clears the sse2 bit when the single-scan is complete. refer to table 14-14 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 2 in a single-scan mode 3:7 mq2 queue 2 operating mode. the mq2 field selects the queue operating mode for queue 2. refer to ta b l e 1 4 - 1 4 for more information. 8 resume 0 after suspension, begin executing with the first ccw in queue 2 or the current sub-queue 1 after suspension, begin executing with the aborted ccw in queue 2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-20 freescale semiconductor table 14-14 shows the bits in the mq2 field which enable different que ue 2 operating modes. 9:15 bq2 beginning of queue 2. the bq2 field indicates the ccw location where queue 2 begins. to allow the length of queue 1 and queue 2 to vary, a programmable pointer identifies the ccw table location where queue 2 begins. the bq2 field also serves as an end-of-queue condition for queue 1. setting bq2 beyond physical ccw table memory space allows queue 1 all 64 entries. software defines the beginning of queue 2 by programming the bq2 field in qacr2. bq2 is usually programmed before or at the same ti me as the queue operating mode for queue 2 is selected. if bq2 is 64 or greater, queue 2 has no entries, and the entire ccw table is dedicated to queue 1 and ccw63 is the end-of-queue 1. if bq2 is zero, the entire ccw table is dedicated to queue 2. as a special case, when a queue operating mode for queue 1 is selected and a trigger event occurs for queue 1 with bq2 set to zero, queue 1 execution is terminated after ccw0 is read. conversions do not occur. the bq2 pointer may be changed dynamically, to alternate between queue 2 scan sequences. a change in bq2 after queue 2 has begun or if queue 2 has a trigger pending does not affect queue 2 until queue 2 is started again.for example, two scan sequences could be defined as follows: the first sequen ce starts at ccw10, with a pause after ccw11 and an eoq programmed in ccw15; the se cond sequence starts at ccw16, with a pause after ccw17 and an eoq programmed in ccw39. with bq2 set to ccw10 and the continuous -scan mode selected, queue execution begins. when the pause is encountered in ccw11, a software interrupt routine can redefine bq2 to be ccw16. therefore, after the end-of-queue is recognized in ccw15, an internal retrigger event is generated and execution restarts at ccw16. when the pause software interrupt occurs again, software can change bq2 ba ck to ccw10. after the end-of-queue is recognized in ccw39, an internal retrigger even t is created and execution now restarts at ccw10. if bq2 is changed while queue 1 is active, th e effect of bq2 as an end-of-queue indication for queue 1 is immediate. however, beware of the risk of losing the end-of-queue 1 through moving bq2. recommend use of eoq (chan63) to end queue 1. note: be sure to do a mode change when changing bq2 and setting sse2. setting bq2 first is recommended. table 14-14. queue 2 operating modes mq2[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse2) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 table 14-13. qacr2 bit descriptions (continued) bits name description qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-21 note if bq2 was assigned to the ccw that queue 1 is currently working on, then that conversion is completed before bq2 takes effect. each time a ccw is read for queue 1, the ccw locati on is compared with the current value of the bq2 pointer to detect a possibl e end-of-queue condition. for example, if bq2 is changed to ccw3 while queue 1 is converting ccw2, queue 1 is terminated after the conversion is completed. however, if bq2 is changed to ccw1 while queue 1 is converting ccw2, the qadc64e would not recognize a bq2 end-of-queue condition until queue 1 execution r eached ccw1 again, presumably on the next pass through the queue. 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 reserved mode 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 13 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 reserved mode table 14-14. queue 2 operating modes (continued) mq2[3:7] operating modes qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-22 freescale semiconductor 14.3.8 status register s (qasr0 and qasr1) the status registers contains info rmation about the state of each que ue and the current a/d conversion. except for the four flag bits (cf1, pf1, cf2, and pf2 ) and the two trigger overr un bits (tor1 and tor2), all of the status register fields c ontain read-only data. the four flag bits and the two tr igger overrun bits are cleared by writing a zero to the bit after the bit was previously read as a one. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field cf1 pf1 cf2 pf2 tor1 tor2 qs cwp sreset 0000_0000_0000_0000 addr 0x30 4810 (qasr0_a); 0x30 4c10 (qasr0_b) figure 14-12. status register 0 (qasr0) table 14-15. qasr0 bit descriptions bits name description 0 cf1 queue 1 completion flag. cf1 indicates that a queue 1 scan has been completed. the scan completion flag is set by the qadc64e when the input channel sample requested by the last ccw in queue 1 is converted, and the result is stored in the result table. the end-of-queue 1 is i dentified when execution is complete on the ccw in the location prior to that pointed to by bq2, when the current ccw cont ains an end-of-queue code instead of a valid channel number, or when t he currently completed ccw is in the last location of the ccw ram. when cf1 is set and interrupts are enabled for that queue completion flag, the qadc64e asserts an interrupt request at the level specified by irl1 in the interrupt register (qadcint). the software reads the completion flag during an interrupt service routine to identify the interrupt request. the interrupt re quest is cleared when t he software writes a zero to the completion flag bit, when the bit was previously read as a one. once set, only software or reset can clear cf1. cf1 is maintained by the qadc64e regardless of whether the corresponding interrupt is enabled. the software polls for cf1 bit to see if it is set. this allows the software to recognize that the qadc64e is finished with a queue 1 scan. the software acknowledges that it has detected the comple tion flag being set by writing a zero to the completion flag after the bit was read as a one. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-23 1 pf1 queue 1 pause flag. pf1 indicates that a queue 1 scan has reached a pause. pf1 is set by the qadc64e when the current queue 1 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf1 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, if th e ccw with the pause bit set is the last ccw in a queue, the queue execution is complete. the queue status becom es idle, not paused, and both the pause and completion flags are se t. another exception occurs in software controlled mode, where the pf1 can be set bu t queue 1 never enters the pause state since queue 1 continues without pausing. when pf1 is set and interrupts are enabled for the corresponding queue, the qadc64e asserts an interrupt request at the level spec ified by irl1 in the interrupt register. the software may read pf1 during an interrupt serv ice routine to identify the interrupt request. the interrupt request is cleared when the softwa re writes a zero to pf1, when the bit was previously read as a one. once set, only software or reset can clear pf1. in external gated single-scan and continuou s-scan mode the definition of pf1 has been redefined. when the gate closes before the end-of-queue 1 is reached, pf1 becomes set to indicate that an incomple te scan has occurred.in single-scan mode, setting pf1 can be used to cause an interrupt and software can then determine if queue 1 should be enabled again. in either external gated mode, setting pf1 indicates that the results for queue 1 have not been collected during one scan (coherently). note: if a pause in a ccw is encountered in external gated mode for either single-scan and continuous-scan mode, the pause flag will not set , and execution continues without pausing. this has allowed for the added definition of pf1 in the external gated modes. pf1 is maintained by the qadc64e regardle ss of whether the corresponding interrupts are enabled. the software may poll pf1 to find out when the qadc64e has reached a pause in scanning a queue.the software ackn owledges that it has detected a pause flag being set by writing a zero to pf1 after the bit was last read as a one. 0 = queue 1 has not reached a pause (or gate has not closed before end-of-queue in gated mode) 1 = queue 1 has reached a pause (or gate cl osed before end-of-queue in gated mode) refer to table 14-16 for a summary of pause response in all scan modes. 2 cf2 queue 2 completion flag. cf2 indicates that a queue 2 scan has been completed. cf2 is set by the qadc64e when the input channel sample requested by the last ccw in queue 2 is converted, and the result is stored in the result table. the end-of-queue 2 is identif ied when the current ccw contains an end-of-queue code instead of a valid channel number, or when t he currently completed ccw is in the last location of the ccw ram. when cf2 is set and interrupts are enabled for that queue completion flag, the qadc64e asserts an interrupt request at the level specified by irl2 in the interrupt register (qadcint). the software reads cf2 during an interrupt service rout ine to identify the interrupt request. the interrupt request is clear ed when the software writes a zero to the cf2 bit, when the bit was previously read as a one. once set, only software or reset can clear cf2. cf2 is maintained by the qadc64e regardless of whether the corresponding interrupts are enabled. the software polls for cf2 to see if it is set. this allows the software to recognize that the qadc64e is finished with a queue 2 scan. the software acknowledges that it has detected the comple tion flag being set by writing a zero to the completion flag after the bit was read as a one. table 14-15. qasr0 bit descriptions (continued) bits name description qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-24 freescale semiconductor 3 pf2 queue 2 pause flag. pf2 indicates that a queue 2 scan has reached a pause. pf2 is set by the qadc64e when the current queue 2 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf2 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, if th e ccw with the pause bit set is the last ccw in a queue, the queue execution is complete. the queue status becom es idle, not paused, and both the pause and completion flags are se t. another exception occurs in software controlled mode, where the pf2 can be set but queue 2 never enters the pause state. when pf2 is set and interrupts are enabled for the corresponding queue, the qadc64e asserts an interrupt request at the level spec ified by irl2 in the interrupt register. the software reads pf2 during an interrupt service routine to identify the interrupt request. the interrupt request is cleared when the software writes a zero to pf2, when the bit was previously read as a one. once set, only software or reset can clear pf2. pf2 is maintained by the qadc64e regardle ss of whether the corresponding interrupts are enabled. the software may poll pf2 to find out when the qadc64e has reached a pause in scanning a queue. the software ackno wledges that it has detected a pause flag being set by writing a zero to pf2 after the bit was last read as a one. 0 queue 2 has not reached a pause 1 queue 2 has reached a pause refer to table 14-16 for a summary of pause response in all scan modes. 4 tor1 queue 1 trigger overrun. tor1 indicates that an unexpected trigger event has occurred for queue 1. tor1 can be set only while queue 1 is in the active state. a trigger event generated by a transition on the external trigger signal or by the periodic/interval timer may be captured as a trigger overrun. tor1 cannot occur when the software initiated single-scan mode or the so ftware initiated cont inuous-scan mode are selected. tor1 occurs when a trigger event is received while a queue is executing and before the scan has completed or paused. tor1 has no effect on the queue execution. after a trigger event has occurred for queue 1, and before the scan has completed or paused, additional queue 1 trigger events ar e not retained. such trigger events are considered unexpected, and the qadc64e sets the tor1 error status bit. an unexpected trigger event may be a system overrun situation, indicating a system loading mismatch. in external gated continuous-scan mode the de finition of tor1 has been redefined. in the case when queue 1 reaches an end-of-queue condition for the second time during an open gate, tor1 becomes set. this is considered an overrun condition. in this case cf1 has been set for the first end-of-queue 1 condition and then tor1 becomes set for the second end-of-queue 1 condition. for tor1 to be se t, software must not clear cf1 before the second end-of-queue 1. the software acknowledges that it has detect ed a trigger overrun being set by writing a zero to the trigger overrun, after the bit was read as a one. once set, only software or reset can clear tor1. 0 no unexpected queue 1 trigger events have occurred 1 at least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an end-of-queue condition for the second time in gated mode) table 14-15. qasr0 bit descriptions (continued) bits name description qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-25 5 tor2 queue 2 trigger overrun. tor2 indicates that an unexpected trigger event has occurred for queue 2. tor2 can be set when queue 2 is in the active, suspended, and trigger pending states. the tor2 trigger overrun can only occur when using an external trigger mode or a periodic/interval timer mode. trigger overruns cannot occur when the software initiated single-scan mode and the software initiated continuous-scan mode are selected. tor2 occurs when a trigger event is received while queue 2 is executing, suspended, or a trigger is pending. tor2 has no effect on the queue execution. a trigger event that causes a trigger overrun is not retained since it is considered unexpected. an unexpected trigger event may be a system overrun sit uation, indicating a system loading mismatch. the software acknowledges that it has detected a trigger overrun being set by writing a zero to the trigger overrun, after the bit was read as a one. once set, only software or reset can clear tor2. 0 no unexpected queue 2 trigger events have occurred 1 at least one unexpected queue 2 trigger event has occurred 6:9 qs queue status. the 4-bit read-only qs field indicates the current condition of queue 1 and queue 2. the following are the five queue status conditions: idle active paused suspended trigger pending the two most significant bits are associated primarily with qu eue 1, and the remaining two bits are associated with queue 2. since th e priority scheme between the two queues causes the status to be interlinked, the status bits are considered as one 4-bit field. table 14-17 shows the bits in the qs field and ho w they affect the status of queue 1 and queue 2. refer to section 14.5, ?trigger and queue interaction examples ,? which shows the 4-bit queue status field trans itions in typical situations. 10:15 cwp command word pointer. the cwp allows the software to know which ccw is executing at present, or was last completed. the comma nd word pointer is a software read-only field, and write operations have no effect. the cw p allows software to monitor the progress of the qadc64e scan sequence. the cwp field is a ccw word pointer with a valid range of 0 to 63. when a queue enters the paused state, the cwp points to the ccw with the pause bit set. while in pause, the cwp value is maintained until a trigger event occurs on the same queue or the other queue. usua lly, the cwp is updated a few clock cycles before the queue status field shows that the queue has become active. for example, software may read a cwp pointing to a ccw in queue 2, and the status field shows queue 1 paused, queue 2 trigger pending. when the qadc64e finishes the scan of the queue, the cwp points to the ccw where the end-of-queue condition was detected. therefore, when t he end-of-queue condition is a ccw with the eoq code, the cwp poi nts to the ccw containing the eoq. when the last ccw in a queue is in the last ccw table location (ccw63), and it does not contain the eoq code, the end-of-queue is de tected when the following ccw is read, so the cwp points to word ccw0. finally, when queue 1 operation is terminated after a ccw is read that is defined as bq2, the cwp points to the same ccw as bq2. during the stop mode, the cwp is reset to zero, since the control registers and the analog logic are reset. when the freeze mode is enter ed, the cwp is unchanged; it points to the last executed ccw. table 14-15. qasr0 bit descriptions (continued) bits name description qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-26 freescale semiconductor one or both queues may be in the id le state. when a queue is idle, ccws are not being executed for that queue, the queue is not in the pause st ate, and there is not a trigger pending. the idle state occurs when a queue is disabled, when a queue is in a rese rved mode, or when a queue is in a valid queue operating mode awaiting a tri gger event to initiate queue execution. table 14-16. pause response scan mode q operation pf asserts? external trigger single-scan pauses yes external trigger continuous-scan pauses yes periodic/interval timer trigger single-scan pauses yes periodic/interval timer continuous-scan pauses yes software initiated single-scan continues yes software initiated continuous-scan continues yes external gated single-scan continues no external gated continuous-scan continues no table 14-17. queue status qs[9:6] queue 1/queue 2 states 0000 queue 1 idle, queue 2 idle 0001 queue 1 idle, queue 2 paused 0010 queue 1 idle, queue 2 active 0011 queue 1 idle, queue 2 trigger pending 0100 queue 1 paused, queue 2 idle 0101 queue 1 paused, queue 2 paused 0110 queue 1 paused, queue 2 active 0111 queue 1 paused, queue 2 trigger pending 1000 queue 1 active, queue 2 idle 1001 queue 1 active, queue 2 paused 1010 queue 1 active, queue 2 suspended 1011 queue 1 active, queue 2 trigger pending 1100 reserved 1101 reserved 1110 reserved 1111 reserved qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-27 a queue is in the active state when a valid queue ope rating mode is selected, wh en the selected trigger event has occurred, or when the qadc64e is pe rforming a conversion spec ified by a ccw from that queue. only one queue can be active at a time. either or both queues can be in the paused state. a queue is paused when the previous ccw executed fr om that queue had the pause bit set. the qadc64e does not execute any ccws from the paused queue until a trigger event occurs. cons equently, the qadc64e can service queue 2 while queue 1 is paused. only queue 2 can be in the suspended state. when a trigger event occurs on queue 1 while queue 2 is executing, the current queue 2 convers ion is aborted. the queue 2 status is reported as suspended. queue 2 transitions back to the active state when queue 1 becomes idle or paused. a trigger pending state is required since both queues cannot be active at the same time. the status of queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. in the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, que ue 2 is aborted and the status is reported as queue 1 activ e, queue 2 suspended. so due to the priority scheme, only queue 2 can be in the trigger pending state. there are two transition cases which cause the queue 2 st atus to be trigger pending before queue 2 is shown to be in the active state. when queue 1 is active and there is a tr igger pending on queue 2, after queue 1 completes or pauses, queue 2 conti nues to be in the trigger pending state for a few clock cycles. the following are fleeti ng status conditions: ? queue 1 idle with queue 2 trigger pending ? queue 1 paused with queue 2 trigger pending figure 14-13 displays the status conditions of the queue status field as the qadc64e goes through the transition from queue 1 ac tive to queue 2 active. figure 14-13. queue status transition the queue status field is affected by the stop mode. si nce all of the analog logic and control registers are reset, the queue status field is re set to queue 1 idle, queue 2 idle. queue 1 queue 2 trigger pending trigger pending active idle active active idle (paused) idle (paused) qadc64e queue status qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-28 freescale semiconductor during the freeze mode, the queue status field is not modified. the queue st atus field retains the status it held prior to freezing. as a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. 14.3.9 conversion command word table the conversion command word (ccw ) table is a ram, 64 words long on 16-bit address boundaries where 10-bits of each entry are implemented. a ccw can be programmed by the software to request a conversion of one analog input channel. the ccw table is writ ten by software and is not modified by the qadc64e. each ccw requests the conve rsion of an analog channel to a digita l result. the ccw specifies the analog channel number, the input sample t ime, and whether the queue is to pause after th e current ccw. the ten implemented bits of the ccw word are read/write data, where they may be written when the software msb 0 1 234567 8 91011121314 lsb 15 field ? cwpq1 ? cwpq2 sreset 00 11_1111 00 11_1111 addr 0x30 4812 (qasr1_a); 0x30 4c12 (qasr1_b) figure 14-14. status register 1 (qasr1) table 14-18. qasr1 bit descriptions bits name description 0:1 ? reserved 2:7 cwpq1 command word pointer for q1 . cwpq1 al lows the software to know what ccw was last completed for queue 1. this field is a software read-only field, and write operations have no effect. cwpq1 allows software to read t he last executed ccw in queue 1, regardless of which queue is active. the cwpq1 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq1 is updated when the conversion result is written. when the qadc64e finishes a conversion in queue 1, both the result register is written and the cwpq1 are updated. finally, when queue 1 operation is terminated after a ccw is read that is defined as bq2, cwp points to bq2 while cwpq1 points to the last ccw queue 1. during the stop mode, the cwpq1 is reset to 63, since the control registers and the analog logic are reset. when the freeze mode is enter ed, the cwpq1 is unchanged; it points to the last executed ccw in queue 1. 8:9 ? reserved 10:15 cwpq2 command word pointer for q2 . cwpq2 allows the software to know what ccw was last completed for queue 2. this field is a software read-only field, and write operations have no effect. cwpq2 allows software to read t he last executed ccw in queue 2, regardless which queue is active. the cwpq2 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq2 is updated when the conversion result is written. when the qadc64e finishes a conversion in queue 2, both the result register is written and the cwpq2 are updated. during the stop mode, the cwpq2 is reset to 63, since the control registers and the analog logic are reset. when the freeze mode is enter ed, the cwp is unchanged; it points to the last executed ccw in queue 2. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-29 initializes the qadc64e. the remaining 6-bits are unimplemented so these read as zeros, and write operations have no effect. each location in the ccw table corresponds to a location in the result word table. when a conversion is completed for a ccw entr y, the 10-bit result is written in the corresponding result word entry. the qadc64 e provides 64 ccw table entries. the beginning of queue 1 is the first location in the ccw table. the first locati on of queue 2 is specified by the beginning of queue 2 pointer (bq2) in qacr2. to dedicate the entire ccw table to queue 1, queue 2 is programmed to be in the disabled mode, and bq 2 is programmed to 64 or greater. to dedicate the entire ccw table to que ue 2, queue 1 is programmed to be in the disabled mode, and bq 2 is specified as the first location in the ccw table figure 14-15 illustrates the operation of the queue structure. figure 14-15. qadc64e conversion queue operation to prepare the qadc64e for a scan se quence, the software writes to th e ccw table to specify the desired channel conversions. the software also establishes the criteria fo r initiating the queue execution by programming the queue operating mode. the queue operating mode determines what type of trigger event causes queue execution to begin. a ?trigger event? is used to refer to any of the ways to cause the conversion command word (ccw) table 0x200 (ccw0) 1 bq2 0x27e (ccw63) 1 a/d converter result word table result 0 result 63 channel select, sample, hold, and analog to digital conversion begin queue 1 begin queue 2 end of queue 1 end of queue 2 pref ist chan 10-bit conversion command word (ccw) format 10-bit result is software readable in three different 16-bit formats p = pause until next trigger ref = use alternate reference voltage ist = input sample time chan = channel number and end_of_queue code result s result 0 right justified, unsigned result format left justified, unsigned result format left justified, signed result format 15 0 15 0 s = sign bit result 15 0 00 00 0 000 00 0 000 00 0 address offsets: 0x280-0x2ff 1 0x380-0x3ff 1 0x300-0x37f 1 msb msb lsb lsb 8 6 9 15 7 7 8 1 7 8 7 8 note 1: these offsets must be added to the modu le base address: a = 0x30 4800 or b = 0x30 4c00 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-30 freescale semiconductor qadc64e to begin executing the ccws in a queue or sub-queue. an ?exter nal trigger? is only one of the possible ?trigger events.? a scan sequence may be initiated by the following: ? a software command ? expiration of the peri odic/interval timer ? external trigger signal ? external gated signal (queue 1 only) the software also specifies whethe r the qadc64e is to perform a singl e pass through the queue or is to scan continuously. when a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. when a continuous-scan mode is sel ected, the queue remains active in the selected queue operating mode after the qadc64e completes each queue scan sequence. during queue execution, the qadc64e reads each ccw from the activ e queue and executes conversions in three stages: ? initial sample ? final sample ? resolution during initial sample, a buffered vers ion of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. during the final sample period, the sa mple buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. each ccw specifies a final input sample time of two or 16 qclk cycles. when an analog-to-digital conversion is complete, the result is written to the corresponding location in the result word table. the qadc64e c ontinues to sequentially execute eac h ccw in the queue until the end of the queue is detected or a pause bit is found in a ccw. when the pause bit is set in the current ccw, the qadc64e stops execution of the queue until a new trigger event occurs. the pause status flag bit is set, which may cause an interrupt to notify the software that the queue has reached the pause state. after the trigger event occurs, the pa used state ends and the qadc64e continues to execute each ccw in the queue until another paus e is encountered or the end of the queue is detected. the following indicate the end-of-queue condition: ? the ccw channel field is programmed with 63 (0x3f) to specify the end of the queue ? the end-of-queue 1 is implied by the beginning of queue 2, which is specifie d in the bq2 field in qacr2 ? the physical end of the queue ram sp ace defines the end of either queue when any of the end-of-queue conditi ons is recognized, a queue completion flag is set, a nd if enabled, an interrupt is issued to the software. the followin g situations prematurely terminate queue execution: ? since queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is su spended by aborting the execution of the ccw in progress, and the queue 1 execution begins. wh en queue 1 execution is completed, queue 2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-31 conversions restart with the first ccw entry in que ue 2 or the first ccw of the queue 2 sub-queue being executed when queue 2 was suspended. altern ately, conversions can restart with the aborted queue 2 ccw entry. the resume bit in qacr2 al lows the software to select where queue 2 begins after suspension. by choosing to re-ex ecute all of the suspended queue 2 queue and sub-queue ccws, all of the sample s are guaranteed to have been ta ken during the same scan pass. however, a high trigger event rate for queue 1 can prohibit the completion of queue 2. if this occurs, the software may choose to begin exec ution of queue 2 with the aborted ccw entry. ? software can change the queue operating mode to disabled mode . any conversion in progress for that queue is aborted. putting a queue into the disabled mode does not power down the converter. ? software can change the queue operating mode to anot her valid mode. any conversion in progress for that queue is aborted. the queue restarts at the beginning of the que ue, once an appropriate trigger event occurs. ? for low power operation, software can set the st op mode bit to prepare the module for a loss of clocks. the qadc64e aborts any conversion in progress when the stop mode is entered. ? when the freeze enable bi t is set by software and the imb3 in ternal freeze line is asserted, the qadc64e freezes at the end of th e conversion in progress. when internal freeze is negated, the qadc64e resumes queue execution beginning with the next ccw entry. refer to section 14.4.7, ?configuration and control using the imb3 interface ? for more information. msb 01234567891011121314 lsb 15 field ? p ref ist chan[6:0] reset unaffected addr 0x30 4a00 ? 0x30 4a7f, 0x30 4e00 ? 0x30 4e7f figure 14-16. conversion command word table (ccw) table 14-19. ccw bit descriptions bits name description 0:5 ? reserved 6 p pause. the pause bit allows software to create sub-queues within queue 1 and queue 2. the qadc64e performs the conversion specif ied by the ccw with the pause bit set, and then the queue enters the pause st ate. another trigger event ca uses execution to continue from the pause to the next ccw. 0 do not enter the pause state after execution of the current ccw 1 enter the pause st ate after execution of the current ccw note: the pause bit will not cause the queue to pause in the software controlled modes or external gated modes. 7 ref alternate reference enabled. setting ref hi gh in the ccw enables the use of an alternate reference. 0 vrh is used as high reference 1 altref signal is used as the high reference qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-32 freescale semiconductor 8 ist input sample time. the ist field allows so ftware to specify the length of the sample window. provision is made to vary the input sample time, through software control, to offer flexibility in the source impedance of the circuitry providing the qadc64e analog channel inputs. longer sample times permit more accurate a/d conversions of signals with higher source impedances. the programmable sample time can also be used to increase the time interval between conversions to adjust the queue execution time or the sampling rate. 0 qclk period x 2 1 qclk period x 8 9:15 chan[6:0] channel number. the chan field selects the input channel number. the software programs the channel field of the ccw with the channel number corresponding to the analog input signal to be sampled and converted. the analog input signal channel number assignments and the signal definitions vary depending on whether the multiplexed or non-multiplexed mode is used by the applic ation. as far as the queue scanning operations are concerned, there is no distinction betwe en an internally or externally multiplexed analog input. refer to section 14.2.5, ?external multiplexing ? for more information on external multiplexing. table 14-20 and table 14-21 show the channel number assignments table 14-20. qadc64e_a multiplexed channel assignments and signal designations multiplexed input signals channel number in ccw chan field port signal name analog signal name other functions / descriptions signal type binary decimal anw/a_pqb0 an00 to an07 ? input 0000000 to 0000111 0 to 7 anx/a_pqb1 an08 to an15 ? input 0001000 to 0001111 8 to 15 any/a_pqb2 an16 to an23 ? input 0010000 to 0010111 16 to 23 anz/a_pqb3 an24 to an31 ? input 0011000 to 0011111 24 to 31 ? reserved ? ? 0100000 to 0101001 32 to 41 ? reserved ? ? 0101010 42 ? reserved ? ? 0101011 43 a_pqb0 a_pqb1 a_pqb2 a_pqb3 an44 an45 an46 an47 anw anx any anz input/output input/output input/output input/output 0101100 0101101 0101110 0101111 44 45 46 47 a_pqb4 a_pqb5 a_pqb6 a_pqb7 an48 an47 an50 an51 ? ? ? ? input/output input/output input/output input/output 0110000 0110001 0110010 0110011 48 49 50 51 table 14-19. ccw bit descriptions (continued) bits name description qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-33 a_pqa0 a_pqa1 a_pqa2 a_pqa3 an52 an53 an54 an55 ma0 ma1 ma2 ? input/output input/output input/output input/output 0110100 0110101 0110110 0110111 52 53 54 55 a_pqa4 a_pqa5 a_pqa6 a_pqa7 an56 an57 an58 an59 ? ? ? ? input/output input/output input/output input/output 0111000 0111001 0111010 0111011 56 57 58 59 vrl vrh/altref 1 ? low ref high ref ? ? ? (vrh ? vrl)/2 input input ? 0111100 0111101 0111110 60 61 62 ? ? end of queue code ? 0111111 63 ? reserved ? ? 1011000 to 1111110 64 to 127 1 whichever is selected in the ccw. table 14-21. qadc64e_b multiplexed channel assignments and signal designations multiplexed input signals channel number in ccw chan field port signal name analog signal name other functions / descriptions signal type binary decimal anw/b_pqb0 an0 to an7 ? input 0000000 to 0000111 0 to 7 anx/b_pqb1 an8 to an15 ? input 0001000 to 0001111 8 to 15 any/b_pqb2 an16 to an23 ? input 0010000 to 0010111 16 to 23 anz/b_pqb3 an24 to an31 ? input 0011000 to 0011111 24 to 31 ? reserved ? ? 0100000 to 0101001 32 to 41 ? reserved ? ? 0101010 42 ? reserved ? ? 0101011 43 b_pqb0 b_pqb1 b_pqb2 b_pqb3 an44 an45 an46 an47 anw anx any anz input/output input/output input/output input/output 0101100 0101101 0101110 0101111 44 45 46 47 table 14-20. qadc64e_a multiplexed channel a ssignments and signal designations (continued) multiplexed input signals channel number in ccw chan field port signal name analog signal name other functions / descriptions signal type binary decimal qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-34 freescale semiconductor the channel field is programmed for channel 63 to i ndicate the end of the queue. channels 60 to 62 are special internal channels. when one of the special cha nnels is selected, the samp ling amplifier is not used. the value of v rl , v r h , or ( v r h - v r l )/2 is placed directly onto the conver ter. also for the internal special channels, programming any input sample time other than two has no be nefit except to lengthen the overall conversion time. 14.3.10 result word table the result word table is a ram, 64 words long and 10 bits wide. an entry is written by the qadc64e after completing an analog conversion specified by the corresponding ccw table en try. software can read or write the result word table, but in normal operation, the software re ads the result word table to obtain analog conversions from the qadc64e . unimplemented bits are read as zeros, and write operations do not have any effect. see figure 14-15 for a diagram of the result word table while there is only one result word table, the data can be accessed in three different data formats: ? right justified in the 16- bit word, with zeros in the higher order unused bits ? left justified, with the most signifi cant bit inverted to form a sign bit, and zeros in the unused lower order bits ? left justified, with zeros in the lower order unused bits b_pqb4 b_pqb5 b_pqb6 b_pqb7 an48 an47 an50 an51 ? ? ? ? input/output input/output input/output input/output 0110000 0110001 0110010 0110011 48 49 50 51 b_pqa0 b_pqa1 b_pqa2 b_pqa3 an52 an53 an54 an55 ma0 ma1 ma2 ? input/output input/output input/output input/output 0110100 0110101 0110110 0110111 52 53 54 55 b_pqa4 b_pqa5 b_pqa6 b_pqa7 an56 an57 an58 an59 ? ? ? ? input/output input/output input/output input/output 0111000 0111001 0111010 0111011 56 57 58 59 vrl vrh/altref 1 ? low ref high ref ? ? ? (vrh ? vrl)/2 input input ? 0111100 0111101 0111110 60 61 62 ? ? end of queue code ? 0111111 63 ? reserved ? ? 1011000 to 1111111 64 to 127 1 whichever is selected in the ccw. table 14-21. qadc64e_b multiplexed channel a ssignments and signal designations (continued) multiplexed input signals channel number in ccw chan field port signal name analog signal name other functions / descriptions signal type binary decimal qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-35 the left justified, signed format corr esponds to a half-scale, offset binary, two?s complement data format. the data is routed onto the imb3 according to the se lected format. the address used to access the table determines the data alignment format. all write opera tions to the result word table are right justified. the three result data formats ar e produced by routing the ram bits onto the data bus. the software chooses among the three formats by r eading the result at the memory address which produces the desired data alignment. the result word table is read/wri te accessible by software. during norma l operation, applications software only needs to read the result table. write operations to the table may occur during test or debug breakpoint operation. when locations in the ccw table are not used by an application, software could use the corresponding locations in the result word table as scratch pad ram, remembering that only 10 bits are implemented. the result alignment is only implemented for software read operations. since write operations are not the normal use for the result register s, only one write data fo rmat is supported, which is right justified data. note some write operations, like bit manipul ation, may not operate as expected because the hardware cannot access a true 16-bit value. msb 01234567891011121314 lsb 15 field ? result sreset 0000_00 undefined addr 0x30 4a80?4aff (rjurr_a); 0x30 4e80?4eff (rjurr_b) figure 14-17. right justified, unsigned result format (rjurr) msb 01234567891011121314 lsb 15 field s 1 1 s = sign bit. result ? sreset undefined 00_0000 addr 0x30 4b00?4b7f (ljsrr_a); 0x30 4f00?4f7f (ljsrr_b) figure 14-18. left justified, signed result format (ljsrr) msb 01234567891011121314 lsb 15 field result ? sreset undefined 00_0000 addr 0x30 4b80?4bff (ljurr_a ); 0x30 4f80?4fff (ljurr_b) figure 14-19. left justified, unsigned result register (ljurr) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-36 freescale semiconductor 14.3.10.1 analog subsystem this section describes the qadc64e analog subsystem, which includes the front-end analog multiplexer and analog-to-dig ital converter. 14.3.11 analog-to-digital converter operation the analog subsystem consists of the path from the input si gnals to the a/d convert er block. signals from the queue control logic are fed to the multiplexer and state machine. the end of convert (eoc) signal and the successive-approximation register (s ar) are the result of the conversion. figure 14-20 shows a block diagram of the qadc64e analog subsystem. figure 14-20. qadc64e analog subsystem block diagram 14.3.11.1 conversion cycle times total conversion time is made up of initial sample time, final sample time, and resolution time. initial sample time refers to the time during which the selected input ch annel is coupled through the buffer amplifier to the sample capacitor. this buffer is us ed to quickly reproduce its input signal on the sample capacitor and minimize charge sharing errors. duri ng the final sampling period the amplifier is bypassed, and the multiplexer input charges the sample capaci tor array directly for improved accuracy. during the resolution period, the voltage in the sa mple capacitor is converted to a di gital value and stored in the sar. initial sample time is fixed at tw o qclk cycles. final sample time can be two or eight qclk cycles, depending on the value of the ist field in th e ccw. resolution time is ten qclk cycles. stop state mach, sar and sar buffer an44 an59 + - final sample buffer chan decoder + - comp. 2 v rh v rl cdac (4 bit) rdac (7 bit) conv. crh crl 4 (one is offset) 7 ccw buffer data bus 10 result ist ref wccw eos/eoc standard converter interface clk zero 7 buffer amp bias cap array equals cdac sample . . . altref qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-37 therefore, conversion time requires a minimum of 14 qc lk clocks (seven s wi th a 2.0-mhz qclk). if the maximum final sample time peri od of 8 qclks is selected, the tota l conversion time is 20 qclks (10 s with a 2.0-mhz qclk) figure 14-21 illustrates the timing for conversions. figure 14-21. conversion timing 14.3.12 channel decode and multiplexer the internal multiplexer selects one of the 16 analog input signals for conversion. the selected input is connected to the sample buffer amplifier. the mult iplexer also includes positive and negative stress protection circuitry, which prevents deselected channe ls from affecting the selected channel when current is injected into the deselected channels. refer to appendix f, ?electri cal characteristics ,? for specific current levels. 14.3.13 sample buffer amplifier the sample buffer is used to raise the effective inpu t impedance of the a/d converter, so that external components (higher bandwidth or higher impedance) ar e less critical to accuracy. the input voltage is buffered onto the sample capacitor to reduce crosstalk between channels. 14.3.14 digital to analog converter (dac) array the digital to analog converter (dac) array consists of binary-weighted capacitors and a resistor-divider chain. the reference voltages, v rh and v rl , are used by the dac to perfor m ratiometric conversions. the dac also converts the followi ng three internal channels: ?v rh ? reference voltage high ?v rl ? reference voltage low ?(v rh ? v rl )/2 ? reference voltage the dac array serves to provide a mechanism for the successive approximation a/d conversion. sample time ?final? sample time resolution (?conv?) time sample time successive approxim ation resolution sequence 2 cycles n cycles: 10 cycles qclk (2 or 8) ?buffer? qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-38 freescale semiconductor resolution begins with the most si gnificant bit (msb) and works down to the least significant bit (lsb). the switching sequence is controlled by the comp arator and successive-appr oximation register (sar) logic. ? sample capacitor ? the sample capacitor is employed to sample and hold the voltage to be converted. 14.3.15 comparator the comparator is used during the approximation pr ocess to sense whether the digitally selected arrangement of the dac array produces a voltage le vel higher or lower than the sampled input. the comparator output feeds into the sar which accumu lates the a/d conversion result sequentially, beginning with the msb. 14.3.16 bias the bias circuit is controlled by the stop signal to power-up and power-down al l the analog circuits. 14.3.17 successive approximation register the input of the successive approxi mation register (sar) is connected to the comparator output. the sar sequentially receives the c onversion value one bit at a time, starting with the ms b. after accumulating the 10 bits of the conversion result, the sar data is transferred to the appr opriate result lo cation, where it may be read from the imb3 by user software. 14.3.18 state machine the state machine receives the qclk, rst, stop , ist, chan[6:0], and start conv signals, from which it generates all timing to perform an a/d conversion. the star t conversion signa l (start conv) indicates to the a/d converter that the desired channel has b een sent to the multip lexor. ist indicates the desired sample time. the end of c onversion (eoc) signal notifies the queue control logic that a result is available for storage in the result ram. 14.4 digital subsystem the digital control subsystem includes the control logi c to sequence the conversi on activity, the clock and periodic/interval timer, c ontrol and status register s, the conversion command word table ram, and the result word table ram. the central element for control of the qadc64e co nversions is the 64-entry ccw table. each ccw specifies the conversion of one i nput channel. depending on the appl ication, one or two queues can be established in the ccw tabl e. a queue is a scan seque nce of one or more input channels. by using a pause mechanism, sub queues can be created in the two queues. each queue can be operated using one of several different scan modes. the scan modes for queue 1 and queue 2 are programmed in qacr1 and qacr2 (control registers 1 and 2). once a queue has been star ted by a trigger event (any of the ways to cause the qadc64e to begin executing the cc ws in a queue or sub-queue), the qadc64e performs a sequence of conversions and places the results in the result word table. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-39 14.4.1 queue priority queue 1 has priority over queue 2 execution. the following cases show the conditions under which queue 1 asserts its priority: ? when a queue is not active, a tr igger event for queue 1 or queue 2 causes the corresponding queue execution to begin. ? when queue 1 is active and a tr igger event occurs for queue 2, que ue 2 cannot begin execution until queue 1 reaches completion or the paused state. the status register records the trigger event by reporting the queue 2 stat us as trigger pending. additional tri gger events for queue 2, which occur before execution can begin, are captured as trigger overruns. ? when queue 2 is active and a trigger event occu rs for queue 1, the curren t queue 2 conversion is aborted. the status register repor ts the queue 2 status as suspe nded. any trigger events occurring for queue 2 while queue 2 is susp ended are captured as trigger ov erruns. once queue 1 reaches the completion or the paused state, queue 2 begins executing again. the pr ogramming of the resume bit in qacr2 determines which ccw is executed in queue 2. refer to section 14.3.7, ?control register 2 ? for more information. ? when simultaneous trigger events occur for que ue 1 and queue 2, queue 1 begins execution and the queue 2 status is ch anged to trigger pending. 14.4.2 sub-queues that are paused the pause feature can be us ed to divide queue 1 and/ or queue 2 into multiple sub-queues. a sub-queue is defined by setting the pause bit in the last ccw of the sub-queue. figure 14-22 shows the ccw format and an example of us ing pause to create s ub-queues. queue 1 is shown with four ccws in each sub-queue and queue 2 has two ccws in each sub-queue. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-40 freescale semiconductor figure 14-22. qadc64e queue operation with pause the queue operating mode selected fo r queue 1 determines what type of trigger event causes the execution of each of the sub-queues within queue 1. similarly, the queue operati ng mode for queue 2 determines the type of trigger event required to execut e each of the sub-queues within queue 2. note when the external trigger rising edge continuous-scan mode is selected for queue 1, and there are six sub-queues wi thin queue 1, a separate rising edge is required on the external trigger si gnal after every pause to begin the execution of each sub-queue (refer to figure 14-22 ). refer to section 14.4.4, ?scan modes ? for information on different scan modes. the choice of single-scan or c ontinuous-scan applies to the full queue, and is not applied to each sub-queue. once a sub-queue is initiated, each ccw is executed sequentially until the last ccw in the sub-queue is executed and the paus e state is entered. execution can onl y continue with the next ccw, which is the beginning of the next sub-queue. a s ub-queue cannot be executed a second time before the overall queue execution has been completed. refer to section 14.3.7, ?control register 2 ? for more information. qadc64e cqp 00 begin queue 1 bq2 63 end of queue 1 begin queue 2 end of queue 2 00 63 channel select sample, hold a/d conversion conversion command word (ccw) table result word table 0 p 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 p 1 p 0 pause pause pause pause pause pause and qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-41 trigger events which occur during th e execution of a sub-queue are ignor ed, except that the trigger overrun flag is set. when a continuous-scan mode is selected, a trigger event oc curring after the completion of the last sub-queue (after the queue comp letion flag is set), causes the ex ecution to continue with the first sub-queue, starting with th e first ccw in the queue. when the qadc64e encounters a ccw with the pause bit set, the queue enters the paused state after completing the conversion specified in the ccw with the pause bit. the pause flag is set and a pause software interrupt may optionally be issued. the status of the queue is shown to be paused, indicating completion of a sub-queue. the qadc 64e then waits for another trigge r event to again begin execution of the next sub-queue. 14.4.3 boundary conditions the following are queue operation boundary conditions: ? the first ccw in a queue contai ns channel 63, the end-of-queue (eoq) code. the queue becomes active and the first ccw is rea d. the end-of-queue is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. ? bq2 (beginning of queue 2) is set at the end of the ccw table (63) and a trigger event occurs on queue 2. refer to section 14.3.7, ?control register 2 ? for more information on bq2. the end-of-queue condition is recognized, a conversion is performed, the comple tion flag is set, and the queue becomes idle. ? bq2 is set to ccw0 and a trigger event occurs on queue 1. after readi ng ccw0, the end-of-queue condition is recognized, the completi on flag is set, and the queue b ecomes idle. a conversion is not performed. ? bq2 is set beyond the end of the ccw table (64 ? 127) and a trigge r event occurs on queue 2. the end-of-queue condition is recogni zed immediately, the completion flag is set, and the queue becomes idle. a conversion is not performed. note multiple end-of-queue conditions ma y be recognized simultaneously, although there is no change in the qad c64e behavior. for example, if bq2 is set to ccw0, ccw0 contains the eo q code, and a trigger event occurs on queue 1, the qadc64e reads ccw0 and detects both end-of-queue conditions. the completion flag is set and queue 1 becomes idle. boundary conditions also exist for combinations of pa use and end-of-queue. one ca se is when a pause bit is in one ccw and an end-of-queue condition is in the next ccw. the conversion specified by the ccw with the pause bit set completes norma lly. the pause flag is set. howeve r, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. examples of this situation include: ? the pause bit is set in ccw5 and the eoq code is in ccw6 ? the pause is set in ccw63 ? during queue 1 operation, the pause bit is set in ccw20 and bq2 points to ccw21 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-42 freescale semiconductor another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same ccw. both the pa use and end-of-queue co nditions are recognized simultaneously. the end-of-queue condition has precedence so a conversion is not performed for the ccw and the pause flag is not set. th e qadc64e sets the completion flag and the queue status becomes idle. examples of this situation are: ? the pause bit is set in ccw10 and eoq is programmed into ccw10 ? during queue 1 operation, the pause bi t set in ccw32, which is also bq2 14.4.4 scan modes the qadc64e queuing mechanism al lows the application to util ize different requirements for automatically scanning input channels. in single-scan mode, a single pass through a sequence of conversions de fined by a queue is performed. in continuous-scan mode, mu ltiple passes through a sequence of c onversions define d by a queue are executed. the possible modes are: ? disabled and reserved mode ? single-scan modes ? software initiated single-scan mode ? external trigger single-scan mode ? external gated single-scan mode ? periodic/interval ti mer single-scan mode ? continuous-scan modes ? software initiated continuous-scan mode ? external trigger continuous-scan mode ? external gated continuous-scan mode ? periodic/interval time r continuous-scan mode 14.4.4.1 disabled mode when the disabled mode is selecte d, the queue is not active. trigger ev ents cannot initiate queue execution. when both queue 1 and queue 2 are disabled, wait st ates are not encountered for imb3 accesses of the ram. when both queues are disa bled, it is safe to change the qclk prescaler values. 14.4.4.2 reserved mode reserved mode allows for future mode definitions. wh en the reserved mode is selected, the queue is not active. it functions the same as disabled mode. warning do not use a reserved mode. un specified operations may result. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-43 14.4.4.3 single-scan modes when the application software wants to execute a single pass through a sequenc e of conversions defined by a queue, a single-scan queue operating mode is sel ected. by programming the mq field in qacr1 or qacr2, the following modes can be selected: ? software initiated single-scan mode ? external trigger single-scan mode ? external gated single-scan mode ? periodic/interval ti mer single-scan mode note queue 2 cannot be programmed for external gated single-scan mode. in all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queue?s control register. the single-scan enable bits, sse1 and sse2, are provided for queue 1 and queue 2 respectively. until the single-scan enable bit is set, any trigger events for that queue are ignored. the single-scan enable bit may be set to a one during the write cycle, wh ich selects the single-scan queue operating mode. the single-scan enable bit is set through software, but will always read as a zero. once set, writing the single-scan enable bit to zero has no effect. only th e qadc64e can clear the single-scan enable bit. the completion flag, completion interrupt , or queue status are used to determine when the queue has completed. after the single-scan enable bit is set, a trigger ev ent causes the qadc64e to begin execution with the first ccw in the queue. the single-scan enable bit remains set until the queue is completed. after the queue reaches completion, the qadc64e resets the si ngle-scan enable bit to zero. if the single-scan enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not affected. however, if the software changes the queue operating mode, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. the conversi on in progress is aborted and the new queue operati ng mode takes effect. in the software-initiated single-scan mode, the writing of a one to th e single-scan enable bit causes the qadc64e to internally generate a trigger event and the queue execution begins immediatel y. in the other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. the single-scan enable bit allows the entire queue to be scanned once. a trigger overrun is captured if a trigger event occurs during queue executi on in an edge-sensitive external trigger mode or a periodic/interval timer mode. in the periodic/interval time r single-scan mode, the next expiration of the timer is the trigger event for the queue. after the queue execution is complete, the queue status is shown as idle. the software can restart the queue by setting the single-scan enable bit to a one. queue execution begins with the first ccw in the queue. 14.4.4.3.1 software init iated single-scan mode software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enab le bit in qacr1 or qacr2. a trigger event is qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-44 freescale semiconductor generated internally and the qadc64e immediately begins execution of the first ccw in the queue. if a pause occurs, another trigger event is generated internally, and then execution continues without pausing. the qadc64e automatically performs the conversions in the queue until an e nd-of-queue condition is encountered. the queue remains idle unt il the software again sets the singl e-scan enable bit. while the time to internally generate and act on a trigger event is ve ry short, software can momentarily read the status conditions, indicating that the queue is paused. the trig ger overrun flag is never se t while in the software initiated single-scan mode. the software initiated single-scan mode is useful in the following applications: ? allows software complete control of the queue execution ? allows the software to easily altern ate between severa l queue sequences. 14.4.4.3.2 external trigger single-scan mode the external trigger single-scan mode is availabl e on both queue 1 and queue 2. the software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. the software must enable the scan to occur by setting the single-scan enable bit for the queue. the first external trigger edge causes the queue to be executed one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. after the queue is completed, the qadc64e clears the single-scan enable bit. software may set the single-scan enable bit again to allow another scan of the queue to be initiated by the next external trigger edge. the external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. analog samples can be taken in sync with an external event, even though the software is not interested in data taken from every edge. the software can start the external tri gger single-scan mode and get one set of data, and at a later ti me, start the queue again for the next set of samples. when a pause bit is encount ered during external trigger single-scan mode, another trigger event is required for queue execution to continue. soft ware involvement is not needed to enable queue execution to continue from the paused state. 14.4.4.3.3 external ga ted single-scan mode the qadc64e provides external gating for queue 1 onl y. when external gated single-scan mode is selected, the input level on the associ ated external trigger signal enable s and disables queue execution. the polarity of the external gated signal is fixed so only a high le vel opens the gate and a low level closes the gate. once the gate is ope n, each ccw is read and th e indicated conversions are performed until the gate is closed. software must enable the scan to occur by setting the single-scan enable bit for queue 1. if a pause in a ccw is enc ountered, the pause flag will not set, and execution continues without pausing. while the gate is open, queue 1 executes one time. e ach ccw is read and the indicated conversions are performed until an end-of -queue condition is encountered. when queue 1 completes, the qadc64e sets the completion flag (cf1) and clears the single-scan en able bit. software may set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. if the gate closes before queue 1 completes execution, the current ccw completes, execution of queue 1 stops, the single-scan enable bit is cleared, and th e pf1 bit is set. software can read the cwpq1 to qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-45 determine the last valid conversion in the queue. soft ware must set the single-sc an enable bit again and should clear the pf1 bit before anothe r scan of queue 1 is in itiated during the next open gate. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conve rsion time interval does not guarant ee the closure will be captured. 14.4.4.3.4 periodic/interv al timer single-scan mode both queues can use the periodic/inte rval timer in a single- scan queue operating mode . the timer interval can range from 128- to 128-kbyte qclk cycles in binary multiples. when the periodic/ interval timer single-scan mode is selected and the software sets the single-scan enable bit in qacr1 or qacr2 , the timer begins counting. when th e time interval elapses, an internal trigger event is created to start the queue and the qadc64e begins execution with the first ccw. the qadc64e automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. wh en a pause occurs, queue execution stops until the timer interval elapses again, and then queue execution continues. when the queue execution reaches an end-of-queue situation, the single-scan enable bit is clea red. software may set the single-scan enable bit again, allowing another scan of the queue to be initia ted by the periodic/interval timer. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. once the queue execution is completed, the single-scan enab le bit must be set again to enable the timer to count again. normally only one queue will be en abled for periodic/inter val timer single-scan mode and the timer will reset at the end-of-queue. however, if both queues are enabled for either single-scan or continuous periodic/interval timer mode , the end-of-queue condition will not reset the timer while the othe r queue is active. in this case, the time r will reset when both queues ha ve reached end-of-queue. see section 14.4.6, ?periodic/interval timer ,? for a definition of periodic/ interval timer reset conditions. the periodic/interval timer si ngle-scan mode can be used in applica tions which need coherent results, for example: ? when it is necessary that all samp les are guaranteed to be taken during the same scan of the analog signals ? when the interrupt rate in the periodic/interv al timer continuous-scan mode would be too high ? in sensitive battery applications, where the single- scan mode uses less power than the software initiated continuous-scan mode 14.4.4.4 continuous-scan modes when the application software want s to execute multiple passes through a sequence of conve rsions defined by a queue, a continuous-scan queue operating mode is selected. by programming the mq1 field in qacr1 or the mq2 field in qacr2, the followin g software initiated m odes can be selected: ? software initiated continuous-scan mode ? external trigger continuous-scan mode qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-46 freescale semiconductor ? external gated continuous-scan mode ? periodic/interval time r continuous-scan mode when a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meani ng or effect. as soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. in the case of the software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. in the other continuous-scan queue operati ng modes, the selected trigger event must occur before the queue can start. a trigger overrun is captured if a trigger event occurs during queue execution in the external trigger c ontinuous-scan mode and the periodic/interval timer continuous-scan mode. after the queue execution is complete, the queue status is shown as idle. since the continuous-scan queue operating modes allow the entire queue to be scanned mu ltiple times, software i nvolvement is not needed to enable queue execution to continue from the idle state. the next trigger event causes queue execution to begin again, starting with the first ccw in the queue. note coherent samples are guaranteed. the time between consecutive conversions has been designed to be consistent. however, there is one exception. for queues that end with a ccw containing e oq code (channel 63), the last queue conversion to th e first queue conversion requires 1 additional ccw fetch cycle. therefore continuous sa mples are not coherent at this boundary. in addition, the time from trigger to first conversion cannot be guaranteed since it is a function of clock synchronization, programmable trigger ev ents, queue priorities, and so on. 14.4.4.4.1 software initia ted continuous-scan mode when the software initiated con tinuous-scan mode is programmed, the trigger event is generated automatically by the qadc64e. queue execution begins immediately. if a pause is encountered, another trigger event is generated internally, and then execution continues without pausing. when the end-of-queue is reached, another in ternal trigger event is generated, and queue execution begins again from the beginning of the queue. while the time to internally generate and act on a tr igger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. the trigger overrun flag is never set while in the software-initiated continuous-scan mode. the software initiated cont inuous-scan mode keeps the result regist ers updated more frequently than any of the other queue operating modes. the software can always read the result table to get the latest converted value for each channel. the channels sc anned are kept up to date by the qadc64e without software involvement. software can read a result value at any time. the software initiated continuous-scan mode may be c hosen for either queue, but is normally used only with queue 2. when the software in itiated continuous-scan m ode is chosen for queue 1, that queue operates qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-47 continuously and queue 2, be ing lower in priority, never gets execut ed. the short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. the software initiated con tinuous-scan mode is a usef ul choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-to-cha nge analog channels. interrupts are normally not used with the software initiated continuou s-scan mode. rather, the so ftware reads the latest conversion result from the re sult table at any time. once initiated, so ftware action is not needed to sustain conversions of channel. 14.4.4.4.2 external trig ger continuous-scan mode the qadc64e provides external trigger signals for both queues. when the external trigger software initiated continuous-scan mode is se lected, a transition on the associated external trigger signal initiates queue execution. the polarity of the ex ternal trigger signal is programmable, so that the software can select a mode which begins queue execution on the rising or falling edge. each ccw is read and the indicated conversions are performed unt il an end-of-queue condition is encount ered. when the next external trigger edge is detected, the queue executi on begins again automatically. soft ware initialization is not needed between trigger events. when a pause bit is encountered in external trigger continuous-scan mode , another trigger event is required for queue execution to continue. soft ware involvement is not needed to enable queue execution to continue from the paused state. some applications need to synchroni ze the sampling of analog channels to external events. there are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. 14.4.4.4.3 external gate d continuous-scan mode the qadc64e provides external gating for queue 1 onl y. when external gated continuous-scan mode is selected, the input level on the associ ated external trigger signal enable s and disables queue execution. the polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. when the gate opens agai n, the queue execution automatically begins again from the beginning of the queue. software initializ ation is not needed between trigger events. if a paus e in a ccw is encountered, the pause flag will not set, and execution conti nues without pausing. the purpose of external gated cont inuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples availa ble. it is up to the progr ammer to ensure that the queue is large enough so that a maximum gate open tim e will not reach an end- of-queue. however it is useful to take advantage of a smaller queue in the manner described in the next paragraph. in the event that the queue completes before the gate closes, a completion flag will be set and the queue will roll over to the beginning and continue conversions until the gate closes. if the gate remains open and the completion flag is not cleared, when the queue co mpletes a second time the trigger overrun flag will be set and the queue will roll-over again. the queue will continue to execute until the gate closes or the mode is disabled. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-48 freescale semiconductor if the gate closes before queue 1 completes execut ion, the current ccw comple tes execution of queue 1 stops and qadc64e sets the pf1 bit to indicate an incomplete queue. software can read the cwpq1 to determine the last valid conversion in the queue. in this mode, if the ga te opens again, execution of queue 1 begins again. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time inte rval does not guarantee the closure will be captured. 14.4.4.4.4 periodic/interval timer continuous-scan mode the qadc64e includes a dedicated periodic/interval timer for initiating a scan sequence on queue 1 and/or queue 2. software selects a programmable timer interval ranging from 128 to 128 kbytes times the qclk period in binary multiples. the qclk pe riod is prescaled down from the imb3 mcu clock. when a periodic/interval timer cont inuous-scan mode is selected for queue 1 and/or queue 2, the timer begins counting. after the programmed interval elapse s, the timer generated trigger event starts the appropriate queue. meanwhile , the qadc64e automatically performs the conversi ons in the queue until an end-of-queue condition or a pa use is encountered. when a pause occurs, the qadc64e waits for the periodic interval to expire again, then continues wi th the queue. once end-of-que ue has been detected, the next trigger event causes queu e execution to begin again with the first ccw in the queue. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue executi on to continue following a pause or queue completi on, or may be considered a trigger overrun. as with all cont inuous-scan queue operating modes, software action is not needed between trigger events. si nce both queues may be triggered by the periodic/interval timer, see section 14.4.6, ?periodic/interval timer ? for a summary of periodic/in terval timer reset conditions. software enables the completion interrupt when usi ng the periodic/interval timer continuous-scan mode. when the interrupt occurs, the softwa re knows that the periodically collec ted analog results have just been taken. the software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. 14.4.5 qadc64e clock (qclk) generation figure 14-23 is a block diagram of the clock subsyste m. the qclk provides the timing for the a/d converter state machine wh ich controls the timing of the conversion. the qclk is also the input to a 17-stage binary divider which implem ents the periodic/interval timer. to retain the specified analog conversion accuracy, th e qclk frequency (f qclk ) must be within the tolerance specified in appendix f, ?electrical characteristics .? before using the qadc64e, the software must initiali ze the prescaler with values that put the qclk within the specified range. though most software applications init ialize the prescaler once and do not change it, write operations to th e prescaler fields are permitted. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-49 warning a change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. therefore, any prescaler write operation should be done only wh en both queues are in the disabled modes. figure 14-23. qadc64e clock subsystem functions the mcu system clock freque ncy (imb3 system clock ? f sysclk ) is the basis of the qadc64e timing. qclk is generated by a software se lectable prescaler that divides f sysclk thus allowing the a/d conversion time to be maximized across f sysclk . the software establishes the frequency of qclk waveform by setting the prescaler field in the qacr0 register. when the value of prescaler > 0 the resulting frequency of qclk is calculated using the following formula: f qclk = f sysclk / (prescaler + 1) the qadc64e requires that f sysclk be at least twice f qclk . therefore if the value in the prescaler field is set to zero, the resulting qc lk frequency is calculated to be: f qclk = f sysclk / 2 qadc clock block prescaler rate selection (from control register 0) binary counter periodic / interval timer select 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 16 2 17 clock generate qclk qadc clock ( f sys / 2 to f sys / 40 ) input sample time queue 1 & 2 timer sar control sar[9:0] periodic/interval trigger event system clock (f sys ) a/d converter state machine for q1 and q2 2 8 (from ccw) mode rate selection qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-50 freescale semiconductor 14.4.6 periodic/interval timer the on-chip periodic/interval timer can be used to generate trigger events at a programmable interval, initiating execution of queue 1 and/ or queue 2. the periodic /interval timer stays re set under the following conditions: ? both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer ? imb3 system reset or the master reset is asserted ? stop mode is selected ? freeze mode is selected note interval timer single-scan mode does not use the periodic/interval timer until the single-scan enable bit is set. the following two conditions will cause a pulsed reset of the periodic/in terval timer during use: ? a queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer ? a queue 2 operating mode change to a mode whic h uses the periodic/interv al timer, provided queue 1 is not in a mode which uses the periodic/interval timer ? roll over of the timer during the low power stop mode, the periodic timer is held in reset. since low power stop mode causes qacr1 and qacr2 to be reset to zero, a valid periodic or interval timer mode mu st be written after stop mode is exited to rel ease the timer from reset. when the imb3 internal freeze line is asserted and a periodic or interval time r mode is selected, the timer counter is reset after the conve rsion in progress completes. when the periodic or inte rval timer mode has been enabled (the timer is counting), but a tri gger event has not been issued, the freeze mode takes effect immediately, and th e timer is held in reset. when the in ternal freeze line is negated, the timer counter starts counting fr om the beginning. refer to section 14.4.7, ?configuration and control using the imb3 interface ? for more information. table 14-22. qadc64e clock programmability control register 0 information input sample time (ist) =0 example number frequency prescaler qclk (mhz) conversion time ( s) 1 20 mhz 0x09 2.0 7.0 2 40 mhz 0x13 2.0 7.0 356 mhz 0x1b 2.0 7.0 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-51 14.4.7 configuration and cont rol using the imb3 interface the qadc64e module communicates wi th other microcontroller modul es via the imb3. the qadc64e bus interface unit (biu) coordinates imb3 activity with internal qadc 64e bus activity. this section describes the operation of the biu, imb3 read/wri te accesses to qadc64e memory locations, module configuration, and genera l-purpose i/o operation. 14.4.7.1 qadc64e bus interface unit the biu is designed to act as a sl ave device on the imb3. the biu has the following functions: to respond with the appropriate bus cycle termination, and to supply imb3 interface timing to all internal module signals. biu components consist of ? imb3 buffers ? address match and module select logic ? the biu state machine ? clock prescaler logic ? data bus routing logic ? interface to the internal module data bus note normal accesses from the imb3 to the qadc64e require two clocks. however, if the cpu tries to access table locations while the qadc64e is accessing them, the qadc64e produces imb3 wait states. from one to four imb3 wait states may be insert ed by the qadc64e in the process of reading and writing. 14.4.7.2 qadc64e bus accessing the qadc64e supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. coherency of results read (ensuring that all results read were taken consecutively in one sc an) is not guaranteed. for example, if a read of two consecut ive 16-bit locations in a result area is made, the qadc64e could change one 16-bit location in the result ar ea between the bus cycles. there is no holding register for the second 16-bit location. all read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. depending on bus master protocol, thes e accesses could include misaligned and 32-bit accesses. figure 14-24 shows the three bus cycles which are im plemented by the qadc64e. the following paragraphs describe how the thr ee types of accesses are used, incl uding misaligned 16-bit and 32-bit accesses. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-52 freescale semiconductor figure 14-24. bus cycle accesses byte access to an even addre ss of a qadc64e location is show n in the top illustration of figure 14-24 . in the case of write cycles, by te 1 of the register is not disturbed. in the case of a read cycle, the qadc64e provides both byte 0 and byte 1. byte access to an odd address of a qadc64e location is shown in the center illustration of figure 14-24 . in the case of write cycles, byte 0 of the register is not disturbed. in th e case of read cy cles, the qadc64e provides both byte 0 and byte 1. 16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of figure 14-24 . the full 16 bits of data is written to and read from the qad c64e location with each access. 16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit qadc64e locations is accessed. the first bus cycle is treated by the qadc64e as an 8-bit read or write of an odd address. the second cycle is an 8-bit read or write of an even address. the qadc64e address space is organized into 16-bit even address lo cations, so a 16-bit read or write of an odd addr ess obtains or provides the lower half of one qadc64e location, and th e upper half of the foll owing qadc64e location. qadc64e bus cyc acc intermodule bus 8-bit access of an even address (isiz = 01, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 8-bit access of an odd address (isiz = 01, a0 = 1; or isiz = 10, a0 = 1) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 16-bit aligned access (isiz = 10, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-53 32-bit accesses to an even address require two bus cy cles to complete the access, and two full 16-bit qadc64e locations are accessed. the first bus cycle reads or writes the addressed 16-bit qadc64e location and the second cycle reads or writes the follow ing 16-bit location. 32-bit accesses to an odd addr ess require three bus cycl es. portions of three di fferent qadc64e locations are accessed. the first bus cycle is treated by the qad c64e as an 8-bit access of an odd address, the second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. the qadc64e address space is organized into 16-bit even a ddress locations, so a 32-bit read or write of an odd address provides the lower half of one qadc64e location, the full 16-bit content of the following qadc64e location, and the upper half of the third qadc64e location. 14.5 trigger and queue interaction examples this section contains exampl es describing queue priority and conversion timing schemes. 14.5.1 queue priority schemes since there are two conversion command queues and only one a/d converter, there is a priority scheme to determine which conversion is to occur. each queue has a variety of trigger events that are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress. for example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting another trigger event to continue the queue, and so on. the following paragraphs and figures outline the prioritizing criteria used to determine which conversion occurs in each overlap situation. note the situations in figure 14-25 through figure 14-43 are labeled s1 through s19. in each diagram, time is shown increasing from left to right. the execution of queue 1 and queue 2 (q 1 and q2) is shown as a string of rectangles representing the execution ti me of each ccw in the queue. in most of the situations, th ere are four ccws (labeled c1 to c4) in both queue 1 and queue 2. in some of the situati ons, ccw c2 is pres umed to have the pause bit set, to show the similari ties of pause and end-of-queue as terminations of queue execution. trigger events are described in table 14-23 . table 14-23. trigger events trigger events t1 events that trigger queue 1 execution (external trigger, software initiated single-scan enable bit, or completion of the previous continuous loop) t2 events that trigger queue 2 execution (external trigger, software initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-54 freescale semiconductor when a trigger event causes a ccw execution in progress to be aborte d, the aborted conversion is shown as a ragged end of a shortened ccw rectangle. the situation diagrams also show when key status bits are set. table 14-24 describes the status bits. below the queue execution flows are three sets of bloc ks that show the status information that is made available to the software. the first two rows of status blocks show the condition of each queue as: ? idle ?active ?pause ? suspended (queue 2 only) ? trigger pending the third row of status blocks shows the 4-bit qs status register field that encodes the condition of the two queues. two transition status cases, qs = 0011 and qs = 0111, are not s hown because they exist only very briefly between stable status conditions. the first three examples in figure 14-25 through figure 14-27 (s1, s2, and s3) show what happens when a new trigger event is recognized be fore the queue has completed servic ing the previous trigger event on the same queue. in situation s1 ( figure 14-25 ), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event. the trigger overrun error status bit is set, and otherwise, the premature trigger even t is ignored. a trigger ev ent which occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress. table 14-24. status bits bit function cf flag set when the end of the queue is reached pf flag set when a queue completes execution up through a pause bit trigger overrun error (tor) set when a new trigger event occurs before the queue is finished serving the previous trigger event qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-55 figure 14-25. ccw priority situation 1 in situation s2 ( figure 14-25 ), more than one trigger event is rec ognized before servicing of a previous trigger event is complete, the trigger overrun bit is ag ain set, but otherwise, the additional trigger events are ignored. after the queue is complete, the first newly detected tr igger event causes queue execution to begin again. when the trigger event ra te is high, a new trigger event can be seen very soon after completion of the previous queue, leaving software little time to retrieve the prev ious results. also, when trigger events are occurring at a high rate for queue 1, the lower prio rity queue 2 channels may not get serviced at all. figure 14-26. ccw priority situation 2 situation s3 ( figure 14-26 ) shows that when the pause feature is in use, the tri gger overrun error status bit is set the same way, and that queue execution continues unchanged. q1 q2 qs idle active idle 0000 1000 0000 0010 0000 tor1 t1 t1 q1: c1 c2 c3 c4 cf1 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle qadc s1 active idle qadc s2 active idle q1 q2 qs idle active idle active idle 1000 1000 0000 0010 0000 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle c1 c2 c3 c4 t1 cf1 c1 c2 c3 c4 tor1 t1 t1 q1: cf1 tor1 t1 tor1 t1 tor2 t2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-56 freescale semiconductor figure 14-27. ccw priority situation 3 the next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced. situation s4 ( figure 14-28 ) shows that a queue 2 trigger event that is recognized while queue 1 is active is saved, and as soon as queue 1 is finished, queue 2 servicing begins. figure 14-28. ccw priority situation 4 situation s5 ( figure 14-29 ) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. situation s5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue. qadc s3 q1 q2 qs idle active idle active idle 1000 0110 0001 0010 active 0000 idle c1 c2 t1 t1 q1: tor1 pf1 c1 c2 0000 q2: 0100 tor2 pf2 t2 t2 0101 c3 c4 t1 t1 tor1 cf1 pause 1001 c3 c4 cf2 t2 t2 tor2 pause active qadc s4 q1 q2 qs idle idle active idle 0000 1000 0010 active 0000 c1 c2 c3 c4 t1 q1: cf1 q2: c1 c2 c3 c4 t2 cf2 idle 1011 triggered qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-57 figure 14-29. ccw priority situation 5 the remaining situations, s6 through s11, show the impact of a queue 1 trig ger event occurring during queue 2 execution. queue 1 is higher in priority the c onversion taking place in queue 2 is aborted, so that there is not a variable latency time in responding to queue 1 trigger events. in situation s6 ( figure 14-30 ), the conversion initiated by the sec ond ccw in queue 2 is aborted just before the conversion is complete, so that queue 1 execution can begi n. queue 2 is considered suspended. after queue 1 is finished, queue 2 st arts over with the first ccw, when the res (resume) control bit is set to 0. situation s7 ( figure 14-31 ) shows that when pause operation is not in use with queue 2, queue 2 suspension works the same way. figure 14-30. ccw priority situation 6 qadc s5 q1 q2 qs idle idle idle 0000 1000 0010 active 0000 c1 c2 t1 q1: c1 c2 pf2 c3 c4 c3 c4 cf2 idle 1011 trig q2: t2 t2 pf1 pause active pause tor2 t2 t2 cf1 tor2 t1 active trig 0110 active active 0101 1001 1011 qadc s 6 idle q1 q2 qs idle idle 0000 1000 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c1 c2 c3 c4 cf2 t2 0010 0000 resume=0 c2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-58 freescale semiconductor figure 14-31. ccw priority situation 7 situations s8 and s9 ( figure 14-32 and figure 14-33 ) repeat the same two situat ions with the resume bit set to a one. when the res bit is set, following su spension, queue 2 resumes ex ecution with the aborted ccw, not the first ccw in the queue. figure 14-32. ccw priority situation 8 qadc s7 t1 t1 pause q1 q2 qs idle idle idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 c1 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active act active resume=0 c2 active suspend suspend qadc s8 idle q1 q2 qs idle idle 0000 1000 0010 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c2 c3 c4 cf2 t2 0000 resume=1 c2 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-59 figure 14-33. ccw priority situation 9 situations s10 and s11 ( figure 14-34 and figure 14-35 ) show that when an a dditional trigger event is detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue 2 were being executed when a new trigger event occurs. trigger overrun on queue 2 thus permits the software to know that queue 1 is taking up so much qadc64e time that queue 2 trigge r events are being lost. figure 14-34. ccw priority situation 10 qadc s9 t1 q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 pause 0110 c1 q2: t2 c2 pf2 t1 c3 c4 cf1 c4 cf2 suspend act active suspend t2 c3 c1 resume=1 c2 c4 active active pause qadc s10 t1 t1 pause q1 q2 qs idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active 0110 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active c1 act t2 tor2 t2 tor2 resume=0 c2 active active suspend suspend pause qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-60 freescale semiconductor figure 14-35. ccw priority situation 11 the above situations cover normal overlap conditions that arise with asynchronous trigger events on the two queues. an additional conflict to consider is that the freeze c ondition can arise while the qadc64e is actively executing ccws. the conventional us e for the freeze mode is for software/hardware debugging. when the cpu background debug mode is enab led and a breakpoint occurs, the freeze signal is issued, which can cause periphe ral modules to stop operation. when freeze is detected, the qadc64e completes the conversion in progress, unlike queue 1 suspending queue 2. after the freeze condition is removed, the qadc64e continues queue exec ution with the next ccw in sequence. trigger events that occur during fre eze are not captured. when a trigger event is pe nding for queue 2 before freeze begins, that trigger event is remembered when the freeze is pa ssed. similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 re sumes execution as soon as queue 1 is finished. situations 12 through 19 ( figure 14-36 to figure 14-43 ) show examples of all of the freeze situations. figure 14-36. ccw freeze situation 12 qadc s11 t1 t1 c3 c4 cf1 pause q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 suspend act c1 active suspend t2 tor2 t2 tor2 c2 pf2 c4 cf2 t2 c3 c2 c4 resume=1 active qadc s12 c3 c4 cf1 c1 c2 t1 q1: freeze qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-61 figure 14-37. ccw freeze situation 13 figure 14-38. ccw freeze situation 14 figure 14-39. ccw freeze situation 15 figure 14-40. ccw freeze situation 16 qadc s13 c1 c2 t2 q2: cf2 c3 c4 freeze qadc s14 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 t2 t2 (triggers ignored) qadc s15 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 t1 t1 (triggers ignored) qadc s16 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 pf1 (triggers ignored) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-62 freescale semiconductor figure 14-41. ccw freeze situation 17 figure 14-42. ccw freeze situation 18 figure 14-43. ccw freeze situation 19 14.5.2 conversion timing schemes this section contains some conve rsion timing examples. example 1 below shows the timing for basic conversions where the following is assumed: ? q1 begins with ccw0 and ends with ccw3 ? ccw0 has pause bit set ? ccw1 does not have pause bit set ? external trigger rise-edge for q1 ? ccw4 = bq2 and q2 is disabled qadc s17 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 pf2 (triggers ignored) qadc s1 8 c1 c2 t1 q1: cf1 c3 c4 freeze t2 c1 c2 q2: c3 cf2 c4 (trigger captured, response delayed after freeze) qadc s19 c1 c2 t1 q1: cf1 c4 freeze cf2 c4 c1 c2 t2 q2: c3 c3 c4 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-63 ? q1 res shows relative result register updates figure 14-44. external trigger mode (positive edge) timing with pause recall qs = 0 => queues disabled; qs = 8 => q1 active, q2 disabled; qs= 4 => q1 paused, q2 disabled. a time separator was provided betw een the triggers and end of conve rsion (eoc). the relationship to qclk displayed is not guaranteed. cwpq1 or cwpq2 typically lag cwp and only match cwp when the associated queue is inactive. another way to view cwpq1(2) is th at these registers update when eoc tr iggers the result register to be written. when the pause bit is set (ccw0), please note that cwp does not increment unt il triggered. when the pause is not set (ccw1), the cwp increments with eoc. the conversion results q1 res(x) show the result as sociated with ccw(x). so that r0 represents the result associated with ccw0. example 2 below shows the timing for conversi ons in gated mode single-scan with the same assumptions as example 1 except: ? no pause bits set in any ccw ? external trigger gated single-scan mode for q1 ? single-scan bit is set when the gate closes and opens again the c onversions start with the first ccw in q1. when the gate closes the active conversi on completes before the queue goes idle. when q1 completes both the cf1 bit sets and the sse bit clears. qclk trig1 eoc qs cwp cwpq1 q1 res ccw1 04 ccw0 last ccw1 ccw2 84 8 r0 r1 conversion time is >= 14 qclks ccw0 last time between triggers qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-64 freescale semiconductor figure 14-45. gated mode , single-scan timing example 3 below shows the timing for conversions in gated continuous-scan mode with the same assumptions in the amended de finition for the pf bit in th is mode to reflect the c ondition that a gate closing occurred before the queue completed is a proposal under consideration at th is time as example 2. note at the end of q1,the completion flag cf1 sets and the queue restarts. also, note that if the queue starts a second time and completes, the trigger overrun flag tor1 sets. trig1 eoc qs cwp cwpq1 q1 res ccw1 0 8 ccw1 last ccw1 ccw2 last 08 r0 r1 ccw0 last ccw1 ccw0 ccw0 r1 ccw0 r0 ccw2 ccw3 r2 sse ccw3 r3 cf1 software must set sse pf1 software must clear pf1 0 (gate) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-65 figure 14-46. gated mode, continuous scan timing 14.6 qadc64e integration requirements the qadc64e requires accurate, noise -free input signals for proper opera tion. this secti on discusses the design of external circuitry to maximize qadc64e performance. the qadc64e uses the exte rnal signals shown in figure 14-1 . there are 16 channel si gnals that can also be used as general-purpos e digital input/output signals. with ex ternal multiplexing mpc561/mpc563 can support 41 analog inputs. in addition, there are thr ee analog reference signals and two analog submodule power signals, shared by each qadc64e module. 14.6.1 port digital input/output signals the sixteen port signals can be used as analog inputs, or as a bidirectional 16-bit di gital input/output port. port a signals are referred to as pqa[7:0] when us ed as a bidirectional 8-bi t digital input/output port. these eight signals may be used for general-purpose digital input si gnals or push-pull digital output signals. port b signals are referred to as pqb[7:0] and operate the same as port a. port a and b signals are connected to a digital input synchr onizer during reads and ma y be used as general purpose digital inputs when the applie d voltages meet high voltage input (v ih ) and low voltage input (v il ) requirements. refer to appendix f, ?electrical characteristics ,? for more information on voltage requirements. trig1 eoc qs cwp cwpq1 q1 res 0 8 last ccw0 ccw1 r1 ccw3 r3 cf1 tor1 ccw0 last xx ccw2 r2 ccw2 ccw1 ccw0 r0 ccw0 ccw3 r3 ccw3 ccw2 r2 ccw3 (gate) q restart q restart qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-66 freescale semiconductor each port a or b signal is configured as an input or output by programmi ng the port data direction register (ddrqa or ddrqb). the digi tal input signal states are read by the so ftware in the uppe r half of the port data register when the port data dire ction register specifies that the signa ls are inputs. the digital data in the port data register is driven onto the port a or b signals when the corresponding bit in the port data direction register spec ifies output. refer to appendix b, ?internal memory map ? for more information. since the outputs are configured as push-pull drivers, external pull-up provisions are not necessary when the output is used to drive another integrated circuit. 14.6.2 external trigger input signals the qadc64e uses two external trigger signals (etr ig[2:1]). each of the tw o input external trigger signals is associated with one of the scan queues, queue 1 or queue 2 the assignment of etrig[2:1] to a queue is made in the qacr0 register by the tr g bit. when trg=0, etrig1 triggers queue 1 and etrig2 triggers queue 2. when trg=1, etrig1 tr iggers queue 2 and etrig2 triggers queue 1. 14.6.3 analog power signals v dda and v ssa signals supply power to the analog subs ystems of the qadc64e module. dedicated power is required to isolate the sensitive analog circ uitry from the normal levels of noise present on the digital power supply. refer to appendix f, ?electrical characteristics ,? for more information. the analog supply signals (v dda and v ssa ) define the limits of the analog reference voltages (v rh and v rl ) and of the analog multiplexer inputs. figure 14-47 is a diagram of the analog input circuitry. figure 14-47. equivalent analog input circuitry sample amp 16 channels v ssa v rl v dda qadc64e 16ch sample amp v rh s/h rc dac comparator c p qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-67 since the sample amplifier is powered by v dda and v ssa , it can accurately transf er input signal levels up to but not exceeding v dda and down to but not below v ssa . if the input signal is out side of this range, the output from the sample amplifier is clipped. in addition, v rh and v rl must be within the range defined by v dda and v ssa . as long as v rh is less than or equal to v dda and v rl is greater than or equal to v ssa and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by v rl and v rh . if v rh is greater than v dda , the sample amplifier can never transfer a fu ll-scale value. if v rl is less than v ssa , the sample amplifier can never transfer a zero value. figure 14-48 shows the results of reference vol tages outside the range defined by v dda and v ssa. at the top of the input signal range, v dda is 10 mv lower than v rh . this results in a ma ximum obtainable 10-bit conversion value of 0x3fe. at th e bottom of the signal range, v ssa is 15 mv higher than v rl , resulting in a minimum obtainable 10-bit conversion value of three. figure 14-48. errors resulting from clipping 14.6.3.1 analog supply filtering and grounding two important factors influencing performance in an alog integrated circuits are supply filtering and grounding. generally, digital circui ts use bypass capac itors on every v dd /v ss signal pair. this applies to analog sub-modules also. the distribution of power and ground is equally important. qadc64e clipping 0 .020 5.100 5.110 input in volts (v rh = 5.12 v, v rl = 0 v) 1 2 3 4 5 6 7 8 3fa 3fb 3fc 3fd 3fe 3ff .010 .030 5.120 5.130 10-bit result (hexadecimal) qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-68 freescale semiconductor analog supplies should be isolated fr om digital supplies as much as pos sible. this necessity stems from the higher performance requirements of ten associated with analog circuits . therefore, deriving an analog supply from a local digital supply is not recomme nded. however, if for econom ic reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of th e supplies already mentioned. note an rc low pass filter coul d be used to isolate the digital and analog supplies when generated by a common regulator . if multiple high precision analog circuits are locally empl oyed (i.e., two a/d convert ers), the analog supplies should be isolated from each other as sharing supplie s introduces the potential for interference between analog circuits. grounding is the most importa nt factor influencing an alog circuit performance in mixed signal systems (or in stand-alone analog systems). clos e attention must be paid not to introduce additional sources of noise into the analog circuitry. common sources of noi se include ground loops, inductive coupling, and combining digital and analog gr ounds together inappropriately. the problem of how and when to combine digital a nd analog grounds arises from the large transients which the digital ground must handle. if the digital gr ound is not able to handle the large transients, the current from the large transients can return to gr ound through the analog ground. it is the excess current overflowing into the analog ground wh ich causes performance degradat ion by developing a differential voltage between the true analog ground and the microcontroller?s ground signa l. the end result is that the ground observed by the analog circuit is no longer tr ue ground and often ends in skewed results. two similar approaches designed to improve or eliminate the problem s associated with grounding excess transient currents involve st ar-point ground systems. one approach is to star-point the different grounds at the power supply origin, thus keep ing the ground isolated. refer to figure 14-49 . qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-69 figure 14-49. star-ground at the point of power supply origin another approach is to star-point the diff erent grounds near the analog ground signal on the microcontroller by using small tr aces for connecting the non-analog grounds to the analog ground. the small traces are mean t only to accommodate dc diff erences, not ac transients. note this star-point scheme still require s adequate grounding for digital and analog subsystems in additi on to the star-point ground. other suggestions for pcb layout in wh ich the qadc64e is employed include: ? analog ground must be low impedance to all analog ground points in the circuit. ? bypass capacitors should be as close to the power signals as possible. ? the analog ground should be isolated from the digital ground. this can be done by cutting a separate ground plane for the analog ground. ? non-minimum traces should be utilized for conn ecting bypass capacitors and filters to their corresponding ground/power points. ? distance for trace runs should be minimized where possible. 14.6.4 analog reference signals v rh and v rl are the dedicated input signals for the hi gh and low reference voltages. separating the reference inputs from the power suppl y signals allows for additional ex ternal filtering, which increases reference voltage precision and stability, and subseque ntly contributes to a higher degree of conversion accuracy. qadc64e vrh vrl vssa vdda vdd vss analog power supply +5v +5v agnd digital power +5v pgnd pcb supply qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-70 freescale semiconductor the altref signal may be selected through the ccw as the high reference for a conversion. this allows for the ability to ?zoom? in on a portion of the convertible range wi th the full 10 bits. refer to table 14-19 . no a/d converter can be more accurat e than its analog reference. any noise in the reference can result in at least that much er ror in a conversion. the reference fo r the qadc64e, supp lied by signals v rh , altref, and v rl , should be low-pass filtered from its source to obtain a noise-free, clean signal. in many cases, simple capacitive bypassing may sufficed. in extreme ca ses, inductors or ferrite beads may be necessary if noise or rf energy is present. se ries resistance is not advisable sin ce there is an effective dc current requirement from the reference volta ge by the internal resi stor string in the rc dac array. external resistance may introduce error in this architecture under certain conditions. any series devices in the filter network should contain a mini mum amount of dc resistance. 14.6.5 analog input signals analog inputs should have low ac impedance at the signals. low ac impedance can be realized by placing a capacitor with good high frequenc y characteristics at the input sign al of the part. ideally, that capacitor should be as large as possi ble (within the practical range of capacitors that still have good high frequency characteristics). this capacitor has two effects: ? it helps attenuate any noise that may exist on the input. ? it sources charge during the sample period when the analog signal source is a high-impedance source. series resistance can be used with the capacitor on an input signal to implement a simple rc filter. the maximum level of filtering at the input signals is application depe ndent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input . simple rc filtering at the signal may be limited by the source impedance of the transducer or circuit supplyi ng the analog signal to be measured. refer to section 14.6.5.3, ?error resu lting from leakage ? for more information. in some cases, the size of the capacitor at the signal may be very small. figure 14-50 is a simplified model of an input channel. re fer to this model in the following discussion of the interaction between the external circui try and the circuitry inside the qadc64e. qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-71 figure 14-50. electrical model of an a/d input signal in figure 14-50 , r f , r src and c f comprise the external filter circuit. c p is the internal parasitic capacitor. c samp is the capacitor array used to sa mple and hold the input voltage. v i is an internal vol tage source used to provide charge to c samp during sample phase. the following paragraphs provide a simplified description of the in teraction between the qadc64e and the external circuitry. this circuitry is assumed to be a simple rc low-pass fi lter passing a signal from a source to the qadc64e input signal. the fo llowing simplifying assumptions are made: ? the external capacitor is perfect (no leakage, no significant dielectric ab sorption characteristics, etc.) ? all parasitic capacitance associated with the input signal is in cluded in the value of the external capacitor ? inductance is ignored ? the ?on? resistance of th e internal switches is 0 ? and the ?off? resistance is infinite 14.6.5.1 analog input considerations the source impedance of the analog signal to be m easured and any intermedia te filtering should be considered whether external multiplexing is used or not. figure 14-51 shows the connection of eight typical analog signal sources to one qadc64e analog input signal through a separate multiplexer chip. also, an example of an analog signal source connected directly to a qadc64e analog input channel is displayed. qadc64e sample amp model s1 amp r f s3 s2 c samp v i c p c f v src internal circuit model external filter = source voltage = internal parasitic capacitance v src r f c f c p c samp = sample capacitor v i = filter impedance = filter capacitor = internal voltage source during sample and hold source r src r src = source impedance qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-72 freescale semiconductor figure 14-51. external multiplexing of analog signal sources ~ ~ ~ ~ ~ ~ ~ ~ c p c samp c p c sa m p c in = c p + c samp r muxout r source 2 typical mux chip qadc64e qadc64e ext mux ex ~ c filter c source r filter 2 c muxin c muxout (mc54hc4051, mc74hc4051, mc54hc4052, mc74hc4052, mc54hc4053, etc.) r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin r source 2 c filter c source r filter 2 c muxin c filter r filter 2 r source 2 c source c pcb c pcb analog signal source filtering and interconnect 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 0.01 f 1 interconnect qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-73 14.6.5.2 settling time fo r the external circuit the values for r src , r f and c f in the external circuitry determine the length of time required to charge c f to the source voltage level (v src ). at time t = 0, v src changes in figure 14-50 while s1 is open, disconnecting the internal ci rcuitry from the external circuitry. assume that th e initial voltage across c f is zero. as c f charges, the voltage across it is determined by the following equation, where t is the total charge time: as t approaches infinity, v cf will equal v src . (this assumes no internal leak age.) with 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. assuming worst case (v src = full scale), table 14-25 shows the require d time for c f to charge to within 1/ 2 of a count of the actual source voltage during 10-bit conversions. table 14-25 is based on the rc network in figure 14-50 . note the following times are completely independent of the a/d converter architecture (assuming the qadc64e is not affecting the charging). the external circuit described in table 14-25 is a low-pass filter. a user in terested in measuring an ac component of the external signal must take the characteristics of this filter into account. 14.6.5.3 error resulting from leakage a series resistor limits the current to a signal, therefore input leakage acting through a large source impedance can degrade a/d accuracy. the maxi mum input leakage current is specified in appendix f, ?electrical characteristics .? input leakage is greate r at higher operating temper atures. in the temperature range from 125 c to 50 c, the leakage current is halved for every 8 ? 12 c reduction in temperature. assuming v rh ? v rl = 5.12 v, one count (assuming 10-bit reso lution) corresponds to 5 mv of input voltage. a typical input leakag e of 200 na acting through 10 k ? of external series resistance results in an error of 0.4 count (2.0 mv). if the source impedance is 100 k ? and a typical leakage of 100 na is present, an error of two counts (10 mv) is introduced. in addition to internal junction leakage, external leakage (e.g., if external cl amping diodes are used) and charge sharing effects with internal capacitors also contribute to the total leakage current. table 14-26 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. the error is listed in terms of 10-bit counts. table 14-25. external circuit settling time to 1/2 lsb (10-bit conversions) filter capacitor (cf) source resistance (r f + r src ) 100 ? 1 k ? 10 k ? 100 k ? 1 f 760 s 7.6 ms 76 ms 760 ms .1 f76 s 760 s 7.6 ms 76 ms .01 f7.6 s76 s 760 s 7.6 ms .001 f 760 ns 7.6 s76 s 760 s 100 pf 76 ns 760 ns 7.6 s76 s qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-74 freescale semiconductor warning leakage from the part below 200 na is obtainable only within a limited temperature range. 14.6.5.4 accommodating positive /negative stress conditions positive or negative stress refers to conditions which exceed nominally defined operating limits. examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ranges) or causing currents into or out of the signal which exceed normal limits. qadc64e specific considerat ions are voltages greater than v dda , v rh or less than v ssa applied to an analog input which cause excessive currents into or out of the input. refer to appendix f, ?electrical characteristics ,? to for more information on exact magnitudes. either stress condition can potentially disrupt conversion results on neighboring inputs. parasitic devices, associated with cmos processes, can cause an im mediate disruptive influen ce on neighboring signals. common examples of parasitic device s are diodes to substrate and bipolar devices with the base terminal tied to substrate (v ssi /v ssa ground). under stress conditions, curren t injected on an adjacent signal can cause errors on the selected channel by devel oping a voltage drop across the selected channel?s impedances. figure 14-52 shows an active parasitic bipolar npn transistor when an input signal is subjected to negative stress conditions. figure 14-53 shows positive stress conditions ca n activate a similar pnp transistor. figure 14-52. input signal subj ected to negative stress table 14-26. error resulting from input leakage (ioff) source impedance leakage value (10-bit conversions) 100 na 200 na 500 na 1000 na 1 k ? ? ? 0.1 counts 0.2 counts 10 k ? 0.2 counts 0.4 counts 1 counts 2 counts 100 k ? 2 counts 4 count 10 counts 20 counts qadc64e par r stress r selected adjacent 10k signal under parasitic i injn i in + stress v stress device signal v in ann ann+1 qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 14-75 figure 14-53. input signal subj ected to positive stress the current into the signal (i injn or i injp ) under negative or positive stress is determined by the following equations: eqn. 14-1 eqn. 14-2 where: v stress = adjustable voltage source v eb = parasitic pnp emitter/base voltage (refer to v negclamp in appendix f, ?electrical characteristics ?) v be = parasitic npn base/emitter voltage (refer to v negclamp in appendix f, ?electrical characteristics ?)) r stress = source impedance (10- k ? resistor in figure 14-52 and figure 14-53 on stressed channel) r selected = source impedance on channel selected for conversion the current into (i in ) the neighboring signal is determined by the k n (current couplin g ratio) of the parasitic bipolar transistor (k n << 1). the i in can be expressed by the following equation: i in = - k n * i inj where i inj is either i injn or i injp . a method for minimizing the impact of stress conditi ons on the qadc64e is to strategically allocate qadc64e inputs so that the lower a ccuracy inputs are adjacent to the inputs most likely to see stress conditions. also, suitable source impedances shoul d be selected to meet design goals and minimize the effect of stress conditions. qadc64e par r stress r selected 10k parasitic i injp i in + v stress device v in v dda an n an n+1 signal under stress adjacent signal i injn v stress v be ? () ? r stress ------------------------------------------------------ = i injp v stress v eb ? v dda ? r stress --------------------------------------------------------------------- - = qadc64e enhanced mode operation mpc561/mpc563 reference manual, rev. 1.2 14-76 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-1 chapter 15 queued serial multi-channel module the mpc561/mpc563 contains one queued serial multi-channel module (qsmcm). the qsmcm provides three serial co mmunication interfaces: the queued serial peripheral interface (qspi) and two serial communications in terfaces (sci/uart). these submodules communicate with the cpu via a common slave bus interface unit (sbiu). the qspi is a full-duplex, synchronous serial inte rface for communicating with peripherals and other mcus. it is enhanced from the original spi in the qsmcm (queued serial module) to include a total of 160 bytes of queue ram to accom modate more receive, transm it, and control information. the duplicate, independent scis ar e full-duplex universal asynchronous receiver tran smitter (uart) serial interface. the original qsm sci is enhanced by the addition of an sci, a common external baud clock source, receive and transmit buf fers on one sci. the scis are full y compatible with the sci systems found on other freescale mcus. the dual, independen t sci, dsci, submodule is used to communicate with external devices and other mcus via an asynchronous serial bus. the dsci ha s all of the capabilities of previous sci systems as well as several significant new features. the following paragraphs describe the features, pins, programming model (m emory map), registers, and the tr ansmit and receive operations of the dsci. the sbiu provides an interface between the qsmcm module and the intermodule bus (imb3). 15.1 block diagram figure 15-1 shows the major components of the qsmcm. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-2 freescale semiconductor figure 15-1. qsmcm block diagram 15.2 key features standard spi features are listed be low, followed by a list of the addi tional features offered on the qspi: ? full-duplex, three-wire synchronous transfers ? half-duplex, two-wire synchronous transfers ? master or slave operation on the spi bus ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? master-master mode fault flag ? easily interfaces to simple expansion parts (a /d converters, eeproms, display drivers, etc.) qspi-enhanced features are as follows: ? programmable queue ? up to 32 preprogrammed transfers ? programmable peripheral chip-selects ? f our pins select up to 16 spi chips ? wraparound transfer mode ? for autoscanning of serial a/d (or other) peripherals, with no cpu overhead ? programmable transfer length ? from 8?16 bits inclusive port qs sbiu imb3* qspi miso/qgpio4 sck/qgpio6 txd1/qgpo1 txd2/qgpo2 rxd1/qgpi1 rxd2/qgpi2 7 qspi queue ram note: sbiu bus and interface to imb3 are each 16 bits wide. pcs3/qgpio3 2 2 dsci sci2 pcs2/qgpio2 mosi/qgpio5 pcs1/qgpio1 pcs0/ss/qgpio0 sci1 receive and transmit queue sbiu bus dsci queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-3 ? programmable transfer delay ? fr om 0.6 s to 0.3 s (at 28 mhz) ? programmable queue pointer ? continuous transfer mode ? up to 256 bits ? optional on-chip expanded qspi chip selects standard sci features are listed below, foll owed by a list of additional features offered. standard sci two-wire system features: ? standard nonreturn-to-zer o (nrz) mark/space format ? advanced error detection mechanism (detects noise duration up to 1/16 of a bit-time) ? full-duplex operation ? software selectable word length (8- or 9-bit words) ? separate transmitter and receiver enable bits ? may be interrupt driven ? four separate interrupt enable bits ? two independent operating sci modules standard sci receiver features: ? receiver wakeup function (i dle or address mark bit) ? idle-line detect ? framing, noise, and overrun error detect ? receive data register full flag standard sci transmitter features: ? transmit data register empty flag ? transmit complete flag ? send break qsmcm-additional sci features: ? 13-bit programmable baud-rate modulus counter ? even/odd parity generation and detection ? two idle-line detect modes ? receiver active flag qsmcm-enhanced sci features: ? 16 register receive buffer on one sci ? 16 register transmit buffer on one sci 15.2.1 mpc561/mpc563 qsmcm details the qsmcm module has an id entical function to the mpc555. the mu xing of the pins is controlled by the qpapcs3 bit in the qsmcm pi n assignment register (pqspar). queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-4 freescale semiconductor 15.3 memory maps the qsmcm memory maps, shown in table 15-1 and table 15-2 , includes the global re gisters, the qspi and dual sci control and status re gisters, and the qspi ram. the qsmcm memory map can be divided into supervisor-only data space and assignable data sp ace. the address offsets shown are from the base address of the qsmcm module. refer to figure 1-4 for a diagram of the mpc561/mpc563 internal memory map. table 15-1. qsmcm register map access 1 address msb 2 0 lsb 15 s 0x30 5000 qsmcm module configuration register (qsmcmmcr) see table 15-7 for bit descriptions. t 0x30 5002 qsmcm test register (qtest) s 0x30 5004 dual sci interrupt level (qdsci_il) see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-5 the supervisor-only data space se gment contains the qsmcm global re gisters. these registers define parameters needed by the qsmcm to integrate with the mcu. access to these registers is permitted only when the cpu is operating in supervisor mode. assignable data space ca n be either restricted to supervisor-onl y access or unrestricte d to both supervisor and user accesses. the supervisor (supv) bit in the qsmcm module configuration register (qsmcmmcr) designates the assignable data space as ei ther supervisor or unrestr icted. if supv is set, then the space is designated as supervisor-only sp ace. access is then permitted only when the cpu is operating in supervisor mode. if supv is clear, both user and supervisor accesses are perm itted. to clear supv, the cpu must be in supervisor mode. the qsmcm assignable data space segment contains the control and status regist ers for the qspi and sci submodules, as well as the qspi ram. all register s and ram can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries. word accesses require two consecutive imb3 bus cycles. s/u 0x30 5020 sci2 control register 0 (scc2r0) s/u 0x30 5022 sci2 control register 1 (scc2r1) s/u 0x30 5024 sci2 status register (sc2sr) s/u 0x30 5026 sci2 data register (sc2dr) s/u 0x30 5028 qsci1 control register (qsci1cr) see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-6 freescale semiconductor 15.4 qsmcm global registers the qsmcm global registers contain system parameters used by the qspi and dual sci submodules for interfacing to the cpu and the intermodule bus. the global registers are listed in table 15-2 . 15.4.1 low-power stop operation when the stop bit in qsmcmmcr is set, the imb3 clock input to the qsmcm is disabled and the module enters a low-power operating state. qsmcmmcr is the only register guaranteed to be readable while stop is asserted. the qspi ram is not readable in low-power stop mode. however, writes to ram or any register are guaranteed valid while stop is asserted. stop can be written by the cp u and is cleared by reset. system software must bring each submodule to an orderly stop before setting stop to avoid data corruption. the sci receiver and tran smitter should be disabled after tr ansfers in progress are complete. the qspi can be halted by setting the halt bit in spcr3 and then setting stop after the halta flag is set in spsr. 15.4.2 freeze operation the frz1 bit in qsmcmmcr determines how th e qsmcm responds when the imb3 freeze signal is asserted. freeze is asserted when the cpu enters background de bug mode. setting frz1 causes the qspi to halt on the first transfer boundary fo llowing freeze assertion. fr eeze causes the sci1 transmit queue to halt on the first tr ansfer boundary following freeze assertion. 15.4.3 access protection the supv bit in the qmcr defines th e assignable qsmcm registers as ei ther supervisor-only data space or unrestricted data space. when the supv bit is set, all regi sters in the qsmcm are placed in supervisor-only space. for any access from within user mode, the imb3 address acknowledge (aack ) signal is asserted and a bus error is generated. table 15-2. qsmcm global registers access 1 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). address msb 2 0 2 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries. lsb 15 s 0x30 5000 qsmcm module configuration register (qsmcmmcr) see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-7 because the qsmcm contains a mix of supervisor and user registers, aack is asserted for either supervisor or user mode accesses, and the bus cycle remains internal. if a supervisor-only register is accessed in user mode, the module responds as if an access had been made to an unauthorized register location, and a bus error is generated. 15.4.4 qsmcm interrupts the interrupt structure of the imb3 supports a total of 32 interrupt levels that are time multiplexed on the irqb [0:7] lines as seen in figure 15-2 . figure 15-2. qsmcm interrupt levels in this structure, all interrupt sources place their asserted level on a time mult iplexed bus during four different time slots, with eight le vels communicated per slot. the il bs[0:1] signals indicate which group of eight are being driven on the interrupt request lines. the qsmcm module is capable of generating one of the 32 possible interrupt levels on the imb3. the levels that the interrupt will drive can be progr ammed into the interrupt request level (ildsci and ilqspi) bits located in the inte rrupt configuration re gister (qdsci_il and qspi_il). this value determines which interrupt signal (irqb [0:7]) is driven onto the bus during the programmed time slot. figure 15-3 shows a block diagram of the interrupt hardware. table 15-3. interrupt levels ilbs[0:1] levels 00 0:7 01 8:15 10 16:23 11 24:31 imb3 clock ilbs[0:1] imb3 irq[7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-8 freescale semiconductor figure 15-3. interrupt hardware block diagram 15.4.5 qspi interrupt generation 15.4.6 qsmcm configuration register (qsmcmmcr) the qsmcmmcr contains parameters for interfacing to the cpu and the intermodule bus. this register can be modified only when the cpu is in supervisor mode. msb 0 1 234567 8 91011121314 lsb 15 field stop frz1 ? supv ? sreset 0 0 00_0000 1 000_0000 addr 0x30 5000 figure 15-4. qsmcm configur ation register (qsmcmmcr) irq[7:0] interrupt level encoder ilbs[0:1] sci1 and 2 int qspi[4:0] int lev reg. [4:0] 2 lev reg. [4:0] 5 5 sci_1 interrupt sci_2 interrupt qspi interrupt 8 interrupt level decoder 8 8 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-9 15.4.7 qsmcm test register (qtest) the qtest register is used fo r factory testing of the mcu. 15.4.8 qsmcm interrupt level registers (qdsci_il, qspi_il) the qdsci_ili and qspi_il register s determine the interrupt level requested by the qsmcm. the two sci submodules (dsci) share a 5-bi t interrupt level field, ildsci. th e qspi uses a separate field, ilqspi. the level value is used to determine which interrupt is serviced first when two or more modules or external peripherals simultane ously request an interrupt. the user can select among 32 levels. this register can be accessed only when the cpu is in supervisor mode. table 15-4. qsmcmm cr bit descriptions bits name description 0 stop stop enable. refer to section 15.4.1, ?low-p ower stop operation .? 0 normal clock operation 1 internal clocks stopped 1 frz1 freeze1 bit. refer to section 15.4.2, ?freeze operation .? 0 ignore the freeze signal 1 halt the qsmcm (on transfer boundary) 2:7 ? reserved 8 supv supervisor / unrestricted. refer to section 15.4.3, ?access protection .? 0 assigned registers are unrestricted (user access allowed) 1 assigned registers are restricted (only supervisor access allowed) 9:11 ? reserved 12:15 ? reserved. these bits are used for the ia rb (interrupt arbitration id) field in qsm implementations that use har dware interrupt arbitration. msb 0 1 234567891011121314 lsb 15 field ? ildsci ? sreset 0000_0000_0000_0000 addr 0x30 5004 figure 15-5. qsm2 dual sci interrupt level register (qdsci_il) table 15-5. qdsci_il bit descriptions bits name description 0:2 ? reserved 3:7 ildsci interrupt level of dual scis 00000lowest interrupt level request (level 0) 11111highest interrupt level request (level 31) 8:15 ? reserved queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-10 freescale semiconductor 15.5 qsmcm pin control registers table 15-7 lists the three qsmcm pin control registers. the qsmcm uses 11 pins. these pins, when not being used by the serial sub-systems, form a parallel port on the mcu. the port qs pin assignment register (pqspar) governs the usage of qspi pins. clearing a bit assigns the corresponding pin to general- purpose i/o; setting a bit as signs the pin to the qspi. pqspar does not affect opera tion of the sci. when the scix transmitter is disabl ed, txdx is a discrete output; when the scix receiv er is disabled, rxdx is a discrete input. when the scix transmitter or receiver is enabled, the associated txdx or rxdx pin is assigned its sci function. the port qs data direction register (ddrqs) dete rmines whether qspi pins are inputs or outputs. clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. ddrqs affects both qspi function and i/o function. table 15-8 summarizes the effect of ddrqs bits on qspi pin function. ddrqs does not affect sci pin function. txdx pins are always outputs, and rxdx pins are always inputs, regardless of whether they are func tioning as sci pins or as portqs pins. msb 0 1234567891011121314 lsb 15 field ? ilqspi sreset 0000_0000_0000_0000 addr 0x30 5006 figure 15-6. qspi_il ? qspi interrupt level register table 15-6. qspi_il bit descriptions bits name description 0:10 ? reserved 11:15 ilqspi interrupt level of spi 00000lowest interrupt level request (level 0) 11111highest interrupt level request (level 31) table 15-7. qsmcm pin control registers address register 0x30 5014 qsmcm port data register (portqs) see section 15.5.1, ?port qs data re gister (portqs) for bit descriptions. 0x30 5016 portqs pin assignment register (pqspar) see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-11 the port qs data register (portqs) latches i/o data. portqs writes drive pins defined as outputs. portqs reads return data present on the pins. to avoid driving undefi ned data, write the first data to portqs before configuring ddrqs. 15.5.1 port qs data register (portqs) portqs determines the actual input or output valu e of a qsmcm port pin if the pin is defined as general-purpose input or output. all qsmcm pins can be used as gene ral-purpose input and/or output. when the scix transmitter is disabled, txdx is a discrete output; when the scix receiver is disabled, rxdx is a discrete input. writes to this register aff ect the pins defined as output s; reads of this register return the actual value of the pins. note the portqs register can be written eith er as a half-word (16-bit) or as 2 individual bytes (8-bit). this allows the sci gpio pin data to written separately than the qspi gpio pin valu es. this allows either the sci pins or the qspi pins to be us ed independently as gpio. table 15-8. effect of dd rqs on qspi pin function qsmcm pin mode ddrqs bit bit state pin function miso master ddqs0 0 serial data input to qspi 1 disables data input slave 0 disables data output 1 serial data output from qspi mosi master ddqs1 0 disables data output 1 serial data output from qspi slave 0 serial data input to qspi 1 disables data input sck 1 1 sck/qgpio6 is a digital i/o pin unless the spi is enabled (spe set in spcr1), in which case it becomes the qspi serial clock sck. master ddqs2 ? clock output from qspi slave ? clock input to qspi pcs0/ss master ddqs3 0 assertion causes mode fault 1 chip-select output slave 0 qspi slave select input 1 disables slave select input pcs[1:3] master ddqs[4:6] 0 disables chip-select output 1 chip-select output slave 0 inactive 1 inactive queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-12 freescale semiconductor 15.5.2 portqs pin assignment register (pqspar) pqspar determines which of the q spi pins, with the exception of the sck pin, are used by the qspi submodule, and which pins are avai lable for general-purpose i/o. pins may be assigned on a pin-by-pin basis. if the qspi is disabled, the sck pin is automatically assi gned its general-purpose i/o function (qgpio6). qspi pins designated by pqspar as general-purpos e i/o pins are controlled only by pqsddr and pqspdr; the qspi has no effect on these pins. pqspar does not affect the operation of the sci submodule. table 15-9 summarizes the qsmcm pin functions. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ? qdr xd2 qdt xd2 qdr xd1 qdt xd1 0qdp cs3 qdp cs2 qdp cs1 qdpc s0 qds ck qdm osi qdm iso sreset 0000 01010000 0000 addr 0x30 5014 figure 15-7. portqs ? port qs data register table 15-9. qsmcm pin functions portqs function qsmcm function alternate function qgpi2 rxd2 c_cnrx0 qgpo2 txd2 c_cntx0 qgpi1 rxd1 ? qgpo1 txd1 ? qgpio6 sck ? qgpio5 mosi ? qgpio4 miso ? qgpio3 pcs3 ? qgpio2 pcs2 ? qgpio1 pcs1 ? qgpio0 pcs0 ? queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-13 15.5.3 portqs data dire ction register (ddrqs) ddrqs assigns qspi pin as an input or an output regardless of whet her the qspi submodule is enabled or disabled. all qspi pins are configured during rese t as general-purpose inputs. this register does not af fect sci operation. the txd1 and txd2 remain output pinsdedicated to the sci submodules, and the rxd1and rxd2 pins remain input pins dedi cated to the sci submodules. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ? qpapc s3 qpapc s2 qpapc s1 qpapc s0 ? qpamosi qpamiso ddrqs* sreset 0000_0000_0000_0000 addr 0x30 5016 note: see bit descriptions in table 15-11 figure 15-8. portqs pin as signment register (pqspar) table 15-10. pqspar bit descriptions bits name description 0?reserved 1 qpapcs3 0 pin is assigned qgpio3 1 pin is assigned pcs3 function 2 qpapcs2 0 pin is assigned qgpio2 1 pin is assigned pcs2 function 3 qpapcs1 0 pin is assigned qgpio3 1 pin is assigned pcs1 function 4 qpapcs0 0 pin is assigned qgpio0 1 pin is assigned pcs0 function 5?reserved 6 qpamosi 0 pin is assigned qgpio5 1 pin is assigned mosi function 7 qpamiso 0 pin is assigned qgpio4 1 pin is assigned miso function 8:15 ddrqs porstqs data direction register. see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-14 freescale semiconductor 15.6 queued serial peripheral interface the queued serial peripheral interf ace (qspi) is used to communicat e with external devices through a synchronous serial bus. the qspi is fully compatible with spi systems found on other freescale products, but has enhanced capabilities. the qspi can perform full duplex three-wire or half duplex two-wire transfers. several transfer rate s, clocking, and interrupt-driven co mmunication options are available. figure 15-10 is a block diagram of the qspi. msb 0 1234567 8 9 10 11 12 13 14 lsb 15 field pqspar* ? qddp cs3 qddp cs2 qddp cs1 qddp cs0 qddsck qddmosi qddmiso sreset 0000_0000_0000_0000 addr 0x30 5016 note: see bit descriptions in table 15-10 figure 15-9. portqs data direction register (ddrqs) table 15-11. ddrqs bit descriptions bits name description 0:7 pqspar portsqs pin assignment register. see section 15.5.2, ?portqs pin assignment register (pqspar) .? 8?reserved 9 qddpcs3 qspi pin data direction for the pin pcs3 0 pin direction is input 1 pin direction is output 10 qddpcs2 qspi pin data direction for the pin pcs2 0 pin direction is input 1 pin direction is output 11 qddpcs1 qspi pin data direction for the pin pcs1 0 pin direction is input 1 pin direction is output 12 qddpcs0 qspi pin data direction for the pin pcs0 0 pin direction is input 1 pin direction is output 13 qddsck qspi pin data direction for the pin sck 0 pin direction is input 1 pin direction is output 14 qpdmosi qspi pin data direction for the pin mosi 0 pin direction is input 1 pin direction is output 15 qpdmiso qspi pin data direction for the pin miso 0 pin direction is input 1 pin direction is output queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-15 figure 15-10. qspi block diagram serial transfers of eight to 16 bits can be specified. programmable transf er length simplifies interfacing to devices that require di fferent data lengths. an inter-transfer delay of approximately 0.8 to 204 s (using a 40-mhz imb3 clock) can be programmed. the default delay is 17 clocks (0.425 s at 40 mhz) . programmable delay simpli fies the interface to devices that require differen t delays between transfers. qspi block control registers end queue pointer queue pointer status register delay counter comparator programmable logic array 160-byte qspi ram chip select command done 4 4 2 baud rate generator pcs[2:1] pcs0/ss miso mosi sck m s m s 8/16-bit shift register rx / tx data register msb lsb 4 4 queue control block control logic a d d r e s s r e g i s t e r tx data rx data queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-16 freescale semiconductor a dedicated 160-byte ram is used to store received data, data to be transmitted, and a queue of commands. the cpu can access these loca tions directly. this allows serial peripherals to be treated like memory-mapped parallel devices. the command queue allows the qspi to perform up to 32 serial transfers wit hout cpu intervention. each queue entry contains all the informat ion needed by the qspi to independent ly complete one serial transfer. a pointer identifies the queue locat ion containing the data and comma nd for the next serial transfer. normally, the pointer address is incr emented after each serial transfer, but the cpu can change the pointer value at any time. support for multiple-tasks can be provided by segmenting the queue. the qspi has four peripheral chip-select pins. the chip-select signals simpli fy interfacing by reducing cpu intervention. if the chip-select signals are extern ally decoded, 16 independent select signals can be generated. wrap-around mode allows cont inuous execution of queued comma nds. in wraparound mode, newly received data replaces previously r eceived data in the receive ram. wr ap-around mode can simplify the interface with a/d converters by continuously updating conversion values stored in the ram. continuous transfer mode allows transfer of an uni nterrupted bit stream. from 8 to 512 bits can be transferred without cpu interventi on. longer transfers are possible, bu t minimal intervention is required to prevent loss of data. a standard delay of 17 imb3 clocks (0.8 s with a 40-mhz imb3 cloc k) is inserted between the transfer of each queue entry. 15.6.1 qspi registers the qspi memory map, shown in table 15-12 , includes the qsmcm global and pin control regi sters, four qspi control registers (spc r[0:3]), the status regi ster (spsr), and the qspi ram. registers and ram can be read and written by the cpu. the memory map can be divided into supervisor-only data space and assignable data space. the address offsets shown are from the base address of the qsmcm module. refer to figure 1-4 for a diagram of the mpc561/mpc563 internal memory map. table 15-12. qspi register map access 1 address msb 2 0 lsb 15 s/u 0x30 5018 qspi control register 0 (spcr0) see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-17 to ensure proper operation, se t the qspi enable bit (spe) in spcr1 only after initializi ng the other control registers. setting this bit starts the qspi. rewriting the same value to a contro l register does not affect qspi ope ration with the exception of writing newqp in spcr2. rewriting the same value to thes e bits causes the ram que ue pointer to restart execution at the designated location. before changing control bits, the qspi should be halte d. writing a different value into a control register other than spcr2 while the qspi is enabled may disrupt operation. spcr2 is buffered, preventing any disruption of the current serial tran sfer. after the current serial transf er is completed, the new spcr2 value becomes effective. 15.6.1.1 qspi control register 0 (spcr0) spcr0 contains parameters for configuring the qspi be fore it is enabled. the cpu has read/write access to spcr0, but the qspi has read access only. spcr0 mu st be initialized before qspi operation begins. writing a new value to spcr0 while the qspi is enableddisrupts operation. s/u 0x30 5180 ? 0x30 51bf transmit data ram (32 half-words) s/u 0x30 51c0 ? 0x30 51df command ram (32 bytes) 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). 2 eight-bit registers, such as spcr3 and spsr, are on 8-bit boundaries. 16-bit registers such as spcr0 are on 16-bit boundaries. msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field mstr womq bits cpol cpha spbr sreset 0 0 0000 0 1 0000_0100 addr 0x30 5018 figure 15-11. qspi control register 0 (spcr0) table 15-12. qspi register map (continued) access 1 address msb 2 0 lsb 15 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-18 freescale semiconductor table 15-13. spcr0 bit descriptions bits name description 0 mstr master/slave mode select 0 qspi is a slave device and only responds to externally generated serial transfers. 1 qspi is the system master and can initia te transmission to external spi devices. 1 womq wired-or mode for qspi pins. this bit contro ls the qspi pins regardless of whether they are used as general-purpose outputs or as qspi outputs, and regardless of whether the qspi is enabled or disabled. 0 pins designated for output by ddrqs operate in normal mode. 1 pins designated for output by ddrqs operate in open drain mode. 2:5 bits bits per transfer. in mast er mode, when bitse is set in a command ram byte, bits determines the number of data bits transferred. when bitse is cleared, eight bits are transferred regardless of the value in bits. in slave mode, the bits fiel d always determines the number of bits the qspi will receive during each transfer before storing the received data. data transfers from 8 to 16 bits are support ed. illegal (reserved) values default to eight bits. table 15-14 shows the number of bits per transfer. 6 cpol clock polarity. cpol is used to determine the i nactive state of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship betwe en master and slave devices. 0 the inactive state of sck is logic zero. 1 the inactive state of sck is logic one. 7 cpha clock phase. cpha determines which edge of sck causes data to change and which edge causes data to be captured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. 0 data is captured on the leading edge of sck and changed on the trailing edge of sck. 1 data is changed on the leading edge of sck and captured on the trailing edge of sck 8:15 spbr serial clock baud rate. the qspi uses a modu lus counter to derive th e sck baud rate from the mcu imb3 clock. baud rate is selected by writ ing a value from 2 to 25 5 into spbr. the following equation determines the sck baud rate: refer to section 15.6.5.2, ?baud rate selection ? for more information. table 15-14. bits per transfer bits[3:0] bits per transfer 0000 16 0001 to 0111 reserved (defaults to 8) 1000 8 1001 9 1010 10 sck baud rate f sys 2spbr -------------------------- - = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-19 15.6.1.2 qspi control register 1 (spcr1) spcr1 enables the qspi and specifie s transfer delays. the cpu has read /write access to spcr1, but the qspi has read access only to all bits except spe. spcr1 must be writte n last during initi alization because it contains spe. the qspi automatically clears this bit after it completes all serial transfer s or when a mode fault occurs. writing a new value to spcr1 while the qspi is enabled disrupts operation. 1011 11 1100 12 1101 13 1110 14 1111 15 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field spe dsckl dtl sreset 0 000_0100 0000_0100 addr 0x30 501a figure 15-12. spcr1 ? q spi control register table 15-15. spcr1 bit descriptions bits name description 0 spe qspi enable. refer to section 15.6.4.1, ?enabling, disabling, and halting the spi. 0 = qspi is disabled. qspi pins can be used for general-purpose i/o. 1 = qspi is enabled. pins allocated by pqspar are controlled by the qspi. 1:7 dsckl delay before sck. when the dsck bit is set in a command ram byte, this field determines the length of the delay from pcs valid to sck transition. the following equation determines the actual delay before sck: where dsckl equals is in the range of 1 to 127. refer to section 15.6.5.3, ?delay before transfer for more information. 8:15 dtl length of delay after transfer. when the dt bit is set in a command ram byte, this field determines the length of the delay after a serial transfer. the following equation is used to calculate the delay: where dtl is in the range of 1 to 255. a zero value for dtl causes a delay-after-transfer value of 8192 f sys (204.8 s with a 40-mhz imb3 clock). refer to section 15.6.5.4, ?delay after transfer for more information. table 15-14. bits per transfer (continued) bits[3:0] bits per transfer pcs to sck delay dsckl f sys ------------------- - = delay after transfer 32xdtl f sys ---------------------- - = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-20 freescale semiconductor 15.6.1.3 qspi control register 2 (spcr2) spcr2 contains qspi queue pointers , wraparound mode control bits, and an interrupt enable bit. the cpu has read/write access to spcr2, but the qspi has read access only. writ es to this register are buffered. new spcr2 values become effective only after comp letion of the current serial transfer. rewriting newqp in spcr2 causes execution to restart at th e designated location. reads of spcr2 return the current value of the register, not the buffer. 15.6.1.4 qspi control register 3 (spcr3) spcr3 contains the loop mode enable bit, halt and m ode fault interrupt enable, and the halt control bit. the cpu has read/write access to spcr3, but the qspi has read access only. spcr3 must be initialized before qspi operation begi ns. writing a new value to spcr3 while the qspi is enabled disrupts operation. msb 0 1 2 34567 8 9 1011121314 lsb 15 field spifie wren wrto endqp ? newqp sreset 0000_0000_0000_0000 addr 0x30 501c figure 15-13. spcr2 ? qspi control register 2 table 15-16. spcr2 bit descriptions bits name description 0 spifie spi finished interrupt enable. refer to section 15.6.4.2, ?qspi interrupts .? 0 qspi interrupts disabled 1 qspi interrupts enabled 1 wren wrap enable. refer to section 15.6.5.8, ?master wraparound mode .? 0 wraparound mode disabled. 1 wraparound mode enabled. 2 wrto wrap to. when wraparound mode is enabled and after the end of queue has been reached, wrto determines which address the qspi execut es next. the end of queue is determined by an address match with endqp. 0 wrap to pointer address 0x0 1 wrap to address in newqp 3:7 endqp ending queue pointer. this field determines the last absolute address in the queue to be completed by the qspi. after completing each command, the qspi compares the queue pointer value of the just-completed command with the valu e of endqp. if the two values match, the qspi sets spif to indicate it has reached the end of the programmed queue. refer to section 15.6.4, ?qspi operation ? for more information. 8:10 ? reserved 11:15 newqp new queue pointer value. this field co ntains the first qspi queue address. refer to section 15.6.4, ?qspi operation ? for more information. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-21 15.6.1.5 qspi status register (spsr) the spsr contains information concer ning the current serial transmission. only the qspi can set bits in this register. to clear status flags, the cpu reads spsr with the flags set and then writes the spsr with zeros in the appropriate bits. wr ites to cptqp have no effect. msb 01234 5 6 7 891011121314 lsb 15 field ? loopq hmie halt spsr* sreset 0000_0000_0000_0000 addr 0x30 501e note: see bit descriptions in table 15-18 figure 15-14. spcr3 ? qspi control register 3 table 15-17. spcr3 bit descriptions bits name description 0:4 ? reserved 5 loopq qspi loop mode. loopq controls f eedback on the data serializer for testing. 0 feedback path disabled. 1 feedback path enabled. 6 hmie halta and modf interrupt enable. hmie enables interrupt requests generated by the halta status flag or the modf status flag in spsr. 0 halta and modf interrupts disabled. 1 halta and modf interrupts enabled. 7 halt halt qspi. when halt is set, the qspi stops on a queue boundary. it remains in a defined state from which it can later be restarted. refer to section 15.6.4.1, ?enabling, disabling, and halting the spi .? 0 qspi operates normally. 1 qspi is halted for subsequent restart. 8:15 spsr see table 15-18 for bit descriptions. msb 01234567 8 9 10 11121314 lsb 15 field spcr3 1 spif modf halta cptqp sreset 0000_0000_0000_0000 addr 0x30 501e (spsr) 2 1 see bit descriptions in table 15-17 2 spsr can be accessed as an 8-bit register at location 0x30 501f or 0x30 541f. figure 15-15. qspi status register (spsr) queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-22 freescale semiconductor 15.6.2 qspi ram the qspi contains a 160-byte block of dual-ported static ram that ca n be accessed by both the qspi and the cpu. because of this dual access capability, up to two wait states may be inserted into cpu access time if the qspi is in operation. the size and type of acces s of the qspi ram by the cpu affects the qspi acces s time. the qspi allows byte, half-word, and word accesses. only word acc esses of the ram by the cpu are coherent because these accesses are an indivisible operation. if the cp u makes a coherent access of the qspi ram, the qspi cannot access the qspi ram until the cpu is finished. however, a word or misaligned word access is not coherent because the cpu must break its access of the qspi ram into two parts, which allows the qspi to access the qspi ram betw een the two accesses by the cpu. the ram is divided into three se gments: receive data ram, transm it data ram, and command data ram. receive data is information re ceived from a serial device external to the mcu. transmit data is information stored for transmission to an external device. command data defi nes transfer parameters. figure 15-16 shows ram organization. table 15-18. spsr bit descriptions bits name description 0:7 spcr3 see bit descriptions in table 15-17 . 8 spif qspi finished flag. spif is set after execut ion of the command at the address in endqp in spcr2. if wraparound mode is enabled (wren = 1), the spif is set, after completion of the command defined by endqp, each time the qspi cycles through the queue. 0 qspi is not finished 1 qspi is finished 9 modf mode fault flag. the qspi asserts modf when the qspi is in master mode (mstr = 1) and the ss input pin is negated by an external driver. refer to section 15.6.8, ?mode fault ? for more information. 0 normal operation 1 another spi node requested to become the netwo rk spi master while the qspi was enabled in master mode (ss input taken low). 10 halta halt acknowledge flag. halta is set when the q spi halts in response to setting the halt bit in spcr3. halta is also set when the imb3 freeze signal is asserted, provided the frz1 bit in the qsmcmmcr is set. to prevent undefined operation, no modification should be made to any qspi control registers or ra m while the qspi is halted. if hmie in spcr3 is set the qspi sends interr upt requests to the cpu when halta is asserted. 0 qspi is not halted. 1 qspi is halted 11:15 cptqp completed queue pointer. cptqp points to the last command executed. it is updated when the current command is complete. when the first comm and in a queue is executing, cptqp contains either the reset value 0x0 or a pointer to the last command completed in the previous queue. if the qspi is halted, cptqp may be used to determine which commands have not been executed. the cptqp may also be used to de termine which locations in the receive data segment of the qspi ram contain valid received data. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-23 figure 15-16. qspi ram 15.6.2.1 receive ram data received by the qspi is stored in this segment, to be read by the cpu. data stored in the receive ram is right-justified, (i.e., the least si gnificant bit is always in the right -most bit position within the word regardless of the serial transfer length). unused bits in a receive que ue entry are set to zero by the qspi upon completion of the individual queue entry. the cpu can access the data using byte, half-word, or word addressing. the cptqp value in spsr shows which queue entries ha ve been executed. the cp u uses this information to determine which locations in receive ra m contain valid data before reading them. 15.6.2.2 transmit ram data that is to be transmitted by th e qspi is stored in this segment. the cpu normally writes one word of data into this segment for each que ue command to be executed. if the co rresponding peripheral, such as a serial input port, is used solely to input data, then this segmen t does not need to be initialized. data must be written to transmit ram in a right-justified format. the qspi cannot modify information in the transmit ram. the qspi copies the information to its data serializer fo r transmission. information remains in transmit ram until overwritten. 15.6.2.3 command ram command ram is used by the qspi in master mode. the cpu writes one byte of control information to this segment for each qspi comm and to be executed. the qspi cannot modify information in command ram. command ram consists of 32 bytes. each byte is divided into two fi elds. the peripheral chip-select field, enables peripherals for transfer. the comma nd control field provide s transfer options. a maximum of 32 commands can be in the queue. these bytes are assi gned an address fr om 0x00 to 0x1f. queue execution by the qspi procee ds from the address in newqp th rough the address in endqp. (both of these fields are in spcr2.) receive ram transmit ram 0x30 5140 0x30 517f 0x30 5180 0x30 51bf half-word 0x30 51c0 0x30 51df command ram byte half-word rr0 rr1 rr2 rrd rre rrf tr0 tr1 tr2 trd tre trf cr0 cr1 cr2 crd cre crf or 0x30 5540 or 0x30 557f or 0x30 55c0 or 0x30 55df or 0x30 5580 oe 0x30 55bf queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-24 freescale semiconductor refer to section 15.6.5, ?master mode operation ? for more information on the command ram. 15.6.3 qspi pins seven pins are associated with the qspi. when not needed by the qspi, they can be configured for general-purpose i/o. table 15-20 identifies the qspi pins and their functions. register ddrqs determines whether the pins are designated as input or output. the user must initialize ddrqs for the qspi to function correctly. msb 0123456 lsb 7 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 1 ???????? cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 command control peripheral chip select the pcs0 bit represents the dual-function pcs0/ss. figure 15-17. cr[0:f] ? command ram 0x30 51c0, 0x30 51df table 15-19. command ram bit descriptions bits name description 0contcontinue 0 control of chip selects returned to portqs after transfer is complete. 1 peripheral chip selects remain asserted after transfer is complete. 1 bitse bits per transfer enable 0eight bits 1 number of bits set in bits field of spcr0. 2 dt delay after transfer 0 delay after transfer is 17 f sys . 1 spcr1 dtl[7:0] specifies delay after transfer pcs valid to sck. 3 dsck pcs to sck delay 0 pcs valid to sck delay is one-half sck. 1 spcr1 dsckl[6:0] specifies delay from pcs valid to sck. 4:7 pcs[3:0] peripheral chip selects. use peripheral chip-select bits to select an external device for serial data transfer. more than one peripheral chip select may be activated at a time, and more than one peripheral chip can be connected to each pcs pin, provided proper fanout is observ ed. pcs0 shares a pin with the slave select (ss ) signal, which initiates slave mode se rial transfer. if ss is taken low when the qspi is in master mode, a mode fault occurs. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-25 15.6.4 qspi operation the qspi uses a dedicated 160-byte block of static ram accessible by both th e qspi and the cpu to perform queued operations. the ram is divided in to three segments: 32 command control bytes, 64 transmit data bytes, and 64 receive data bytes. once the cpu has set up a queue of qspi commands, wr itten the transmit data segment with information to be sent, and enabled th e qspi, the qspi operates i ndependently of the cpu. th e qspi executes all of the commands in its queue, sets a flag indicating completion, and then either interrupts the cpu or waits for cpu intervention. qspi ram is organized so that one byte of command data, one word of transmit data, and one word of receive data correspond to each queue entry, 0x0 to 0x2f. the cpu initiates qspi operation by setting up a queue of qspi commands in command ram, writing transmit data into transmit ram, then enabling th e qspi. the qspi executes the queued comm ands, sets a completion flag (spif), and then either interrupts the cpu or waits for intervention. there are four queue pointers. the cpu can access three of them through fields in qspi registers. the new queue pointer (newqp), containe d in spcr2, points to the first co mmand in the queue. an internal queue pointer points to the command currently bei ng executed. the completed queue pointer (cptqp), contained in spsr, points to the last command executed. the end queue pointer (endqp), contained in spcr2, points to the final command in the queue. the internal pointer is initialized to the same value as newqp. during normal operation, the command pointed to by the internal pointer is executed, the value in the internal pointer is copied into cptqp, the internal pointer is incremented, and then the sequence repeats. execution continues at the internal pointer address unless the newqp value is changed. after each command is executed, endqp and cptqp are table 15-20. qspi pin functions pin names mnemonic mode function master in slave out miso master slave serial data input to qspi serial data output from qspi master out slave in mosi master slave serial data output from qspi serial data input to qspi serial clock sck 1 1 all qspi pins (except sck) can be used as general-purpose i/o if they are not used by the qspi while the qspi is operating. sck can only be used for general-purpose i/o if the qspi is disabled. master slave clock output from qspi clock input to qspi peripheral chip selects pcs[1:3] m aster outputs select peripheral(s) peripheral chip select 2 slave select 3 2 an output (pcs0) when the qspi is in master mode. 3 an input (ss ) when the qspi is in slave mode. pcs0 / ss master slave output selects peripheral(s) input selects the qspi slave select 4 4 an input (ss ) when the qspi is in master mo de; useful in multimaster systems. ss master may cause mode fault queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-26 freescale semiconductor compared. when a match occurs, the spif flag is set and the qspi stops and clears spe, unless wraparound mode is enabled. at reset, newqp is initialized to 0x0. when the qspi is enabled, execution begins at queue address 0x0 unless another value has been written into newqp. endqp is initialized to 0x0 at reset but should be changed to the last queue entry before the qspi is enabled. newqp and endq p can be written at any time. when newqp changes, the internal pointer va lue also changes. however, if newqp is written while a transfer is in progress, the transfer is completed normally. leaving newqp and endqp set to 0x0 transfers only the data in transmit ram location 0x0. 15.6.4.1 enabling, disab ling, and halting the spi the spe bit in the spcr1 enables or disables the qs pi submodule. setting spe causes the qspi to begin operation. if the qspi is a master, se tting spe causes the qspi to begin initiating serial transfers. if the qspi is a slave, the qspi begins monitoring the pcs0/ss pin to respond to the exte rnal initialization of a serial transfer. when the qspi is disabl ed, the cpu may use the qspi ram. when the qspi is enabled, both the qspi and the cpu have access to the qspi ram. the cpu has both read and write access to all 160 bytes of the qspi ram. the qspi can read- only the transmit data segment a nd the command control segment and can write-only the receive data segment of the qspi ram. the qspi turns itself off automatical ly when it is finished by cleari ng spe. an error condition called mode fault (modf) also clears spe. this error occurs when pcs0/ss is configured for input, the qspi is a system master (mstr = 1), and pcs0/ss is driven low externally. setting the halt bit in spcr3 stops the qspi on a queue bounda ry. the qspi halts in a known state from which it can later be restarted. when halt is set, th e qspi finishes executing the current serial transfer (up to 16 bits) and then halts. while halted, if the command control bit (cont of the qspi ram) for the last command was asserted, the qspi continues driving the peripheral chip select pins with the value designated by the last command befo re the halt. if cont was cleared, the qspi drives the peripheral chip-select pins to the va lue in register portqs. if halt is set during the last command in the que ue, the qspi completes the last command, sets both halta and spif, and clears spe. if the last queue command has not been executed, asserting halt does not set spif or clear spe. qspi executi on continues when the cpu clears halt. to stop the qspi, assert the halt bit in spcr3, then wait until the halta bit in spsr is set. spe can then be safely cleared, providing an orderly method of shutting down the qspi quickly after the current serial transfer is completed. the cpu can disable the qspi immediat ely by clearing spe. however, loss of data from a current serial transfer may result and conf use an external spi device. 15.6.4.2 qspi interrupts the qspi has three possible interr upt sources but only one interrupt vector. these sources are spif, modf, and halta. when the cpu re sponds to a qspi interrupt, the in terrupt cause must ascertained by reading the spsr. any interrupt that was set may then be cleared by writing to sps r with a zero in the bit position corresponding to the interrupt source. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-27 the spifie bit in spcr2 enables the qspi to genera te an interrupt request upon assertion of the spif status flag. because it is buffered, the value written to spifie applies only upon comp letion of the queue (the transfer of the entry indicated by endpq). thus , if a single sequence of queue entries is to be transferred (i.e., no wrap), then spifie should be se t to the desired state before the first transfer. if a sub-queue is to be used, the same cpu write that causes a branch to the sub-queue may enable or disable the spif interrupt for the sub-queue. the prim ary queue retains its own selected interrupt mode, either enabled or disabled. the spif interrupt must be cleare d by clearing spif. subsequent in terrupts may then be prevented by clearing spifie. clearing spifie doe s not immediately clear an in terrupt already caused by spif. 15.6.4.3 qspi flow the qspi operates in either master or slave mode. master mode is used when the mcu initiates data transfers. slave mode is used when an external de vice initiates transfers. sw itching between these modes is controlled by mstr in spcr0. before entering either mode, appropriate qsmc m and qspi registers must be initialized properly. in master mode, the qspi executes a queue of commands defined by control bits in each command ram queue entry. chip-select pins are activated, data is transmitted from the transm it ram and received by the receive ram. in slave mode, operation pr oceeds in response to ss pin assertion by an external spi bus master. operation is similar to master mode, but no pe ripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. when the qspi is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. although the qspi inherently suppor ts multi-master operation, no spec ial arbitration mechanism is provided. a mode fault flag (modf) indicates a request for spi master arbitration. system software must provide arbitration. no te that unlike previous spi systems, mstr is not cleared by a mode fault being set nor are the qspi pin output drivers disabled. the qspi and associated output drivers must be disabled by clearing spe in spcr1. figure 15-18 shows qspi initialization. figure 15-19 through figure 15-23 show qspi master and slave operation. the cpu must initialize the qsmcm global a nd pin registers and the qspi control registers before enabling the qspi for either mode of opera tion. the command queue must be written before the qspi is enabled for master mode operation. any data to be transmitted should be written into transmit ram before the qspi is enabled. during wraparound ope ration, data for subsequent transmissions can be written at any time. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-28 freescale semiconductor figure 15-18. flowchart of qspi initialization operation initialize qsmcm global registers initialize qspi control registers initialize pqspar, portqs, and ddrqs initialize qspi ram enable qspi begin a2 qspi initialization mstr = 1 ? a1 y n in this order queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-29 figure 15-19. flowchart of qspi master operation (part 1) read command control and transmit data from ram using queue pointer address a1 working queue pointer changed to newqp is qspi disabled? n y n execute serial transfer store received data in ram using queue pointer address b1 qspi cycle begins (master mode) y assert peripheral chip select(s) is pcs to sck delay programmed? n execute standard delay y execute programmed delay has newqp been written? queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-30 freescale semiconductor figure 15-20. flowchart of qspi master operation (part 2) is delay after transfer asserted? y n execute programmed delay b1 write queue pointer to cptqp status bits c1 negate peripheral chip selects y n is continue bit asserted? execute standard delay queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-31 figure 15-21. flowchart of qspi master operation (part 3) assert spif status flag request interrupt is interrupt enable bit spifie set? is wrap enable bit set? y n reset working queue pointer to newqp or 0x0000 y disable qspi a1 n increment working queue pointer n is halt or freeze asserted? a1 halt qspi and set halta n is interrupt enable bit hmie set? y y n is halt or freeze asserted? c1 y n y is this the last command in the queue? request interrupt queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-32 freescale semiconductor figure 15-22. flowchart of qspi slave operation (part 1) read transmit data from ram using queue pointer address a2 queue pointer changed to newqp n y n write queue pointer to cptqp status bits store received data in ram using queue pointer address b2 qspi cycle bgins (slave mode y execute serial transfer when sck received n y is slave select pin asserted? has newqp been written? is qspi disabled? queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-33 figure 15-23. flowchart of qspi slave operation (part 2) set spif status flag request interrupt is interrupt enable bit spifie set? is wrap enable bit asserted? y n reset working queue pointer to newqp or 0x0000 y disable qspi a2 n increment working queue pointer n is halt or freeze asserted? a2 halt qspi and set halta n is interrupt enable bit hmie set? y y n is halt or freeze asserted? c2 y n y is this the last command in the queue? qspi slv2 flow6 request interrupt queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-34 freescale semiconductor normally, the spi bus performs sync hronous bidirectional transfers. the serial clock on the spi bus master supplies the clock signal sck to time the transfer of data. four possible combinat ions of clock phase and polarity can be specified by the cpha and cpol bits in spcr0. data is transferred with the most significant bit first. the number of bits transferred per command defaults to eight, but can be set to any value from eight to sixteen bits by writing a value into the bits field in spcr0 and setting bitse in command ram. typically, spi bus outputs are not open drain unless multiple spi masters are in the system. if needed, the womq bit in spcr0 can be set to provide wired-or , open drain outputs. an external pull-up resistor should be used on each out put line. womq affects all qspi pins regardless of whether they are assigned to the qspi or used as general-purpose i/o. 15.6.5 master mode operation setting the mstr bit in spcr0 select s master mode operation. in master mode, the qs pi can initiate serial transfers, but cannot respond to externally initiated transfers. when the slave select input of a device configured for master mode is asserted, a mode fault occurs. before qspi operation begins , pqspar must be written to assign the necessary pins to the qspi. the pins necessary for master mode operati on are miso, mosi, sck, and one or more of the chip-select pins. miso is used for serial data input in master mode, and mosi is used fo r serial data output. either or both may be necessary, depending on the part icular application. sck is the seri al clock output in master mode and must be assigned to th e qspi for proper operation. the portqs data register must ne xt be written with values that make the qgpio6/sck (bit 13 qdsck of portqs) and qgpio[3:0]/pcs[3:0] (bits 12:9 qdp cs[3:0] of portqs) outputs inactive when the qspi completes a series of transfers. pins allocat ed to the qspi by pqspar are controlled by portqs when the qspi is inactive. portqs i/o pins driven to states opposite those of the inactive qspi signals can generate glitches that momentarily enable or part ially clock a slave device. for example, if a slave device opera tes with an inactive sck state of l ogic one (cpol = 1) and uses active low peripheral chip-selec t pcs0, the qdsck and qdpcs0 bits in portqs must be set to 0b11. if qdsck and qdpcs0 = 0b00, fall ing edges will appear on qgpio6/sck and gpio 0/pcs0 as the qspi relinquishes control of these pins a nd portqs drives them to logic zer o from the inactive sck and pcs0 states of logic one. before master mode operation is init iated, qsmcm register ddrq s is written last to direct the data flow on the qspi pins used. configure the sck, mosi and appropriate chip-select pi ns pcs[3:0] as outputs. the miso pin must be configured as an input. after pins are assigned and configur ed, write appropriate data to the command queue. if data is to be transmitted, write the data to transmit ram. initialize the queue poin ters as appropriate. qspi operation is initiated by settin g the spe bit in spcr1. shortly afte r spe is set, the qspi executes the command at the command ram addr ess pointed to by newqp. data at the pointer address in transmit ram is loaded into the data serializer and transmitted. data that is simu ltaneously received is stored at the pointer address in receive ram. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-35 when the proper number of bits have been transferre d, the qspi stores the working queue pointer value in cptqp, increments the working que ue pointer, and loads the next data for transfer from transmit ram. the command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to newqp. if a ne w queue pointer value is written while a transfer is in progress, that transfer is completed normally. when the cont bit in a command ram byte is set, pcs pins are conti nuously driven to specified states during and between transfers. if the chip-select pattern changes during or between transfers, the original pattern is driven until execution of the following tran sfer begins. when cont is cleared, the data in register portqs is driven between transfers. the data in portqs must match the inactiv e states of sck and any peripheral chip-selects used. when the qspi reaches the end of the queue, it sets the spif flag. if the spifie bit in spcr2 is set, an interrupt request is generated when spif is asserted. at this point, the qspi clears spe and stops unless wraparound mode is enabled. 15.6.5.1 clock phase and polarity in master mode, data transfer is s ynchronized with the internally-generat ed serial clock sck. control bits, cpha and cpol, in spcr0, control clock phase a nd polarity. combinations of cpha and cpol determine upon which sck edge to drive outgoing data from the mosi pin and to latch incoming data from the miso pin. 15.6.5.2 baud rate selection baud rate is selected by writing a value from two to 255 into the spbr field in spcr0. the qspi uses a modulus counter to derive the sck baud rate from the mcu imb3 clock. the following expressions apply to the sck baud rate: eqn. 15-1 or eqn. 15-2 giving spbr a value of zero or one di sables the baud rate generator. sck is disabled and assumes its inactive state. at reset, the sck baud rate is init ialized to one eighth of the imb3 clock frequency. table 15-21 provides some example sck baud rates with a 40-mhz imb3 clock. table 15-21. example sck frequencies with a 40-mhz imb3 clock division ratio spbr value sck frequency 4 2 10.00 mhz 636.67 mhz 845.00 mhz sck baud rate f sys 2xspbr ---------------------- - = spbr f sys 2xsck baud rate desired ----------------------------------------------------------------------- = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-36 freescale semiconductor 15.6.5.3 delay before transfer the dsck bit in each comm and ram byte inserts either a standard (dsck = 0) or user-specified (dsck = 1) delay from chip-selec t assertion until the leadi ng edge of the serial clock. the dsckl field in spcr1 determines the length of the user-d efined delay before the assertion of sck. the following expression determines the actual delay before sck when dsckl is in the range of 1?127: eqn. 15-3 note a zero value for dsckl causes a delay of 128 imb3 clocks, which equals 3.2 s for a 40-mhz imb3 clock. becaus e of design limits, a dsckl value of one defaults to the same timing as a value of two. when dsck equals zero, dsckl is not used. instea d, the pcs valid-to-sck tr ansition is one-half the sck period. 15.6.5.4 delay after transfer delay after transfer can be used to provide a periphe ral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d c onverters to complete conversion. writing a value to the dtl field in spcr1 specifies a delay period. th e dt bit in each command ram byte determines whether the standard delay period (d t = 0) or the specifie d delay period (dt = 1) is used. the following expression is used to calculate the delay: where dtl is in the range from one to 255. a zero value for dtl causes a de lay-after-transfer value of 8192 imb3 clock frequency (204.8 s with a 40-mhz imb3 clock). if dt is zero in a command ram by te, a standard delay is inserted. 14 7 2.86 mhz 28 14 1.43 mhz 58 29 689 khz 280 140 143 khz 510 255 78.43 khz table 15-21. example sck frequencies with a 40-mhz imb3 clock (continued) division ratio spbr value sck frequency pcs to sck delay dsckl f sys ------------------- - = delay after transfer 32xdtl f sys --------------------- = standard delay after transfer 17 f sys ------------- = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-37 delay after transfer can be used to provide a periphe ral deselect interval. a delay can also be inserted between consecutive transfers to allow seri al a/d converters to complete conversion. adequate delay between transfers mu st be specified for long data str eams because the q spi requires time to load a transmit ram entry for transfer. receiving devices need at least the standard delay between successive transfers. if the imb3 clock is operating at a slower rate, the delay between transfers must be increased proportionately. 15.6.5.5 transfer length there are two transfer length options. the user can choose a default value of eight bits, or a programmed value from eight (0b1000) to 16 ( 0b0000) bits, inclusive. reserved values (from 0b0001 to 0b0111) default to eight bits. the programmed value must be written into the bits fi eld in spcr0. the bitse bit in each command ram byte determin es whether the default value (bitse = 0) or the bits value (bitse = 1) is used. 15.6.5.6 peripheral chip selects peripheral chip-select signals are used to select an external device for serial data transfer. chip-select signals are asserted when a command in the queue is executed. signals are asserted at a logic level corresponding to the value of the pcs[3:0] bits in each command byte. more than one chip-select signal can be asserted at a time, and more than one extern al device can be connected to the pcs pins, provided proper fanout is observed. pcs0 shar es a pin with the slave select ss signal, which initiates slave mode serial transfer. if ss is taken low when the qspi is in master mode, a mode fault occurs. to configure a peripheral chip select , set the appropriate bit in the pqspar, then configure the chip-select pin as an output by setting the appr opriate bit in ddrqs. the value of the bit in portqs that corresponds to the chip-select pin determines the base state of the chip-select signal. if the ba se state is zero, chip-select assertion must be active high (pcs bit in command ram mu st be set); if base stat e is one, assertion must be active low (pcs bit in command ram must be clea red). portqs bits are cl eared during reset. if no new data is written to portqs befo re pin assignment and c onfiguration as an out put, the base state of chip-select signals is zero and chip-select pi ns are configured for active-high operation. 15.6.5.7 optional enhanced peripheral chip selects the mpc561/mpc563 have an optional on-chip decoder fo r the peripheral chip selects. it is enabled if any of the pcs[4:7]en bits are enab led in the pdmcr2 register (see table 2-6 ). the decode translates the normal pcs[0:3] chip selects into a 1 of 8 decode. the polarity of th e new pcs outputs can be selected by the state of the pcsv bit in the pdmcr2. see table 15-22 . table 15-22. pcs enhanced functionality pcs_in[3:0] pcs_out[7:0] if pc sv = 0 pcs_out[7:0] if pcsv = 1 0000 00000001 11111110 0001 00000010 11111101 0010 00000100 11111011 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-38 freescale semiconductor note pcs_in[3:0] is driven from qsmc m module. pcs_out[7:0] will be driven from the pads to the pins. if the bits pcs4en, pcs5en, pcs6en, pcs7en are negated (logic 0), pcs_ out[3:0] will be the same as pcs_in[3:0]. the design assumes that if one of these enable bits is set, pcs function is selected in qsmcm module. 15.6.5.8 master wraparound mode wraparound mode is enabled by setti ng the wren bit in spcr2. the queue can wrap to pointer address 0x0 or to the address pointed to by newqp, depe nding on the state of the wrto bit in spcr2. in wraparound mode, the qspi cycles through the queue continuously, even while the qspi is requesting interrupt service. spe is not cleared when the last command in the queue is executed. new receive data overwrites previously received data in receive ram. each time the end of the queue is reached, the spif flag is set. spif is not automatically reset. if interr upt-driven qspi service is used, the service routine must clear the spif bit to end the current interrupt reque st. additional interrupt re quests during servicing can be prevented by clearing spifie, but spifie is buffered. clearing it does not end the current request. wraparound mode is exited by clearing the wren bi t or by setting the halt bit in spcr3. exiting wraparound mode by clearing sp e is not recommended, as clearing spe may abort a serial transfer in progress. the qspi sets spif, clears spe, and stops th e first time it reaches th e end of the queue after wren is cleared. after halt is set, the qspi finishes the curre nt transfer, then stops executing commands. after the qspi stops, spe can be cleared. 0011 00001000 11110111 0100 00010000 11101111 0101 00100000 11011111 0110 01000000 10111111 0111 10000000 01111111 1000 00000000 11111111 1001 reserved reserved 1010 1011 1100 1101 1110 1111 table 15-22. pcs enhanced functionality (continued) pcs_in[3:0] pcs_out[7:0] if pc sv = 0 pcs_out[7:0] if pcsv = 1 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-39 15.6.6 slave mode clearing the mstr bit in spcr0 selects slave mode operation. in slave mode, the qspi is unable to initiate serial transfers. transfers are initiated by an external spi bus master. slave mode is typically used on a multi-master spi bus . only one device can be bus master (operate in master mode) at any given time. before qspi operation is initiated, qsmcm register pq spar must be written to assign necessary pins to the qspi. the pins necessary for slave mode operation are miso, mosi, sck, and pcs0/ss . miso is used for serial data output in slave mode, and mosi is used for serial data input. either or both may be necessary, depending on the part icular application. sck is the serial clock input in slave mode and must be assigned to the qspi for proper operation. as sertion of the active-low slave select signal ss initiates slave mode operation. before slave mode operation is initiated, ddrqs must be written to direct data flow on the qspi pins used. configure the mosi, sck and pcs0/ss pins as inputs. the miso pi n must be configured as an output. after pins are assigned and configured, write data to be transmitt ed into transmit ram. command ram is not used in slave mode, and does not need to be initialized. set the queue pointers, as appropriate. when spe is set and mstr is clear, a low state on the slave select pcs0/ss pin begins slave mode operation at the address indi cated by newqp. data that is received is stored at the pointer address in receive ram. data is simultaneously loaded into the data serializer from the pointer address in transmit ram and transmitted. transfer is sy nchronized with the externally ge nerated sck. the cpha and cpol bits determine upon which sck edge to latch incoming data from the miso pin and to drive outgoing data from the mosi pin. because the command ram is not used in slave mode, the cont, bitse, dt, dsck, and peripheral chip-select bits have no effect. the pcs0/ss pin is used only as an input. the spbr, dt and dsckl fields in spcr0 and spcr1 bits ar e not used in slave m ode. the qspi drives neither the clock nor the chip-sel ect pins and thus cannot control clock rate or transfer delay. because the bitse option is not ava ilable in slave mode, the bits fi eld in spcr0 specifies the number of bits to be transferred for all transfers in the queue. when the num ber of bits designated by bits[3:0] has been transferred, the qspi stor es the working queue pointer value in cptqp, increments the working queue pointer, and loads new transmit data from transmit ram into the data serializer. the working queue pointer address is used the next time pcs0/ss is asserted, unless the rcpu writes to newqp first. the qspi shifts one bit for each pulse of sc k until the slave select input goes high. if ss goes high before the number of bits specified by the bits field is transferred, the qspi resumes operation at the same pointer address the next time ss is asserted. the maximum value that the bits field can have is 16. if more than 16 bits are transmitted before ss is negated, pointers are increm ented and operation continues. the qspi transmits as many bits as it receives at ea ch queue address, until the bits value is reached or ss is negated. ss does not need to go high between transfers as the qspi transfers da ta until reaching the end of the queue, whether ss remains low or is toggled between transfers. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-40 freescale semiconductor when the qspi reaches the end of the queue, it sets the spif flag. if the spifie bit in spcr2 is set, an interrupt request is generated when spif is asserted. at this point, the qspi clears spe and stops unless wraparound mode is enabled. slave wraparound mode is enabled by setting the wren bit in spcr2. the queue can wrap to pointer address 0x0 or to the address pointed to by newqp, depending on the state of the wrto bit in spcr2. slave wraparound operation is identical to master wraparound operation. 15.6.6.1 description of slave operation after reset, the qsmcm registers a nd the qspi control registers must be initialized as described above. although the command control segmen t is not used, the transmit a nd receive data segments may, depending upon the application, need to be initialized. if meaningf ul data is to be se nt out from the qspi, the data to the transmit data should be writ ten to the segment before enabling the qspi. if spe is set and mstr is not set, a low state on the slave select (pcs0/ss ) pin commences slave mode operation at the address indicated by newqp. the qspi transmits the da ta found in the transmit data segment at the address indicated by ne wqp, and the qspi stores received data in the receive data segment at the ad-dress indicated by newqp. da ta is transferred in re sponse to an external sl ave clock input at the sck pin. because the command control segment is not used, th e command control bits and peripheral chip-select codes have no effect in slave mode operation. the qspi does not drive any of the four peripheral chip-selects as outputs. pcs0/ss is used as an input. although cont cannot be used in slave mode, a provision is made to enable receipt of more than 16 data bits. while keeping the qspi selected (pcs0/ss is held low), the qspi stores the number of bits, designated by bits, in the current receive data segment address, in crements newqp, and continues storing the remaining bits (up to the bits valu e) in the next receive data segment address. as long as pcs0/ss remains low, the qspi continues to store th e incoming bit stream in sequential receive data segment addresses, until either the value in bits is reached or the end-of-queue address is used with wraparound mode disabled. when the end of the queue is reached, the spif flag is asserted, optionally causing an interrupt. if wraparound mode is disabled, any ad ditional incoming bits are ignored. if wraparound mode is enabled, storing continues at either address 0x0 or the address of newqp, depending on the wrto value. when using this capa bility to receive a long incoming data stream, the proper delay between transfers must be used. the qspi requires time , approximately 0.425 s with a 40-mhz imb3 clock, to prefetch the next transmit ram entry for the next transfer. therefore, a baud rate may selected that provides at leas t a 0.6-s delay between successive transfers to ensure no loss of incoming data. if the imb3 clock is operating at a slower rate, the delay between transfers must be increased proportionately. because the bitse option in the co mmand control segment is no longer available, bits sets the number of bits to be transferred for all transfers in the queue until the cp u changes the bits va lue. as mentioned above, until pcs0/ss is negated (brought high), the qspi conti nues to shift one bit fo r each pulse of sck. if pcs0/ss is negated before the proper number of bits ( according to bits) is recei ved, the next time the queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-41 qspi is selected it resumes storing bits in the same r eceive-data segment address wher e it left off. if more than 16 bits are transferred before negating the pcs0/ss , the qspi stores the num ber of bits indicated by bits in the current receive data segment address, th en increments the address and continues storing as described above. note pcs0/ss does not necessarily have to be negated between transfers. once the proper number of bits (desi gnated by bits) are transferred, the qs pi stores the received data in the receive data segment, stores the internal work ing queue pointer value in cptqp, increments the internal working queue pointer, and loads the new tran smit data from the transmit data segment into the data serializer. the internal working queue pointer address is used the next time pcs0/ss is asserted, unless the cpu writes to the newqp first. the dt and dsck command control bits are not used in slave mode. as a slave, the qspi does not drive the clock line nor the chip-select lines and, therefore, does not generate a delay. in slave mode, the qspi shifts out th e data in the transmit data segment. the trans-mit data is loaded into the data seriali zer (refer to figure 15-1 ) for transmission. when the pcs0/ss pin is pulled low the miso pin becomes active and the serializer then shifts the 16 bits of data out in seque nce, most significant bit first, as clocked by the incoming sck signal. the qspi uses cpha and cp ol to determine which incoming sck edge the mosi pin uses to latch incoming data, and which edge the miso pin uses to drive the data out. the qspi transmits and receives data until reaching the end of the queue (defined as a match with the address in endqp), regard less of whether pcs0/ss remains selected or is toggled between serial transfers. receiving the proper number of bits causes the received data to be stored. the qspi always transmits as many bits as it receive s at each queue address, until the bits value is reached or pcs0/ss is negated. 15.6.7 slave wraparound mode when the qspi reaches the end of the queue, it alwa ys sets the spif flag, whether wraparound mode is enabled or disabled. an optional interrupt to the cpu is gen-erated when spif is asserted. at this point, the qspi clears spe and stops unl ess wraparound mode is enabled. a description of spifie bit can be found in queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-42 freescale semiconductor executed again. spe is not cleared by the qspi. new receive data overwrites previously received data located in the receive data segment. wraparound mode is properl y exited in two ways: ? the cpu may disable wrap-around mode by cleari ng wren. the next time end of the queue is reached, the qspi sets spif, clears spe, and stops. ? the cpu sets halt. this second method halts th e qspi after the current transfer is completed, allowing the cpu to negate spe. the cpu ca n immediately stop the qspi by clearing spe; however, this method is not recommended, as it cau ses the qspi to abort a serial transfer in process. 15.6.8 mode fault modf is asserted by the qspi when the qspi is th e serial master (mstr = 1) and the slave select (pcs0/ss ) input pin is pulled low by an external dr iver. this is possible only if the pcs0/ss pin is configured as input by qddr. this low input to ss is not a normal operating c ondition. it indicates that a multimaster system conflict may exist, that a nother mcu is requesting to become the spi network master, or simply that the hardware is incorrectly affecting pcs0/ss . spe in spcr1 is cleared, disabling the qspi. the qspi pins revert to control by qpdr. if modf is set and hmie in spcr3 is asserted, the qspi generates an interrupt to the cpu. the cpu may clear modf by reading spsr with modf asserted, follow ed by writing spsr with a zero in modf. after correcting the mode fault problem , the qspi can be re-e nabled by asserting spe. the pcs0/ss pin may be configured as a ge neral-purpose output instead of input to the qspi. this inhibits the mode fault checking function. in this case, modf is not used by the qspi. 15.7 serial communication interface the dual, independent, serial co mmunication interface (dsc i) communicates with external devices through an asynchronous serial bus. th e two sci modules are functionall y equivalent, except that the sci1 also provides 16-deep queue cap abilities for the transmit and recei ve operations. the scis are fully compatible with other freescale sci systems. the dsci has all of the capabilities of previous sci systems as well as several si gnificant new features. figure 15-24 is a block diagram of the sci transmitter. figure 15-25 is a block diagram of the sci receiver. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-43 figure 15-24. sci transmitter block diagram loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk transmitter control logic pin buffer and control h (8) 76543210l 10 (11)-bit tx shift register txd scxdr tx buffer transfer tx buffer shift enable jam enable preamble?jam 1's break?jam 0's force pin direction (out) size 8/9 parity generator transmitter baud rate clock tc tdre sci rx requests sci interrupt request fe nf or idle rdrf tc tdre scxsr status register pf internal data bus raf tie tcie sccxr1 control register 1 0 15 15 0 start stop open drain output mode enable (write-only) queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-44 freescale semiconductor figure 15-25. sci receiver block diagram 0 loops woms ilt pt pe m wake rie ilie te re rwu sbk tie tcie sccxr1 control register 1 0 15 fe nf or idle rdrf tc tdre scxsr status register pf raf 15 0 wake-up logic pin buffer rxd msb all ones data recovery 16 parity detect receiver baud rate clock scxdr rx buffer (read-only) sci tx requests sci interrupt request internal data bus h(8)76543210l 10 (11)-bit rx shift register start stop queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-45 15.7.1 sci registers the sci programming model includes the qsmcm gl obal and pin control registers and the dsci registers. the dsci registers, listed in table 15-23 , consist of five control register s, three status registers, and 34 data registers. all registers may be read or written at any time by the cpu. rewriting the same value to any dsci register does not disrupt operation; however, writing a differ ent value into a dsci register when the dsci is running may di srupt operation. to change register valu es, the receiver and transmitter should be disabled with the transmitter allowed to finish first. the status flags in re gister scxsr can be cleared at any time. table 15-23. sci registers address name usage 0x30 5008 scc1r0 sci1 control register 0 see queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-46 freescale semiconductor *reads access the rdrx; writes access the tdrx. during scix initialization, two bits in the sccxr1 should be written las t: the transmitter enable (te) and receiver enable (re) bits, which enable scix. regi sters sccxr0 and sccxr1 should both be initialized at the same time or before te and re are asserted. a single half-word write to sccxr1 can be used to initialize scix and enable the transmitter and receiver. 15.7.2 sci control register 0 (sccxr0) sccxr0 contains the scix baud rate selection fiel d and two bits controlling the clock source. the baud rate must be set before the sci is enabled. th e cpu can read and writ e sccxr0 at any time. changing the value of sccxr0 bits during a transfer operation can disrupt the transfer. before changing register values, allow the sci to complete the curren t transfer, then disable th e receiver and transmitter. 0x30 502c ? 0x30 504a qsci1 transmit queue memory area qsci1 transmit queue data locations (on half-word boundary) 0x30 504c-6a qsci1 receive queue memory area qsci1 receive queue data locations (on half-word boundary) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field othr lnkbd ? scxbr sreset 0 0 0 0_0000_0000_0100 addr 0x30 5008; 0x30 5020 figure 15-26. sccxr0 ? sci control register 0 table 15-24. sccxr0 bit descriptions bits name description 0 othr this bit is reserved and should always be programmed to 0. 1 lnkbd this bit is reserved and should always be programmed to 0. 2?reserved 3:15 scxbr sci baud rate. the sci baud rate is programmed by writing a 13-bit value to this field. writing a value of zero to scxbr disables the baud rate generator. baud clock rate is calculated as follows: where scxbr is in the range of 1 to 8191. refer to section 15.7.7.3, ?baud clock,? for more information. table 15-23. sci registers sci baud rate f sys 32xscxbr ----------------------------- - = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-47 15.7.3 sci control register 1 (sccxr1) sccxr1 contains scix configuratio n parameters, including transmitter a nd receiver enable bits, interrupt enable bits, and operating m ode enable bits. the cpu can read or wr ite this register at any time. the sci can modify the rwu bit under certain circumstances. changing the value of sccxr1 bits during a transfer operation can disrupt the transfer. before changing register values, allow the sci to complete the curren t transfer, then disable th e receiver and transmitter. msb 0 1 2 3456 7 891011121314 lsb 15 field ? loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk sreset 0000_0000_0000_0000 addr 0x30 500a; 0x30 5022 figure 15-27. sci contro l register 1 (sccxr1) table 15-25. sccxr1 bit descriptions bits name description 0?reserved 1 loops loop mode 0 normal sci operation, no looping, feedback path disabled. 1 sci test operation, loop ing, feedback path enabled. 2 woms wired-or mode for sci pins 0 if configured as an output, txd is a normal cmos output. 1 if configured as an output, txd is an open drain output. 3 ilt idle-line detect type. refer to section 15.7.7.9, ?idle-line detection .? 0 short idle-line detect (start count on first one). 1 long idle-line detect (start coun t on first one after stop bit(s)). 4 pt parity type. refer to section 15.7.7.4, ?parity checking .? 0even parity. 1 odd parity. 5 pe parity enable. refer to section 15.7.7.4, ?parity checking . 0 sci parity disabled. 1 sci parity enabled. 6 m mode select. refer to section 15.7.7.2, ?serial formats .? 0 10-bit sci frame. 1 11-bit sci frame. 7 wake wakeup by address mark. refer to section 15.7.7.10, ?receiver wake-up .? 0 sci receiver awakened by idle-line detection. 1 sci receiver awakened by address mark (last bit set). 8 tie transmit interrupt enable 0 sci tdre interrupts disabled. 1 sci tdre interrupts enabled. 9 tcie transmit complete interrupt enable 0 sci tc interrupts disabled. 1 sci tc interrupts enabled. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-48 freescale semiconductor 15.7.4 sci status register (scxsr) scxsr contains flags that show sc i operating conditions. these flags are cleared either by scix hardware or by a read/write sequence. the sequence consists of reading the scxsr (either the upper byte, lower byte, or the entire half-word) with a flag bit set, th en reading (or writing, in th e case of flags tdre and tc) the scxdr (either the lower byte or the half-word). the contents of the two 16-bit registers scxsr and scxdr appear as upper and lower half-words, respectively, when the scxsr is re ad into a 32-bit register. an upper byte access of scxs r is meaningful only for reads. note that a word read can simultan eously access both register s scxsr and scxdr. this action clears the receive status flag bits that were se t at the time of the read, but does not clear the tdre or tc flags. to clear tc, the scxs r read must be followed by a write to register scxdr (either the lower byte or the half-word). the tdre flag in the status register is read-only. if an internal sci signal for setti ng a status bit comes after the cpu has read the asserted status bits but before the cpu has read or written the scxdr, the ne wly set status bit is not cleared. instead, scxsr must be read again with the bit set and scxdr must be read or written before th e status bit is cleared. note none of the status bits ar e cleared by reading a status bit while it is set and then writing zero to that same bit. instead, the procedure outlined above must be followed. note fu rther that readin g either byte of scxsr causes all 16 bits to be accessed, and any status b its already set in ei ther byte are armed to clear on a subsequent read or write of scxdr. 10 rie receiver interrupt enable 0 sci rdrf and or interrupts disabled. 1 sci rdrf and or interrupts enabled. 11 ilie idle-line interrupt enable 0 sci idle interrupts disabled. 1 sci idle interrupts enabled. 12 te transmitter enable 0 sci transmitter disabled (txd pin can be used as general-purpose output) 1 sci transmitter enabled (txd pi n dedicated to sci transmitter). 13 re receiver enable 0 sci receiver disabled (rxd pin can be used as general-purpose input). 1 sci receiver enabled (rxd pin is dedicated to sci receiver). 14 rwu receiver wakeup. refer to section 15.7.7.10, ?receiver wake-up .? 0 normal receiver operation (received data recognized). 1 wakeup mode enabled (received data ignored until receiver is awakened). 15 sbk send break 0 normal operation. 1 break frame(s) transmitted after completion of current frame. table 15-25. sccxr1 bit descriptions (continued) bits name description queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-49 msb 0123456 7 8 9 1011121314 lsb 15 field ? tdre tc rdrf raf idle or nf fe pf sreset 0000_000 1 1 0 0 0 0 0 0 0 addr 0x30 500c; 0x30 5024 figure 15-28. scix status register (scxsr) table 15-26. scxsr bit descriptions bits name description 0:6 ? reserved 7 tdre transmit data register empty. tdre is set when the byte in tdrx is tr ansferred to the transmit serial shifter. if this bit is zero, the transfer is yet to occur and a write to tdrx will overwrite the previous value. new data is not transmitted if tdrx is written without first clearing tdre. 0 transmit data register still contains data to be sent to the tran smit serial shifter. 1 a new character can now be written to the transmit data register. for transmit queue operation, this bit should be ignored by software. 8 tc transmit complete. tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle-line), or queued breaks (logic zero). 0 sci transmitter is busy. 1 sci transmitter is idle. for transmit queue operation, tc is cleared when scxsr is read with tc set, followed by a write to sctq[0:15]. 9 rdrf receive data register full. rdrf is set when the contents of the receive serial shifter are transferred to register rdrx. if one or more e rrors are detected in the received word, the appropriate flag(s) (nf, fe, or pf) are set within the same clock cycle. 0 receive data register is empty or contains previously read data. 1 receive data register contains new data. for receiver queue operation, this bit should be ignored by software. 10 raf receiver active flag. raf indicates whether the receiver is busy. this flag is set when the receiver detects a possible start bit and is cleared when t he chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. 0 sci receiver is idle. 1 sci receiver is busy. 11 idle idle line detected. idle is set when the rece iver detects an idle-line condition (reception of a minimum of 10 or 11 consecutive ones as specified by ilt in sccxr1). this bit is not set by the idle-line condition when rwu in sccxr1 is set. once cleared, idle is not set again until after rdrf is set (after the line is active and becomes id le again). if a break is received, rdrf is set, allowing a subsequent idle line to be detected again. under certain conditions, the idle flag may be set immediately following the negation of re in sccxr1. system designs should ensure th is causes no detrimental effects. 0 sci receiver did not detect an idle-line condition. 1 sci receiver detected an idle-line condition. for receiver queue operation, idle is cleared when scxsr is read with idle set, followed by a read of scrq[0:15]. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-50 freescale semiconductor 15.7.5 sci data register (scxdr) the scxdr consists of two data registers located at the same addr ess. the receive data register (rdrx) is a read-only register that contains data receive d by the sci serial interface. data is shifted into the receive serial shifter and is transferred to rdrx. the transmit data register (tdrx) is a write-only register that contains data to be transmit ted. data is first written to tdrx, then tr ansferred to the transmit serial shifter, where additional format bits are added before transmission. 12 or overrun error. or is set when a new byte is ready to be transferred from the receive serial shifter to register rdrx, and rdrx is already full (rdrf is still set). data transfer is inhibited until or is cleared. previous data in rdrx remains valid, but additional data received during an overrun condition (including the byte that set or) is lost. note that whereas the other rece iver status flags (nf, fe, and pf) reflect the status of data already transferred to rdrx, the or flag reflects an operational condition that resulted in a loss of data to rdrx. 0 rdrf is cleared before new data arrives. 1 rdrf is not cleared before new data arrives. 13 nf noise error flag. nf is set when the receiver detec ts noise on a valid start bit, on any of the data bits, or on the stop bit(s). it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times for noise. if the three samples are not at the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until the entire frame is received and rdrf is set. although no interrupt is explic itly associated with nf, an inte rrupt can be generated with rdrf, and the interrupt handler can check nf. 0 no noise detected in the received data. 1 noise detected in the received data. for receiver queue operation nf is cleared when scxsr is read with nf set, followed by a read of scrq[0:15]. 14 fe framing error. fe is set when the receiver det ects a zero where a stop bit (one) was expected. a framing error results when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. fe is not set until the entire frame is received and rdrf is set. although no interrupt is explicitly associated with fe, an interrupt can be generated with rdrf, and the interrupt handler can check fe. 0 no framing error detected in the received data. 1 framing error or break detected in the received data. 15 pf parity error. pf is set when the receiver detect s a parity error. pf is not set until the entire frame is received and rdrf is set. although no interrupt is explicitly associated with pf, an interrupt can be generated with rdrf, and the interrupt handler can check pf. 0 no parity error detected in the received data. 1 parity error detected in the received data. table 15-26. scxsr bit descriptions (continued) bits name description queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-51 15.7.6 sci pins the rxd1 and rxd2 pins are the receive data pins for the sci1 and sci2, respectively. txd1 and txd2 are the transmit data pins for the two sci modules. the pins and their functions are listed in table 15-28 . 15.7.7 sci operation the sci can operate in polled or interrupt-driven m ode. status flags in scxs r reflect sci conditions regardless of the operating mode chos en. the tie, tcie, rie, and ilie bits in sccxr1 enable interrupts for the conditions indicated by the tdre, tc, rdrf, and idle bits in scxsr, respectively. 15.7.7.1 definition of terms bit-time the time required to transmit or receiv e one bit of data, which is equal to one cycle of the baud frequency. start bit one bit-time of logic zero that indicates the beginning of a data fram e. a start bit must begin with a one-to-zer o transition and be preceded by at least three receive time samples of logic one. stop bit one bit-time of logic one that indicates the end of a data frame. msb 0 123456 7 8 9 10 11 12 13 14 lsb 15 field ? r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 sreset 0000_000 undefined addr 0x30 500e figure 15-29. sci data register (scxdr) table 15-27. scxdr bit descriptions bits name description 0:6 ? reserved 7:15 r[8:0]/ t[8:0] r[7:0]/t[7:0] cont ain either the eight data bits received when scxdr is read, or the eight data bits to be transmitted when scxdr is written. r8/t8 are used when the sci is configured for nine-bit operation (m = 1). when the sci is configured for 8-bit operation, r8/t8 have no meaning or effect. accesses to the lower byte of scxdr triggers the mechanism for clearing the status bits or for initiating transmissions whether byte, half-word, or word accesses are used. table 15-28. sci pin functions pin names mnemonic mode function receive data rxd1, rxd2 receiver disabled receiver enabled general purpose input serial data input to sci transmit data txd1, txd2 transmitter disabled transmitter enabled general purpose output serial data output from sci queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-52 freescale semiconductor frame a complete unit of serial informati on. the sci can use 10-bit or 11-bit frames. data frame a start bit, a specifie d number of data or information bits, and at leas t one stop bit. idle frame a frame that consists of consecu tive ones. an idle frame has no start bit. break frame a frame that consists of cons ecutive zeros. a break frame has no stop bits. 15.7.7.2 serial formats all data frames must have a start bit and at least one stop bit. receiving and transm itting devices must use the same data frame format. the sci provides hardware support for bot h 10-bit and 11-bit frames. the m bit in sccxr1 specifies the number of bits per frame. the most common data frame format for nrz (non-return to zero) serial interfaces is one start bit, eight data bits (lsb first), and one stop bit (ten bits total). the most co mmon 11-bit data fram e contains one start bit, eight data bits, a pa rity or control bit, and one stop bit. ten-bit and 11-bit frames are shown in table 15-29 . 15.7.7.3 baud clock the sci baud rate is programmed by wr iting a 13-bit value to the scxbr fi eld in sci contro l register zero (sccxr0). the baud rate is derive d from the mcu imb3 clock by a m odulus counter. writing a value of zero to scxbr[12:0] disables the baud rate gene rator. the baud rate is calculated as follows: or eqn. 15-4 table 15-29. serial frame formats 10-bit frames sccxr1 bits start data parity/control stop m pe 17?2 00 1711 01 18?1 00 11-bit frames sccxr1 bits start data parity/control stop m pe 18?2 1 1 the msb data bit can also serve as a second stop bit. by setting this bit permanently to one, communication with other scis requiring two stop bits could be accommodated. 11 1811 11 19?110 sci baud rate f sys 32 x scxbr ----------------------------- - = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-53 where scxbr is in the range {1, 2, 3, ..., 8191}. the sci receiver operates asynchronously . an internal clock is necessary to synchronize with an incoming data stream. the sci baud rate generator produces a receive time sampling cl ock with a frequency 16 times that of the sci baud rate. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. table 15-30 shows possible baud rates for a 40-mhz imb3 clock. the maximu m baud rate with this imb3 clock speed is 1250 kbaud. 15.7.7.4 parity checking the pt bit in sccxr1 selects eith er even (pt = 0) or odd (pt = 1) parity. pt affects received and transmitted data. the pe bit in sccxr1 determines whether parity checking is enabled (pe = 1) or disabled (pe = 0). when pe is set, the msb of data in a frame (i.e., the bit prece ding the stop bit) is used for the parity function. for transmitted data, a parity bit is generated. fo r received data, the parity bit is checked. when parity checking is enabled, the pf bit in the sci status register (scxsr) is set if a parity error is detected. enabling parity affects the number of data bits in a frame, which can in turn affect frame size. table 15-31 shows possible data an d parity formats. table 15-30. examples of scix baud rates 1 1 these rates are based on a 40-mhz imb3 clock. nominal baud rate actual baud rate percent error value of scxbr 1,250,000.00 57,600.00 38,400.00 32,768.00 28,800.00 19,200.00 14,400.00 9,600.00 4,800.00 2,400.00 1,200.00 600.00 300.00 1,250,000.00 56,818.18 37,878.79 32,894.74 29,069.77 19,230.77 14,367.81 9,615.38 4,807.69 2,399.23 1,199.62 600.09 299.98 0.00 -1.36 -1.36 0.39 0.94 0.16 -0.22 0.16 0.16 -0.03 -0.03 0.02 -0.01 1 22 33 38 43 65 87 130 260 521 1042 2083 4167 table 15-31. effect of parity checking on data size mpe result 0 0 8 data bits 0 1 7 data bits, 1 parity bit scxbr f sys 32 x sci baud rate desired ------------------------------------------------------------------------ = queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-54 freescale semiconductor 15.7.7.5 transmitter operation the transmitter consists of a serial shifter and a parallel data register (tdrx) located in the sci data register (scxdr). the serial shifter cannot be directly accessed by the cp u. the transmitter is double-buffered, which means that data can be loaded in to the tdrx while other data is shifted out. the te bit in sccxr1 enables (te = 1) and disables (te = 0) the transmitter. the shifter output is connected to the txd pin whil e the transmitter is opera ting (te = 1, or te = 0 and transmission in progress). wired-or operation should be specified when more than one transmitter is used on the same sci bus. the woms bit in sccxr1 dete rmines whether txd is an open drain (wired-or) output or a normal cmos output. an external pull- up resistor on txd is necessary for wired-or operation. woms controls txd func tion, regardless of whether the pi n is used by the sci or as a general-purpose output pin. data to be transmitted is written to scxdr, then tran sferred to the serial shifter. before writing to tdrx, the transmit data register empty (tdre) flag in scxsr should be checked. when tdre = 0, the tdrx contains data that has not been transferred to the sh ifter. writing to scxdr ag ain overwrites the data. if tdre = 1, then tdrx is empty, and new da ta may be written to tdrx, clearing tdre. as soon as the data in the transmit serial shifter has shifted out and if a new data frame is in tdrx (tdre = 0), then the new data is transferred from tdrx to the transmit serial shifter and tdre is set automatically. an interrupt may opti onally be generated at this point. the transmission complete (tc) flag in scxsr shows transmitter shifte r state. when tc = 0, the shifter is busy. tc is set when all shifting operations ar e completed. tc is not au tomatically cleared. the processor must clear it by first readi ng scxsr while tc is set, then wri ting new data to scxdr, or writing to sctq[0:15] for transmit queue operation. the state of the serial shifter is checked when the te b it is set. if tc = 1, an idle frame is transmitted as a preamble to the following data frame. if tc = 0, the current operation continues un til the final bit in the frame is sent, then the preamble is transmitted. the tc bit is set at the end of preamble transmission. the sbk bit in sccxr1 is used to insert break fr ames in a transmission. a non-zero integer number of break frames are transmitted while sb k is set. break transmission begins when sbk is set, and ends with the transmission in progress at the time either sbk or te is cleared. if sbk is set while a transmission is in progress, that transmission fini shes normally before the break begins. to ensure the minimum break time, toggle sbk quickly to one and back to zero. the tc bit is set at the end of break transmission. after break transmission, at least one bit- time of logic level one (mark idle) is transmitted to ensure that a subsequent start bi t can be detected. if te remains set, after all pending idle, data and break frames are sh ifted out, tdre and tc are set and txd is held at logi c level one (mark). 1 0 9 data bits 1 1 8 data bits, 1 parity bit table 15-31. effect of parity checking on data size mpe result queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-55 when te is cleared, the transmitter is disabled after all pending idle, data , and break frames are transmitted. the tc flag is set, a nd control of the txd pin reverts to pqspar and ddrqs. buffered data is not transmitted after te is cleared. to avoid losing data in the buffer, do not clear te until tdre is set. some serial communication systems re quire a mark on the txd pin even when the tran smitter is disabled. configure the txd pin as an output, then write a one to either qdtx1 or qdtx2 of the portqs register. see section 15.5.1, ?port qs da ta register (portqs) .? when the transmitter releases control of the txd pin, it reverts to driv ing a logic one output. to insert a delimiter between two messages, to pl ace non-listening receivers in wake-up mode between transmissions, or to signal a re-tra nsmission by forcing an idle-line, clear and then set te before data in the serial shifter has shifted out. th e transmitter finishes the transmissi on, then sends a preamble. after the preamble is transmitted, if tdre is set, the transmit ter marks idle. otherwise, normal transmission of the next sequence begins. both tdre and tc have associated interrupts. the in terrupts are enabled by the tr ansmit interrupt enable (tie) and transmission complete interrupt enable (tci e) bits in sccxr1. servic e routines can load the last data frame in a sequence into scxdr, then term inate the transmission when a tdre interrupt occurs. two sci messages can be separated with minimum idle time by using a preamble of 10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). follow these steps: 1. write the last data frame of the first message to the tdrx 2. wait for tdre to go high, indicati ng that the last data frame is tr ansferred to the transmit serial shifter 3. clear te and then set te back to one. this queues the preamble to fo llow the stop bit of the current transmission immediately. 4. write the first data frame of th e second message to register tdrx in this sequence, if the first data frame of the second message is not transferred to tdrx prior to the finish of the preamble transmission, then the transmit data li ne (txdx pin) marks idle (logic one) until tdrx is written. in addition, if the last data frame of the firs t message finishes shifting out (including the stop bit) and te is clear, tc goes high and tran smission is considered complete. the txdx pin reverts to being a general-purpose output pin. 15.7.7.6 receiver operation the receiver can be divided into two segments. the first is the re ceiver bit processor logic that synchronizes to the asynchronous receive data and evaluates the logic sense of each bit in the serial stream. the second receiver segment contro ls the functional operation and the interface to the cpu including the conversion of the serial data st ream to parallel access by the cpu. 15.7.7.7 receiver bit processor the receiver bit processor contains logic to synchronize the bit-time of the incoming data and to evaluate the logic sense of each bit. to acco mplish this an rt clock, which is 16 times the baud rate, is used to sample each bit. each bit-time ca n thus be divided into 16 time periods called rt1?rt16. the receiver queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-56 freescale semiconductor looks for a possible start bit by watching for a high- to-low transition on the rxdx pin and by assigning the rt time labels appropriately. when the receiver is enabled by writ ing re in sccxr1 to one, the recei ver bit pro-cessor logic begins an asynchronous search for a start bit. the goal of this search is to gain synchronization with a frame. the bit-time synchronization is done at the beginning of each frame so th at small differences in the baud rate of the receiver and transmitter are not cumulative. scix also synchronizes on all one-to-zero transitions in the serial data stream, whic h makes scix tolerant to sm all frequency variations in the received data stream. the sequence of events used by the recei ver to find a start bit is listed below. 1. sample rxdx input during each rt period and maintain these samples in a serial pipeline that is three rt periods deep. 2. if rxdx is low during this rt period, go to step 1. 3. if rxdx is high during this rt peri od, store sample and proceed to step 4. 4. if rxdx is low during this rt period, but not high for the previous three rt periods (which is noise only), set an internal working noise flag and go to step 1, since this transi tion was not a valid start bit transition. 5. if rxdx is low during this rt period and has been high for the prev ious three rt periods, call this period rt1, set raf, and proceed to step 6. 6. skip rt2 but place rt3 in the pipeline and proceed to step 7. 7. skip rt4 and sample rt5. if both rt3 and rt5 ar e high (rt1 was noise only), set an internal working noise flag. go to step 3 and clear raf. otherwise, place rt5 in the pipeline and proceed to step 8. 8. skip rt6 and sample rt7. if any two of rt3, rt 5, or rt7 is high (rt1 was noise only), set an internal working noise flag. go to step 3 and clear raf. otherwise, place rt7 in the pipeline and proceed to step 9. 9. a valid start bit is found and synchronization is ac hieved. from this point on until the end of the frame, the rt clock will increment starting over again with rt1 on each one -to-zero transition or each rt16. the beginning of a bit-ti me is thus defined as rt1 and the end of a bit-time as rt16. upon detection of a valid start bit, synchronization is established and is mainta ined through the reception of the last stop bit, after which the procedure starts all over again to sear ch for a new valid start bit. during a frame?s reception, scix resynchronizes the rt clock on any one-to-zero transitions. additional logic in the recei ver bit processor determines the logic level of the re ceived bit and implements an advanced noise-detection function. during each bit-time of a frame (including the start and stop bits), three logic-sense samples are taken at rt8, rt9, and rt10. the logic sense of the bit-time is decided by a majority vote of these three samples. this logic level is shifted into register rdrx for every bit except the start and stop bits. if rt8, rt9, and rt10 do not all agree, an internal worki ng noise flag is set. addi tionally for the start bit, if rt3, rt5, and rt7 do not all agree, the internal working noise flag is set. if this flag is set for any of the bit-times in a frame, the nf flag in scxsr is set concurrently with the rdrf flag in scxsr when the data is transferred to register rdrx. the user must determine if the data recei ved with nf set is valid. noise on the rxdx pin does not necessarily corrupt all data. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-57 the operation of the receiver bit processor is shown in figure 15-30 . this example demonstrates the search for a valid start bit and the synchronization procedure as outlined above. the possibilities of noise durations greater than one bit-time are not considered in this examples. figure 15-30. start search example 15.7.7.8 receiver functional operation the re bit in sccxr1 enables (re = 1) and disables (re = 0) the receiver. the receiv er contains a receive serial shifter and a parallel receiv e data register (rdrx) located in the sci data register (scxdr). the serial shifter cannot be di rectly accessed by the cpu. the receiver is double-buffe red, allowing data to be held in the rdrx while ot her data is shifted in. receiver bit processor logi c drives a state machine that determines the logic level for each bit-time. this state machine controls when the bit processor logic is to sample the rx d pin and also cont rols when data is to be passed to the receive serial shifter. a receive time clock is used to control sampling and synchronization. data is shifted into the receive serial shifter accordi ng to the most recent synchronization of the receive time clock with the incoming data stream. from this point on, data movement is synchronized with the mcu imb3 cl ock. operation of the receiver stat e machine is detailed in the queued serial module reference manual . the number of bits shifted in by the receiver depends on the serial format. however, all frames must end with at least one stop bit. when the stop bit is recei ved, the frame is considered to be complete, and the received data in the serial shifter is transferred to the rdrx. the receiver data register flag (rdrf) is set when the data is transferred. the stop bit is always a logic one. if a logic zero is sensed during this bit-time, the fe flag in scxsr is set. a framing error is usually cau sed by mismatched baud rates between the receiver and transmitter or by a significant burst of noise. note that a framing error is not always detected; the data in the expected stop bit-time may happen to be a logic one. noise errors, parity errors, and fr aming errors can be detected whil e a data stream is being received. although error conditions are detected as bits are recei ved, the noise flag (nf), the parity flag (pf), and the framing error (fe) flag in scxsr are not set until data is transferred from the serial shifter to the rdrx. r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 2 r t 3 r t 4 r t 5 r t 6 r t 7 r t 8 r t 9 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 2 r t 3 11 111 0 0 *** * restart rt clock perceived start bit actual start bit lsb ** ** ** 0123456 * 1 1 11 0 00 0 0 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-58 freescale semiconductor rdrf must be cleared before the next transfer from the shifter can take place. if rdrf is set when the shifter is full, transfers are inhibite d and the overrun error (or) flag in sc xsr is set. or indicates that the rdrx needs to be serviced faster. when or is set, th e data in the rdrx is preserved, but the data in the serial shifter is lost. when a completed frame is received into the rdrx, either the rdrf or or flag is always set. if rie in sccxr1 is set, an interrupt results whenever rdrf is set. the receiver status fl ags nf, fe, and pf are set simultaneously with rdrf, as appropriate. these re ceiver flags are never set with or because the flags apply only to the data in the receive serial shifter. the receiver status flags do not have se parate interrupt enables, since they are set simultaneously with rd rf and must be read at the same time as rdrf. when the cpu reads scxsr and scxdr in sequence, it acquires status an d data, and also clears the status flags. reading scxsr acquires status and arms th e clearing mechanism. read ing scxdr acquires data and clears scxsr. 15.7.7.9 idle-line detection during a typical serial transmission, frames are transmitted isochronicall y and no idle time occurs between frames. even when all the data bits in a frame are logic ones, the start bit pr ovides one logi c zero bit-time during the frame. an idle line is a sequence of contiguous on es equal to the current frame size. frame size is determined by the state of the m bit in sccxr1. the sci receiver has both short and long idle-line detection capability . idle-line detection is always enabled. the idle-line type (ilt) bit in sccxr1 dete rmines which type of detection is used. when an idle-line condition is detected, th e idle flag in scxsr is set. for short idle-line detection, the receiver bit proc essor counts contiguous logi c one bit-times whenever they occur. short detection provide s the earliest possible recognition of an idle-line condition, because the stop bit and contiguous logic ones before and after it are counted. for long idle-l ine detection, the receiver counts logic ones after the st op bit is received. only a complete idle frame causes the idle flag to be set. in some applications, software overhead can cause a bit-time of logic level one to occur between frames. this bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. when the ilie bit in sccxr1 is set, an interrupt reque st is generated when the idle flag is set. the flag is cleared by reading scxsr and scxd r in sequence. for rece iver queue operation, id le is cleared when scxsr is read with idle set, follow ed by a read of scrq[0:15]. idle is not set again until after at least one frame has been received (rdrf = 1) . this prevents an extended idle interval from causing more than one interrupt. 15.7.7.10 receiver wake-up the receiver wake-up function allows a transmitting device to direct a tr ansmission to a si ngle receiver or to a group of receivers by sending an address frame at the start of a message. hardware activates each receiver in a system under certain conditions. resident software must process address information and enable or disable receiver operation. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-59 a receiver is placed in wake-up m ode by setting the rwu bit in sccx r1. while rwu is set, receiver status flags and interrupts are disa bled. although the software can clear rwu, it is normally cleared by hardware during wake-up. the wake bit in sccxr1 determines which type of wake-up is used. when wake = 0, idle-line wake-up is selected. when wake = 1, address-mark wake-up is selected. both types require a software-based device addressing a nd recognition scheme. idle-line wake-up allows a receiver to sl eep until an idle line is detected. when an idle line is detected, the receiver clears rwu and wakes up. th e receiver waits for the first fram e of the next transmission. the data frame is received normally, transferred to the rd rx, and the rdrf flag is set. if software does not recognize the address, it can set rwu and put the recei ver back to sleep. for idle-line wake-up to work, there must be a minimum of one fram e of idle line between transmissi ons. there must be no idle time between frames within a transmission. address mark wake-up uses a speci al frame format to wake up the receiver. when the msb of an address-mark frame is set, that fr ame contains address information. th e first frame of each transmission must be an address frame. when the msb of a frame is set, the receiver clears rwu and wakes up. the data frame is received normally, transferred to the rd rx, and the rdrf flag is set. if software does not recognize the address, it can set rwu and put the recei ver back to sleep. address mark wake-up allows idle time between frames and elimin ates idle time between transmissi ons. however, there is a loss of efficiency because of an a dditional bit-time per frame. 15.7.7.11 internal loop mode the loops bit in sccxr1 controls a fe edback path in the data serial sh ifter. when loops is set, the sci transmitter output is fed back into th e receive serial shifter. txd is asse rted (idle line). both transmitter and receiver must be enabled before entering loop mode. 15.8 sci queue operation 15.8.1 queue operation of sci1 for transmit and receive the sci1 serial module allows for que ueing on transmit and receive data frames. in the standard mode, in which the queue is disabled, the sci1 operates as previously defined (i .e., transmit and receive operations done via sc1dr). however, if the sc i1 queue feature is enabled (by setting the qte and/or qre bits within qsci1cr) a set of 16 entry queues is allocated for the r eceive and/or transmit operation. through software control the queue is capabl e of continuous receive and transfer operations within the sci1 serial unit. 15.8.2 queued sci1 status and control registers the sci1 queue uses the following registers: ? qsci1 control register (qsci1cr, address offset 0x28) ? qsci1 status register (q sci1sr, address offset 0x2a) queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-60 freescale semiconductor 15.8.2.1 qsci1 control register (qsci1cr) msb 0123 4 5 6 7 8 9 10 11121314 lsb 15 field qtpnt qthfi qbhfi qthei qbhei ? qte qre qtwe qtsz sreset 0000_0000_0000_0000 addr 0x30 5028 figure 15-31. qsci1 control register (qsci1cr) table 15-32. qsci1cr bit descriptions bits name description 0:3 qtpnt queue transmit pointer. qtpnt is a 4-bit counte r used to indicate the next data frame within the transmit queue to be loaded into the sc1dr. this f eature allows for ease of testability. this field is writable in test mode on ly; otherwise it is read-only. 4 qthfi receiver queue top-half full interrupt. when set, qthfi enables an sci1 interrupt whenever the qthf flag in qsci1sr is set. the interrupt is bl ocked by negating qthfi. this bit refers to the queue locations scrq[0:7]. 0 qthf interrupt inhibited 1 queue top-half full (qthf) interrupt enabled 5 qbhfi receiver queue bottom-half full interrupt. when set, qbhfi enables an sci1 interrupt whenever the qbhf flag in qsci1sr is set. the interrupt is blocked by negating qbhfi. this bit refers to the queue locations scrq[8:15]. 0 qbhf interrupt inhibited 1 queue bottom-half full (qbhf) interrupt enabled 6 qthei transmitter queue top-half empty interrupt. when set, qthei enables an sci1 interrupt whenever the qthe flag in qsci1sr is set. the interrupt is blocked by negating qthei. this bit refers to the queue locations sctq[0:7]. 0 qthe interrupt inhibited 1 queue top-half empty (qthe) interrupt enabled 7 qbhei transmitter queue bottom-half empty interrup t. when set, qbhei enables an sci1 interrupt whenever the qbhe flag in qsci1sr is set. t he interrupt is blocked by negating qbhei. this bit refers to the queue locations sctq[8:15]. 0 qbhe interrupt inhibited 1 queue bottom-half empty (qbhe) interrupt enabled 8?reserved 9 qte queue transmit enable. when set, the transmit queue is enabled and the tdre bit should be ignored by software. the tc bit is redefined to indicate when the entire queue is finished transmitting. when clear, the sci1 functions as de scribed in the previous sections and the bits related to the queue (section 5.5 and its subsecti ons) should be ignored by software with the exception of qte. 0 transmit queue is disabled 1 transmit queue is enabled queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-61 15.8.2.2 qsci1 status register (qsci1sr) 10 qre queue receive enable. when set, the receive queue is enabled and the rdrf bit should be ignored by software. when clear, the sci1 functi ons as described in the previous sections and the bits related to the queue (section 5.5 and it s subsections) should be ignored by software with the exception of qre. 0 receive queue is disabled 1 receive queue is enabled 11 qtwe queue transmit wrap enable. when set, the tr ansmit queue is allowed to restart transmitting from the top of the queue after reaching the bottom of the queue. after each wrap of the queue, qtwe is cleared by hardware. 0 transmit queue wrap feature is disabled 1 transmit queue wrap feature is enabled 12:15 qtsz queue transfer size. the qtsz bits allo w programming the number of data frames to be transmitted. from 1 (qtsz = 0b0000) to 16 (qts z = 0b1111) data frames can be specified. qtsz is loaded into qpend initially or when a wrap occurs. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ? qor qthf qbhf qthe qbhe qrpnt qpend sreset 000 0 1 1 1 1 0000 0000 addr 0x30 502a figure 15-32. qsci1 status register (qsci1sr) table 15-33. qsci1sr bit descriptions bits name description 0:2 ? reserved 3 qor receiver queue overrun error. the qor is set when a new data frame is ready to be transferred from the sc1dr to the queue and the queue is already full (qthf or qbhf are still set). data transfer is inhibited until qor is cleared. previous data transferred to the queue remains valid. additional data received during a queue overrun condition is not lost provided the receive queue is re-enabled before or (sc1sr) is set. the or flag is set when a new data frame is received in the shifter but the data register (sc1dr) is st ill full. the data in the shifter that generated the or assertion is overwritten by the next received data frame, but the data in the sc1dr is not lost. 0 the queue is empty before valid data is in the sc1dr 1 the queue is not empty when valid data is in the sc1dr 4 qthf receiver queue top-half full. qthf is set when the receive queue locations scrq[0:7] are completely filled with new data received via the se rial shifter. qthf is cleared when register qsci1sr is read with qthf set, foll owed by a write of qthf to zero. 0 the queue locations scrq[0:7] are partially filled with newly received data or is empty 1 the queue locations scrq[0:7] are completely full of newly received data table 15-32. qsci1cr bit descriptions (continued) bits name description queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-62 freescale semiconductor 15.8.3 qsci1 transmitter block diagram the block diagram of the enhancements to the sci transmitter is shown in figure 15-33 . 5 qbhf receiver queue bottom-half full. qbhf is set when the receive queue locations scrq[8:15] are completely filled with new data received via the serial shifter. qbhf is cleared when register qsci1sr is read with qbhf set, follo wed by a write of qbhf to zero. 0 the queue locations scrq[8:15] are partially filled with newly received data or is empty 1 the queue locations scrq[8:15] are completely full of newly received data 6 qthe transmitter queue top-half empty. qthe is se t when all the data frames in the transmit queue locations sctq[0:7] have been transferred to the transmit serial shifter. qthe is cleared when register qsci1sr is read with qthe se t, followed by a write of qthe to zero. 0 the queue locations sctq[0:7] still contain data to be sent to the transmit serial shifter 1 new data may now be written to the queue locations sctq[0:7] 7 qbhe transmitter queue bottom-half empty. qbhe is set when all the data frames in the transmit queue locations sctq[8:15] has been transferred to the tr ansmit serial shifter. qbhe is cleared when register qsci1sr is read wi th qbhe set, followed by a write of qbhe to zero. 0 the queue locations sctq[8:15] still contain data to be sent to the transmit serial shifter 1 new data may now be written to the queue locations sctq[8:15] 8:11 qrpnt queue receive pointer. qrpnt is a 4-bit counter used to indicate the position where the next valid data frame will be stored within the receive que ue. this field is writable in test mode only; otherwise it is read-only. 12:15 qpend queue pending. qpend is a 4-bit decrementer used to indicate the number of data frames in the queue that are awaiting transfer to the sc1dr. this field is writable in test mode only; otherwise it is read-only. from 1 (qpend = 0b0000) to 16 (or done, qpend = 1111) data frames can be specified. table 15-33. qsci1sr bit descriptions (continued) bits name description queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-63 figure 15-33. queue transmitter block enhancements 15.8.4 qsci1 additional transmit operation features ? available on a single sci channel (sci1) implemented by the queue transmit enable (qte) bit set by software. when enabled, (qte = 1) the tdre bit shou ld be ignored by software and the tc bit is redefined (as described later). ? when the queue is disabled (qte = 0), the sci f unctions in single buffer tr ansfer mode where the queue size is set to one (qts z = 0000), and tdre and tc func tion as previously defined. locations sctq[0:15] can be used as general purpose 9-bit register s. all other bits pertaining to the queue should be ignored by software. ? programmable queue up to 16 transmits (sctq[0:15]) which may allow for infinite and continuous transmits. ? available transmit wrap function to prevent message breaks for tr ansmits greater than 16. this is achieved by the transmit wrap enable (qtwe) bit. when qtwe is set, the hardware is allowed to 10 (11) - bit tx shift register stop start h(8)76543210l txd sctq0 sctq1 sctq15 9-bit 16:1 mux tr a n s m i t t e r baud rate clock 4-bits qtsz[0:3] qthei qbhei queue control qte qpend[0:3] qthe qbhe qtwe queue status queue control logic sci interrupt request sc1dr tx buffer sci1 non-queue operation data bus queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-64 freescale semiconductor restart transmitting from the top of the queue (sctq0). after each wrap, qtwe is cleared by hardware. ? transmissions of more than 16 data frames mu st be performed in multiples of 16 (qtsz = 0b1111) except for the last set of transmis sions. for any single non-c ontinuous transmissions of 16 or less or the last transmit set compos ed of 16 or fewer data frames, programming of qtsz to the corresponding value of 16 or less where qtwe = 0 is allowed. ? interrupt generation when the top half (sctq[0:7] ) of the queue has been emptied (qthe) and the bottom half (sctq[8:15]) of the queue has been emptied (qbhe). this may allow for uninterrupted and continuous tran smits by indicating to the cpu th at it can begin refilling the queue portion that is now emptied. ? the qthe bit is set by hardware when the top half is empty or the tr ansmission has completed. the qthe bit is cleared when the qsci1sr is read with qthe set, followed by a write of qthe to zero. ? the qbhe bit is set by hardware when the bottom half is empty or the transmission has completed. the qbhe bit is cleared when the qs ci1sr is read with qbhe set, followed by a write of qbhe to zero. ? in order to implement the transmit queue, q te must be set (qsci1cr), te must be set (scc1r1), qthe must be cleared (qsci1 sr), and tdre must be set (sc1sr). ? enable and disable options for the interrupts qthe and qbhe as controlled by qthei and qbhei respectfully. ? programmable 4-bit register queue transmit size (qtsz) for confi guring the queue to any size up to 16 transfers at a time. this value may be rewr itten after transmission has started to allow for the wrap feature. ? 4-bit status register to indicate the number of data transfers pe nding (qpend). this register counts down to all 0?s where the next count rolls over to al l 1?s. this counter is writable in test mode; otherwise it is read-only. ? 4-bit counter (qtpnt) is used as a pointer to indicate the next data frame within the transmit queue to be loaded into the sc1dr. this counter is wr itable in test mode; otherwise it is read-only. ? a transmit complete (tc) bit re-defined when the queue is enabled (qte = 1) to indicate when the entire queue (including when wrapped) is finish ed transmitting. this is indicated when qpend = 1111 and the shifter has completed shifting data out . tc is cleared when the scxsr is read with tc = 1 followed by a write to sctq[0:15]. if the queue is disabled (qte = 0), the tc bit operates as originally designed. ? when the transmit queue is enabled (qte = 1), writes to the transmit data register (sc1dr) have no effect. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-65 15.8.5 qsci1 transmit flow chart implementing the queue reset set qte=1 shift data out load tdr (sc1dr) with sctq[qtpnt] decrement qpend, qpend = 1111 no yes set qthei, qbhei hardware software load qpend with qtsz, increment qtpnt qtpnt=1000? qbhe=0? reset qtpnt to 0000 write qtsz=n clear qthe, tc write sctq[0:n] set te qte=1, te=1 no yes tdre=1, qthe=0? refers to action performed in parallel qte, te=1? no yes qtpnt = 1111? qtwe = 1 set qthe, qbhe clear qte no set qthe set qbhe no yes no yes yes yes write qtsz for wrap clear qthe possible set of qtwe clear qbhe clear qtwe te=0, tc=1, tdre=1 qte=0, qtpnt=0, qtwe=0 qthei=0, qthe=1 qbhei=0, qbhe=1 & qthe = 0? no (tdre=1) queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-66 freescale semiconductor figure 15-34. queue transmit flow figure 15-35. queue transmit software flow qthe = 1? ye s no enable queue interrupt reset configure the transmit flow qbhe = 1? ye s no qthei = 1, if transmitting greater than 16 data frames, write qtsz=n for first pass use of the queue set qte and te = 1 enable queue interrupt for first use of the queue. if finished transmitting, then clear qte and/or te if finished transmitting, then clear qte and/or te done done read status register with tc = 1, write sctq[0:n] (clears tc) read status register with qthe=1 write qthe = 0 (and qbhe if transmitting more than 8 data must have equaled 16) read qthe=1, write qthe=0 write new data sctq[0:7] to wrap, write new qtsz=n set qtwe (previous qtsz if transmitting greater than 8 data frames on wrap read qbhe=1,write qbhe=0 write new data to sctq[8:15] frames) qbhei = 1 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-67 15.8.6 example qsci1 transmit for 17 data bytes figure 15-36 below shows a transmission of 17 data frames. the bold type indicates the current value for qtpnt and qpend. the italic type indicates the action just perfo rmed by hardware. regular type indicates the actions that should be perf ormed by software before the next event. figure 15-36. queue transmit example for 17 data bytes 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq0 sctq7 sctq8 sctq15 write new qtsz for when wrap occurs qtsz=0 (16+1=17),set qtwe, clear qthe write sctq0 for 17th transfer 0000 0111 1000 1111 qtpnt qpend 0000 qtsz=0000 (1 data frame) sctq0 sctq7 sctq8 sctq15 load qpend with qtsz (0) reset qtpnt 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq0 sctq7 sctq8 sctq15 data to be transferred available register space 0001 1111 qthe interrupt received transmit queue enabled 1 2 3 qbhe interrupt received (wrap occurred) clear qtwe queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-68 freescale semiconductor 15.8.7 example sci transmit for 25 data bytes figure 15-37 below is an example of a tr ansmission of 25 data frames. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-69 figure 15-37. queue transmit example for 25 data frames 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq0 sctq7 sctq8 sctq15 0000 0111 1000 1111 qtpnt qpend 1000 qtsz=1000 (9 data frames) sctq0 sctq7 sctq8 sctq15 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq0 sctq7 sctq8 sctq15 0001 0000 0111 1000 1111 qtpnt qpend 1000 qtsz=1000 (9 data frames) sctq0 sctq7 sctq8 sctq15 0000 0000 0001 data to be transferred available register space 1001 1111 qthe interrupt received write qtsz = 8 (16 + 9 = 25) write sctq [0:7] for 8 more data frames set qtwe clear qthe load qpend with qtsz clear qtwe write sctq8 clear qbhe 3 1 2 4 transmit queue enabled qbhe interrupt received (wrap occurred) reset qtpnt qthe interrupt received queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-70 freescale semiconductor 15.8.8 qsci1 receiver block diagram the block diagram of the enhancements to the sci receiver is shown below in figure 15-38 . figure 15-38. queue receiver block enhancements 15.8.9 qsci1 additional receive operation features additional qsci1 features include: ? available on a single sci channel (sci1) implemented by the queue receiver enable (qre) bit set by software. when the queue is enabled, software should ignore the rdrf bit. ? when the queue is disabled (qre = 0), the sc i functions in single buf fer receive mode (as originally designed) and rdrf and or function as previously defined. lo cations scrq[0:15] can rxd receiver baud rate clock 10 (11) - bit rx shift register stop start h(8)76543210l scrq0 scrq1 scrq15 16:1 mux 4-bits qre qthfi qbhfi queue control qrpnt[0:3] qthf qbhf queue status queue control logic sci interrupt request qor scxdr rx buffer sci1 non-queue operation data bus queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-71 be used as general purpose 9-bit re gisters. software should ignore all other bits pertaining to the queue. ? only data that has no errors (f e and pf both false) is allowed into the queue. the status flags fe and pf, if set, reflect the status of data not al lowed into the queue. the receive queue is disabled until the error flags are cleared vi a the original sci mechanism and the queue is re-initialized. the pointer qrpnt indicates the que ue location where the data frame would have been stored. ? queue size capable to receive up to 16 data frames (s crq[0:15]) which may al low for infinite and continuous receives. ? interrupt generation can occur when the top half (scrq[0:7]) of the queue has been filled (qthf) and the bottom half (scrq[8:15]) of the queue has been filled (qbhf). this may allow for uninterrupted and conti nuous receives by indicating to the cpu to start r eading the queue portion that is now full. ? the qthf bit is set by hardware when the top ha lf is full. the qthf bit is cleared when the scxsr is read with qthf set, fo llowed by a write of qthf to zero. ? the qbhf bit is set by hardware when the botto m half is full. the qbhf bit is cleared when the scxsr is read with qbhf set, fo llowed by a write of qbhf to zero. ? in order to implement the receive queue, the foll owing conditions must be met: qre must be set (qsci1cr); re must be set (s cc1r1); qor and qthf must be cleared (qsci1sr); and or, pf, and fe must be cleared (sc1sr). ? enable and disable options for the interrupts qt hf and qbhf as controlled by the qthfi and qbhfi, respectfully. ? 4-bit counter (qrpnt) is used as a pointer to indicate where the next valid data frame will be stored. ? a queue overrun error flag (qor) to indicate when the queue is already full when another data frame is ready to be st ored into the queue (similar to the or bit in single buffe r mode). the qor bit can be set for qthf = 1 or qbhf = 1, de pending on where the store is being attempted. ? the queue can be exited when an idle line is us ed to indicate when a group of serial transmissions is finished. this can be achieved by using the ilie bit to enable the inte rrupt when the idle flag is set. the cpu can then clear qre and/or re allowing the receiver queue to be exited. ? for receiver queue opera tion, idle is cleared when sc1sr is read with idle set, followed by a read of scrq[0:15]. ? for receiver queue opera tion, nf is cleared when the sc1sr is read with nf set, followed by a read of scrq[0:15]. when noise occurs, the data is loaded into the receive queue, and operation continues unaffected. however, it may not be possible to determine which data frame in the receive queue caused the noise flag to be asserted. ? the queue is successful ly filled (16 data frames) if error fl ags (fe and pf) are clear, qthf and qbhf are set, and qrpnt is reset to all zeroes. ? qor indicates that a new data fr ame has been received in the data register (sc1dr), but it cannot be placed into the receive queue due to either the qthf or qbhf flag being set (qsci1sr). under this condition, the receive queue is disabled (q re = 0). software may service the receive queue and clear the appropriate flag (qthf, qbhf). data is not lost provided that the receive queue is re-enabled before or (sc1sr) is set, which occurs when a new data frame is received in the shifter queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-72 freescale semiconductor but the data register (sc1dr) is still full. the data in the shifter that generated the or assertion is overwritten by the next received data frame, but the data in the sc1dr is not lost. queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-73 15.8.10 qsci1 receive flow chart implementing the queue figure 15-39. queue receive flow re=0, qrwe=0 qrpnt=0000 set qre load rx data to qrpnt = 0000? no ye s scrq[qrpnt], qre=0, qor=0 hardware software refers to action performed in parallel qthf=1, qbhf=1 qthfi=0, qbhfi=0 no ye s set qthfi, qbhfi clear qthf, qbhf set re reset increment qrpnt qre, re=1? no ye s qre/re=1 qthf/qor=0 fe/pe/or=0 qrpnt=8 & qbhf qrpnt=0 & qthf fe, pe = 0? qrpnt = 1000? reset qrpnt to 0000 rdrf=1? clear qre set qthf set qbhf ye s no no set qor clear qthf clear qbhf ye s ye s no no ye s queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-74 freescale semiconductor 15.8.11 qsci1 receive queue software flow chart figure 15-40. queue receive software flow qthf=1? yes no enable queue interrupts reset configure the receive queue qbhf = 1? yes no read status register with qbhf = 1 read scrq[8:15] read status register with qthfi, qbhfi = 1, set qre and re = 1 qthf = 1 read scrq[0:7] read status register with qthf & qbhf = 1, write qthf & qbhf = 0 functioncan be used to indicate when a group of serial transmissions is finished enable ilie=1 to detect an idle line idle = 1? yes no clear qre and/or re to exit the queue done write qthf = 0 write qbhf = 0 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 15-75 15.8.12 example qsci1 receive operation of 17 data frames figure 15-41 shows an example receive opera tion of 17 data frames. the bol d type indicates the current value for the qrpnt. action of the queue may be fo llowed by starting at the top of the figure and going left to right and then down the page. figure 15-41. queue receive example for 17 data bytes 0000 0111 1000 1111 qrpnt scrq0 scrq7 scrq8 scrq15 0000 0111 1000 1111 qrpnt scrq0 scrq7 scrq8 scrq15 read scsr and scrq[0:7] clear qthf 0000 0111 1000 1111 qrpnt scrq0 scrq7 scrq8 0000 0111 1000 1111 qrpnt scrq0 scrq7 0001 data available received space qthf interrupt received scrq15 read scrq[8:15] clear qbhf qbhf interrupt received scrq8 scrq15 clear qre/re receive queue enabled read scrq0 idle interrupt received 1 2 3 4 queued serial multi-channel module mpc561/mpc563 reference manual, rev. 1.2 15-76 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-1 chapter 16 can 2.0b controller module the mpc561/mpc563 contains three can 2.0b cont roller modules (toucan). each toucan is a communication controller that implements the controller area ne twork (can) protoc ol, an asynchronous communications protocol used in au tomotive and industrial control sy stems. it is a high speed (one mbit/sec), short distance, priority ba sed protocol that can run over a vari ety of mediums (for example, fiber optic cable or an unshielded twiste d pair of wires). the toucan suppor ts both the standard and extended identifier (id) message formats sp ecified in the can prot ocol specification, revisi on 2.0, part b. the third toucan has its signals muxed with mios14 gpio or qsmcm sc i2 signals. these signals are configured as gpio inputs at reset and must be changed to toucan si gnals in the mios before enabling the toucan. each toucan module contains 16 message buffers that ar e used for transmit and re ceive functions. it also contains message filters, which are used to qualify the received message ids when comparing them to the receive buffer identifiers. figure 16-1 shows a block diagram of a toucan module. figure 16-1. toucan block diagram 16.1 features each toucan module provides these features: ? full implementation of can protoc ol specification, version 2.0 a/b ? standard data and remote fr ames (up to 109 bits long) ? extended data and remote fr ames (up to 127 bits long) control slave bus cntx0 cnrx0 interface unit 16 rx/tx message buffers transmitter receiver imb 16-bit counter can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-2 freescale semiconductor ? zero to eight bytes data length ? programmable bit rate up to one mbit/sec ? 16 rx/tx message buffers of 0-8 bytes data length ? content-related addressing ? no read/write semaphores required ? three programmable mask regist ers: global (for message buffe rs 0 through 13), special for message buffer 14, and special for message buffer 15 ? programmable transmit-first scheme: lowest id or lowest buffer number ? ?time stamp?, based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? programmable i/o modes ? maskable interrupts ? independent of the transmission medium (external transceiver is assumed) ? open network architecture ? multimaster concept ? high immunity to emi ? short latency time for high-priority messages ? low power sleep mode with prog rammable wakeup on bus activity ? outputs have open drain drivers ? support for sae j1939 and sae j2284 ? support for devicenet? and smart distributed system 16.2 external signals each toucan module interface to the external can bus consists of tw o signals: cntx0 which transmits serial data, and cnrx0 wh ich receives serial data. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-3 figure 16-2. typical can network each can station is connected physica lly to the can bus through an exte rnal transceiver. the transceiver provides the transmit drive, waveshaping, and rece ive/compare functions re quired for communicating on the can bus. it can also provide protection agains t damage to the toucan caused by a defective can bus or a defective can station. 16.2.1 toucan signal sharing the cntx0 and cnrx0 signals of toucan_a and t oucan_b are available at all times. the cntx0 and cnrx0 signals of toucan_c are shared with mios14 gpio signals (mpio32b11, mpio32b12) or qsmcm sci2 signals (txd2/qgpo2, rxd2/qgpi2 ). the signal functions for these signals are controlled by the pdmcr2[tcnc] register. note only one function can be enabled on a signal at a time. 16.3 toucan architecture the toucan module uses a flexible design that allows each of its 16 message buffers to be designated either a transmit (tx) buffer or a receive (rx) buffer. in addition, to reduce the cpu overhead required for message handling, each message buffer is assigned an interrupt flag bit to indicate that th e transmission or reception completed successfully. oo can controller (toucan) mpc56x can system can station 2 can station n can station 1 transceiver transceiver transceiver cntx0 cnrx0 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-4 freescale semiconductor 16.3.1 tx/rx message buffer structure figure 16-3 displays the extended (29-bit) id message buffer structure. figure 16-4 displays the standard (11-b it) id message buffer structure. 16.3.1.1 common fields for exte nded and standard format frames table 16-1 describes the message buffer fields that are common to both extended and standard identifier format frames. msb 07 811 l 12 lsb 15 0x0 time stamp code length control/status 0x2 id[28-18] srr ide id[17-15] id_high 0x4 id[14-0] rtr id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved figure 16-3. extended id message buffer structure msb 07 811 l 12 lsb 15 0x0 time stamp code length control/status 0x2 id[28:18] rtr 0 0 0 0 id_high 0x4 16-bit time stamp id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved figure 16-4. standard id message buffer structure table 16-1. common extended/standard format frames field description time stamp contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the can bus. code refer to ta bl e 1 6 - 2 and table 16-3 . can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-5 length (rx) length (in bytes) of the rx da ta stored in offset 0x6 through 0xd of the buffer.this field is written by the toucan module, copied from the dlc (data length code) field of the received frame. length (tx) length (in bytes) of the data to be transmitted, located in of fset 0x6 through 0xd of the buffer. this field is written by the cpu and is used as the dlc field value. if rtr (remote transmission request) = 1, the frame is a remote frame and will be transm itted without data field, rega rdless of the value in tx length. data this field can store up to eight data bytes for a frame. for rx frames, the data is stored as it is received from the bus. for tx frames, the cpu prov ides the data to be transmitted within the frame. reserved the cpu controls access to this word entry field (16 bits). table 16-2. message buffer codes for receive buffers rx code before rx new frame description rx code after rx new frame comment 0b0000 not active ? message buffer is not active. ? ? 0b0100 empty ? message buffer is active and empty. 0b0010 ? 0b0010 full ? message buffer is full. 0b0110 if a cpu read occurs before the new frame, new receive code is 0010. 0b0110 overrun ? addtional frame was received into a full buffer before the cpu read the first one. 0b0xy1 1 1 for tx message buffers, upon read, the busy bit should be ignored. busy ? message buffer is now being filled with a new receive frame. this condition will be cleared within 20 cycles. 0b0010 an empty buffer was filled (xy was 10). 0b0110 a full/overrun buffer was filled (y was 1). table 16-3. message buffer codes for transmit buffers rtr initial tx code description code after successful transmission x 0b1000 message buffer not ready for transmit. ? 0 0b1100 data frame to be transmitted once, unconditionally. 0b1000 1 0b1100 remote frame to be transmitted once, and message buffer becomes an rx message buffer for data frames. 0b0100 0 0b1010 1 1 when a matching remote request frame is detected, the code for such a message buffer is changed to be 0b1110. data frame to be transmitted only as a response to a remote frame, always. 0b1010 0 0b1110 data frame to be transmitted only once, unconditionally, and then only as a response to remote frame, always. 0b1010 table 16-1. common extended/standard format frames (continued) field description can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-6 freescale semiconductor 16.3.1.2 fields for extended format frames table 16-4 describes the message buffer fields used only for extended identifier format frames. 16.3.1.3 fields for standard format frames table 16-5 describes the message buffer fields used only for standard identifier format frames. 16.3.1.4 serial message buffers to allow double buffering of messages , the toucan has two shadow buffers called serial message buffers. the toucan uses these two buffers for buffering both received messages and messages to be transmitted. only one serial message buffer is active at a time, and its function depends upon the operation of the toucan at that time. these buffers are not accessible or visible to the user. table 16-4. extended format frames field description id[28:18]/[17:15] contains the 14 most si gnificant bits of the extended identifier, located in the id_high word of the message buffer. substitute remote request (srr) contains a fixed recessive bit, used only in extended format. should be set to one for tx buffers. it will be stored as received on the can bus for rx buffers. id extended (ide) if extended format frame is used, this field should be set to one. if zero, standard format frame should be used. id[14:0] bits [14:0] of the exten ded identifier, located in the id _low word of the message buffer. remote transmission request (rtr) this bit is located in the least significant bit of the id_low word of the message buffer 0 data frame 1 remote frame table 16-5. standard format frames field description 16-bit time stamp the id_low word, which is not needed for standard form at, is used in a standard format buffer to store the 16-bit value of the free-running timer which is ca ptured at the beginning of the identifier field of the frame on the can bus. id[28:18] contains bits [28:18] of the identifier, located in the id_high word of the message buffer. the four least significant bits in this register (corres ponding to the ide bit and id[17:15] for an extended identifier message) must all be written as logic ze ros to ensure proper operation of the toucan. rtr this bit is located in the id_high word of the message buffer; 0 data frame 1 remote frame rtr/srr bit treatment if the toucan transmits this bit as a one and receives it as a zero, an ?arbitration loss? is indicated. if the toucan transmits this bit as a zero and receives it as a one, a bit error is indicated. if the toucan transmits a value and receives a matching response, a successful bit transmission is indicated. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-7 16.3.1.5 message buffer acti vation/deactivation mechanism each message buffer must be activate d once it is configured for the de sired operation. a buffer is activated by writing the appropriate code to th e control/status word for that buffer. once the buffer is activated, it will start the normal transm it and receive processes. a buffer is deactivated by writing th e appropriate deactivation code to the control/status word for that buffer. a buffer is typically deactiv ated to reconfigure the buffer (for example to change the buffer?s function from rx to tx or tx to rx). the buffer sh ould also be deactivated before changing a receive buffer?s message identifier or before loading a new message to be transmitted into a transmit buffer. for more details on activation and deactivation of message buffers and the effects on message buffer operation, refer to section 16.4, ?toucan operation .? 16.3.1.6 message buffer lo ck/release/busy mechanism in addition to the activation/deactivation mechanis m, the toucan also uses a lock/release/busy mechanism to ensure data coherenc y during the receive process. the mechanism includes a lock status for each message buffer and uses the tw o serial message buffers to facili tate frame transfers within the toucan. reading the control/status word of a receive message buf fer triggers the lock for that buffer. while locked, a received message cannot be transferred into that buffer from one of the serial message buffers. if a message transfer between the message buffer a nd a serial message buffer is in progress when the control/status word is read, the busy status is indicated in the code field, and the lock is not activated. the user can release the lock on a me ssage buffer in one of two ways. reading the c ontrol/status word of another message buffer locks that buffer, releasing the previously locked buffer. a global release can also be performed on any locked message buffer by reading the free-running timer. once a lock is released, any message transfers betwee n a serial message buffer an d a message buffer that were delayed due to that buffer being locked will take place. for more details on the message buffer locking mechanism, and the effects on message buffer operation, refer to section 16.4, ?toucan operation .? 16.3.2 receive mask registers the receive mask registers are used as acceptance masks for received fr ame ids. the following masks are defined: ? a global mask, used for receive buffers 0-13 ? two separate masks for buffers 14 and 15 the value of the mask registers s hould not be changed duri ng normal operation. if th e mask register data is changed after the masked identifier of a received message is matched to a locked message buffer, that message will be transferred into that message buff er once it is unlocked, regardless of whether that message?s masked identifier still ma tches the receive buffer identifier. table 16-6 shows mask bit values. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-8 freescale semiconductor table 16-7 shows mask examples for normal and extended messages. refer to section 16.7, ?programming model ? for more information on rx mask registers. 16.3.3 bit timing the toucan module uses three 8-bi t registers to set up the bit timi ng parameters required by the can protocol. control registers one and two (can ctrl1, canctrl2) contain the propseg, pseg1, pseg2, and the rjw fields that allo w configuration of the bit timing parameters. the prescaler divide register (presdiv) allows selection of the ratio used to derive the seri al clock (s-clock) from the system clock. the time quanta clock opera tes at the s-clock frequency. table 16-8 provides examples of system clock, can bit rate, and s-cloc k bit timing parameters, and figure 16-5 shows the relationship between table 16-6. receive mask register bit values mask bit values 0 the corresponding incoming id bit is ?don?t care? 1 the corresponding id bit is checked against the incoming id bit to see if a match exists table 16-7. mask examples for normal/extended messages message buffer (mb)/mask base id id[28:18] ide extended id id[17:0] match mb2 1 1 1 1 1 1 1 1 0 0 0 0 ? ? mb3 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? mb4 0 0 0 0 0 0 1 1 1 1 1 0 ? ? mb5 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? mb14 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? rx global mask 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 ? rx message in 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 1 1 match for extended format (mb3). 1 1 1 1 1 1 1 1 0 0 1 0 ? 2 2 2 match for standard format (mb2). 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 ? 3 3 no match for mb3 because of id0. 0 1 1 1 1 1 1 1 0 0 0 0 ? ? 4 4 no match for mb2 because of id28. 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? 5 5 no match for mb3 because of id28, match for mb14. rx 14 mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 ? rx message in 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ? 6 6 no match for mb14 because of id27. 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14 7 7 match for mb14. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-9 the system clock and the can bit segments. refer to section 16.7, ?programming model ,? for more information on the bi t timing registers. figure 16-5. relationship between s ystem clock and can bit segments a bit is divided into f our separate non-overlapping time segments called sync_seg, propseg, pseg1, and pseg2. these are illustrated in figure 16-5 . the period of the nominal bi t time (nbt) is the sum of the segment durations: t nbt = t sync_seg + t propseg + t pseg1 + t pseg2 the sample point indicated in figure 16-5 is the position of the actual samp le point if a single sample per bit is selected (canctrl1[samp] bit = 0). if three samples per bi t are selected, the sample point indicated in figure 16-5 marks the position of the final sample. table 16-8. example system clock, can bit rate, and s-clock frequencies system clock frequency (mhz) can bit rate (mhz) possible s-clock frequency (mhz) possible number of time quanta/bit presdiv value + 1 56 1 56 56 1 40 1 40 40 1 25 1 25 25 1 20 1 10, 20 10, 20 2, 1 16 1 8, 16 8, 16 2, 1 56 0.500 56 118 1 40 0.500 40 80 1 25 0.500 25 50 1 20 0.500 1, 2, 2.5 2, 4, 5 20, 10, 8 system clock s-clock time quantum sync_seg nominal bit time (nbt) sample point propseg pseg1 pseg2 transmit point baud rate prescaler (presdiv) ss ss can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-10 freescale semiconductor 16.3.3.1 configuring th e toucan bit timing the following considerations must be obs erved when programming bit timing functions. ? if the programmed presdiv value results in a single system cl ock per one time quantum, then the pseg2 field in canctrl2 register must not be programmed to zero. ? if the programmed presdiv value results in a single system cl ock per one time quantum, then the information processing time (ipt) equals three time quanta; otherwise it e quals two time quanta. if pseg2 equals two, then the toucan transmits one time quantum late rela tive to the scheduled sync segment. ? if the prescaler and bit timing cont rol fields are programme d to values that result in fewer than 10 system clock periods per can bit time and the can bus loading is 100%, then any time the rising edge of a start-of-frame (sof) symbol transmitted by another node occurs during the third bit of the intermission between messages, the toucan ma y not be able to prep are a message buffer for transmission in time to begi n its own transmission and arbitr ate against the message which transmitted the early sof. ? the toucan bit time must be pr ogrammed to be greater than or eq ual to nine system clocks, or correct operation is not guarantee d.the duration of the synchroni zation segment, sync_seg, is not programmable and is fixed at one time quantum. 16.3.4 error counters the toucan has two error counters, the transmit (tx) error counter and the receive (rx) error counter. refer to section 16.7, ?programming model ,? for more information on error counters. the rules for increasing and decreasing these counter s are described in the can protocol, and are fully implemented in the toucan. each counter ha s the following features: ? eight-bit up/down-counter ? increment by eight (rx error c ounter also increments by one) ? decrement by one ? avoid decrement when equal to zero ? rx error counter reset to a value between 119 and 127 inclusive, when the toucan transitions from error passive to error active 16 0.500 1, 2 2, 4 16, 8 56 0.125 1, 2 8, 16 56, 28 40 0.125 1, 2 8, 16 40, 20 25 0.125 1, 1.25, 2.5 8,10, 20 25, 20,10 20 0.125 1, 2, 2.5 8, 16, 20 20, 10, 8 16 0.125 1, 2 8,16 16, 8 table 16-8. example system clock, can bit rate, and s-clock frequencies (continued) system clock frequency (mhz) can bit rate (mhz) possible s-clock frequency (mhz) possible number of time quanta/bit presdiv value + 1 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-11 ? following reset, both counters reset to zero ? detect values for error passive, bus off and error active transitions ? cascade usage of tx error counter with an additional in ternal counter to dete ct the 128 occurrences of 11 consecutive recessive bi ts necessary to transition from bus off into error active. both counters are read-only (excep t in test/freeze/halt modes). the toucan responds to any bus state as described in the can protocol, transmitting an error active or error passive flag, delaying its tran smission start time (error passiv e) and avoiding any influence on the bus when in the bus off state. the following ar e the basic rules for toucan bus state transitions: ? if the value of the tx error counter or rx error co unter increments to a valu e greater than or equal to 128, the fault confinement state (fcs[1:0]) field in the error status register is updated to reflect an error passive state. ? if the toucan is in an error passive state, and either the tx error counter or rx error counter decrements to a value less than or equal to 127 wh ile the other error counter already satisfies this condition, the fcs[1:0] field in the error status register is updated to reflect an error active state. ? if the value of the tx error counter increases to a value greater than 255, th e fcs[1:0] field in the error status register is updated to reflect a bus off state, and an interrupt may be issued. the value of the tx error counter is reset to zero. ? if the toucan is in the bus off state, the tx er ror counter and an additional internal counter are cascaded to count 128 occurrences of 11 consecut ive recessive bits on the bus. to do this, the tx error counter is first reset to zero, and then the internal counter begins counting consecutive recessive bits. each time the in ternal counter counts 11 consecuti ve recessive bits, the tx error counter is incremented by one and the internal counter is reset to zero. when the tx error counter reaches the value of 128, the fcs[1:0] field in the e rror status register is upda ted to be error active, and both error counters ar e reset to zero. any time a dominant bit is detected following a stream of less than 11 consecutive recessive bi ts, the internal counter resets it self to zero but does not affect the tx error counter value. ? if only one node is operating in a system, the tx error counter is incremented with each message it attempts to transmit, due to the resulti ng acknowledgment errors. however, acknowledgment errors never cause the toucan to change from the error passive state to the bus off state. ? if the rx error counter increments to a value grea ter than 127, it stops incrementing, even if more errors are detected whil e being a receiver. after the next su ccessful message reception, the counter is reset to a value between 119 and 127, to enable a return to the error active state. the three basic states and the transition beha vior of the can controller are shown in figure 16-6 . can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-12 freescale semiconductor figure 16-6. can controller state diagram 16.3.5 time stamp the value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the can bus. for a message being received, the ti me stamp is stored in the time stamp entry of the receive message buffer at the time the message is writ ten into that buffer. for a messag e being transmitted, the time stamp entry is written into the transmit message buffe r once the transmission has completed successfully. the free-running timer can optionally be reset upon the reception of a frame into message buffer 0. this feature allows network time s ynchronization to be performed. 16.4 toucan operation the basic operation of the toucan can be divided into four areas: ?reset ? initialization of the module ? transmit message handling ? receive message handling example sequences for performing each of these pr ocesses is given in the following paragraphs. 16.4.1 toucan reset the toucan can be reset in two ways: ? hard reset of the module via sreset . ? soft reset of the module, using the softrs t bit in the module c onfiguration register error active error passive bus off (tx error > 127 or rx error > 127) and (tx error < 255) tx error > 255 (tx error 127 and rx error 127) normal state 128 occurences of 11 consecutive recessive bits, tx error and rx error are reset to 0. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-13 following the negation of reset, the toucan is not synchronized with the can bus, and the halt, frz, and frzack bits in the module confi guration register are set. in this state, the t oucan does not initiate frame transmissions or rece ive any frames from the can bus. the c ontents of the message buffers are not changed following reset. any configuration change or initiali zation requires that the toucan be frozen by either the assertion of the halt bit in the module conf iguration register or by reset. 16.4.2 toucan initialization initialization of the toucan includes the initial config uration of the message buffe rs and configuration of the can communication parameters following a reset, as well as any reconfiguration which may be required during operation. the following is a ge neral initialization sequence for the toucan: 1. initialize all operation modes a) initialize the transmit and receive pin modes in canctrl0 b) initialize the bit timing parameters prop seg, psegs1, pseg2, and rjw in canctrl1 and canctrl2 c) select the s-clock rate by programming the presdiv register d) select the internal arbitrati on mode (lbuf bit in canctrl1) 2. initialize message buffers a) the control/status word of all me ssage buffers must be written ei ther as an active or inactive message buffer. b) all other entries in each message buf fer should be initia lized as required 3. initialize mask registers for acceptance mask as required 4. initialize toucan interrupt handler a) initialize the interrupt conf iguration register (canicr) wi th a specific request level b) set the required mask bits in the imask regi ster (for all message buffer interrupts), in canctrl0 (for bus off and error interrupt s), and in canmcr for the wake interrupt 5. negate the halt bit in the modul e configuration register. at this point, the toucan attempts to synchronize with the can bus note in both the transmit and receive proces ses, the first action in preparing a message buffer must be to deactivate the buffer by setting its code field to the proper value. this step is ma ndatory to ensure data coherency. 16.4.3 transmit process the transmit process include s preparation of a message buffer for transmission, as well as the internal steps performed by the toucan to decide which message to transmit. this involves loading the message and id to be transmitted into a message buffer and then act ivating that buffer as an active transmit buffer. once this is done, the toucan performs all additional step s necessary to transmit the message onto the can bus. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-14 freescale semiconductor the user should prepare or change a message buffer for transmission by executing the following steps. 1. write the control/status word to hold the transmit bu ffer inactive (code = 0b1000) 2. write the id_high and id_low words 3. write the data bytes 4. write the control/status word (active tx code, tx length) note steps 1 and 4 are mandatory to ensure data coherency. once an active transmit code is writte n to a transmit message buffer, that buffer begins participating in an internal arbitration process as soon as the receiver senses that the can bus is free, or at the inter-frame space. if there are multiple messages awaiting transmi ssion, this internal arbitr ation process selects the message buffer from which the next frame is transmitted. when this process is over and a messa ge buffer is selected for transmi ssion, the frame from that message buffer is transferred to the seri al message buffer for transmission. the toucan transmits no more than ei ght data bytes, even if the transm it length contains a value greater than eight. at the end of a successful transmission, the value of the free-running timer (whi ch was captured at the beginning of the identifier field on th e can bus), is written into the time stamp field in the message buffer. the code field in the control/status word of the messa ge buffer is updated and a status flag is set in the iflag register. 16.4.3.1 transmit message buffer deactivation any write access to the control/status word of a transmit message buffe r during the proce ss of selecting a message buffer for transmission immediately deacti vates that message buffer, removing it from the transmission process. if the transmit message buffer is de activated while a message is being transferred from it to a serial message buffer, the message is not transmitted. if the transmit message buffer is de activated after the message is transf erred to the serial message buffer, the message is transmitted, but no interrupt is requested, and the transmit code is not updated. if a message buffer containing the lo west id is deactivated while that message is undergoing the internal arbitration process to determine wh ich message should be sent, then th at message may not be transmitted. 16.4.3.2 reception of transmitted frames the toucan receives a frame it ha s transmitted if an empty message buffer with a matc hing identifier exists. 16.4.4 receive process during the receive process, the following events occur: can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-15 ? the user configures the me ssage buffers for reception ? the toucan transfers received me ssages from the serial message buffers to the receive message buffers with matching ids ? the user retrieves these messages the user should prepare or change a message buffer for frame receptio n by executing the following steps. 1. write the control/status word to hold the receive buffer inactive (code = 0b0000) 2. write the id_high and id_low words 3. write the control/status word to mark th e receive message buffer as active and empty note steps 1 and 3 are mandatory for data coherency. once these steps are performed, the message buffer func tions as an active receiv e buffer and participates in the internal matching process, wh ich takes place every time the touc an receives an er ror-free frame. in this process, all active receive buffers compare th eir id value to the newly received one. if a match is detected, the following actions occur: 1. the frame is transferred to the first (l owest entry) matching receive message buffer 2. the value of the free-running timer (captured at the beginning of the identifier field on the can bus) is written into the time st amp field in the message buffer 3. the id field, data field, a nd rx length field are stored 4. the code field is updated 5. the status flag is set in the iflag register the user should read a receiv ed frame from its message buffer in th e following order: 1. control/status word (mandatory, as it act ivates the internal lock for this buffer) 2. id (optional, since it is ne eded only if a mask was used) 3. data field word(s) 4. free-running timer (optional, as it releases the internal lock) if the free running timer is not read, that message buffer remains locked until the read process starts for another message buffer. only a single message buffer is locked at a time. when a receive d message is read, the only mandatory read operation is that of the c ontrol/status word. this ensures data coherency. if the busy bit is set in the messa ge buffer code, the cpu should defer accessing that buffer until this bit is negated. refer to table 16-2 . note the user should check the status of a message buffer by reading the status flag in the iflag register and not by reading the control/status word code field for that message buffer. this pr events the buffer from being locked inadvertently. because the received identifier field is always stored in the matching receive message buffer, the contents of the identifier field in a receive message buffer may change if one or more of the id bits are masked. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-16 freescale semiconductor 16.4.4.1 receive message buffer deactivation any write access to the control/status word of a rece ive message buffer during the process of selecting a message buffer for reception immediately deactivates th at message buffer, removi ng it from the reception process. if a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted and no interrupt is requested. if this occurs, that receive message buffe r may contain mixed data from two different frames. the cpu should not write data into a receive messag e buffer. if this occurs while a message is being transferred from a serial me ssage buffer, the control/st atus word will reflect a full or overrun condition, but no interrupt is requested. 16.4.4.2 locking and releasing message buffers the lock/release/busy mechanism is de signed to guarantee data coherenc y during the receive process. the following examples demonstrate how the lock /release/busy mechanism affects toucan operation: 1. reading a control/status word of a message buffe r triggers a lock for that message buffer. a new received message frame which matc hes the message buffer cannot be written into this message buffer while it is locked. 2. to release a locked message buffer, the cpu either locks another message buffer by reading its control/status word or globally releases any locked message buffer by reading the free-running timer. 3. if a receive frame with a matchi ng id is received during the time the message buffer is locked, the receive frame is not immediately transferred into that message buffer, but remains in the serial message buffer. there is no indication when this occurs. 4. when a locked message buffer is released, if a fr ame with a matching identifier exists within the serial message buffer, then this frame is transferred to the matching message buffer. 5. if two or more receive frames with matchi ng ids are received while a message buffer with a matching id is locked, the last received frame with that id is kept within the serial message buffer, while all preceding ones are lost. there is no indication when this occurs. 6. if the control/status word of a receive message buffer is read while a frame is being transferred from a serial message buffer, the busy code is indicated. the user should wait until this code is cleared before continuing to read from the messa ge buffer to ensure data coherency. in this situation, the read of the control/stat us word does not lock the message buffer. polling the control/status word of a receive message buffer can lock it , preventing a message from being transferred into that buffer. if the control/status wo rd of a receive message buffer is read, it should be followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to ensure that the locked buffer is unlocked. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-17 16.4.5 remote frames the remote frame is a message frame that is tran smitted to request a data frame. the toucan can be configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote frame and then wait for the responding data frame to be received. to transmit a remote frame, a message buffer is initia lized as a transmit message buffer with the rtr bit set to one. once this remote frame is transmitted su ccessfully, the transmit message buffer automatically becomes a receive me ssage buffer, with the same id as th e remote frame that was transmitted. when the toucan receives a remote frame, it compar es the remote frame id to the ids of all transmit message buffers programmed with a code of 1010. if ther e is an exact matching id, the data frame in that message buffer is transmitted. if the rtr bit in the ma tching transmit message buffer is set, the toucan transmits a remote frame as a response. a received remote frame is not stored in a receive message buffer. it is only used to trigger the automatic transmission of a frame in response. the mask registers are not us ed in remote frame id matching. all id bits (except rtr) of the incoming received frame must match for the re mote frame to trigger a response transmission. 16.4.6 overload frames the toucan does not initiate overl oad frame transmissions unless it detects the following conditions on the can bus: ? a dominant bit is the first or second bit of intermission ? a dominant bit is the seventh (last) bit of the end-of-frame (eof) field in receive frames ? a dominant bit is the eighth (last) bit of the error frame delimiter or overload frame delimiter 16.5 special operating modes the toucan module has three special operating modes: ? debug mode ? low-power stop mode ? auto power save mode 16.5.1 debug mode debug mode is entered when the frz1 bit in canmcr is set and one of the following events occurs: ? the halt bit in the canmcr is set; or ? the imb3 freeze line is asserted once entry into debug mode is request ed, the toucan waits until an inte rmission or idle condition exists on the can bus, or until the toucan enters the error passive or bus of f state. once one of these conditions exists, the toucan waits for the completion of all in ternal activity. once this happens, the following events occur: can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-18 freescale semiconductor ? the toucan stops transm itting or receiving frames ? the prescaler is disabled, thus halting all can bus communication ? the toucan ignores its rx signals a nd drives its tx signals as recessive ? the toucan loses synchronization with the can bus and the notrdy and frzack bits in canmcr are set ? the cpu is allowed to read and write the error counter registers after engaging one of the mechanis ms to place the toucan in debug m ode, the frzack bit must be set before accessing any other registers in the touc an; otherwise unpredictable operation may occur. to exit debug mode, the imb3 freeze line must be negated or the halt bit in canmcr must be cleared. once debug mode is exited, the touc an resynchronizes with the can bus by waiting for 11 consecutive recessive bits before beginning to participate in can bus communication. 16.5.2 low-power stop mode before entering low-power stop mode, th e toucan waits for the can bus to be in an idle state, or for the third bit of intermission to be recessive. the toucan th en waits for the completion of all internal activity (except in the can bus interface) to be complete. then the following events occur: ? the toucan shuts down its clocks, stopping mo st internal circuits, thus achieving maximum power savings ? the bus interface unit continues to operate, allowing the cpu to access the module configuration register ? the toucan ignores its rx signals a nd drives its tx signals as recessive ? the toucan loses synchronizat ion with the can bus, and the stopack and notrdy bits in the module configuration register are set to exit low-power stop mode: ? reset the toucan either by asserting one of th e imb3 reset lines or by asserting the softrst bit canmcr ? clear the stop bit in canmcr ? the toucan module can optionally exit low-power stop mode via the self wake mechanism. if the selfwake bit in canmcr was set at the time the toucan entered stop mode, then upon detection of a recessive to dom inant transition on the can bus, th e toucan clears the stop bit in canmcr and its clocks begin running. when the toucan is in low-power stop mode, a rece ssive to dominant transiti on on the can bus causes the wakeint bit in the error and status register (estat ) to be set. this event generates an interrupt if the wakemsk bit in canmcr is set. consider the following notes re garding low-power stop mode: can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-19 ? when the self wake mechanism is activated, the toucan tries to receive the frame that woke it up. (it assumes that the dominant bit detected is a st art-of-frame bit.) it will not arbitrate for the can bus at this time. ? if the stop bit is set while the toucan is in th e bus off state, then the toucan enters low-power stop mode and stops counting rece ssive bit times. the count continues when stop is cleared. ? to place the toucan in low-power stop mode with the self wake mechanism engaged, write to canmcr with both stop and selfwake set, and then wait for the toucan to set the stopack bit. ? to take the toucan out of low- power stop mode when the self wa ke mechanism is enabled, write to canmcr with both stop an d selfwake clear, and then wait for the toucan to clear the stopack bit. ? the selfwake bit should not be set after the toucan has al ready entered low-power stop mode. ? if both stop and selfwake are set and a recessi ve to dominant edge immediately occurs on the can bus, the toucan may never set the stopac k bit, and the stop bit will be cleared. ? to prevent old frames from being sent when th e toucan awakes from low-power stop mode via the self wake mechanism, disable all transmit s ources, including transmit buffers configured for remote request responses, before placi ng the toucan in low-power stop mode. ? if the toucan is in debug mode when the stop b it is set, the toucan assumes that debug mode should be exited. as a result, it tries to synchronize with the ca n bus, and only then does it await the conditions required for entry into low-power stop mode. ? unlike other modules, the toucan does not come out of reset in low-power stop mode. the basic toucan initialization procedure should be execute d before placing the m odule in low-power stop mode. (refer to section 16.4.2, ?toucan initialization .?) ? if the toucan is in low-power stop mode with th e self wake mechanism engaged and is operating with a single system clock per time quantum, th ere can be extreme cases in which the toucan would wake-up on a recessive to dominant edge which may not conform to the can protocol. toucan synchronization is shifted one time quantum from the wake- up event. this shift lasts until the next recessive-to-dominant edge, which res ynchronizes the toucan to be in conformance with the can protocol. the same holds true when the toucan is in auto power save mode and awakens on a recessive to dominant edge. 16.5.3 auto power save mode auto power save mode enables nor mal operation with optimiz ed power savings. once the auto power save (aps) bit in canmcr is se t, the toucan looks for a set of conditi ons in which there is no need for the clocks to be running. if these c onditions are met, the toucan stops its clocks, thus saving power. the following conditions activat e auto power save mode: ? no rx/tx frame in progress ? no transfer of rx/tx frames to and from a serial message buffer, and no tx frame awaiting transmission in any message buffer ? no cpu access to the toucan module can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-20 freescale semiconductor ? the toucan is not in debug mode, lo w-power stop mode, or the bus off state while its clocks are stopped, if the toucan senses th at any one of the aforem entioned conditions is no longer true, it restarts its clocks. the toucan then continues to monitor thes e conditions and stops or restarts its clocks accordingly. 16.6 interrupts the toucan can generate one interrupt level to be passed to the cpu. th is level is programmed into the priority level bits in the interrupt configuration regi ster (canicr). this value determines which interrupt signal is driven onto the bus when an interrupt is requested. each one of the 16 message buffers can be an interrupt source, if its correspondi ng imask bit is set. there is no distinction between transmit a nd receive interrupts for a particular buffer. each of the buffers is assigned a bit in the iflag register. an iflag bi t is set when the corresponding buffer completes a successful transmission/reception. an iflag bit is cleared when the cpu reads iflag while the associated bit is set, and then writes it back as ze ro (and no new event of the same type occurs between the read and the write actions). the other three interrupt sources (bus off, error and wake up) act in the same way, and have flag bits located in the error and status register (estat). th e bus off and error interrupt mask bits (boffmsk and errmsk) are located in canctrl0, and the wake up interrupt mask bi t (wakemsk) is located in the module configuration register. refer to section 16.7, ?programming model ,? for more information on these registers. the toucan module is capable of ge nerating one of the 32 possible inte rrupt levels on the imb3. the 32 interrupt levels are time multiplexed on the imb3 irq[0:7] lines. all inte rrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. the ilbs[0:1] signals indicate which group of eight are being driven on th e interrupt request lines. the level that the toucan will drive onto internal ir q[7:0] signals is programme d in the three interrupt request level (irl) bits located in the interrupt c onfiguration register. the tw o ilbs bits in the icr register determine on which slot th e toucan should drive its interrupt signal. under the control of ilbs, each interrupt request level is driv en during the time multiplexed bus du ring one of four different time slots, with eight levels communicat ed per time slot. no hardware pr iority is assigned to interrupts. furthermore, if more than one source on a module re quests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 16-7 displays the interrupt levels on irq with ilbs. table 16-9. interrupt levels ilbs[0:1] levels 00 0:7 01 8:15 10 16:23 11 24:31 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-21 figure 16-7. interrupt levels on irq with ilbs 16.7 programming model table 16-10 shows the toucan address map. the lowercas e ?x? appended to each register name represents ?a?, ?b? or ?c? for the toucan_a, t oucan_b, or toucan_c modul e, respectively. refer to figure 1-4 to locate each toucan module in the mpc561/mpc563 address map. the column labeled ?access? indicates the privilege level at which the cpu must be operating to access the register. a designa tion of ?s? indicates that supervisor mode is requir ed. a designation of ?s/u? indicates that the register can be programmed for either supervisor mode access or unrestricted access. the address space for each toucan modul e is split, with 128 bytes startin g at the base address, and an extra 256 bytes starting at the base address +128. th e upper 256 are fully used for the message buffer structures. of the lower 128 bytes, some are not used. registers with bits mark ed as ?reserved? should always be written as logic 0. typically, the toucan control registers are programm ed during system initiali zation, before the toucan becomes synchronized with the can bus. the configuration regi sters can be changed after synchronization by halting the touc an module. this is done by setting the halt bit in the toucan module configuration register (canmcr). the toucan responds by asserting canmcr[notrdy]. additionally, the control register s can be modified while the mc u is in background debug mode. note the toucan has no hard-wired prot ection against invalid bit/field programming within its regi sters. specifically, no pr otection is provided if the programming does not meet can protocol requirements. table 16-10. toucan register map access address msb 0 lsb 15 s 0x30 7080(a) 0x30 7480(b) 0x30 7880(c) toucan module configuration register (canmcr_x) see table 16-11 for bit descriptions. s 0x30 7082(a) 0x30 7482(b) 0x30 7882(c) toucan test register (cantcr_x) . imb3 clock ilbs [1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-22 freescale semiconductor s 0x30 7084(a) 0x30 7484(b) 0x30 7884(c) toucan interrupt register (canicr_x) see table 16-12 for bit descriptions. s/u 0x30 7086(a) 0x30 7486(b) 0x30 7886(c) control register 0 (canctrl0_x) see table 16-13 for bit descriptions. control register 1 (canctrl1_x) see table 16-16 for bit descriptions. s/u 0x30 7088(a) 0x30 7488(b) 0x30 7888(c) control and prescaler divider register (presdiv_x) see table 16-17 for bit descriptions. control register 2 (canctrl2_x) see table 16-18 for bit descriptions. s/u 0x30 708a(a) 0x30 748a(b) 0x30 788a(c) free-running timer register (timer_x) see table 16-19 for bit descriptions. ? 0x30 708c ? 0x30 708e(a) 0x30 748c ? 0x30 748e(b) 0x30 788c ? 0x30 788e(c) reserved s/u 0x30 7090(a) 0x30 7490(b) 0x30 7890(c) receive global mask ? high (rxgmskhi_x) see table 16-20 for bit descriptions. s/u 0x30 7092(a) 0x30 7492(b) 0x30 7892(c) receive global mask ? low (rxgmsklo_x) see table 16-20 for bit descriptions. s/u 0x30 7094(a) 0x30 7494(b) 0x30 7894(c) receive buffer 14 mask ? high (rx14mskhi_x) see section 16.7.10, ?receive buffer 14 mask registers (rx14mskhi, rx14msklo) ,? for bit descriptions. s/u 0x30 7096(a) 0x30 7496(b) 0x30 7896(c) receive buffer 14 mask ? low (rx14msklo_x) see section 16.7.10, ?receive buffer 14 mask registers (rx14mskhi, rx14msklo) ,? for bit descriptions. s/u 0x30 7098(a) 0x30 7498(b) 0x30 7898(c) receive buffer 15 mask ? high (rx15mskhi_x) see section 16.7.11, ?receive buffer 15 mask registers (rx15mskhi, rx15msklo) ,? for bit descriptions. s/u 0x30 709a(a) 0x30 749a(b) 0x30 789a(c) receive buffer 15 mask ? low (rx15msklo_x) see section 16.7.11, ?receive buffer 15 mask registers (rx15mskhi, rx15msklo) ,? for bit descriptions. ? 0x30 709c ? 0x30 709e(a) 0x30 749c? 0x30 749e(b) 0x30 789c ? 0x30 789e(c) reserved s/u 0x30 70a0(a) 0x30 74a0(b) 0x30 78a0(c) error and status register (estat_x) see table 16-23 for bit descriptions. s/u 0x30 70a2(a) 0x30 74a2(b) 0x30 78a2(c) interrupt masks (imask_x) see table 16-26 for bit descriptions. s/u 0x30 70a4(a) 0x30 74a4(b) 0x30 78a4(c) interrupt flags (iflag_x) see table 16-27 for bit descriptions. table 16-10. toucan register map (continued) access address msb 0 lsb 15 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-23 s/u 0x30 70a6(a) 0x30 74a6(b) 0x30 78a6(c) receive error counter (rxectr_x) see table 16-28 for bit descriptions. transmit error counter (txectr_x) see table 16-28 for bit descriptions s/u 0x30 7100 ? 0x30 710f(a) 0x30 7500 ? 0x30 750f(b) 0x30 7900 ? 0x30 790f(c) mbuff0 1 toucan x message buffer 0. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7110 ? 0x30 711f(a) 0x30 7510 ? 0x30 751f(b) 0x30 7910 ? 0x30 791f(c) mbuff1 1 toucan x message buffer 1. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7120 ? 0x30 712f(a) 0x30 7520 ? 0x30 752f(b) 0x30 7920 ? 0x30 792f(c) mbuff2 1 toucan x message buffer 2. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7130 ? 0x30 713f(a) 0x30 7530 ? 0x30 753f(b) 0x30 7930 ? 0x30 793f(c) mbuff3 1 toucan x message buffer 3. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7140 ? 0x30 714f(a) 0x30 7540 ? 0x30 754f(b) 0x30 7940 ? 0x30 794f(c) mbuff4 1 toucan x message buffer 4. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7150 ? 0x30 715f(a) 0x30 7550 ? 0x30 755f(b) 0x30 7950 ? 0x30 795f(c) mbuff5 1 toucan x message buffer 5. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7160 ? 0x30 716f(a) 0x30 7560 ? 0x30 756f(b) 0x30 7960 ? 0x30 796f(c) mbuff6 1 toucan x message buffer 6. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x307170 ? 0x30717f(a) 0x30 7570 ? 0x30 757f(b) 0x30 7970 ? 0x30 797f(c) mbuff7 1 toucan x message buffer 7. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7180 ? 0x30 718f(a) 0x30 7580 ? 0x30 758f(b) 0x30 7980 ? 0x30 798f(c) mbuff8 1 toucan x message buffer 8. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 7190 ? 0x30 719f(a) 0x30 7590 ? 0x30 759f(b) 0x30 7990 ? 0x30 799f(c) mbuff9 1 toucan x message buffer 9. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 71a0 ? 0x30 71af(a) 0x30 75a0 ? 0x30 75af(b) 0x30 79a0 ? 0x30 79af(c) mbuff10 1 toucan x message buffer 10. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 71b0 ? 0x30 71bf(a) 0x30 75b0 ? 0x30 75bf(b) 0x30 79b0 ? 0x30 79bf(c) mbuff11 1 toucan x message buffer 11. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 71c0 ? 0x30 71cf(a) 0x30 75c0 ? 0x30 75cf(b) 0x30 79c0 ? 0x30 79cf(c) mbuff12 1 toucan x message buffer 12. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 71d0 ? 0x30 71df(a) 0x30 75d0 ? 0x30 75df(b) 0x30 79d0 ? 0x30 79df(c) mbuff13 1 toucan x message buffer 13. see figure 16-3 and figure 16-4 for message buffer definitions. table 16-10. toucan register map (continued) access address msb 0 lsb 15 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-24 freescale semiconductor figure 16-8. toucan messag e buffer memory map s/u 0x30 71e0 ? 0x30 71ef(a) 0x30 75e0 ? 0x30 75ef(b) 0x30 79e0 ? 0x30 79ef(c) mbuff14 1 toucan x message buffer 14. see figure 16-3 and figure 16-4 for message buffer definitions. s/u 0x30 71f0 ? 0x30 71ff(a) 0x30 75f0 ? 0x30 75ff(b) 0x30 79f0 ? 0x30 79ff(c) mbuff15 1 toucan x message buffer 15. see figure 16-3 and figure 16-4 for message buffer definitions. 1 the last word of each of the mbuff arrays (address 0x....e ) is reserved and may cause an rcpu exception if read. table 16-10. toucan register map (continued) access address msb 0 lsb 15 toucan message buffer map 0x30 7100, 0x30 7500 0x30 7102, 0x30 7502 message buffer 0 0x30 7104, 0x30 7504 0x30 7106, 0x30 7506 0x30 710d, 0x30 750d 0x30 710e, 0x30 750e 0x30 7110, 0x30 7510 message buffers 1 ? 15 0x30 71ff, 0x30 75ff control/status , 0x30 7900 , 0x30 7902 , 0x30 7904 , 0x30 7906 , 0x30 790d , 0x30 790e , 0x30 7910 , 0x30 79ff id high id low 8-byte data field reserved toucan_a, b, and c addresses: can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-25 16.7.1 toucan module config uration register (canmcr) msb 01234567891011121314 lsb 15 field stop frz ? halt not rdy wake msk soft rst frz ack supv self wake aps stop ack ? sreset 0101_1001_1000_0000 addr 0x30 7080 (canmcr_a); 0x30 7480 (canmcr_b); 0x30 7880 (canmcr_c) figure 16-9. toucan module conf iguration register (canmcr) table 16-11. canmcr bit descriptions bits name description 0 stop low-power stop mode enable. the stop bit may only be set by the cpu. it may be cleared either by the cpu or by the to ucan, if the selfwake bit is set. before asserting the stop mode, the cpu should disable all interrupts in the toucan, otherwise it may be interrupted while in stop mode upon a non wake-up condition. wake-int can still be enabled by setting wakemsk. 0 enable toucan clocks 1 disable toucan clocks 1 frz freeze assertion response. when frz = 1, the toucan can enter debug mode when the imb3 freeze line is asserted or the halt bit is set. clearing this bit field causes the toucan to exit debug mode. refer to section 16.5.1, ?debug mode ? for more information. 0 toucan ignores the imb3 freeze signal and the halt bit in the module configuration register. 1 toucan module enabled to enter debug mode. 2?reserved 3 halt halt toucan s-clock. setting the halt bit has the same effect as assertion of the imb3 freeze signal on the toucan without requiring that freeze be asserted. this bit is set to one after reset. it should be cleared after initializing the message buffers and control registers. toucan message buffer receive and transmit functions are inactive until this bit is cleared. when halt is set, write access to certain registers and bits that are normally read-only is allowed. 0 the toucan operates normally 1 toucan enters debug mode if frz = 1 4 notrdy toucan not ready. this bit indicates that the toucan is either in low-power stop mode or debug mode. this bit is read-only and is set only when the toucan enters low-power stop mode or debug mode. it is cleared once the toucan exits either mode, either by synchronization to the can bus or by the self wake mechanism. 0 toucan has exited low-power stop mode or debug mode. 1 toucan is in low-power stop mode or debug mode. 5 wakemsk wakeup interrupt mask. the wakem sk bit enables wake-up interrupt requests. 0 wake up interrupt is disabled 1 wake up interrupt is enabled can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-26 freescale semiconductor 6 softrst soft reset. when this bit is asserted, the toucan resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (canmcr, canicr, cant cr, imask, a nd iflag). the configuration registers that control the interface with the can bus are not changed (canctrl[0:2] and presdiv). message buffers and receive message masks are also not changed. this allows softrst to be used as a debug feature while the system is running. setting softrst also clears the stop bit in canmcr. after setting softrst, allow one complete bus cycle to elapse for the internal toucan circuitry to completely reset before executing another access to canmcr. the toucan clears this bit once th e internal reset cycle is completed. 0 soft reset cycl e completed 1 soft reset cycle initiated 7 frzack toucan disable. when the toucan enters debug mode, it sets the frzack bit. this bit should be polled to determine if the toucan has entered debug mode. when debug mode is exited, this bit is negated once the toucan prescaler is enabled. this is a read-only bit. 0 the toucan has exited debug mode and the prescaler is enabled 1 the toucan has entered debug mode, and the prescaler is disabled 8 supv supervisor/user data space. the supv bit plac es the toucan registers in either supervisor or user data space. 0 registers with access controlled by the supv bit are accessible in either user or supervisor privilege mode 1 registers with access controlled by the supv bit are restricted to supervisor mode 9 selfwake self wake enable. this bit allows the toucan to wake up when bus activity is detected after the stop bit is set. if this bit is set w hen the toucan enters low-power stop mode, the toucan will monitor the bus for a recessive to dominant transition. if a recessive to dominant transition is detected, the toucan immediately clears the stop bit and restarts its clocks. if a write to canmcr with selfwake set occu rs at the same time a recessive-to-dominant edge appears on the can bus, the bit will not be set, and the module clocks will not stop. the user should verify that this bit has been set by reading canmcr. refer to section 16.5.2, ?low-power stop mode ? for more information on entry into and exit from low-power stop mode. 0 self wake disabled 1 self wake enabled 10 aps auto power save. the aps bit allows the toucan to automatically shut off its clocks to save power when it has no process to execute, and to automatically restart these clocks when it has a task to execute without any cpu intervention. 0 auto power save mode disabled; clocks run normally 1 auto power save mode enabled; clocks stop and restart as needed 11 stopack stop acknowledge. when the toucan is placed in low-power stop mode and shuts down its clocks, it sets the stopack bit. this bit should be polled to determine if the toucan has entered low-power stop mode. when the toucan exits low-power stop mode, the stopack bit is cleared once the toucan?s clocks are running. 0 the toucan is not in low-power stop mode and its clocks are running 1 the toucan has entered low-power stop mode and its clocks are stopped 12:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in toucan implementations that use hard ware interrupt arbitration. table 16-11. canmcr bit descriptions (continued) bits name description can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-27 16.7.2 toucan test configuration register cantcr ? toucan test configur ation register0x30 7082, 0x30 7482, 0x30 7882 this register is used for factory test only. 16.7.3 toucan interrupt conf iguration register (canicr) 16.7.4 control regi ster 0 (canctrl0) msb 01234 5 6 7 8 9 1011121314 lsb 15 field ? irl ilbs ? sreset 0000_0000_00 00_1111 addr 0x30 7084 (canicr_a); 0x30 7484 (canicr_b); 0x30 7884 (canicr_c) figure 16-10. toucan interrupt configuration register (canicr) table 16-12. canicr bit descriptions bits name description 0:4 ? reserved 5:7 irl interrupt request level. when the toucan generates an interrupt request, this field determines which of the interrupt request signals is asserted. 8:9 ilbs interrupt level byte select. this field selects one of four time-multiplexed slots during which the interrupt request is asserted. the ilbs and ir l fields together select one of 32 effective interrupt levels. 00 levels 0 to7 01 levels 8 to 15 10 levels 16 to 23 11 levels 24 to 31 10:15 ? reserved msb 0 1 2 3 4 5 6 7 8 9 10 11121314 lsb 15 field boffmsk errmsk ? rxmode txmode canctrl1 sreset 0000_0000_0000_0000 addr 0x30 7086 (canctrl0_a); 0x30 7486 (canctrl0_b); 0x30 7886 (canctrl0_c) figure 16-11. control register 0 (canctrl0) can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-28 freescale semiconductor 16.7.5 control regi ster 1 (canctrl1) table 16-13. canctrl0 bit descriptions bits name description 0 boffmsk bus off interrupt mask. the boff mask bit provides a mask for the bus off interrupt. 0 bus off interrupt disabled 1 bus off interrupt enabled 1 errmsk error interrupt mask. the errmsk bit provides a mask for the error interrupt. 0 error interrupt disabled 1 error interrupt enabled 2:3 ? reserved 4:5 rxmode receive signal configuration control. th ese bits control the conf iguration of the cnrx0 signals. refer to table 16-14 . 6:7 txmode transmit signal configuration control. this bit field controls the configuration of the cntx0 signals. refer to table 16-15 . 8:15 canctrl1 see table 16-16 and section 16.7.5, ?control register 1 (canctrl1) .? table 16-14. rx mode[1:0] configuration signal rx1 rx0 receive signal configuration cnrx0 x 0 0 cnrx0 signal is interpreted as a dominant bit 1 cnrx0 signal is interpreted as a recessive bit x 1 0 cnrx0 signal is interpreted as a recessive bit 1 cnrx0 signal is interpreted as a dominant bit table 16-15. transmit signal configuration txmode[1:0] transmitsignal configuration 00 full cmos 1 ; positive polarity (cntx0 = 0 is a dominant level) 1 full cmos drive indicates that both dominant and recessive levels are driven by the chip. 01 full cmos 1 ; negative polarity (cntx0 = 1 is a dominant level) 1x open drain 2 ; positive polarity 2 open drain drive indicates that only a dominant level is driven by the chip. during a recessive level, the cntx0 signal is disa bled (three stated), and t he electrical level is achieved by external pull-up/pull-down devices. the assertion of both tx mode bits causes the polarity inversion to be cancelled (open drain mode forces the polarity to be positive). msb 01234567 8 9 10 11 12 1314 lsb 15 field canctrl0 samp ? tsync lbuf ? propseg sreset 0000_0000_0000_0000 addr 0x30 7086 (canctrl1_a); 0x30 7486 (c anctrl1_b); 0x30 7886 (canctrl1_c) figure 16-12. control register 1 (canctrl1) can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-29 16.7.6 prescaler divide register (presdiv) table 16-16. canctrl1 bit descriptions bits name description 0:7 canctrl0 see table 16-13 8 samp sampling mode. the samp bit determines whether the toucan module will sample each received bit one time or three times to determine its value. 0 one sample, taken at the end of phase buffer segment one, is used to determine the value of the received bit. 1 three samples are used to determine the value of the received bit. the samples are taken at the normal sample point and at the two preceding periods of the s-clock. 9?reserved 10 tsync timer synchronize mode. the tsync bi t enables the mechanism that resets the free-running timer each time a message is received in message buffer zero. this feature provides the means to synchronize multiple toucan stations with a special ?sync? message (global network time). 0 timer synchronization disabled. 1 timer synchronization enabled. note: there can be a bit clock skew of four to five counts between different toucan modules that are using this feature on the same network. 11 lbuf lowest buffer transmitted first. the lbuf bit defines the transmit-first scheme. 0 message buffer with lowest id is transmitted first. 1 lowest numbered buffer is transmitted first. 12 ? reserved 13:15 propseg propagation segment time. propseg defines the length of the propagation segment in the bit time. the valid programmed values are zero to seven. the propagation segment time is calculated as follows: propagation segment time = (propseg + 1) time quanta where 1 time quantum = 1 serial clock (s-clock) period msb 01234567891011121314 lsb 15 field presdiv canctrl2 sreset 0000_0000_0000_0000 addr 0x30 7088 (presdiv_a); 0x30 7488 (presdiv_b); 0x30 7888 (presdiv_c) figure 16-13. prescaler divide register can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-30 freescale semiconductor 16.7.7 control regi ster 2 (canctrl2) table 16-17. presdiv bit descriptions bits name description 0:7 presdiv prescaler divide factor. presdiv determines the ratio between the system clock frequency and the serial clock (s-clock). the s-clock is determined by the following calculation: eqn. 16-1 the reset value of presdiv is 0x00, which fo rces the s-clock to default to the same frequency as the system clock. the vali d programmed values are 0 through 255. 8:15 canctrl2 see table 16-18 . msb 01234567 8 9 1011121314 lsb 15 field presdiv rjw pseg1 pseg2 sreset 0000_0000_0000_0000 addr 0x30 7088 (canctrl2_a); 0x30 7488 (canctrl2_b); 0x30 7888 (canctrl2_c) figure 16-14. control register 2 (canctrl2) table 16-18. canctrl2 bit descriptions bits name description 0:7 presdiv see table 16-17 . 8:9 rjw resynchronization jump width. the rjw field defines the maximum number of time quanta a bit time may be changed during resynchronization. the valid programmed values are zero through three. the resynchronization jump width is calculated as follows: resynchronizaton jump width = (rjw + 1) time quanta 10:12 pseg1 pseg1[2:0] ? phase buffer segment 1. the pseg1 field defi nes the length of phase buffer segment one in the bit time. the valid pr ogrammed values are zero through seven. the length of phase buffer segment 1 is calculated as follows: phase buffer segment 1 = (pseg1 + 1) time quanta 13:15 pseg2 pseg2 ? phase buffer se gment 2. the pseg2 field defines the length of phase buffer segment two in the bit time. the valid pr ogrammed values are zero through seven. the length of phase buffer segment two is calculated as follows: phase buffer segment 2 = (pseg2 + 1) time quanta s-clock f sys presdiv 1 + ----------------------------------- - = can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-31 16.7.8 free running timer (timer) 16.7.9 receive global mask re gisters (rxgmskhi, rxgmsklo) msb 01234567891011121314 lsb 15 field timer sreset 0000_0000_0000_0000 addr 0x30 708a (timer_a); 0x30 748a (timer_b); 0x30 788a (timer_c) figure 16-15. free running timer register (timer) table 16-19. timer bit descriptions bits name description 0:15 timer the free running timer counter can be read and written by the cpu. the timer starts from zero after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the toucan bit-clock. during a message, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it increments at the nominal bit rate. the timer value is captured at the beginning of the identifier field of any frame on the can bus. the captured value is written into the ?t ime stamp? entry in a message buffer after a successful reception or transmission of a message. msb 0123456789101112131415 field mid 28 mid 27 mid 26 mid 25 mid 24 mid 23 mid 22 mid 21 mid 20 mid 19 mid 18 01mid 17 mid 16 mid 15 sreset 1111111111101111 addr 0x30 7090 (rxgmskhi_a); 0x30 7490 (r xgmskhi_b); 0x30 7890 (rxgmskhi_c); 0x30 7092 (rxgmsklo_a); 0x30 7492 (rxgmsklo_b); 0x30 7892 (rxgmsklo_c) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field mid 14 mid 13 mid 12 mid 11 mid 10 mid 9 mid 8 mid 7 mid 6 mid 5 mid 4 mid 3 mid 2 mid 1 mid 0 0 sreset 1111111111111110 figure 16-16. receive global mask register: high (rxgmskhi), low (rxgmsklo) can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-32 freescale semiconductor 16.7.10 receive buffer 14 mask re gisters (rx14mskhi, rx14msklo) the receive buffer 14 mask registers have the same structure as the re ceive global mask registers and are used to mask buffer 14. table 16-20. rxgmskhi, rxgmsklo bit descriptions bits name description 0:31 mid x the receive global mask registers use four bytes. the mask bits are applied to all receive-identifiers, excluding receive-buffers 14 and 15, which have their own specific mask registers. base id mask bits mid[28:18] are used to mask standard or extended format frames. extended id bits mid[17:0] are used to mask only extended format frames. the rtr/srr bit of a received frame is never compared to the corresponding bit in the message buffer id field. however, remote request frames (rtr = 1) once received, are never stored into the message buffers. rtr mask bit locations in the mask registers (bits 11 and 31) are always zero, regardless of any write to these bits. the ide bit of a received frame is always compared to determine if the message contains a standard or extended identifier. its location in the mask registers (bit 12) is always one, regardless of any write to this bit. msb 0123456789101112131415 field mid2 8 mid2 7 mid2 6 mid2 5 mid2 4 mid2 3 mid2 2 mid2 1 mid2 0 mid1 9 mid1 8 01mid 17 mid 16 mid 15 sreset 1111111111101111 addr 0x30 7094 (rx14mskhi_a); 0x30 7494 (rx14mskhi_b); 0x30 7894 (rx14mskhi_c); 0x30 7096 (rx14msklo_a); 0x30 7496 (rx14msklo_b); 0x30 7896 (rx14msklo_c) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field mid1 4 mid1 3 mid1 2 mid1 1 mid1 0 mid9 mid8 mid7 mid6 mi d5 mid4 mid3 mid2 mid 1 mid 0 0 sreset 1111111111111110 figure 16-17. receive buffer 14 mask registers: high (rx14mskhi), low (rx14msklo) table 16-21. rx14mskhi, rx14 msklo field descriptions bits name description 0:31 mid x the receive buffer 14 mask registers use 4 bytes. base id mask bits mid[28:18] are used to mask standard or extended format frames. extended id bits mid[17:0] are used to mask only extended format frames. the rtr/srr bit of a received frame is never compared to the corresponding bit in the message buffer id field. however, remote request frames (rtr = 1) once received, are never stored into the message buffers. rtr mask bit locations in the mask registers (bits 11 and 31) are always zero, regardless of any write to these bits. the ide bit of a received frame is always compared to determine if the message contains a standard or extended identifier. its location in the mask registers (bit 12) is always one, regardless of any write to this bit. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-33 16.7.11 receive buffer 15 mask re gisters (rx15mskhi, rx15msklo) the receive buffer 15 mask registers have the same structure as the re ceive global mask registers and are used to mask buffer 15. 16.7.12 error and status register (estat) this register reflects various erro r conditions, general stat us, and has the enable bits for three of the toucan interrupt sources. the reported error conditions are those which ha ve occurred since the last time the register was read. a read clears these bits to zero. msb 0123456789101112131415 field mid 28 mid 27 mid 26 mid 25 mid 24 mid 23 mid 22 mid 21 mid 20 mid 19 mid 18 01mid 17 mid 16 mid 15 sreset 1111111111101111 addr 0x30 7098 (rx15mskhi_a); 0x30 7498 (rx15mskhi_b); 0x30 7898 (rx14mskhi_c); 0x30 709a (rx14msklo_a); 0x30 749a (rx14msklo_b); 0x30 789a (rx14msklo_c) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field mid 14 mid 13 mid 12 mid 11 mid 10 mid 9 mid 8 mid 7 mid 6 mid 5 mid 4 mid 3 mid 2 mid 1 mid 0 0 sreset 1111111111111110 figure 16-18. receive buffer 15 mask registers: high (rx15mskhi), low (rx15msklo) table 16-22. rx15mskhi, rx15 msklo field descriptions bits name description 0:31 mid x the receive buffer 14 mask registers use 4 bytes. base id mask bits mid[28:18] are used to mask standard or extended format frames. extended id bits mid[17:0] are used to mask only extended format frames. the rtr/srr bit of a received frame is never compared to the corresponding bit in the message buffer id field. however, remote request frames (rtr = 1) once received, are never stored into the message buffers. rtr mask bit locations in the mask registers (bits 11 and 31) are always zero, regardless of any write to these bits. the ide bit of a received frame is always compared to determine if the message contains a standard or extended identifier. its location in the mask registers (bit 12) is always one, regardless of any write to this bit. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field bit err ack err crc err form err stuff err tx warn rx warn idle tx/rx fcs ? boff int err int wake int sreset 0000_0000_0000_0000 addr 0x30 70a0 (estat_a); 0x30 74a0 (estat_b); 0x30 78a0 (estat_c) figure 16-19. error and status register (estat) can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-34 freescale semiconductor table 16-23. estat bit descriptions bits name description 0:1 biterr transmit bit error. the biterr[1:0] field is used to indicate when a transmit bit error occurs. refer to table 16-24 . note: the transmit bit error field is not modified during the arbitration field or the ack slot bit time of a message, or by a transmitter that detects dominant bits while sending a passive error frame. 2 ackerr acknowledge error. the ackerr bit indicates whether an acknowledgment has been correctly received for a transmitted message. 0 no ack error was detected since the last read of this register 1 an ack error was detected since the last read of this register 3 crcerr cyclic redundancy check error. the crcerr bit indicates whether or not the crc of the last transmitted or re ceived message was valid. 0 no crc error was detected since the last read of this register 1 a crc error was detected since the last read of this register 4 formerr message format error. the formerr bit indicates whether or not the message format of the last transmitted or re ceived message was correct. 0 no format error was detected since the last read of this register 1 a format error was detected since the last read of this register 5 stufferr bit stuff error. the stufferr bit indicates whether or not the bit stuffing that occurred in the last transmitted or re ceived message was correct. 0 no bit stuffing error was detected sinc e the last read of this register 1 a bit stuffing error was detected since the last read of this register 6 txwarn transmit error status flag. the txwarn st atus flag reflects the status of the toucan transmit error counter. 0 transmit error counter < 96 1 transmit error counter 96 7 rxwarn receiver error status flag. the rxwarn stat us flag reflects the status of the toucan receive error counter. 0 receive error counter < 96 1 receive error counter 96 8 idle idle status. the idle bit indicates when there is activity on the can bus. 0 the can bus is not idle 1 the can bus is idle 9tx/rx transmit/receive status. the tx/rx bit indicate s when the toucan module is transmitting or receiving a message. tx/rx has no meaning when idle = 1. 0 the toucan is receiving a message if idle = 0 1 the toucan is transmitting a message if idle = 0 10:11 fcs fault confinement state. the fcs[1:0] fi eld describes the state of the toucan. refer to table 16-25 . if the softrst bit in canmcr is asserted while t he toucan is in the bus off state, the error and status register is reset, in cluding fcs[1:0]. however, as soon as the toucan exits reset, fcs[1:0] bits will again reflect the bus off state. refer to section 16.3.4, ?error counters ? for more information on entry into and exit from the various fault confinement states. 12 ? reserved can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-35 16.7.13 interrupt mask register (imask) 13 boffint bus off interrupt. the boffint bit is used to request an interrupt when the toucan enters the bus off state. 0 no bus off interrupt requested 1 when the toucan state changes to bus off, this bit is set, and if the boffmsk bit in canctrl0 is set, an interrupt request is generated. this interrupt is not requested after reset. 14 errint error interrupt. the errint bit is used to request an interrupt when the toucan detects a transmit or receive error. 0 no error interrupt request 1 if an event which causes one of the error bits in the error and status register to be set occurs, the error interrupt bit is set. if the errmsk bit in canctrl0 is set, an interrupt request is generated. to clear this bit, first read it as a one, t hen write as a zero. writing a one has no effect. 15 wakeint wake interrupt. the wakeint bit indicates that bus activity has been detected while the toucan module is in low-power stop mode. 0 no wake interrupt requested 1 when the toucan is in low-power stop mode and a recessive to dominant transition is detected on the can bus, this bit is set. if the wakemsk bit is set in canmcr, an interrupt request is generated. table 16-24. transmit bit error status biterr[1:0] bit error status 00 no transmit bit error 01 at least one bit sent as dominant was received as recessive 10 at least one bit sent as recessive was received as dominant 11 not used table 16-25. fault confinement state encoding fcs[1:0] bus state 00 error active 01 error passive 1x bus off msb 01234567891011121314 lsb 15 field imaskh imaskl sreset 0000_0000_0000_0000 addr 0x30 70a2 (imask_a); 0x30 74 a2 (imask_b); 0x30 78a2 (imask_c) figure 16-20. interrupt mask register (imask) table 16-23. estat bit descriptions (continued) bits name description can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-36 freescale semiconductor 16.7.14 interrupt flag register (iflag) 16.7.15 error counters (rxectr, txectr) table 16-26. imask bit descriptions bits name description 0:7, 8:15 imaskh, imaskl imask contains two 8-bit fields, imaskh and imaskl. imask can be accessed with a 16-bit read or write, and imaskh and imaskl can be accessed with byte reads or writes. imask contains one interrupt ma sk bit per buffer. it allows the cpu to designate which buffers will generate interrupts after successful transmission/reception. setting a bit in imask enables interrupt requests for the corresponding message buffer. msb 01234567891011121314 lsb 15 field iflagh iflagl sreset 0000_0000_0000_0000 addr 0x30 70a4 (iflag_a); 0x30 74a 4 (iflag_b); 0x30 78a4 (iflag_c) figure 16-21. interrupt flag register (iflag) table 16-27. iflag bit descriptions bits name description 0:7, 8:15 iflagh, iflagl iflag contains two 8-bit fields, iflagh and iflagl. iflag can be accessed with a 16-bit read or write, and iflagh and iflagl can be accessed with byte reads or writes. iflag contains one interrupt flag bit per buffer . each successful transmission/reception sets the corresponding iflag bit and, if the correspon ding imask bit is set, an interrupt request will be generated. to clear an interrupt flag, first read the flag as a one, and then write it as a zero. should a new flag setting event occur between the time that the cpu reads the flag as a one and writes the flag as a zero, the flag is not clea red. this register can be written to zeros only. msb 01234567891011121314 lsb 15 field rxectr txectr sreset 0000_0000_0000_0000 addr 0x30 70a6 (rxectr_a/txectr_a); 0x30 74a6 (rxectr_b/txectr_b); 0x30 78a6 (txectr_c/txectr_c) figure 16-22. receive error counter (rxectr), transmit error counter (txectr) table 16-28. rxectr, txectr bit descriptions bits name description 0:7, 8:15 rxectr, txectr both counters are read only, except when the toucan is in test or debug mode. can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 16-37 can 2.0b controller module mpc561/mpc563 reference manual, rev. 1.2 16-38 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-1 chapter 17 modular input/output subsystem (mios14) the modular i/o system (mios) consis ts of a library of flexible i/o a nd timer functions including i/o port, counters, input capture, output comp are, pulse and period measurement, and pwm. because the mios14 is composed of submodules, it is easily conf igurable for different kinds of applications. the mios14 is composed of the following submodules: ? one mios14 bus interface submodule (mbism) ? one mios14 counter pr escaler submodule (mcpsm) ? six mios14 modulus count er submodules (mmcsm) ? 10 mios14 double action submodules (mdasm) ? 12 mios14 pulse-width modulation submodules (mpwmsm) ? one mios14 16-bit parallel port i/o submodule (mpiosm) ? two interrupt request submodules (mirsm) 17.1 block diagram figure 17-1 is a block diagram of the mios14. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-2 freescale semiconductor figure 17-1. mpc561/mpc563 mios14 block diagram bus interface unit submodule 16-bit counter bus set modular i/o bus (miob) mda30 mda29 mda15 mda14 (to all submodules) imb3 bus mda28 mda27 submodules interrupt mda28 mda27 mda13 mda11 mda14 mda13 pwm19 mda11 pwm17 pwm16 mda31 mda30 mda12 mdasm 11 mdasm12 mdasm13 mdasm14 mdasm15 mdasm 27 mdasm28 mdasm29 mdasm30 mdasm31 mda12 mda31 cb23 pwm18 cb8 cb22 cb6 cb7 mcpsm mpwm21 pwm pwmsm21 mpwm16 pwm mpwmsm16 mpwm5 pwm pwmsm5 mpwm0 pwm pwmsm0 channel and i/o signals: 6xpwmsm 6xpwmsm double action double action double action double action double action double action double action double action double action double action counter prescaler mirsm0/1 cb24 channel and i/o signals: mpiosm32 mpio32b0 mpio32b15 modulus counter mmcsm6 c l modulus counter mmcsm7 c l modulus counter mmcsm8 c l modulus counter mmcsm22 c l modulus counter mmcsm23 c l modulus counter mmcsm24 c l modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-3 17.2 mios14 key features the basic features of th e mios14 are as follows: ? modular architecture at the silicon implem entation level ? disable capability in each submodule to allow power saving when its function is not needed ? six 16-bit counter buses to allow action submodules to use counter data ? when not used for timing functions, every channel si gnal can be used as a port signal: i/o, output only or input only, depending on the channel function. ? submodules? signal status bits re flect the status of the signal ? mios14 counter prescaler submodule (mcpsm): ? centralized counter clock generator ? programmable 4-bit modulus down-counter ? wide range of possible division ratios: 2 through 16 ? count inhibit under software control ? mios14 modulus counter submodule (mmcsm): ? programmable 16-bit modulus up- counter with built-in programma ble 8-bit prescaler clocked by mcpsm output. ? maximum increment frequency of the counter: ? clocked by the internal mcpsm output: f sys / 2 ? clocked by the external signal: f sys / 4 ? flag setting and possible interrupt generation on overflow of the up-counter ? time counter on internal clock with interr upt capability after a pre-determined time ? optional signal usable as an external event counter (pulse accumula tor) with overflow and interrupt capability after a pre-dete rmined number of external events. ? usable as a regular free-running up-counter ? capable of driving a dedicated 16-bit counter bus to provide timing information to action submodules (the value driven is the cont ents of the 16-bit up-counter register) ? optional signal to externally force a lo ad to the counter with modulus value ? mios14 double action submodule (mdasm): ? versatile 16-bit dual ac tion unit allowing two events to occur before software intervention is required ? six software selectable modes allowing the mdasm to perform pulse width and period measurements, pwm generation, si ngle input capture and output compare operations as well as port functions ? software selection of one of the six possibl e 16-bit counter buses us ed for timing operations ? flag setting and possible interrupt ge neration after mdasm action completion ? software selection of output pulse polarity ? software selection of tote m-pole or open-drain output ? software readable output signal status modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-4 freescale semiconductor ? possible use of signal as i/o por t when mdasm function is not needed ? mios14 pulse width modula tion submodule (mpwmsm): ? output pulse width modulated (pwm) signa l generation with no software involvement ? built-in 8-bit programmable pr escaler clocked by the mcpsm ? pwm period and pulse width values provided by software: ? double-buffered for glitch-free period and pulse width changes ? two-cycle minimum output pe riod/pulse-width increment (50 ns @ 40 mhz) ? 50% duty-cycle output ma ximum frequency: 10 mhz ? up to 16 bits output pulse width resolution ? wide range of periods: ? 16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to 6.71 s (with 102.4 s steps) ? eight bits of resoluti on: period range from 12.8 s (with 50-ns steps) to 26.2 ms (with 102.4- s steps) ? wide range of frequencies: ? maximum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-2 prescaler selection: 305 hz (3.27 ms) ? minimum output frequency at f sys = 40 mhz with 16 bi ts of resolution and divide-by-4096 prescaler selection: 0.15 hz (6.7 s) ? maximum output frequency at f sys = 40 mhz with eight bits of resolution and divide-by-2 pres caler selection: 78125 hz (12.8 s) ? minimum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-4096 prescaler se lection: 38.14 hz (8.2 ms) ? programmable duty cy cle from 0% to 100% ? possible interrupt generation after every period ? software selectable output pulse polarity ? software readable output signal status ? possible use of signal as i/o por t when pwm function is not needed ? mios14 16-bit parallel por t i/o submodule (mpiosm): ? up to 16 parallel i/ o signals per mpiosm ? uses four 16-bit registers in the address space , one for data and one for direction and two reserved ? simple data direction regi ster (ddr) concept for sel ection of signal direction 17.2.1 submodule numbering, naming, and addressing a block is a group of four 16-bit registers. each of the blocks within the mios14 addressing range is assigned a block number. the first block is located at the base address of the mios14. the blocks are numbered sequentiall y starting from 0. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-5 every submodule instantiation is also assigned a num ber. the number of a given submodule is the block number of the first block of this submodule. a submodule is assigned a na me made of its acronym fo llowed by its s ubmodule number. for example, if submodule number 18 were an mpwmsm , it would be named mpwmsm18. this numbering convention does not apply to the mbism, the mcpsm, and the mirsms. the mbism and the mcpsm are unique in the mios14 and do not need a number. the mirsms are numbered incrementally starting from zero. the mios14 base address is defined at the chip level and is referred to as the ?mios14 base address.? the mios14 addressable range is four kbytes. the base address of a given implem ented submodule within the mios14 is the sum of the base address of the mios14 and the submodule number multiplied by eight. refer to table 17-1 . this does not apply to the mbism, the mcpsm a nd the mirsms. for these submodules, refer to the mios14 memory map in figure 17-2 . 17.2.2 signal naming convention in figure 17-2 , mdasm signals have a prefix mda, mpwmsm signals have a prefix of mpwm and the port signals have a prefix of mpio. the modulus c ounter clock and load signals are multiplexed with mdasm signals. the mios14 input and output signal names are compos ed of five fields acc ording to the following convention: ??m? ? modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-6 freescale semiconductor ? for example a mdasm plac ed as submodule number n would have its corresponding channel i/o signal named mdan ? mpwmsm: ? submodule short_prefix: ?pwm? ? signal attribute suffix: none ? for example a mpwmsm placed as submodule number n would have its corresponding channel i/o signal named mpwmn ?mpiosm: ? submodule short_prefix: ?pio? ? signal attribute suffix: b ? for example a mpiosm placed as submodule number n would have its corresponding i/o signals named mpionb0 to mpionb15 for bit-0 to bit-15, respectively. in the mios14, some signals are multiplexed between submodules using the same signal names for the inputs and outputs which are connected as shown in table 17-1 . 17.3 mios14 configuration the complete mios14 submodule and si gnal configuration is shown in table 17-1 . table 17-1. mios14 configuration description sub- module type bloc k no. connected to: mirs m no. mirsm bit position base address offset signal function input signal name output signal name alternate signal name cba cbb cbc cbd bsl0= 0 bsl1= 0 bsl0= 1 bsl1= 0 bsl0=0 bsl1=1 bsl0= 1 bsl1= 1 pwmsm 0 0 0 0x30 6000 pwm, i/o mpwm0 mpwm0 mdi1 pwmsm 1 0 1 0x30 6008 pwm, i/o mpwm1 mpwm1 mdo2 pwmsm 2 0 2 0x30 6010 pwm, i/o mpwm2 mpwm2 ppm_tx1 pwmsm 3 0 3 0x30 6018 pwm, i/o mpwm3 mpwm3 ppm_rx1 pwmsm 4 0 4 0x30 6020 pwm, i/o mpwm4 mpwm4 mdo6/ mpio32b6 pwmsm 5 0 5 0x30 6028 pwm, i/o mpwm5 mpwm5 mpio32b7 mmcsm 6 cb6 0 6 0x30 6030 clock in mda11 load in mda12 mmcsm 7 cb7 0 7 0x30 6038 clock in mda30 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-7 load in mda31 mmcsm 8 cb8 0 8 0x30 6040 clock in mpwm 16 load in mpwm 17 mdo3 reserve d 9-10 mdasm 11 cb6 cb22 cb7 cb8 0 11 0x30 6058 channel i/o mda11 mda11 mdasm 12 cb6 cb22 cb7 cb8 0 12 0x30 6060 channel i/o mda12 mda12 mdasm 13 cb6 cb22 cb23 cb24 0 13 0x30 6068 channel i/o mda13 mda13 mdasm 14 cb6 cb22 cb23 cb24 0 14 0x30 6070 channel i/o mda14 mda14 mdasm 15 cb6 cb22 cb23 cb24 0 15 0x30 6078 channel i/o mda15 mda15 pwmsm 16 1 0 0x30 6080 pwm, i/o mpwm 16 mpwm 16 pwmsm 17 1 1 0x30 6088 pwm, i/o mpwm 17 mpwm 17 mdo3 pwmsm 18 1 2 0x30 6090 pwm, i/o mpwm 18 mpwm 18 mdo6 pwmsm 19 1 3 0x30 6098 pwm, i/o mpwm 19 mpwm 19 mdo7 pwmsm 20 1 4 0x30 60a0 pwm, i/o mpwm 20 mpwm 20 mpio32b8 pwmsm 21 1 5 0x30 60a8 pwm, i/o mpwm 21 mpwm 21 mpio32b9 mmcsm 22 cb22 1 6 0x30 60b0 clock in mda13 load in mda14 mmcsm 23 cb23 1 7 0x30 60b8 clock in mda27 load in mda28 mmcsm 24 cb24 1 8 0x30 60c0 clock in mpwm 18 mdo6 table 17-1. mios14 configurat ion description (continued) sub- module type bloc k no. connected to: mirs m no. mirsm bit position base address offset signal function input signal name output signal name alternate signal name cba cbb cbc cbd bsl0= 0 bsl1= 0 bsl0= 1 bsl1= 0 bsl0=0 bsl1=1 bsl0= 1 bsl1= 1 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-8 freescale semiconductor load in mpwm 19 mdo7 reserve d 25-2 6 mdasm 27 cb6 cb22 cb23 cb24 1 11 0x30 60d8 channel i/o mda27 mda27 mdasm 28 cb6 cb22 cb23 cb24 1 12 0x30 60e0 channel i/o mda28 mda28 mdasm 29 cb6 cb22 cb7 cb8 1 13 0x30 60e8 channel i/o mda29 mda29 mdasm 30 cb6 cb22 cb7 cb8 1 14 0x30 60f0 channel i/o mda30 mda30 mdasm 31 cb6 cb22 cb7 cb8 1 15 0x30 60f8 channel i/o mda31 mda31 mpios m 32 0x30 6100 gpio mpio32 b0 mpio32 b0 vf0 /mdo1 gpio mpio32 b1 mpio32 b1 vf1 /mcko gpio mpio32 b2 mpio32 b2 vf2 /msei gpio mpio32 b3 mpio32 b3 vfls0 /mseo gpio mpio32 b4 mpio32 b4 vfls1 gpio mpio32 b5 mpio32 b5 mdo5 gpio mpio32 b6 mpio32 b6 mpwm4/ mdo6 gpio mpio32 b7 mpio32 b7 mpwm5 gpio mpio32 b8 mpio32 b8 mpwm20 gpio mpio32 b9 mpio32 b9 mpwm21 gpio mpio32 b10 mpio32 b10 ppm_ tsync gpio mpio32 b11 mpio32 b11 c_cnrx0 table 17-1. mios14 configurat ion description (continued) sub- module type bloc k no. connected to: mirs m no. mirsm bit position base address offset signal function input signal name output signal name alternate signal name cba cbb cbc cbd bsl0= 0 bsl1= 0 bsl0= 1 bsl1= 0 bsl0=0 bsl1=1 bsl0= 1 bsl1= 1 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-9 17.3.1 mios14 signals the mios14 requires 34 signals: 10 mdasm signals , 8 dedicated mpwmsm signals, 12 dedicated mpiosm signals and 4 signals ar e shared between the mpwmsm and mpiosm. the required signal function on shared signals is chosen using the pdmc r2 register in the usiu. the usage of all mios14 signals is shown in the block diagram of figure 17-1 and in the configuration description of table 17-1 . 17.3.2 mios14 bus system the internal bus system within the mios14 is cal led the modular i/o bus (miob). the miob makes communications possible between any submodule and the imb3 bus master through the mbism. the miob is divided into three dedicated buses: gpio mpio32 b12 mpio32 b12 c_cntx0 gpio mpio32 b13 mpio32 b13 ppm_tcl k gpio mpio32 b14 mpio32 b14 ppm_rx0 gpio mpio32 b15 mpio32 b15 ppm_tx0 reserve d 33- 255 mbism 256 0x30 6800 reserve d 257 mcpsm 258 0x30 6810 reserve d 259- 383 mirsm0 384- 391 0x30 6c00 mirsm1 392- 399 0x30 6c40 reserve d 400- 511 table 17-1. mios14 configurat ion description (continued) sub- module type bloc k no. connected to: mirs m no. mirsm bit position base address offset signal function input signal name output signal name alternate signal name cba cbb cbc cbd bsl0= 0 bsl1= 0 bsl0= 1 bsl1= 0 bsl0=0 bsl1=1 bsl0= 1 bsl1= 1 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-10 freescale semiconductor ? the read/write and control bus ? the request bus ? the counter bus set 17.3.3 read/write and control bus the read/write and control bus (rwcb) allows read and write data transfer s to and from any i/o submodule through the mbism. it include s signals for data and addresses as well as control signals. the control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master accesses. 17.3.4 request bus the request bus (rqb) provides interrupt request signals along with i/o submodule identification and priority information to the mbism. note some submodules do not generate inte rrupts and are therefore independent of the rqb. 17.3.5 counter bus set the 16-bit counter bus set (cbs) is a set of six 16-bit counter buses. the cbs makes it possible to transfer information between submodules. t ypically, counter submodul es drive the cbs, while action submodules process the data on these buses. note, however, that some submodules are self -contained and therefore independent of the counter bus set. 17.4 mios14 programming model the address space of the mios14 consist of 4 k bytes starting at the base address of the module (0x306000). the overall address map organization is shown in figure 17-2 . all mios14 unimplemented locations within the addressable range, return a logic 0 when accessed. in addition, the internal tea (transfer error acknowle dge) signal is asserted. all unused bits within mios14 regi sters return a 0 when accessed. 17.4.1 bus error support a bus error signal is generated when access to an unimp lemented or reserved 16-bi t register is attempted, or when a priviledge violation occurs. a bus error is generated under any of the following conditions: ? attempted access to unimplemented 16-bit regi sters within the decoded register block boundary. ? attempted user access to supervisor registers ? attempted access to test regi sters when not in test mode ? attempted write to read-only registers modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-11 17.4.2 wait states the mios14 does not generate wait states. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-12 freescale semiconductor reserved supervisor/ mbism mcpsm base address 0x30 6c00 0x30 6fff 0x30 6800 reserved reserved unrestricted supervisor supervisor 0x30 6c00 0x30 6c04 0x30 6c06 0x30 6c30 0x30 6000 0x30 6810 reserved mios1lvl0 reserved mios14rpr0 mios1er0 reserved mios14sr0 submodules 31 to 16 submodules 15 to 0 channels 0x30 6c02 0x30 6c40 0x30 6c40 0x30 6c44 0x30 6c46 0x30 6c70 reserved mios14lvl1 reserved mios14rpr 1 mios14er1 mios14sr1 reserved 0x30 6c42 mpwmsm0 mpwmsm1 mpwmsm2 mpwmsm3 0x30 6000 0x30 6008 0x30 6010 0x30 6018 mpwmsm4 mmcsm6 mdasm11 0x30 6030 0x30 6058 mdasm12 mdasm13 mdasm14 mdasm15 0x30 6060 0x30 6068 0x30 6070 0x30 6078 mpwmsm16 mpwmsm17 mpwmsm18 mpwmsm19 0x30 6088 0x30 6098 0x30 6080 0x30 6090 mmcsm22 mdasm27 0x30 60b0 0x30 60d8 mdasm28 mdasm29 mdasm30 0x30 60e8 0x30 60f8 mdasm31 mpiosm32 0x30 6100 0x30 60e0 0x30 60f0 0x30 6020 mpwmsm5 0x30 6028 mmcsm7 0x30 6038 mmcsm8 0x30 6040 mmcsm23 0x30 60b8 mmcsm24 0x30 60c0 mpwmsm20 0x30 60a0 mpwmsm21 0x30 60a8 mirsm1 mirsm0 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-13 figure 17-2. mios14 memory map 17.5 mios14 i/o ports each signal of each submodule can be us ed as an input, output, or i/o port: 17.6 mios14 bus interface submodule (mbism) the mios14 bus interface submodule (m bism) is used as an interface between th e miob (modular i/o bus) and the imb3. it allows the cpu to communicate with the mios14 submodules. 17.6.1 mios14 bus interface (mbism) registers table 17-3 is the address map for the mbism submodule. 17.6.1.1 mios14 test and signal control register (mios14tpcr) this register is used for mios14 fa ctory testing and to control the vf and vfls signal usage. control of other multiplexed functions is in the pdmcr2 register. table 17-2. mios14 i/o ports submodule number of pins per module type mpiosm 16 i/o mmcsm 2 i mdasm 1 i/o mpwmsm 1 i/o msb 01234567891011121314 lsb 15 0x30 6800 mios14 test and signal control register (mios14tpcr) 0x30 6802 mios14 vector register (mios14vect) -reserved 0x30 6804 mios14 module-version number register (mios14vnr) 0x30 6806 mios14 module cont rol register (mios14mcr) 0x30 6808 reserved 0x30 680a reserved 0x30 680c reserved 0x30 680e reserved figure 17-3. mbism registers modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-14 freescale semiconductor 17.6.1.2 mios14 vector register (mios14vect) this register is reserved and is shown for information purposes only. 17.6.1.3 mios14 module and vers ion number register (mios14vnr) this read-only register contains the hard-c oded values of the module and version number. msb 0 1234567891011 12 13 14 lsb 15 field test ? vf vfls sreset 0000_0000_0000_0000 addr 0x30 6800 figure 17-4. test and signal control register (mios14tpcr) table 17-3. mios14tpcr bit descriptions bits name description 0 test test ? this bit is used for mios14 factory testing and should always be programmed to a 0. 1:13 ? reserved 14 vf vf pin multiplex ? this bit controls the func tion of the vf pins (vf0/mpio32b0, vf1/mpio32b1, vf2/mpio32b2) 0 = mios14 general-purpose i/o is sele cted (mpio32b0, mp io32b1, mpio32b2) 1 = vf function is selected (vf[0:2]) 15 vfls vfls pin multiplex ? this bit controls t he function of the vfls signals (vfls0/mpio32b3, vfls1/mpio32b4) 0 = mios14 general-purpose i/o is selected (mpio32b3, mpio32b4) 1 = vfls function is selected (vfls[0:1]) msb 012345678 91011121314 lsb 15 field ? vect ? sreset 0000_0000_0000_0000 addr 0x30 6802 figure 17-5. vector register (mios14vect) msb 01234567891011121314 lsb 15 field mn vn 1 1 this field contains the revision level of the mios mo dule and may change with different revisions of the device. reset unaffected addr 0x30 6804 figure 17-6. mios14 module/version number register (mios14vnr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-15 17.6.1.4 mios14 module confi guration register (mios14mcr) the mios14mcr register is a collectio n of read/write stop, freeze, reset, and supervisor bits, as well as interrupt arbitration number bits . these bits are detailed in table 17-5 . table 17-4. mios14vnr bit descriptions bits name description 0:7 mn module number = 0x0e on the mpc561/mpc563 8:15 vn version number. may change with different revisions of the device. msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field stop rsv frz rst ? supv ? sreset 0000_0000_0000_0000 addr 0x30 6806 figure 17-7. module configurat ion register (mios14mcr) table 17-5. mios14mcr bit descriptions bits name description 0 stop stop enable ? the stop bit, while asserted, activates the miob freeze signal regardless of the state of the imb3 freeze signal. the miob freeze signal is further validated in some submodules with internal freeze enable bits in order for the submodule to be stopped. the mbism continues to operate to allow the cpu a ccess to the submodule?s registers. the miob freeze signal remains active until reset or until the stop bit is written to zero by the cpu (via the imb3). the stop bit is cleared by reset. 0 allows mios14 operation. 1 selectively stops mios14 operation. 1? reserved 2 frz freeze enable ? the frz bit, while asserted, activates the miob freeze signal only when the imb3 freeze signal is active. the miob freeze signal is further validated in some submodules with internal freeze enable bits in order for t he submodule to be frozen. the mbism continues to operate to allow the cpu access to the submodule ?s registers. the miob freeze signal remains active until the frz bit is written to zero or the imb3 freeze signal is negated. the frz bit is cleared by reset. 0 ignores the freeze signal on the imb3, allows mios14 operation. 1 selectively stops mios14 operation when the freeze signal appears on the imb3. 3 rst module reset ? the rst bit is always read as 0 and can be written to 1. when the rst bit is written to 1 operation of the mios14 completely stops and resets all the values in the submodule. this completely stops the operation of the mios14 and reset all the values in the submodules registers that are affected by reset. this bit provides a way of resetting the complete mios14 module regardless of the reset state of th e cpu. the rst bit is cleared by reset. 0 writing a 0 to rst has no effect. 1 reset the mios14 submodules. 4:7 ? reserved modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-16 freescale semiconductor 17.7 mios14 counter prescaler submodule (mcpsm) the mios14 counter prescaler submodule (mcpsm) divides the mios14 clock (f sys ) to generate the counter clock. it is designe d to provide all the submodules with th e same division of the main mios14 clock (division of f sys ). it uses a 4-bit modulus counter. the cl ock signal is prescale d by loading the value of the clock prescaler register into the prescaler counter ev ery time it overflows. this allows all prescaling factors between 2 and 16. counting is enabled by asserting mcpsmsc r[pren]. the counter can be stopped at any time by nega ting this bit, thereby st opping all submodules using the output of the mcpsm (counter clock). a block diagra m of the mcpsm is given in figure 17-8 . the following sections desc ribe the mcpsm in detail. figure 17-8. mcpsm block diagram 17.7.1 mcpsm features ? centralized counter clock generator 8 supv supervisor data space selector ? the supv bi t tells if the address space from 0x30 6000 to 0x30 67ff in the mios14 is accessed at the supervisor privilege level (see figure 17-2 ). when cleared, these addresses are accessed at the unrestricted privilege level. the supv bit is cleared by reset. 0 unrestricted data space. 1 supervisor data space. 9:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in mios14 implementations that use hardware interrupt arbitration. these bits are not used on mpc561/mpc563. table 17-5. mios14mcr bit descriptions (continued) bits name description f sys prescaler pren cp2 cp1 cp0 decrementer clock register load cp3 enable mcpsmscr 4-bit overflow dec. counter clock = 1? modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-17 ? programmable 4-bit modulus down-counter ? wide range of possible division ratios: 2 through 16 ? count inhibit under software control 17.7.1.1 mcpsm signal functions the mcpsm has no associated external signals. 17.7.1.2 modular i/o bu s (miob) interface ? the mcpsm is connected to all the signals in the re ad/write and control bus, to allow data transfer from and to the mcpsm registers, and to contro l the mcpsm in the differ ent possible situations. ? the mios14 counter prescaler submodul e does not use any 16-bit counter bus. ? the mios14 counter prescaler subm odule does not use the request bus. 17.7.2 effect of reset on mcpsm when the reset signal is asserted, all the bits in the mcpsm status and cont rol register are cleared. note the mcpsm is still disabled afte r the reset signal is negated and counting must be explicitly enab led by asserting mcpsmscr[pren]. 17.7.3 mcpsm registers the privilege level to access to the mcpsm registers is supervisor only. 17.7.3.1 mcpsm regi sters organization table 17-6. mcpsm register address map address register 0x30 6810 reserved 0x30 6812 reserved 0x30 6814 reserved 0x30 6816 mcpsm status/control register (mcpsmscr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-18 freescale semiconductor 17.7.3.2 mcpsm status/control register (mcpsmscr) note if the binary value 0b0001 is entered in psl[3:0], the output signal is stuck at zero, no clock is output. msb 0 1 234567891011121314 lsb 15 field pren fren ? psl3:0 sreset 0000_0000_0000_0000 addr 0x30 6816 figure 17-9. mcpsm status/control register (mcpsmscr) table 17-7. mcpsmscr bit descriptions bits name description 0 pren prescaler enable bit ? this active high r ead/write control bit enables the mcpsm counter. the pren bit is cleared by reset. 0 mcpsm counter disabled. 1 mcpsm counter enabled. 1 fren freeze bit ? this active high read/write cont rol bit when set make possible a freeze of the mcpsm counter if the miob freeze line is activated. note: this line is active when mios14mcr[stop] is set or when mios14mcr[f ren] and the imb3 freeze line are set. when the mcpsm is frozen, it stops counting. then when the fren bit is reset or when the freeze condition on the miob is negated, the count er restarts from where it was before freeze. the fren bit is cleared by reset. 0 mcpsm counter not frozen. 1 mcpsm counter frozen if miob freeze active. 2:11 ? reserved 12:15 psl[3:0] clock prescaler ? this 4-bit read/write data register stores the modulus value for loading into the clock prescaler. the new value is loaded into the counter on the next time the counter equals one or when disabled (pren =0). table 17-8. clock prescaler setting psl[3:0] value divide ratio hex binary 0x0 0b0000 16 0x1 0b0001 no counter clock output 0x2 0b0010 2 0x3 0b0011 3 ... ... ... 0xe 0b1110 14 0xf 0b1111 15 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-19 17.8 mios14 modulus coun ter submodule (mmcsm) the mmcsm is a versatile count er submodule capable of perfor ming complex counting and timing functions, including modulus counting, in a wide ra nge of applications. the mmcsm may also be configured as an event counter, allowing the overflow flag to be set after a pr edefined number of events (internal clocks or external events), or as a time source for other submodules. note the mmcsm can also operate as a free running counter by loading the modulus value of zero. the main components of the mmcsm are an 8-bit pres caler counter, an 8-bit pr escaler register, a 16-bit up-counter register, a 16-bit modulus latch register, counter loading and interrupt flag generation logic. the contents of the modulus latch register is tr ansferred to the counter under the following three conditions: 1. when an overflow occurs 2. when an appropriate transition occurs on the external load signal 3. when the program writes to the counter register. in this case, th e value is first written into the modulus register and immediatel y transferred to the counter. software can also write a value to the modulus register for later loading into the counter with one of the two first criteria. a software control register selects whether the clock in put to the counter is one of the prescaler outputs or the corresponding input signal. the polarity of th e external input signal is also programmable. the following sections describe the mmcsm in de tail. a block diagram of the mmcsm is shown in figure 17-10 . modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-20 freescale semiconductor figure 17-10. mmcsm block diagram figure 17-11. mmcsm modulus up-counter 17.8.1 mmcsm features ? programmable 16-bit modulus up-c ounter with a built-in programma ble 8-bit prescaler clocked by mcpsm ? maximum increment frequency of the counter: ? clocked by the internal mcpsm output: f sys / 2 ? clocked by the external signal: f sys / 4 ? flag setting and possible interrupt genera tion on overflow of the up-counter register 16-bit up-counter reg. edge 16-bit counter bus clock input overflow miob detect load control 16-bit modulus signal (mmcnc) edge modulus load detect signal (mmcnl) counter clock clock select load clock mmcsmml mmcsmcnt flag 8-bit clock prescaler 8-bit prescale mod.register clock enable request bus fren cls1 cls0 cp7 - cp0 pinc pinl edgn edgp latch reg. pinc 0xffff modulus value two?s complement counter reload modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-21 ? time counter on internal clock with interr upt capability after a pre-determined time ? external event counter (pulse accumulator) with overflow a nd interrupt capability after a pre-determined number of external events ? usable as a regular free-running up-counter ? capable of driving a dedicated 16-bit counter bus to provide timing information to action submodules (the value driven is the cont ents of the 16-bit up-counter register) ? optional signal for counting external events ? optional signal to externally fo rce a load of the modulus counter 17.8.1.1 mmcsm signal functions the mmcsm has two dedicated external signals. an external modulus load signal (mmcnl) allows the modulus value stored in the modulus latch register (mmcsmml) to be loaded into the up-counter regi ster (mmcsmcnt) at any time. both rising and falling edges of the load signal may be used, acco rding to the edgep and edgen bit settings in the mmcsmscr. an external event clock signal (mmcnc) can be select ed as the clock source for the up-counter register (mmcsmcnt) by setting the appropriate value in th e cls bit field of the status/control register (mmcsmscr). either rising or falling edge may be used according to the setting of these bits. when the external clock source is selected, the mmc sm is in the event counter mode. the counter can simply counts the number of events occurring on th e input signal. alternatively, the mmcsm can be programmed to generate an interrupt when a predefined number of events have been counted; this is done by presetting the counter with the two?s comple ment value of the desired number of events. 17.8.2 mmcsm prescaler the built-in prescaler cons ists of an 8-bit modulus counter, clocked by the mcpsm output. it is loaded with an 8-bit value every time the counter overflows or whenever the prescaler output is selected as the clock source. this 8-bit value is st ored in the mmcsmscr[cp]. the pres caler overflow si gnal is used to clock the mmcsm up-counter. this allows the mmcsmcnt to be in cremented at the mcpsm output frequency divided by a value between 1 and 256. 17.8.3 modular i/o bus (miob) interface ? the mmcsm is connected to all th e signals in the read/write and c ontrol bus, to allo w data transfer from and to the mmcsm registers, and to contro l the mmcsm in the different possible situations. ? the mmcsm drives a de dicated 16-bit counter bus with the value currently in the up-counter register ? the mmcsm uses the request bus to transmit the flag line to the interrupt request submodule (mirsm). a flag is set when an overflow has occurred in the up-counter register. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-22 freescale semiconductor 17.8.4 effect of reset on mmcsm when the reset signal is asserted, only the fren , edgp, edgn, and cls bits in the mmcsmscr are cleared. the clock prescaler cp, pinc, and pinl bits in the same register are not cleared. ? the pinc and pinl bits in the mmcsmscr always reflect the state of the appropriate external pins. ? the mmcsm is disabled after re set and must be explicitly enab led by selecting a clock source using the cls bits. the mmcsmcnt and the mmcsmml, together with the cl ock prescaler register bi ts, must be initialized by software, because they are undefined after a hardware reset. a modulus value must be written to the mmcsmcnt (which also writes into the mmcsmml) be fore the mmcsmscr is written to. the latter access initializes th e clock prescaler. 17.8.5 mmcsm registers the privilege level to access to the mmcsm regi sters depends on the mios14mcr supv bit. the privilege level is unrestricted after sreset and can be changed to supervisor by software. 17.8.5.1 mmcsm register organization table 17-9. mmcsm address map address register mmcsm6 0x30 6030 mmcsm6 up-counter register (mmcsmcnt) see table 17-10 for bit descriptions. 0x30 6032 mmcsm6 modulus latch register (mmcsmml) see table 17-11 for bit descriptions. 0x30 6034 mmcsm6 status/control register duplicated (mmcsmscrd) see section 17.8.5.5, ? mmcsm status/control register (mmcsmscr) ? for bit descriptions. 0x30 6036 mmcsm6 status/contr ol register (mmcsmscr). see table 17-12 for bit descriptions. mmcsm7 0x30 6038 mmcsm7 up-counter register (mmcsmcnt) 0x30 603a mmcsm7 modulus latch register (mmcsmml) 0x30 603c mmcsm7 status/control register duplicated (mmcsmscrd) 0x30 603e mmcsm7 status/con trol register (mmcsmscr) mmcsm8 0x30 6040 mmcsm8 up-counter register (mmcsmcnt) 0x30 6042 mmcsm8 modulus latch register (mmcsmml) 0x30 6044 mmcsm8 status/control register duplicated (mmcsmscrd) 0x30 6046 mmcsm8 status/contr ol register (mmcsmscr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-23 17.8.5.2 mmcsm up-counter register (mmcsmcnt) mmcsm22 0x30 60b0 mmcsm22 up-counter register (mmcsmcnt) 0x30 60b2 mmcsm22 modulus latch register (mmcsmml) 0x30 60b4 mmcsm22 status /control register duplicated (mmcsmscrd) 0x30 60b6 mmcsm22 status/control register (mmcsmscr) mmcsm23 0x30 60b8 mmcsm23 up-counter register (mmcsmcnt) 0x30 60ba mmcsm23 modulus latch register (mmcsmml) 0x30 60bc mmcsm23 status/control register duplic ated (mmcsmscrd) 0x30 60be mmcsm23 status/control register (mmcsmscr) mmcsm24 0x30 60c0 mmcsm24 up-counter register (mmcsmcnt) 0x30 60c2 mmcsm24 modulus latch register (mmcsmml) 0x30 60c4 mmcsm24 status/control register duplic ated (mmcsmscrd) 0x30 60c6 mmcsm24 status/control register (mmcsmscr) msb 01234567891011121314 lsb 15 field cnt sreset undefined addr 0x30 6030, 0x30 6038, 0x30 6040, 0x30 60b0, 0x30 60b8, 0x30 60c0 figure 17-12. mmcsm up-counter register (mmcsmcnt) table 17-10. mmcsmcnt bit descriptions bits name description 0:15 cnt counter value ? these bits are read/write data bits representing the 16-bit value of the up-counter. it contains the value that is driven onto the 16-bit counter bus. note: writing to mmcsmcnt simultaneously writes to mmcsmml. table 17-9. mmcsm address map (continued) address register modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-24 freescale semiconductor 17.8.5.3 mmcsm modulus la tch register (mmcsmml) 17.8.5.4 mmcsm status/control register (mmcsmscrd) (duplicated) the mmcsmscrd and the mmcsmscr are the same re gisters accessed at two different addresses. reading or writing to one of these two addresses has exactly the same effect. the duplication of the scr regi ster allows coherent 32-bi t accesses when using a rcpu. warning the user should not writ e directly to the address of the mmcsmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. 17.8.5.5 mmcsm status/control register (mmcsmscr) the status/control register (scr) is a collection of read-only signal status bits, read/w rite control bits and an 8-bit read/write data register, as detailed below. msb 01234567891011121314 lsb 15 field ml sreset undefined addr 0x30 6032, 0x30 603a, 0x30 604 2, 0x30 60b2, 0x30 60ba, 0x30 60c2 figure 17-13. mmcsm modulus latch register (mmcsmml) table 17-11. mmcsmml bit descriptions bits name description 0:15 ml modulus latches ? these bits are read/write dat a bits containing the 16- bit modulus value to be loaded into the up-counter. the value loaded in this register must be the one ?s complement of the desired modulus count. the up-counter increments from this one?s comple ment value up to 0xffff to get the correct number of steps before an overflow is generated to reload the modulus value into the up-counter. msb 01234567891011121314 lsb 15 field pinc pinl fren edgn edgp cls ? cp sreset undefined addr 0x30 6036, 0x30 603e, 0x30 6046, 0x30 60b6, 0x30 60be, 0x30 60c6 figure 17-14. mmcsm status/control register (mmcsmscr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-25 table 17-12. mmcsmscr bit descriptions bits name description 0 pinc clock input signal status bit ? this read-only st atus bit reflects the logi c state of the clock input signal mmcnc (mda11, mda13, mda27, mda30, pwm16, and pwm18). 1 pinl modulus load input signal status bit ? this read-only status bit reflects the logic state of the modulus load signal mmcnl (mda12, mda14, mda28, mda31, pwm17, and pwm19). 2 fren freeze enable ? this active high read/write control bit enables the mmcsm to recognize the miob freeze signal. 3 edgn modulus load falling-edge sensitivity ? this ac tive high read/write control bit sets falling-edge sensitivity for the mmcnl signal, such that a high-to-low transition causes a load of the mmcsmcnt. 4 edgp modulus load rising-edge sensitivity this active high read/write control bit sets rising -edge sensitivity for the mmcnl signal, such that a low-to-high transition causes a load of the mmcsmcnt. see table 17-13 for details about edge sensitivity. 5:6 cls clock select ? these read/write control bits select the clock source for the modulus counter. either the rising edge or falling edge of the clock signal on the mmcnc signal may be selected, as well as, the internal mmcsm prescaler outp ut or disable mode (no clock source). see ta b l e 1 7 - 1 4 for details about the clock selection. 7?reserved 8:15 cp clock prescaler ? this 8-bit data field is also accessible as an 8-bit data register. it stores the two?s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. the new value is loaded into the prescaler counter on the next counter overflow, or upon setting the cls1 ? cls0 bits for selecting the clock prescaler as the clock source. ta b l e 1 7 - 1 5 gives the clock divide ratio according to the value of cp. table 17-13. mmcsmcnt edge sensitivity edgn edgp edge sensitivity 1 1 mmcsmcnt load on rising and falling edges 1 0 mmcsmcnt load on falling edges 0 1 mmcsmcnt load on rising edges 0 0 none (disabled) table 17-14. mmcsmcnt clock signal cls clocking selected 11 mmcsm clock prescaler 10 clock signal rising-edge 01 clock signal falling-edge 00 none (disable) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-26 freescale semiconductor 17.9 mios14 double action submodule (mdasm) the mios14 double action submodule (mda sm) is a function included in the mios14 library. it is a versatile 16-bit dual action subm odule capable of performing two ev ent operations before software intervention is required. it can perform two event ope rations such as pwm gene ration and measurement, input capture, output compare, etc. the mdasm is composed of two timi ng channels (a and b), an output flip-flop, an input edge detector and some control logic. all control and status bi ts are contained in the mdasm status a nd control register. the following sections describe the mdasm in de tail. a block diagram of the mdasm is shown in figure 17-15 . table 17-15. prescaler values prescaler value (cp in hex) mios14 prescaler clock divided by ff 1 fe 2 fd 3 fc 4 fb 5 fa 6 f9 7 f8 8 ...... ........ 02 254 (2^8 -2) 01 255 (2^8 -1) 00 256 (2^8) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-27 figure 17-15. mdasm block diagram 17.9.1 mdasm features ? versatile 16-bit dual acti on unit allowing up to two events to o ccur before software intervention is required ? six software selectable modes allowing the mdasm to perform pulse width and period measurements, pwm generation, si ngle input capture and output co mpare operations as well as port functions ? software selection of one of the four possibl e 16-bit counter buses used for timing operations ? flag setting and possible interrupt ge neration after mdasm action completion ? software selection of output pulse polarity ? software selection of tote m-pole or open-drain output ? software readable output signal status 16-bit comparator a 4 x 16-bit counter bus control register bits mio bus select output flip-flop i/o signal edge detect 16-bit register a output buffer 16-bit register b1 16-bit register b2 16-bit comparator b register b bsl1 bsl0 forca forcb flag wor pin counter buses request bus counter bus set mode0 mode1 mode2 mode3 edpol modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-28 freescale semiconductor 17.9.1.1 mdasm signal functions the mdasm has one dedicated external signal. this signal is used in input or in output depending on the selected mode. when in input, it allows the m dasm to perform input capture, input pulse width measurement and input peri od measurement. when in output, it allows output co mpare, single shot output pulse, single output compare and output port bit opera tions as well as output pulse width modulation. note in disable mode, the signal becomes a high impedance input and the input level on this signal is reflected by the state of the pin bit in the mdasmscr register. 17.9.2 mdasm description the mdasm contains two timing cha nnels a and b associated with th e same input/output signal. the dual action submodule is so called because its timing channel conf iguration allows two events (input capture or output compare) to occur before software intervention is required. six operating modes allow th e software to use the md asm?s input capture and output compare functions to perform pulse width me asurement, period measurement, single pulse generation and continuous pulse width generation, as well as standard input capture and output compare. the mdasm can also work as a single i/o signal. see table 17-16 for details. channel a comprises one 16-bit data register and one 16-bit comparator. channel b also consists of one 16-bit data register and one 16-bit comparator, however, internally, channel b has two data registers b1 and b2, and the operating mode determines which register is acc essed by the software: ? in the input modes (ipwm, ipm and ic), registers a and b2 are used to hold the captured values; in these modes, the b1 re gister is used as a tem porary latch for channel b. ? in the output compare modes (ocb and ocab), regi sters a and b2 are used to define the output pulse; register b1 is not used in these modes. ? in the output pulse width modul ation mode (opwm), registers a and b1 are used as primary registers and hidden register b2 is used as a double buffer for channel b. register contents are always tran sferred automatically at the correc t time so that the minimum pulse (measurement or gene ration) is just one 16-bit c ounter bus count. the a and b data registers are always read/write registers, accessible via the miob. in the input modes, the edge detect circuitry triggers a capt ure whenever a rising or falling edge (as defined by the edpol bit) is applied to the input signal. th e signal on the input signal is schmitt triggered and synchronized with the mios14 clock. in the disable mode (dis) and in the input modes, th e pin bit reflects the state present on the input signal (after being schmitt trigge red and synchronized). in th e output modes the pin bit reflects the value present on the output flip-flop. the output flip-fl op is used in output modes to hold the logic level applied to the output signal. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-29 the 16-bit counter bus selector is common to all i nput and output functions; it connects the mdasm to one of the four 16-bit counter buses available to that submodule instance and is controlled in software by the 16-bit counter bus selector bits bsl0 and bsl1 in the mdasmscr register. 17.9.3 mdasm modes of operation the mode of operation of the mdasm is determin ed by the mode select bits mode[0:3] in the mdasmscr register (see table 17-16 ). to avoid spurious interrupts, and to make sure that the flag line is activa ted according to the newly selected mode, the following sequence of operations should be adopted when changing mode: 1. disable mdasm interrupts (by resetting the enable bit in the relevant mirsm) 2. change mode (via disable mode) 3. reset the corresponding flag bit in the relevant mirsm 4. re-enable mdasm interrupts (if desired) note when changing between output modes, it is not necessary to follow this procedure, as in these modes the flag bit merely indicates to the software that the compare value can be update d. however changing modes without passing via the disable mode doe s not guarantee the subsequent functionality. 17.9.3.1 disable (dis) mode the disable mode is selected by setting mode[0:3] to 0b0000. in this mode, all input capture a nd output compare functions of the mdasm are disabled and the flag line is maintained inactive, but the input port signa l function remains available. the associated signal becomes a high impedance input and th e input level on this signal is refl ected by the state of the pin bit in the mdasmscr register. all control bits remain accessible, allowing th e software to pr epare for future table 17-16. mdasm modes of operation mode[0:3] mode description of mode 0000 dis disabled ? input signal is high impedance; pin gives state of the input signal. 0001 ipwm input pulse width measurement ? capture on th e leading edge and the trailing edge of an input pulse. 0010 ipm input period measurement ? capt ure two consecutive rising/falling edges. 0011 ic input capture ? capture when the designated edge is detected. 0100 ocb output compare, flag line activated on b compar e ? generate leading and trailing edges of an output pulse. 0101 ocab output compare, flag line activated on a and b compare ? generate leading and trailing edges of an output pulse. 1xxx opwm output pulse width modulation ? generate contin uous pwm output with 7, 9, 11, 12, 13, 14, 15 or 16 bits of resolution. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-30 freescale semiconductor mode selection. data registers a and b are accessible at consecutive addr esses. writing to data register b stores the same value in registers b1 and b2. warning when changing modes, it is imperative to go throu gh the dis mode. failure to do this could lead to invalid a nd unexpected output compare or input capture results, and to fl ags being set incorrectly. 17.9.3.2 input pulse width measurement (ipwm) mode ipwm mode is selected by setting mode[0:3] to 0b0001. this mode allows the width of a positive or negative pulse to be determined by capturing the leading edge of the pulse on channel b a nd the trailing edge of th e pulse on channel a; succes sive captures are done on consecutive edges of opposite polari ty. the edge sensitivity is se lected by the edpol bit in the mdasmscr register. this mode also allows the software to determine th e logic level on the input si gnal at any time by reading the pin bit in the mdasmscr register. the channel a input capture function re mains disabled until the first lead ing edge triggers the first input capture on channel b (refer to figure 17-16 ). when this leading edge is detected, the count value of the 16-bit counter bus selected by the bsl[1:0] bits is la tched in the 16-bit data re gister b1; the flag line is not activated. when the next trailing edge is detecte d, the count value of the 16-bit counter bus is latched into the 16-bit data register a and, at the same time, th e flag line is activated and the contents of register b1 are transferred to register b2. reading data register b returns the value in register b2. if subsequent input capt ure events occur while the flag bit is set in the corresponding mirsm, data registers a and b will be updated with the latest captured values and the flag line will remain active. if a 32-bit coherent operation is in progress when the trailing edge is detected, the transfer from b1 to b2 is deferred until the coherent operation is completed. operation of the mdasm then continues on channels b and a as previously described. the input pulse width is calcu lated by subtracting the value in data regi ster b from the value in data register a. figure 17-16 provides an example of how the mdasm can be used for input pulse width measurement. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-31 figure 17-16. input pulse width measurement example 17.9.3.3 input period me asurement (ipm) mode ipm mode is selected by setting mode[0:3] to 0b0010. this mode allows the period of an input signal to be determined by ca pturing two consecu tive rising edges or two consecutive falling edges; successive input captures are done on consecutive edges of the same polarity. the edge sensitivity is defined by the edpol bit in the mdasmscr register. this mode also allows the software to determine th e logic level on the input si gnal at any time by reading the pin bit in the mdasmscr register (refer to figure 17-17 ). when the first edge having the selected polarity is detected, the 16-bit counter bus value is latched into the 16-bit data register a. data in register b1 is transferred to data regist er b2 and the data in register a is transferred to register b1. on this first capture the flag line is not activated, and the value in re gister b2 is meaningless. on the second and subsequent captures, the fl ag line is activated when the data in register a is transferred to register b1. when the second edge of the same pola rity is detected, the c ounter bus value is latche d into data register a, the data in register b1 is transferred to data regi ster b2, the flag line is activated to signify that the beginning and end points of a complete period have been captured, and finally the data in register a is transferred to register b1. this se quence of events is repeated for each subsequent capture. reading data register b returns the value in register b2. flag reset by software mode selection; edpol = 1 (channel a capture on falling edge, channel b capture on rising edge) input counter flag bit 0xxxxx 0xxxxx 0x1000 register b1 register b2 0x1000 0x1000 0x1100 0x1100 0x1400 0x1000 0x1400 0x1525 0x1400 0x1525 0x1400 0x16a0 edge trigger register a 0xxxxx 0xxxxx edge trigger rising falling edge trigger edge trigger rising falling edge trigger rising flag set flag set b1 is an internal register, not accessible to software flag reset by software pulse 1 pulse 2 pulse 1 = reg a- reg b = 0x0100 pulse 2 = reg a- reg b = 0x0125 16-bit bus signal 2 3 1 1 2 3 0x0500 0x1400 0x1525 0x16a0 0xxxxx 0x1000 0x1100 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-32 freescale semiconductor if a 32-bit coherent operation is in pr ogress when an edge (except for the fi rst edge) is detected, the transfer of data from b1 to b2 is deferred until the cohere nt operation is completed. at any time, the input level present on the input signal can be read on the pin bit. the input pulse period is calculated by subtracting the value in data re gister b from the value in data register a. figure 17-17 provides an example of how the mdasm can be used for input period measurement. figure 17-17. input period measurement example 17.9.3.4 input capture (ic) mode ic mode is selected by se tting mode[0:3] to 0b0011. this mode is identical to the i nput period measurement mode (ipm) described above, with the exception that the flag line is also ac tivated at the occurrence of the first det ected edge of the se lected polarity. in this mode the mdasm functions as a standard input capture function. in this ca se the value latched in channel b can be ignored. figure 17-18 provides an example of how th e mdasm can be used for input capture. flag reset by software mode selection; edpol = 0 (channel a capture on rising edge) input signal counter bus flag bit 0xxxxx 0x1000 0xxxxx 0x1000 register b1 register b2 0x1000 0xxxxx 0x1000 0x1400 0x1400 0x0400 0x1400 0x1400 0x1000 0x16a0 0x1400 0x16a0 edge trigger register a 0xxxxx 0xxxxx rising edge trigger rising flag set flag set internal register, not accessible to software flag reset by softwa re edge trigger rising 1 2 3 2 1 3 flag set period = reg a -reg b 2 1 3 flag set period = reg a -reg b 16-bit 0x0500 0x1000 0x1100 0x1400 0x1525 0x16a0 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-33 figure 17-18. mdasm input capture example 17.9.3.5 output compare (ocb and ocab) modes output compare mode (either oc a or ocb) is selected by sett ing mode[0:3] to 0b010x. the mode0 controls the activation criteria fo r the flag line, (i.e., when a compar e occurs only on ch annel b or when a compare occurs on either channel). this mode allows the mdasm to perf orm four different output functions: ? single-shot output pulse (two edges), wi th flag line activated on the second edge ? single-shot output pulse (two edges), with flag line activated on both edges ? single-shot output transition (one edge) ? output port signal, with out put compare function disabled in this mode the leading and tra iling edges of variable width output pulses are generate d by calculated output compare events occurring on channels a and b, re spectively. oc mode may al so be used to perform a single output compare function, or ma y be used as an output port bit. in this mode, channel b is accessed vi a register b2. a write to register b2 writes the same value to register b1 even though the contents of b1 are not used in this mode. both channels work together to generate one ?single shot? output pulse signal. ch annel a defines the leading edge of the output pulse, while channel b defines the trailing edge of the pulse. flag line ac tivation can be done when a match occurs on channel b only or when a compare occurs on either ch annel (as defined by the mode0 in the mdasmscr register). when this mode is first selected, (i.e., coming from disable mode, both comparat ors are disabled). each comparator is enabled by writing to its data register; it rema ins enabled until the next successful comparison is made on that channel, whereupon it is disable d. the values stored in registers a and b are compared with the count value on the selected 16- bit counter bus when their corresponding comparators are enabled. flag reset by software mode selection; edpol = 0 (cha nnel a capture on rising edge) input signal counter bus flag bit 0xxxxx 0x1000 0xxxxx 0x1000 register b1 register b2 0x1000 0xxxxx 0x1000 0x1400 0x1400 0x1000 0x1400 0x1400 0x1000 0x16a0 0x1400 0x16a0 edge trigger register a 0xxxxx 0xxxxx rising edge trigger rising flag set flag set internal register, not accessible to software flag reset by software edge trigger rising flag reset by software (ignored) flag set 16-bit 0x0500 0x1000 0x1100 0x1400 0x1525 0x16a0 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-34 freescale semiconductor the output flip-flop is set when a match occurs on ch annel a. the output flip-fl op is reset when a match occurs on channel b. the polarity of the output signal is selected by th e edpol bit. the output flip-flop level can be obtained at any time by reading the pin bit. if subsequent enabled output compares occur on channe ls a and b, the output pulse s continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the so ftware to force the output flip-flop to the level corresponding to a comparison on channel a or b, respectively. note the flag line is not affected by these ?force? operations. totem pole or open-drain output circ uit configurations can be sele cted using the wor bit in the mdasmscr register. note if both channels are loaded with the same value, the output flip-flop provides a logic zero level output and th e flag bit is still set on the match. note 16-bit counter bus compare only occurs when the 16-bit counter bus is updated. 17.9.3.5.1 single shot ou tput pulse operation the single shot output pulse operation is selected by writing the leading e dge value of the desired pulse to data register a and the trailing edge value to data register b. a single pulse will be output at the desired time, thereby disabling the comparators until new values are written to the data registers. to generate a single shot output pulse, the ocb mode should be used to only generate a flag on the b match. in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). figure 17-19 provides an example of how the mdasm can be used to generate a single output pulse. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-35 figure 17-19. single shot output pulse example 17.9.3.5.2 single output compare operation the single output compare operation is selected by writing to only one of the two data registers (a or b), thus enabling only one of the comparators. following the first successful match on the enabled channel, the output level is fixed and remains at the same leve l indefinitely with no further software intervention being required. to generate a single output compare, the ocab mode shoul d be used to generate a flag on both the a and the b match. note in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). figure 17-20 provides an example of how the mdasm can be used to perform a single output compare. flag reset by software mode selection; mode0 = 0 output signal flag bit 0x1000 0x1000 0x1100 0xxxxx register b1 register b2 0xxxxx 0x1100 0x1000 0x1000 0xxxxx 0x1100 0xxxxx 0x1000 0x1100 0x1000 0x1100 0xxxxx 0x0500 0x1000 0x1100 0x0000 0x1000 0x1100 register a 0x1100 0xxxxx internal register, not accessible to software a event b event write to a and b reoccurrences of the timer count do not trigger the output pulse unless r egisters a and b have been written again. counter bus 16-bit modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-36 freescale semiconductor figure 17-20. single shot ou tput transition example 17.9.3.5.3 output port bit operation the output port bit operation is se lected by leaving both channels disa bled, (i.e., by writing to neither register a nor b). the edpol bit al one controls the output value. the same result can be achieved by keeping edpol at zero and using the forca and forcb bits to obtain th e desired output level. 17.9.3.6 output pulse widt h modulation (opwm) mode opwm mode is selected by sett ing mode[0:3] to 1xxx. the mode[1 :3] bits allow some of the comparator bits to be masked. this mode allows pulse width m odulated output waveforms to be ge nerated, with eight selectable frequencies. frequencies are only rele vant as such if the counter bus is driven by a counter as a time reference. both channels (a a nd b) are used to generate one pwm output signal on the mdasm signal. channel b is accessed via register b1. register b2 is not accessible. channels a and b define respectively the leading and trailing edges of the pwm output pulse. the value in register b1 is transferred to register b2 each time a match occurs on either channel a or b. note a forca or forcb does not cause a transfer from b1 to b2. the value loaded in register a is compared with th e value on the 16-bit counter bus each time the counter bus is updated. when a match on a occu rs, the flag line is activated a nd the output flip-flop is set. the value loaded in register b2 is co mpared with the value on the 16-bit counter bus each time the counter bus is updated. when a match occurs on b, the output flip-flop is reset. f lag reset by software mode selection; mode0 = 1 output signal flag bit 0x1000 0x1000 0xxxxx 0xxxxx register b1 register b2 0xxxxx 0xxxxx 0x1000 0x1000 0xxxxx 0x1100 0xxxxx 0x1000 0x1100 0x1000 0x1100 0xxxxx 0x0500 0x1000 0x1100 0x1000 0x1100 0x1000 register a 0xxxxx 0xxxxx internal register, not accessible to software a event b event write to a write to b flag reset by software reoccurences of the timer count do not trigger a response unless registers a or b have been written again. counter bus 16-bit modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-37 note if both channels are loaded with the sa me value, when a simultaneous match on a and b occurs, the submodule behave s as if a simple match on b had occurred except for the flag line wh ich is activated. th e output flip-flop is reset and the value in register b1 is transferred to register b2 on the match. the polarity of the pwm output signa l is selected by the edpol bit. the output flip-flop level can be obtained at any time by reading the pin bit. if subsequent compares occur on channels a and b, the pwm pulses continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the so ftware to force the output flip-flop to the level corresponding to a comparis on on a or b respectively. note that the flag line is not activated by the forca and forcb operations. warning data registers a and b must be loaded with the values needed to produce the desired pwm output pulse. note 16-bit counter bus compare only occurs when the 16-bit counter bus is updated. figure 17-21 provides an example of how the mdasm can be used for pulse width modulation. figure 17-21. mdasm output pulse width modulation example to generate pwm output pulses of diff erent frequencies, the 16-bit compar ator can have some of its bits masked. this is controlled by bits mode2, mo de1and mode0. the frequency of the pwm output (f pwm ) is given by the following equation (assuming th e mdasm is connected to a 16-bit counter bus used as time reference and f sys is the frequency of the mios14 clock): edpol = 0 output signal 16-bit counter bus flag bit 0x1000 0x1000 0x1800 0x1500 register b1 0x1500 0x1500 0x1000 0x1000 0x1700 0x1500 0x1700 0x1000 0x1700 0x1000 0x1700 0x1700 0x1000 0x1100 0x1800 0x0000 0x1000 0x1700 register a 0x1800 0x1800 internal register, not accessible to software a compare b compare write 0x1000 to a write to b1 register b2 write to b1 a compare b compare write 0x1800 to b1 flag reset by software flag reset by software modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-38 freescale semiconductor where: ?n mcpsm is the overall mcpsm cloc k divide ratio (2, 3, 4,...,16). ?n counter is the divide ratio of the pr escaler of the counter (used as a time reference) that drives the 16-bit counter bus. ?n mdasm is the maximum count reachable by the coun ter when using n bits of resolution (this count is equal to 2 n ). a few examples of frequenc ies and resolutions that can be obtained are shown in table 17-17 . when using 16 bits of resolution on the comparator (mode[2:0] = 0b000), the output can vary from a 0% duty cycle up to a duty cycle of 65535/6553 6. in this case it is not possibl e to have a 100% duty cycle. in cases where 16-bit resolution is not needed, it is possible to have a duty cycle ranging from 0% to 100%. setting bit 15 of the value st ored in register b to one results in the output being ?alway s set?. clearing bit 15 (to zero) allows normal comparis ons to occur and the normal output waveform is obtained. changes to and from the 100% duty cy cle are done synchronously on an a or b match, as are all other width changes. table 17-17. mdasm pwm example output frequencies/resolutions at f sys =40mhz resolution (bits) n mcpsm n counter n mdasm pwm output frequency (hz) 1 1 this information is valid only if the mdasm is connected to an mmcsm operating as a free-running counter. 16 16 256 65536 0.15 16 2 1 65536 305.17 15 16 256 32768 0.29 15 2 1 32768 610.35 14 16 256 16384 0.59 14 2 1 16384 1 220.70 13 16 256 8192 1.19 13 2 1 8192 2 441.41 12 16 256 4096 2.38 12 2 1 4096 4 882.81 11 16 256 2048 4.77 11 2 1 2048 9 765.63 9 16 256 512 19.07 9 2 1 512 39 062.50 7 16 256 128 76.29 7 2 1 128 156 250 f pwm = f sys n mcpsm ? n counter ? n mdasm modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-39 in the opwm mode, the wor bit selects whether the output is totem pole driven or open-drain. 17.9.4 modular i/o bus (miob) interface ? the mdasm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mdasm registers, and to contro l the mdasm in the differ ent possible situations. ? the mdasm is connected to four 16-bit counter buses available to that submodule instance, so that the mdasm can select by software which one to use. ? the mdasm uses the request bus to transmit th e flag line to the inte rrupt request submodule (mirsm). 17.9.5 effect of reset on mdasm when the reset signal is asserted, the mdasm register s are reset according to the values specified in section 17.9.6, ?mdasm registers .? 17.9.6 mdasm registers the privilege level to access the mdasm register s depends on the mios14mcr [supv]. the privilege level is unrestricted after reset and can be changed to supervisor by software. 17.9.6.1 mdasm registers organization the mdasm register map comprises f our 16-bit register locat ions. as shown in belo w, the register block contains four mdasm re gisters. note that the mdasmscrd is the duplication of the mdasmscr. this is done to allow 32-bit aligned accesses. warning the user should not write directly to the address of the mdasmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. all unused bits return zero when read by the software. all register addresses in this section are specified as offsets from the base address of the mdasm. table 17-18. mdasm address map address register mdasm11 0x30 6058 mdasm11 data a register (mdasmar) see section 17.9.6.2, ?mdasm da ta a (mdasmar) register ? for bit descriptions. 0x30 605a mdasm11 data b register (mdasmbr) see section 17.9.6.3, ?mdasm da ta b (mdasmbr) register ? for bit descriptions. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-40 freescale semiconductor 0x30 605c mdasm11 status/control register duplicated (mdasmscrd) see table 17-21 for bit descriptions. 0x30 605e mdasm11 status/control register (mdasmscr) see table 17-21 for bit descriptions. mdasm12 0x30 6060 mdasm12 data a register (mdasmar) 0x30 6062 mdasm12 data b register (mdasmbr) 0x30 6064 mdasm12 status/control register duplicated (mdasmscrd) 0x30 6066 mdasm12 status/control register (mdasmscr) mdasm13 0x30 6068 mdasm13 data a register (mdasmar) 0x30 606a mdasm13 data b register (mdasmbr) 0x30 606c mdasm13 status/control register duplicated (mdasmscrd) 0x30 606e mdasm13 status/control register (mdasmscr) mdasm14 0x30 6070 mdasm14 data a register (mdasmar) 0x30 6072 mdasm14 data b register (mdasmbr) 0x30 6074 mdasm14 status/control register duplicated (mdasmscrd) 0x30 6076 mdasm14 status/control register (mdasmscr) mdasm15 0x30 6078 mdasm15 data a register (mdasmar) 0x30 607a mdasm15 data b register (mdasmbr) 0x30 607c mdasm15 status/control register duplicated (mdasmscrd) 0x30 607e mdasm15 status/control register (mdasmscr) mdasm27 0x30 60d8 mdasm27 data a register (mdasmar) 0x30 60da mdasm27 data b register (mdasmbr) 0x30 60dc mdasm27 status/control register duplicated (mdasmscrd) 0x30 60de mdasm27 status/control register (mdasmscr) mdasm28 0x30 60e0 mdasm28 data a register (mdasmar) 0x30 60e2 mdasm28 data b register (mdasmbr) table 17-18. mdasm address map (continued) address register modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-41 17.9.6.2 mdasm data a (mdasmar) register 0x30 60e4 mdasm28 status/control register duplicated (mdasmscrd) 0x30 60e6 mdasm28 status/control register (mdasmscr) mdasm29 0x30 60e8 mdasm29 data a register (mdasmar) 0x30 60ea mdasm29 data b register (mdasmbr) 0x30 60ec mdasm29 status/control register duplicated (mdasmscrd) 0x30 60ee mdasm29 status/control register (mdasmscr) mdasm30 0x30 60f0 mdasm30 data a register (mdasmar) 0x30 60f2 mdasm30 data b register (mdasmbr) 0x30 60f4 mdasm30 status/control register duplicated (mdasmscrd) 0x30 60f6 mdasm30 status/control register (mdasmscr) mdasm31 0x30 60f8 mdasm31 data a register (mdasmar) 0x30 60fa mdasm31 data b register (mdasmbr) 0x30 60fc mdasm31 status/control register duplicated (mdasmscrd) 0x30 60fe mdasm31 status/control register (mdasmscr) msb 01234567891011121314 lsb 15 field ar sreset undefined addr 0x30 6058, 0x30 6060, 0x30 6068, 0x30 6070, 0x30 6078, 0x30 60d8, 0x30 60e0, 0x30 60e8, 0x30 60f0, 0x30 60f8 figure 17-22. mdasm data a register (mdasmar) table 17-18. mdasm address map (continued) address register modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-42 freescale semiconductor 17.9.6.3 mdasm data b (mdasmbr) register table 17-19. mdasm ar bit descriptions bits name description 0:15 ar mdasmar is the data register associated with ch annel a; its use varies with the different modes of operation: dis mode: mdasmar can be accessed to pre pare a value for a subsequent mode selection. ipwm mode: mdasmar contai ns the captured value corresponding to the trailing edge of the measured pulse. ipm and ic modes: mdasmar contains the captured va lue corresponding to the most recently detected dedicated edge (rising or falling edge). ocb and ocab modes: mdasmar is loaded with the value corresponding to the leading edge of the pulse to be generated. writing to mdasmar in the ocb and ocab modes also enables the corresponding channel a comparator until the next successful comparison. opwm mode: mdasmar is loaded with the value corresponding to the leading edge of the pwm pulse to be generated. note: in ic, ipm, or ipwm mode, when a read to regist er a or b occurs at the same time as a counter bus capture into that register and the counter bus is changing value, then the counter bus capture to that register is delayed. msb 01234567891011121314 lsb 15 field br sreset undefined addr 0x30 605a, 0x30 6062, 0x30 606a, 0x30 6072, 0x30 607a, 0x30 60da, 0x30 60e2, 0x30 60ea, 0x30 60f2, 0x30 60fa figure 17-23. mdasm datab register (mdasmbr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-43 17.9.6.4 mdasm status/control register (mdasmscrd) (duplicated) the mdasmscrd and the mdasmscr are the same registers accessed at two different addresses. reading or writing to one of these two addresses has exactly the same effect. warning the user should not write directly to the address of the mdasmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. the duplication of the scr regi ster allows coherent 32-bit accesses when using an rcpu. 17.9.6.5 mdasm status/control register (mdasmscr) the status and control register ga thers a read only bit reflecting the status of the mdasm signal as well as read/write bits related to its control and configuration. the signal input status bit reflects the status of the corresponding signal when in input mode. when in output mode, the pin bit only reflects the status of the output flip-flop. table 17-20. mdasm br bit descriptions bits nam e description 0:15 br mdasmbr is the data register a ssociated with channel b; its use varies with the different modes of operation. writing to register b always writes to b1 and, depending on the mode selected, sometimes to b2. reading register b either reads b1 or b2 depending on the mode selected. in the dis mode, mdasmbr can be accessed to prepare a value for a subsequent mode selection. in this mode, register b1 is accessed in order to prepare a value for the opwm mode. unused register b2 is hidden and cannot be read, but is written with th e same value when register b1 is written. in the ipwm mode, mdasmbr contai ns the captured value corresponding to the leading edge of the measured pulse. in this mode, register b2 is accesse d; buffer register b1 is hidden and is not readable. in the ipm and ic modes, mdasmbr contains the captur ed value corresponding to the previously dedicated edge (rising or falling edge). in this mode, register b2 is accessed; buffer regist er b1 is hidden and is not readable. in the ocb and ocab modes, mdasmbr is loaded with the value corresponding to the trailing edge of the pulse to be generated. writing to mdasmbr in the ocb and ocab modes also enables the corresponding channel b comparator until the next successful comparison. in this mode, register b2 is accessed; buffer register b1 is hidden and is not readable. in the opwm mode, mdasmbr is loaded with the value co rresponding to the trailing edge of the pwm pulse to be generated. in this mode, register b1 is access ed; buffer register b2 is hidden and cannot be accessed. note: in ic, ipm, or ipwm mode, when a read to register a or b occurs at the same time as a counter bus capture into that register and the counter bus is changing value, then the counter bus capture to that register is delayed. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-44 freescale semiconductor msb 0 1 2 3 4 5 6 7 8 9 10 11 121314lsb 15 field pin wor fren ? edpol forca forcb ? bsl ? mode sreset ? 000_0000_0000_0000 addr 0x30 605e, 0x30 6066, 0x30 606e, 0x30 6076, 0x30 607e, 0x30 60de, 0x30 60e6, 0x30 60ee, 0x30 60f6, 0x30 60fe figure 17-24. mdasm status/control register (mdasmscr) table 17-21. mdasmscr bit descriptions bits name description 0 pin pin input status ? the pin input status bi t reflects the status of the corresponding bit. 1 wor wired-or bit ? in the dis, ipwm, ipm and ic modes, the wor bit is not used; reading this bit returns the value that was previously written. in the ocb, ocab and opwm modes, the wor bit selects whether the output buffer is configured for open-drain or totem pole opera tion. when open-drain mode is selected, the edpol bit is not used; writing to edpo l will have no effect on the output voltage. 1 output buffer is open-drain. 0 output buffer is totem pole. the wor bit is cleared by reset. 2 fren freeze enable bit ? this active high read/write control bit enables the mdasm to recognize the miob freeze signal. 1 = the mdasm is frozen if the miob freeze line is active. 0 = the mdasm is not frozen even if the miob freeze line is active. the fren is cleared by reset. 3?reserved 4 edpol polarity bit ? in the dis mode, this bit is not used; reading it return s the last value written. in the ipwm mode, this bit is used to select the capture edge sensitivity of channels a and b. 1 channel a captures on a falling edge. channel b captures on a rising edge. 0 channel a captures on a rising edge. channel b captures on a falling edge. in the ipm and ic modes, the edpol bit is used to select the input capture edge sensitivity of channel a. 1 channel a captures on a falling edge. 0 channel a captures on a rising edge. in the ocb, ocab and opwm modes, the edpol bit is used to select the voltage level on the output signal. if open-drain mode is selected via the wor bit, the edpol bit is disabled and writing to it will have no effect on the output voltage. 1 the complement of the output flip-flop logi c level appears on the output signal: a match on channel a resets the output signal; a match on channel b sets the output signal. 0 the output flip-flop logic level appears on t he output signal: a match on channel a sets the output signal, a match on channel b resets the output signal. the edpol bit is cleared by reset. 5 forca force a bit ? in the ocb, ocab and opwm mo des, the forca bit allows the software to force the output flip-flop to behave as if a successf ul comparison had occurred on channel a (except that the flag line is not activated). writing a one to forca sets the outp ut flip-flop; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forca bit is not used and writing to it has no effect. forca is cleared by reset and is always read as zero. writing a one to both forca and forcb simu ltaneously resets the output flip-flop. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-45 6 forcb force b bit ? in the ocb, ocab and opwm mo des, the forcb bit allows the software to force the output flip-flop to behave as if a successf ul comparison had occurred on channel b (except that the flag line is not activated). writing a one to forcb resets the output flip-flop; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forcb bit is not used and writing to it has no effect. forcb is cleared by reset and is always read as zero. writing a one to both forca and forcb simu ltaneously resets the output flip-flop. 7:8 ? reserved 9:10 bsl bus select bits ? these bits are used to sele ct which of the six 16-bit counter buses is used by the mdasm. each mdasm instance has four po ssible counter buses that may be connected. see table 17-23 for more information. note: unconnected counter buses inputs are grounded. 11 ? reserved 12:15 mode mode select bits ? the four mode select bi ts select the mode of operation of the mdasm. to avoid spurious interrupts, it is recommended that mdasm interrupts are disabled before changing the operating mode. the mode select bits are cleared by reset. note: the reserved modes should not be set; if th ese modes are set, the mdasm behavior is undefined. table 17-22. mdasm mode selects mdasm control register bits bits of resolution counter bus bits ignored mdasm mode of operation mode 0000 ? ? dis ? disabled 0001 16 ? ipwm ? input pulse width measurement 0010 16 ? ipm ? input period measurement 0011 16 ? ic ? input capture 0100 16 ? ocb ? output compare, flag on b compare 0101 16 ? ocab ? output compare, flag on a and b compare 0110 ? ? reserved 0111 ? ? reserved 1000 16 ? opwm ? output pulse width modulation 1001 15 0 opwm ? output pulse width modulation 1010 14 0,1 opwm ? output pulse width modulation 1011 13 0-2 opwm ? output pulse width modulation 1100 12 0-3 opwm ? output pulse width modulation 1101 11 0-4 opwm ? output pulse width modulation table 17-21. mdasmscr bit descriptions (continued) bits name description modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-46 freescale semiconductor 17.10 mios14 pulse width modu lation submodule (mpwmsm) the mios14 pulse width modulation submodule (mpw msm) is a function included in the mios14 library. it allows pulse width modulated signals to be generated over a wide range of frequencies, independently of other mios14 output signals and with no software in tervention. the output pulse width can vary from 0% to 100%. the minimum pulse width is twice the minimum mios14 clock period (i.e., the minimum pulse width is 50 ns when f sys is 40 mhz). the mwpmsm can run in a double-buffered mode, to avoid spurious update. the following sections de scribe the mpwmsm in detail. a block diagram of the mpwmsm is shown in figure 17-25 . 1110 9 0-6 opwm ? output pulse width modulation 1111 7 0-8 opwm ? output pulse width modulation table 17-23. mdasm counter bus selection sub- module type block number connected to: cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 mdasm 11 cb6 cb22 cb7 cb8 mdasm 12 cb6 cb22 cb7 cb8 mdasm 13 cb6 cb22 cb23 cb24 mdasm 14 cb6 cb22 cb23 cb24 mdasm 15 cb6 cb22 cb23 cb24 mdasm 27 cb6 cb22 cb23 cb24 mdasm 28 cb6 cb22 cb23 cb24 mdasm 29 cb6 cb22 cb7 cb8 mdasm 30 cb6 cb22 cb7 cb8 mdasm 31 cb6 cb22 cb7 cb8 table 17-22. mdasm mode selects (continued) mdasm control register bits bits of resolution counter bus bits ignored mdasm mode of operation mode modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-47 figure 17-25. mpwmsm block diagram 17.10.1 mpwmsm terminology terminology used in the mios14 pulse width m odulation submodule incl udes the following: bits of resolution the mpwmsm contains a 16- bit modulus down-counter that counts from the desired loaded value to 0x0001. the term ?b its of resolution? is used in this document to indicate the size of the e quivalent free running binary counter. to cover the worst case, the number of bits is rounded to the lower number. for example, if the counter is preset with a value between 128 and 255, it is said to have seven bits of resolution. if it is pres et with a value betwee n 256 and 511, it is said to have eight bits of resolution, and so on. resolution the term ?resolution? is used in this document to define the minimum mpwmsm output increment in time units. 17.10.2 mpwmsm features ? output pulse width modulated (pwm) signal generation with no software intervention ? built-in 8-bit programmable pr escaler clocked by the mcpsm 16-bit down counter 8- bit prescaler ps7 - ps0 output submodule bus buffer (ncount) = 0x0001 pol next period register mpwmperr 16-bit pulse width register next pulse width register mpwmpulr2 output flip-flop pin trsp en counter output signal mpwmcntr request bus <= comparator load fren clock flag en ddr output logic output logic mpwmpulr1 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-48 freescale semiconductor ? pwm period and pulse width values provided by software: ? double-buffered for glitch-free period and pulse width changes ? minimum output period/pulse-width increment: 50 ns (assuming f sys = 40 mhz) ? maximum 50% duty-cycle output fr equency: 10 mhz (assuming f sys = 40 mhz) ? up to 16 bits of resolution for the output pulse width ? wide range of periods ? 16 bits of resolution: period range from 3.27 ms (with 50-ns step s) to 6.71 s (with 102.4 s steps) ? eight bits of resolution: period range from 12.8 s (with 50-ns steps) to 26.2 ms (with 102.4- s steps) ? wide range of frequencies ? maximum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-2 prescaler selection: 305 hz (3.27 ms.) ? minimum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-4096 prescaler selection: 0.15 hz (6.7 s.) ? maximum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-2 prescaler selection: 78125 hz (12.8 s.) ? minimum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.15 hz (26.2 ms.) ? programmable duty cy cle from 0% to 100% ? possible interrupt generatio n at start of every period ? software selectable output pulse polarity ? software readable output signal status ? possible use of signal as i/o por t when pwm function is not needed 17.10.3 mpwmsm description the purpose of the mpwmsm is to create a variable pulse width output signal at a wide range of frequencies, independently of other mios14 output signals. the mpwmsm include s its own counter, and thus does not use the mios 14 counter bus set. however the mpwmsm uses the prescale d clock bus that originates in the mios14 counter prescaler submodule (mcpsm). th e mpwmsm pulse width can vary from 0% to 100%, with up to 16 bits of resoluti on. the finest output resolution is the mios14 clock period multiplied by two (f or a mios14 clock with f sys = 40 mhz, the finest output pulse width resolution is 50 ns). with the full 16 bits of resolu tion and the mcpsm set to divide by two, the period of the output signal can range from 3.276 ms to 6.71 s (assuming f sys = 40 mhz). by reducing the amount of bits of resolution, the out put signal period can be reduced. for example, the period can be as fast as 204.8 s (4882 hz) with 12 bits of resolution, as fast as 12.8 s (78.125 khz) with eight bits of resolution, and as fast as 3.2 s (312.5 khz) with six bits of resolution (still assuming a f sys = 40 mhz and the mcpsm set to divide by two). the mpwmsm is composed of: modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-49 ? an output flip-flop with output buffer and polarity control ? an input/output signal with data direction control ? an 8-bit prescaler and clock selection logic ? a 16-bit down-counter (mpwmcntr) ? a register to hold the ne xt period values (mpwmperr) ? two registers to hold the current a nd next pulse width values (mpwmpulr) ? a less-than or equal comparator ? a status and control register (mpwmscr) 17.10.3.1 clock selection the mpwmsm contains an 8-bit prescaler cloc ked by the output signal from the mios14 counter prescaler submodule (f sys /2 to f sys /16). the mpwmsm clock selector allows the choice, by software, of one of 256 divide ratios which give to the mpwm sm a large choice of fre quencies available for the down-counter. the mpwmsm down-count er is thus capable of counti ng with a clock frequency ranging from f sys /2 to f sys /4096. switching the mpwmsm from disable to enable will reload the value of mpwmscr[cp] into the 8-bit prescaler counter. 17.10.3.2 counter a 16-bit down-counter in the mpwmsm provides the time reference for the output signal. the counter is software writable. when writing to the counter (i.e., at the mpwmcntr address), it also writes to the mpwmperr register. when in tran sparent mode (trsp = 1), writing to the mpwmperr will also write to the counter. the down-counter is readable at anytime. the value loaded in the down-counter corresponds to the period of the output signal. when the mpwmsm is enabled, the counter begins counting. as long as it is enabled, the counter counts down freely. the counter counts at the rate establis hed by the prescaler. when the count down reaches 0x0001, the load operation is executed and the valu e in the mpwmperr register is loaded in the mpwmcntr register, (i.e., the counter). then the counter restarts to count down from that value. 17.10.3.3 period register the period section is composed of a 16-bit data re gister (mpwmperr). the software establishes the period of the output signal in register mpwmperr. when the mpwmsm is running in transparent m ode, the period value in register mpwmperr is immediately transferred to the c ounter on a write to the mpwmperr. when the mpwmsm is running in double-buffered mo de, the period value in register mpwmperr can be changed at any time without affecting the curre nt period of the output si gnal. the new value of mpwmperr will be transferred to the counter onl y when the counter reaches the value of 0x0001 and generates a load signal. period values of 0x0000, 0x0001, and 0x0002 are mpwmsm special cases: modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-50 freescale semiconductor ? the value 0x0000 in the period register, causes the c ounter to act like a fr ee running counter. this condition creates a period of 65536 pwm clock periods. ? the value 0x0001 in the period register will always cause a period match to occur and the counter will never decrement below 0x0001. this condition is defined as a period of ?1? pwm clock count. the output flip-flop is always set unless mp wmpulr = 0x0000, when the output flip-flop is always reset. refer to section 17.10.3.5, ?duty cycles (0% and 100%) ? for details about 0% and 100% duty cycles. ? writing value 0x0002 in the period re gister causes a period match to occur every two clock periods. the counter decrements from 0x0002 to 0x0001, and then it is initialized back to 0x0002. this condition is defined as a period of 2 clock counts. note that th e value 0x0002 loaded in the period register and a value of 0x0001 in th e pulse width register is the condition to obtain the maximum possible output frequency for a given clock period. the relationship between the output frequency obtained (f pwmo ) and the mios14 clock frequency (f sys ), the mcpsm clock divide ratio (n mcpsm ), the counter divide ratio (n mpwmsm ) and the value loaded in the counter (v counter ) is given by the following equation: 17.10.3.4 pulse width registers the pulse width section is com posed of two 16-bit data regist ers (mpwmpulr1 and mpwmpulr2). only mpwmpulr1 is accessible by software. the software establishes the pulse width of the mpwmsm output signal in mpwmpulr1. mpwm pulr2 is used as a double buffer of mpwmpulr1. when the mpwmsm is running in transparent m ode, the pulse width value in mpwmpulr1 is immediately transferred in mpwmpulr2 so th at the new value takes effect immediately. note when the mpwmsm is in disable mode, writing to mpwmpulr1 will write automatically to mpwmpulr2. when the mpwmsm is not running in double-buffe red mode, the pulse width value in mpwmpulr1 can be changed at any time without affecting the current pulse width of the output signal. the new value in mpwmpulr1 will be transferre d to mpwmpulr2 only when the dow n-counter reaches the value of 0x0001. when the counter first reaches the value in mpwmpulr 2, the output flip-flop is set. the output is reset when the counter reaches 0x0001. the pulse width match st arts the width of the output signal, it does not affect the counter. mpwmpulr1 is software readable an d writable at any time . the mpwmsm does not modify the content of mpwmpulr1. the pwm output pulse width can be as wide as one period minus one mpwm sm clock count: (i.e., mpwmpulr2 = mpwmperr ? [one mpwmsm clock c ount]). at the other end of the pulse width range, mpwmpulr2 can contain 0x0001 to creat e a pulse width of one pwm clock count. f pwmo = f sys n mcpsm ? n mpwmsm ? v counter modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-51 for example, with 0x00ff in the counter and 0x0002 in mpwmpulr2, the period is 255 pwm clock count and the pulse width is 2 pwm clock counts. for a given system clock frequency, with a given counter divi de ratio and clock sel ection divide ratio, the output pulse width is give n by the following equation: where v mpwmb2 is the value in the register b2 in such conditions, the minimum output pulse width that can be obtained is given by: and the maximum pulse width by: 17.10.3.5 duty cycles (0% and 100%) the 0% and 100% duty cycles are special cases to give flexibility to the so ftware to create a full range of outputs. the ?always set? and ?alway s clear? conditions of th e output flip-flop are es tablished by the value in register mpwmpulr2. these boundary conditions are generated by soft ware, just like another pulse. when the pwm output is being used to generate an analog level, the 0% and 100% represent the full scale values. the 0% output is created with a 0x0000 in register mpwmpulr2, which preven ts the output flip-flop from ever being set. the 100% output is created when the content of regi ster mpwmpulr2 is equal to or greater than the content of register mpwmperr. thus, the width re gister match occurs on c ounter reload. the state sequencer provides the timing to ensure that th e first appearance of a 100% value in register mpwmpulr2 causes a glitchless always-set condition of the out put flip-flop when trsp = ?0?. note even if the output is forced to 100%, the 16-bit up counter continues its counting and that output changes to or from the 100% value are done synchronously to the selected period. note when a pwm output period is selected to be 655 36 pwm clocks by loading 0x0000 in the period register, it is not possible to have an 100% duty cycle output signal. in this case, the ma ximum duty cycle available is of 65535/65536. pulse_width n mcpsm n mpwmsm 2v mpwmb2 2 f sys -------------------------------------------------------------------------------------------------------- - = minimum_pulse_width n mcpsm n mpwmsm 2 f sys ------------------------------------------------------------------ - = maximum_pulse_width n mcpsm n mpwmsm 22 bit_of_resolution 1 ? () 2 f sys ------------------------------------------------------------------------------------------------------------------------------- --------- - = modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-52 freescale semiconductor 17.10.3.6 pulse/frequency range table table 17-24 summarizes the frequency and minimum pulse width values that can be obtained respectively with divide-by-1 and divide-by- 256 mpwmsm clock prescaler optio ns, while using a mios14 clock frequency of 40 mhz, and for e ach mcpsm clock divide ratios. table 17-24. pwm pulse/frequency ranges (in hz) using /1 or /256 option (40 mhz) minimum pulse width bits of resolution 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 with /1 option 50 ns/2 305 610 1220 2441 4882 9765 19.5 k 39k 78k 156k 312k 625k 1250 k 2500 k 5000 k 10000 k 75 ns/3 203 407 814 1628 3255 6510 13k 26k 52k 104k 208k 416k 833 k 1666 k 3333 k 6666k 100 ns/4 152 305 610 1220 2441 4882 9765 19.5 k 39k 78k 156k 312k 625 k 1250 k 2500 k 5000k 125 ns/5 122 244 488 976 1953 3906 7812 15.6 k 31.3 k 62.5k 125k 250k 500 k 1000 k 2000 k 4000k 150 ns/6 101 203 407 814 1628 3255 6510 13k 26k 52k 104k 208k 416 k 833k 1666 k 3333k 175 ns/7 87.2 174 348 697 1395 2790 5580 11.1 k 22.3 k 44.6k 89.3 k 178k 357k 714k 1428 k 2857k 200 ns/8 76.3 152 305 610 1220 2441 4882 9765 19.5 k 39k 78k 156 k 312 k 625k 1250 k 2500k 225 ns/9 67.8 135 271 542 1085 2170 4340 8680 17.3 k 34.7k 69.4 k 138k 277k 555k 1111 k 2222k 250 ns/10 61 122 244 488 976 1953 3906 7812 15.k 31.3k 62.5 k 125k 250 k 500 k 1000 k 2000k 275 ns/11 55.5 111 222 443 887 1775 3551 7102 14.2 k 28.4k 56.8 k 113k 227 k 454k 909 k 1818 k 300 ns/12 50.8 101 203 407 814 1628 3255 6510 13k 26k 52k 104k 208 k 416k 833 k 1666 k 325 ns/13 46.9 93.9 187 375 751 1502 3004 6009 12k 24k 48k 96.1 k 192 k 384k 769 k 1538 k 350 ns/14 43.6 87.2 174 348 697 1395 2790 5580 11.1 k 22.3 k 44.6 k 89.3 k 178 k 357k 714 k 1428k 375 ns/15 40.7 81.4 162 325 651 1302 2604 5208 10.4 k 20.8 k 41.6 k 83.3 k 166 k 333k 666 k 1333 k 400 ns/16 38.1 76.3 152 305 610 1220 2441 4882 9765 19.5k 39k 78k 156k 312k 625k 1250k with /256 option 12.8 s/512 1.192 2.384 4.768 9.536 19. 07 38.14 76.29 152.5 305.1 610.3 1220 2441 4882 9765 19.5k 39k 19.2 s/768 0.794 1.589 3.178 6.357 12.71 25.43 50.86 101.7 203.4 406.9 813. 8 1627 3255 6510 13 k 26k modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-53 17.10.3.7 mpwmsm status and control register (scr) one register is used to initializ e the mpwmsm and monitor its operati on. control bits are included to allow the software to enable the pwm generator, es tablish the output signal polar ity, select the counter clock rate and set the glitch-free mode . a status bit is included to allow the software to read the state of the output signal. 17.10.3.8 mpwmsm interrupt a valid mpwmsm interrupt is recognized when a pulse occurs on the flag line to set the flag bit and the interrupt enable bit is set for the co rresponding level in the mirsm (refer to section 17.12, ?mios14 interrupts ,? section 17.12.1, ?mios14 interrupt structure ? and section 17.12.2, ?mios14 interrupt request submodule (mirsm) ? for details about interrupts). a set flag pulse is generated at the start of every period. 25.6 s /1024 0.596 1.192 2.384 4.768 9.536 19.07 38.14 76.29 152.5 305.1 610. 3 1220 2441 4882 9765 19.5k 32 s/1280 0.476 0.953 1.907 3.814 7.629 15.24 30.51 61.03 122 244.1 488. 2 976. 5 1953 3906 7812 15.6k 38.4 s /1536 0.397 0.795 1.589 3.179 6.358 12.71 25.43 50.86 101.7 203.5 406. 9 813. 8 1627 3255 6510 13k 44.8 s /1792 0.34 0.681 1.362 2.724 5.449 10.89 21.80 43.59 87.19 174.4 348. 8 697. 5 1395 2790 5580 11.1k 51.2 s /2048 0.298 0.596 1.192 2.384 4.768 9.536 19.07 38.14 76.29 152.5 305. 1 610. 3 1220 2441 4882 9765 57.6 s /2304 0.264 0.529 1.059 2.119 4.238 8.477 16.95 33.90 67.81 135.6 271. 2 542. 5 1085 2170 4340 8680 64 s/2560 0.238 0.476 0.953 1.907 3. 814 7.629 15.24 30.51 61.03 122 244. 1 488. 2 976.5 1953 3906 7812 70.4 s /2816 0.216 0.433 0.867 1.734 3.468 6.936 13.87 27.74 55.48 110.9 221. 9 443. 9 887.8 1775 3551 7102 76.8 s /3072 0.198 0.397 0.795 1.589 3.179 6.358 12.71 25.43 50.86 101.7 203. 5 406. 9 813.8 1627 3255 6510 83.2 s /3328 0.183 0.366 0.733 1.467 2.934 5. 869 11.74 23.47 46.95 93.9 187. 8 375. 6 751.2 1502 3004 6009 89.6 s /3584 0.170 0.340 0.681 1.362 2.724 5.449 10.89 21.80 43.59 87.19 174. 4 348. 8 697.5 1395 2790 5580 96 s/3840 0.159 0.318 0.636 1.271 2.543 5.086 10.17 20. 34 40.69 81.38 162. 8 325. 5 651 1302 2604 5208 table 17-24. pwm pulse/frequency ranges (in hz) us ing /1 or /256 option (40 mhz) (continued) minimum pulse width bits of resolution 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-54 freescale semiconductor the flag bit is a status bit which indicates, when se t, that the output period has started and that registers mpwmperr and mpwmpulr1 are av ailable for updates when in doubl e-buffered mode. the level of the resulting interrupt is determined in the mirsm. 17.10.3.9 mpwmsm port functions the mpwmsm has one dedicated i/o external signal. the output flip-flop is the basic out put of the mpwmsm. except when th e pulse width is at 100% or 0%, the output flip-flop is reset at th e beginning of each period and is se t at the beginning of the designated pulse width until the end of the period. as a software option, the polarity of the signal presented to the output signal may be the state of the output flip-flop or the i nverse of the output flip-flop. the mpwmsm is connected to an external, input/output signal. when in the disabled mode, the pol bit (polarity) and the ddr bit (data direction) in the scr register al low the mpwmsm to be used as an i/o port. 17.10.3.10 mpwmsm data coherency byte accesses to mpwmpu lr and mpwmperr are suppor ted, but are not recommended as the transfer from the primary registers to the secondary registers are done as a 16-bit word transfer. for most mpwmsm operations, 16-bit accesses are sufficient and long wo rd accesses (32-bit) are treated as two 16-bit accesses, with one exception ? a long word write to the period/pulse wi dth registers. in this case, if the long word write take s place within the pwm period, there is no visible effect on the output signal and the new values stored in mpwmperr and mpwmpulr are rea dy to be loaded into the buffer registers at the start of the next period. if, however, the long word wr ite coincides with the end of the period, then the transfer of values from the primary to the secondary re gisters is delayed until the end of the next period; during this peri od the previous values are used fo r the period and width. this feature enables updates of the period and pulse-width values without getting erroneous pulses. 17.10.4 modular input/output bus (mios14) interface the mpwmsm is connected to all the signals in the read /write and control bus, to allow data transfer from and to the mpwmsm registers, a nd to control the mpwmsm in th e different possible situations. ? the mpwmsm is not using any of the 16-bit counter buses. ? the mpwmsm uses the request bus to transmit to the request submodule. 17.10.5 effect of reset on mpwmsm the mpwmsm is affected by reset according to what is described in the section related to register description. the mpwmperr, mpwmpulr, and mpwmcntr registers, together with the cl ock prescaler register bits, must be initialized by software, sinc e they are undefined after hardware reset. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-55 a value must be written to the mpwmcntr (which writes the same value into the mpwmperr) and a pulse width value written to mpwmpulr, before the mpwmscr is written to. the latter access initializes the clock prescaler. 17.10.6 mpwmsm registers the privilege level to access to the mpwmsm registers depends on th e mios14mcr[supv]. the privilege level is unrestricted after reset a nd can be change to s upervisor by software. 17.10.6.1 mpwmsm registers organization the mpwmsm register map comprises four 16-bit register locat ions, as shown in table 17-25 . all unused bits return zero when read by the software. all regist er addresses in this section are specified as offsets from the base address of the mpwmsm. table 17-25. mpwmsm address map address register mpwmsm0 0x30 6000 mpwmsm0 period register (mpwmperr) see table 17-26 for bit descriptions. 0x30 6002 mpwmsm0 pulse register (mpwmpulr) see table 17-27 for bit descriptions. 0x30 6004 mpwmsm0 count register (mpwmcntr) see table 17-28 for bit descriptions. 0x30 6006 mpwmsm0 status/c ontrol register (mpwmscr) see table 17-29 for bit descriptions. mpwmsm1 0x30 6008 mpwmsm1 period register (mpwmperr) 0x30 600a mpwmsm1 pulse register (mpwmpulr) 0x30 600c mpwmsm1 count register (mpwmcntr) 0x30 600e mpwmsm1 status/c ontrol register (mpwmscr) mpwmsm2 0x30 6010 mpwmsm2 period register (mpwmperr) 0x30 6012 mpwmsm2 pulse register (mpwmpulr) 0x30 6014 mpwmsm2 count register (mpwmcntr) 0x30 6016 mpwmsm2 status/c ontrol register (mpwmscr) mpwmsm3 0x30 6018 mpwmsm3 period register (mpwmperr) 0x30 601a mpwmsm3 pulse register (mpwmpulr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-56 freescale semiconductor 0x30 601c mpwmsm3 count register (mpwmcntr) 0x30 601e mpwmsm3 status/c ontrol register (mpwmscr) mpwmsm4 0x30 6020 mpwmsm4 period register (mpwmperr) 0x30 6022 mpwmsm4 pulse register (mpwmpulr) 0x30 6024 mpwmsm4 count register (mpwmcntr) 0x30 6026 mpwmsm4 status/c ontrol register (mpwmscr) mpwmsm5 0x30 6028 mpwmsm5 period register (mpwmperr) 0x30 602a mpwmsm5 pulse register (mpwmpulr) 0x30 602c mpwmsm5 count register (mpwmcntr) 0x30 602e mpwmsm5 status/c ontrol register (mpwmscr) mpwmsm16 0x30 6080 mpwmsm16 period register (mpwmperr) 0x30 6082 mpwmsm16 pulse register (mpwmpulr) 0x30 6084 mpwmsm16 coun t register (mpwmcntr) 0x30 6086 mpwmsm16 status/control register (mpwmscr) mpwmsm17 0x30 6088 mpwmsm17 period register (mpwmperr) 0x30 608a mpwmsm17 pulse register (mpwmpulr) 0x30 608c mpwmsm17 coun t register (mpwmcntr) 0x30 608e mpwmsm17 status/control register (mpwmscr) mpwmsm18 0x30 6090 mpwmsm18 period register (mpwmperr) 0x30 6092 mpwmsm18 pulse register (mpwmpulr) 0x30 6094 mpwmsm18 coun t register (mpwmcntr) 0x30 6096 mpwmsm18 status/control register (mpwmscr) mpwmsm19 0x30 6098 mpwmsm19 period register (mpwmperr) 0x30 609a mpwmsm19 pulse register (mpwmpulr) 0x30 609c mpwmsm19 coun t register (mpwmcntr) table 17-25. mpwmsm address map (continued) address register modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-57 17.10.6.2 mpwmsm period register (mpwmperr) the period register contains the binary value corresponding to the period to be generated. 17.10.6.3 mpwmsm pulse width register (mpwmpulr) the pulse width register contains the binary value of the pulse width to be generated. 0x30 609e mpwmsm19 status/control register (mpwmscr) mpwmsm20 0x30 60a0 mpwmsm20 period register (mpwmperr) 0x30 60a2 mpwmsm20 pulse register (mpwmpulr) 0x30 60a4 mpwmsm20 coun t register (mpwmcntr) 0x30 60a6 mpwmsm20 status/control register (mpwmscr) mpwmsm21 0x30 60a8 mpwmsm21 period register (mpwmperr) 0x30 60aa mpwmsm21 pulse register (mpwmpulr) 0x30 60ac mpwmsm21 coun t register (mpwmcntr) 0x30 60ae mpwmsm21 status/control register (mpwmscr) msb 01234567891011121314 lsb 15 field per sreset undefined addr 0x30 6000, 0x30 6008, 0x30 6010, 0x30 6018, 0x30 6020, 0x30 6028, 0x30 6080, 0x30 6088, 0x30 6090, 0x30 6098, 0x30 60a0, 0x30 60a8 figure 17-26. mpwmsm period register (mpwmperr) table 17-26. mpwmperr bit descriptions bits name description 0:15 per period. these bits contain the binary value corresponding to the period to be generated. table 17-25. mpwmsm address map (continued) address register modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-58 freescale semiconductor 17.10.6.4 mpwmsm counter register (mpwmcntr) the counter register reflects the act ual value of the mpwmsm counter. this register is writable only th rough the period register (pwmperr). writes to th e counter register will write the same value to the period register. 17.10.6.5 mpwmsm status/control register (mpwmscr) the status and control regi ster gathers read only bits reflecting th e status of the mpwmsm signal as well as read/write bits related to its control and configuration. msb 01234567891011121314 lsb 15 field pul sreset undefined addr 0x30 6002, 0x30 600a, 0x30 6012, 0x30 601a, 0x30 6022, 0x30 602a, 0x30 6082, 0x30 608a, 0x30 6092, 0x30 609a, 0x30 60a2, 0x30 60aa figure 17-27. mpwmsm pulse width register (mpwmpulr) table 17-27. mpwmpulr bit descriptions bits name description 0:15 pul pulse width. these bits contain the bi nary value of the pulse width to be generated. msb 01234567891011121314 lsb 15 field cnt sreset undefined addr 0x30 6004, 0x30 600c, 0x30 6014, 0x30 601c, 0x30 6024, 0x30 602c, 0x30 6084, 0x30 608c, 0x30 6094, 0x30 609c, 0x30 60a4, 0x30 60ac figure 17-28. mpwmsm counter register (mpwmcntr) table 17-28. mpwmcntr bit descriptions bits name description 0:15 cnt counter. these bits reflect the actual value of the mpwmsm counter. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field pin ddr fren trsp pol en ? cp sreset u 000_00 undefined addr 0x30 6004, 0x30 600c, 0x30 6014, 0x30 601c, 0x30 6024, 0x30 602c, 0x30 6084, 0x30 608c, 0x30 6094, 0x30 609c, 0x30 60a4, 0x30 60ac figure 17-29. mpwmsm status/control register (mpwmscr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-59 . table 17-29. mpwmscr bit descriptions bits name description 0 pin pin input status bit ? the pin bit reflects the state present on the mpwmsm signal. the software can thus monitor the pin state. the pin bit is a read-only bit. writ ing to the pin bit has no effect. 1 ddr data direction register ? the ddr bit indicates the direction for the signal when the pwm function is not used (disable mode). 0 signal is in input. 1 signal is in output. the ddr bit is cleared by reset. table 17-30 lists the different uses for the polarity (p ol) bit, the enable (en) bit and the data direction register (ddr) bit. 2 fren freeze enable bit ? this active high read/write control bit enables the mpwmsm to recognize the freeze signal on the miob. 0 mpwmsm not frozen even if the miob freeze line is active. 1 mpwmsm frozen if the miob freeze line is active. the fren is cleared by reset. 3 trsp transparent mode ? the trsp bit indicates t hat the mpwmsm is in transparent mode. in transparent mode, when the software writes to either the mpwmperr or mpwmpulr1 register the value written is immediately transferred to the counter or register mpwmpulr2 respectively. 0 double-buffered mode. 1 transparent mode. the trsp bit is cleared by reset. 4 pol output polarity control bit ? the pol bit work s in conjunction with the en bit and controls whether the mpwmsm drives the signal with the dire ct or the inverted value of the output flip-flop. table 17-30 lists the different uses for the polarity (p ol) bit, the enable (en) bit and the data direction register (ddr) bit. 5 en enable pwm signal generation ? the en bit defines whether the mpwmsm generates a pwm signal or is used as an i/o channel: 0 pwm generation disabled (signal can be used as i/o). 1 pwm generation enabled (the signal is in output mode). each time the submodule is enabled, the value of cp is loaded into the prescaler. the en bit is cleared by reset. 6:7 ? reserved 8:15 cp clock prescaler ? this 8-bit read/write data register stores the modulus value for loading into the built-in 8-bit clock prescaler. the value loaded defines the divide ratio for the signal that clocks the mpwmsm. the new value is loaded into t he prescaler counter on the prescaler counter overflow, or upon the en bit of the mpwmscr being set. table 17-31 gives the clock divide ratio according to the value of cp. table 17-30. pwmsm output signal polarity selection control bits signal direction signal state periodic edge variable edge optional interruption pol en ddr 0 0 0 input input ? ? ? 0 0 1 output always low ? ? ? 0 1 x output high pulse falling edge rising edge falling edge 1 0 0 input input ? ? ? modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-60 freescale semiconductor 17.11 mios14 16-bit parallel po rt i/o submodule (mpiosm) the mios14 parallel port i/o submodule (mpiosm) is a function included in the mios14 library in order to provide the required port i/o capability. the mp iosm can operate without the involvement of other mios14 submodules. each implemented mpiosm provides i/o capability for up to 16 signals. the following sections describe the mpiosm in deta il. a block diagram of one bit of the mpiosm is shown in figure 17-30 . the mpiosm contains 16 such blocks. figure 17-30. mpiosm 1-bit block diagram 1 0 1 output always high ? ? ? 1 1 x output low pulse rising edge falling edge rising edge table 17-31. prescaler values prescaler value (cp in hex) mcpsm divide ratio: ff 1 fe 2 fd 3 fc 4 fb 5 fa 6 f9 7 f8 8 ...... ........ 02 254 (2^8 -2) 01 255 (2^8 -1) 00 256 (2^8) table 17-30. pwmsm output signal polarity selection (continued) i/o signal data register data register output input driver mios14 bus (miob) direction modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-61 17.11.1 mpiosm features ? a submodule of the mios14 library ? uses two 16-bit register s in the address space ? up to 16 bidirectional pa rallel input/output signals ? simple ddr (data directio n register) concept for si gnal direction selection 17.11.2 mpiosm signal functions table 17-32 shows the mpiosm i/o signal f unctions according to the setti ng of the ddr when writing to or reading from the dr. 17.11.3 mpiosm description 17.11.3.1 mpiosm port function a mios14 parallel port i/o subm odule can handle up to 16 input/out put signals. the number of i/o signals is determined at the time of silicon implementation. the mpiosm has two 16-bit registers: the data register (dr) and the data direction register (ddr). each signal of the mpiosm may be programmed as an i nput or an output, determined by the state of the corresponding bit in the ddr. the data direction register can be written to or read by the proc essor. during the programmed output state, a read of the data regi ster reads the value of the output data la tch and not the i/o signal. see figure 17-30 and table 17-32 . during reset, all mpiosm signals are configured as inputs. th e contents of the data register are undefined after reset. as a general practice, it is recommended to write a value in the data register before configuring its corresponding i/o signal as an output. 17.11.3.2 non-bonded mpiosm pads a non-bonded mpiosm pad reads ?0? when it is configur ed as an input. when conf igured as an output, it indicates the current state of the output data latch. table 17-32. mpiosm i/o signal function operation performed ddr i/o signal function write 0 the i/o signal is in input mode. data is written into the dr. write 1 data is written into the dr and output to the i/o signal. read 0 the i/o signal is in input mode. the state of the i/o signal is read. read 1 the i/o signal is in an output mode. the dr is read. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-62 freescale semiconductor 17.11.4 modular i/o bus (miob) interface ? the mpiosm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mpiosm registers, and to contro l the mpiosm in the diff erent possible situations. ? the mpiosm does not use the counter bus se t and is therefore not connected to it. ? the mpiosm does not generate any interrupts and is therefore not connected to this bus. 17.11.5 effect of reset on mpiosm when the reset signal is asserted, all the ddr bits are cleared. the data bits are undefined after reset. 17.11.6 mpiosm testing no special test logic has been impl emented in this submodule. to be flexible while selecting the number of implemented signals, the test patterns are implemented in a bit per bit modular fashion. 17.11.7 mpiosm registers the privilege level to access to the mpiosm registers depends on the mios14mcr[supv]. the privilege level is unrestricted after reset a nd can be change to s upervisor by software. 17.11.8 mpiosm register organization 17.11.8.1 mpiosm data register (mpiosmdr) msb 0 1234567891011121314lsb 15 0x30 6100 mpiosm data register (mpiosmdr) 0x30 6102 mpiosm data direction register (mpiosmddr) 0x30 6104 reserved 0x30 6106 reserved figure 17-31. mpiosm ? register organization msb 012345678 9101112131415 field data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 sreset undefined addr 0x30 6100 figure 17-32. mpiosm data register (mpiosmdr) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-63 17.11.8.2 mpiosm data direction register (mpiosmddr) 17.12 mios14 interrupts this section describes the interrupt functions of the mios14 and its submodules and how these interrupts are passed to the cpu via the periph eral bus. interrupt requests from th e mios14 are treated as exceptions by the cpu and are dealt with by the cpu?s exception pr ocessing routines. for a mo re detailed description of exception processing in the rele vant microprocesso rs, please refer chapter 3, ?central processing unit ? and to the rcpu reference manual . 17.12.1 mios14 interrupt structure the mios14 and its submodules are capable of generati ng interrupts on different le vels to be transmitted to the cpu via the peripheral bus. inside the mios 14, all the information re quired for requesting and servicing the interrupts are treat ed in two different sections: ? the interrupt request submodules (mirsm) ? the interrupt control section (ics) of the mbism the mirsm gathers in service request flags from each group of up to 16 submodules and transfers those requests to the mios14 interru pt control section (ics). figure 17-34 shows a block diagram of the whole interrupt architecture. table 17-33. mpiosmdr bit descriptions bits name description 15:0 data15? data0 these bits are read/write data bi ts that define the value to be driven to the pad in output mode, for each implemented i/o signal of t he mpiosm. the msb is 15, lsb is 0. msb 012345678 9101112131415 field ddr 15 ddr 14 ddr 13 ddr 12 ddr 11 ddr 10 ddr 9 ddr 8 ddr 7 ddr 6 ddr 5 ddr 4 ddr 3 ddr 2 ddr 1 ddr 0 sreset 0000_0000_0000_0000 addr 0x30 6100 figure 17-33. mpiosm data direction register (mpiosmddr) table 17-34. mpiosmddr bit descriptions bits name description 0:15 ddr15? ddr0 these bits are read/write data bits that define the data direction status for each implemented i/o signal of the mpiosm 0 = corresponding signal is input. 1 = corresponding signal is output. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-64 freescale semiconductor figure 17-34. mios14 interrupt structure 17.12.2 mios14 interrupt request submodule (mirsm) each submodule that is capable of ge nerating an interrupt can assert a fl ag line when an event occurs. on mpc561/mpc563 each mirsm serves 14 submodules. each mirsm includes: ? one 16-bit status register (for the flags) ? one 16-bit enable register for each implemented level ? one 16-bit irq pending register for each implemented level one bit position in each of the above re gisters is associated with one submodule. status register enable register irq pend. register mirsm0 (flags) imb3 mbism interrupt control status register enable register irq pend. register mirsm1 (flags) submodule 31 submodule 16 submodule 15 submodule 0 note: submodules 9, 10, 25, and 26 are reserved on the mpc561, mpc562, mpc563, and mpc564. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-65 note if a submodule in a group of 16 cannot generate interrupts, then its corresponding flag bit in the status regi ster is inactive and is read as zero. when an event occurs in a submodule that activates a flag line, the co rresponding flag bit in the status register is set. the status register is read/write, but a flag bit can be reset only if it has previously been read as a one. writing a ?one? to a flag bit has no effect. when the software intends to clear only one flag bit within a status register, the software must write an all-ones 16-bit value except for the bit position to be cleared which is a zero. the enable register is initialized by the software to indicate whether each interrupt request is enabled for the levels defined in the ics. note in the case of multiple requests leve ls implementation in the same mios14, it is possible to enable interrupts at more than one different levels for the same submodule. it is the responsibilit y of the software to manage this. each bit in the irq pending register is the result of a logical ?and? between th e corresponding bits in the status and in the enable registers. if a flag bit is set and the level enable bit is also set, then the irq pending bit is set, and the information is transferred to the in terrupt control section that is in charge of sending the corresponding level to th e cpu. the irq pending register is read only. note when the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the correspondi ng flag is set. this allows the traditional software approach of polling the flag bits to see which ones are set. the status register makes flag polling easy, since up to 16 flag bits are contained in one register. the submodule number of an interr upting source defines the corr esponding mirsm number and the bit position in the status registers. to find the mirs m number and bit position of an interrupting source, proceed as follow: 1. divide the interrupting submodule number by 16 2. the integer result of the division gives the mirsm number 3. the reminder of the division gives the bit position 17.12.3 mirsm0 interrupt registers 17.12.3.1 interrupt status register (mios14sr0) this register contains the flag bits that are raised when the submodules genera te an interrupt. each bit corresponds to a given submodule. modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-66 freescale semiconductor 17.12.3.2 interrupt enable register (mios14er0) this register contains the interrupt enable bits for the submodules. each bit corresponds to a given submodule. 17.12.3.3 interrupt request pending register (mios14rpr0) this register is a read only register that contains the interrupt pending bits for the submodules. each bit corresponds to a given submodule. when one of these bits is set, it mean s that a submodule raised its flag and the corresponding enable was set. msb 01234567891011121314 lsb 15 field flg 15 flg 14 flg 13 flg 12 flg 11 ?flg 8 flg 7 flg 6 flg 5 flg 4 flg 3 flg 2 flg 1 flg 0 sreset undefined addr 0x30 6c00 figure 17-35. interrupt status register (mios14sr0) table 17-35. mios14sr0 bit description bits name description 0:4 flg15:11 flag bits ? mdasm flag bits [15:11] 5:6 ? reserved 7:9 flg8:6 flag bits ? mmcsm flag bits [8:6] 10:15 flg5:0 flag bits ? pwmsm flag bits [5:0] msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field en15 en14 en13 en12 en11 ? en8 en7 en6 en5 en4 en3 en2 en1 en0 sreset 0000_0000_0000_0000 addr 0x30 6c04 figure 17-36. interrupt enable register (mios14er0) table 17-36. mios14er0 bit descriptions bits name description 0:4 en15:11 enable bits ? mdasm enable bits [15:11] 5:6 ? reserved 7:9 en8:6 enable bits ? mmcsm enable bits [8:6] 10:15 en5:0 enable bits ? pwmsm enable bits [5:0] modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-67 as this register is read on ly, a write to this register has no other effect than gene rating a bus error if the bus error option is selected. 17.12.4 mirsm1 interrupt registers 17.12.4.1 interrupt status register (mios14sr1) this register contains the flag bits that are raised when the submodules genera te an interrupt. each bit corresponds to a given submodule. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field irp15 irp14 irp13 irp12 irp1 ? irp8 irp7 irp6 irp5 irp4 irp3 irp2 irp1 irp0 sreset 0000_0000_0000_0000 addr 0x30 6c06 figure 17-37. interrupt request pending register (mios14rpr0) table 17-37. mios14pr0 bit descriptions bits name description 0:4 irp15:1 1 pending bits ? mdasm pending bits [15:11] 5:6 ? reserved 7:9 irp8:6 pending bits ? mmcsm pending bits [8:6] 10:15 irp5:0 pending bits ? pwmsm pending bits [5:0] msb 01234567891011121314 lsb 15 field flg 31 flg 30 flg 29 flg 28 flg 27 ?flg 24 flg 23 flg 22 flg 21 flg 20 flg 19 flg 18 flg 17 flg 16 sreset 0000_0000_0000_0000 addr 0x30 6c40 figure 17-38. interrupt status register (mios14sr1) table 17-38. mios14sr1 bit descriptions bits name description 0:4 flg31:27 flag bits ? mdasm flag bits [31:27] 5:6 ? reserved 7:9 flgl24:22 flag bits? mmcsm flag bits [24:22] 10:15 flg21:16 flag bits ? pwmsm flag bits [21:16] modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-68 freescale semiconductor 17.12.4.2 interrupt enable register (mios14er1) this register contains the interrupt enable bits for the submodules. each bit corresponds to a given submodule. 17.12.4.3 interrupt request pending register (mios14rpr1) this register is a read only register that contains the interrupt pending bits for the submodules. each bit corresponds to a given submodule. when one of these bits is set, it mean s that a submodule raised its flag and the corresponding enable was set. as this register is read on ly, a write to this register has no other effect than gene rating a bus error if the bus error option is selected. msb 01234567891011121314 lsb 15 field en 31 en 30 en 29 en 28 en 27 ?en 24 en 23 en 22 en 21 en 20 en 19 en 18 en 17 en 16 sreset 0000_0000_0000_0000 addr 0x30 6c44 figure 17-39. interrupt enable register (mios14er1) table 17-39. mios14er1 bit descriptions bits name description 0:4 en31:27 enable bits ? mdasm enable bits [31:27] 5:6 ? reserved 7:9 en24:22 enable bits ? mmcsm enable bits [24:22] 10:15 en21:16 enable bits ? pwmsm enable bits [21:16] msb 01234567891011121314 lsb 15 field irp 31 irp 30 irp 29 irp 28 irp 27 ?irp 24 irp 23 irp 22 irp 21 irp 20 irp 19 irp 18 irp 17 irp 16 sreset undefined addr 0x30 6c46 figure 17-40. interrupt request pending register (mios14rpr1) table 17-40. mios14rpr1 bit descriptions bits name description 0:4 irp31:27 pending bits ? mdasm pending bits [31:27] 5:6 ? reserved modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-69 17.12.5 interrupt co ntrol section (ics) the interrupt control section delivers the interrupt level to the cpu. the interrupt control section adapts the characteristics of the miob reque st bus to the characteristics of th e interrupt structure of the imb3. when at least one of the flags is set on an enable d level, the ics receives a signal from the corresponding irq pending register. this signal is the result of a logical ?or? betw een all the bits of the irq pending register. the signal received from the irq pending register is associated with the in terrupt level register within the ics. this level is coded on five bits in this register : three bits represent one of eight levels and the two other represent the four time mul tiplex slots. according to this le vel, the ics sets the correct irq [7:0] lines with the correct ilbs[1:0] time multiplex lines on th e peripheral bus. the cpu is then informed as to which of the thirty-two interrupt levels is requested. based on the interrupt level requested, the softwa re must determine which submodule requested the interrupt. the software may use a find- first-one type of instruction to de termine, in the concerned mirsm, which of the bits is set. the cpu ca n then serve the re quested interrupt. 17.12.6 mbism interrupt registers table 17-41 shows the mbism interrupt registers. 17.12.6.1 mios14 interrupt level register 0 (mios14lvl0) this register contains the interrupt level that applies to the submodules numbers 15 to zero. 7:9 irp24:22 pending bits ? mmcsm pending bits [24:22] 10:15 irp21:16 pending bits ? pwmsm pending bits [21:16] table 17-41. mbism interrupt registers address map address register 0x30 6c30 mios14 interrupt level register 0 (mios14lvl0) see table 17-42 for bit descriptions. 0x30 6c70 mios14 interrupt level register 1 (mios14lvl1) see table 17-43 for bit descriptions. msb 01234567891011121314 lsb 15 field ? lvl tm ? sreset 0000_0000_0000_0000 addr 0x30 6c30 figure 17-41. mios14 interrupt level register 0 (mios14lvl0) table 17-40. mios14rpr1 bit descriptions (continued) bits name description modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-70 freescale semiconductor 17.12.6.2 mios14 interrupt level register 1 (mios14lvl1) this register contains the interrupt level th at applies to the submodules number 15 to zero. 17.13 mios14 function examples the versatility of the mios14 time r architecture is based on multip le counters and capture/compare channel units interconnected on 16-bit counter buses. this section includes some typical application examples to show how the submodules can be in terconnected to form timing f unctions. the diagrams used to illustrate these examples show only the blocks utilized for that function. to illustrate the timing range of the mios14 in differ ent applications, many of the following paragraphs include time intervals quoted in microseconds and seconds. the assumptions used are that f sys is at 40 mhz with minimum overall prescaling (50 ns cycle) and with the maximum overall prescaling (32 s cycle). for other f sys clock cycle rates and prescal er choices, the times ment ioned in these paragraphs scale appropriately. 17.13.1 mios14 input double edge pulse width measurement to measure the width of an input pulse, the mios14 double acti on submodule (mdasm) has two capture registers so that only one interrupt is needed af ter the second edge. the software can read both edge table 17-42. mios14lvl0 bit descriptions bits name description 0:4 ? reserved 5:7 lvl interrupt request level. this field represents one of eight possible levels. 8:9 tm time multiplexing. this field determines the multiplexed time slot 10:15 ? reserved msb 01234567891011121314 lsb 15 field ? lvl tm ? sreset 0000_0000_0000_0000 addr 0x30 6c70 figure 17-42. mios14 interrupt level register 1 (mios14lvl1) table 17-43. mios14lvl1 bit descriptions bits name description 0:4 ? reserved 5:7 lvl interrupt request level. this field represents one of eight possible levels. 8:9 tm time multiplexing. this field determines the multiplexed time slot. 10:15 ? reserved modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-71 samples and subtract them to get the pulse width. the leading edge sample is double latched so that the software has the time of one full pe riod of the input signal to read the samples to be sure that nothing is lost. depending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be measured. note that a software option is provided to also gene rate an interrupt after the first edge. in the example shown in figure 17-43 , a counter submodule is used as the time-base for a mdasm configured in the input pulse width measurement m ode. when the leading edge (programmed for being either rising or falling) of the inpu t signal occurs, the state of the 16-bit counter bus is saved in register b1. when the trailing edge occurs, the 16-b it counter bus is latched into regi ster a and the content of register b1 is transferred to register b2. this operation leaves register b1 free for the next leading edge to occur on the next clock cycle. when enab led, an interrupt is provided afte r the trailing edge, to notify the software that pulse width measurem ent data is available for a new pulse. after the trailing edge, the software has one cycle time of the input signal to obt ain the values for each edge . when software attention is not needed for every pulse, the interrupt can be disabled. the software can read registers a and b2 coherently (using a 32-bit re ad instruction) at any time, to get the latest edge measurements. the software work is less than half that needed with a timer that requires the software to read one edge and save the value and then wait for the second edge. figure 17-43. mios14 example: double capture pulse width measurement 17.13.2 mios14 input double edge period measurement two samples are available to the software fr om an mios14 double action submodule for period measurement. the software can read the previous and the current edge sa mples and subtract them. as with pulse width measurement, the software can be sure not to miss samples by en suring that the interrupt response time is faster than the fastes t input period. alternately, when the so ftware is just interested in the latest period measurement, one 32-bi t coherent read instruction can ge t both the current and the previous samples. depending on the prescaler divide ratio, period times can be measured from 50 ns to 6.7 s. 16-bit up-counter submodule bus clock select 16-bit register b1 edge detect input signal 16-bit register a input capture interrupt on from prescaler or pin trailing bus select edge tw o 16-bit counter buses 16-bit register b2 mios14 modulus counter submodule mios14 double action submodule in ipwm mode (mod3-mod0 = 0b0001) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-72 freescale semiconductor figure 17-44 shows a counter submodule and a dasm co mbination as an example of period measurement. the software designates whether the rising or falling edge of the input signal is to be used for the measurements. when the edge is detected, the st ate of the 16-bit counter bus is stored in register a and the content of register b1 is transferred to regist er b2. after register b2 is safely latched, the content of register a is transferred to regi ster b1. this procedure gives the soft ware coherent current and previous samples in registers a and b2 at all times. an interrupt is available fo r the cases where the software needs to be aware of each new sample. note that a software option is provided to also generate an interrupt after the first edge. figure 17-44. mios14 example: double capture period measurement 17.13.3 mios14 double edge single output pulse generation software can initialize the mios14 to generate both th e rising and the fa lling edge of an output pulse. with a mdasm, pulses as narrow as 50 ns can be generate d since software action is not needed between the edges. pulses as long as 2.1 s can be generated. when an interrupt is desi red, it can be selected to occur on every edge or only after the second edge. figure 17-45 shows how a counter submodule and a mdasm can be used to generate both edges of a single output pulse. the software puts the compare value for one edge in register a and the other one in register b2. the mdasm automatically creates both edges and the pulse can be selected by software to be a high-going or a low-goi ng. after the trailing edge, the mdasm st ops to await furt her commands from the software. note that a single edge output can be generated by writing to only one register. 16-bit up-counter submodule bus clock select 16-bit register b1 edge detect input signal 16-bit register b2 input capture interrupt on from prescaler or pin designated bus select edge 16-bit register a tw o 16-bit counter buses mios14 modulus counter submodule mios14 double action submodule in ipm mode (mod3-mod0 = 0b0010) modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 17-73 figure 17-45. mios14 example: double edge output compare 17.13.4 mios14 output pulse wi dth modulation with mdasm output waveforms can be generated with any duty cycl e without software involve ment. the software sets up a mdasm with the compare times fo r the rising and falling edges and they are automatically repeated. the software does not need to res pond to interrupts to generate conti nuous pulses. the frequency may be selected as the frequency of a free-running counter time -base, times a binary multiplier selected in the mdasm. multiple pwm outputs can be created from multiple mdasms and share one counter submodule, provided that the frequencies of all of the output signals are a binary multiple of the time-base and that the counter submodule is operating in a free-running mode. each mdasm has a software selectable ?don?t care? on high-order bits of the time-base comparison so that the frequency of one output can be a binary multiple of another signal. masking the time-base se rves to multiply the frequency of the time-base by a binary number to form the frequency of the output wavefo rm. the duty cycle can vary from one cycle to 64-kbyte cycles. the frequency can range from 0.48 hz to 156 khz, though the resolution decreases at the higher frequencies to as low as seven bits. the genera tion of output square wave signals is of course the special case wh ere the high and low times are equal. when an mmcsm is used to drive the time-base, the modulus value is the period of the output pwm signal. figure 17-46 shows such an example. the polarity of th e leading edge of an output waveform is programmable for a rising or a falling edge. the so ftware selects the period of the output signal by programming the mmcsm with a modulus value. the leading edge compare value is written into register a by software and the trailing edge time is written into register b 1. when the leading edge value is reached, the content of register b1 is transferred to register b2, to form the next trailing edge value. subsequent changes to the output pulse width are made by writing a new ti me into register b1. updates to the pulse width are always synchronized to the leadi ng edge of the waveform. 16-bit up-counter submodule bus clock select 16-bit compare b output flip-flop output signal 16-bit compare a 16-bit register b2 16-bit register a output compare interrupt on from prescaler or pin trailing bus select edge tw o 16-bit counter buses mios14 double action submodule in ocb mode (mod3 - mod0 = 0b0100) mios14 modulus counter submodule modular input/output subsystem (mios14) mpc561/mpc563 reference manual, rev. 1.2 17-74 freescale semiconductor it is typical to use the pulse width modulation mode of the mdas m without interr upts, although an interrupt can be enabled to occur on the leading edge. when the output is an unchanging repetitive waveform, the mdasm continuously generates the si gnal without any software intervention. when the software needs to change the pulse width, a new trailing edge time is written to the mdasm. the output is changed on the next full pulse. when the software needs to change the output at a regular rate, such as an acceleration curve, the leading edge interrupt gi ves the software one period time to update the new trailing edge time. figure 17-46. mios14 example: pulse width modulation output 17.13.5 mios14 input pulse accumulation counting the number of pulses on an in put signal is another capability of the mios14. pulse accumulation uses an mmcsm. since the counters in the count er submodules are software accessible, pulse accumulation does not require the use of an acti on submodule. the pulse accumulation can operate continuously, interrupting only on binary overflow of the 16-bit count er. when an mmcsm is used, an interrupt can instead be created when the pulse accu mulation reaches a preprogrammed value. to do that, the two?s complement of the value is put in the modulus register and th e interrupt occurs when the counter overflows. 16-bit up-counter submodule bus 16-bit compare b output flip-flop output pin 16-bit compare a 16-bit register b2 16-bit register a output compare interrupt on bus from prescaler or pin leading 16-bit register b1 edge modulus register modulus control clock select load select tw o 16-bit counter buses mios14 double action submodule in ocab mode (mod3 ? mod0 = 0b0101) mios14 modulus counter submodule mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-1 chapter 18 peripheral pin multiplexing (ppm) module the peripheral pin multiplexing (ppm ) module has two main functions. th e first function allows the ppm to act as a parallel-to-serial co mmunications module. using the ppm in this way can reduce the number of signals required to connect the mpc561/mpc563 to an external device or devices. the second function allows the ppm to short in ternal signals thus giving increased access to multiple functions multiplexed on the same device signal. see figure 18-1 for a comparison of the mpc555 n-signal i/o and the mpc561/mpc563 ppm i/o. 18.1 key features ? synchronous serial interface between mcu and an external device ? four internal parallel data source s can be multiplexed through the ppm ? tpu3_a: 16 channels ? tpu3_b: 16 channels ? mios: 12 pwm channels, four mda channels ? internal gpio: 16 general-purpose inputs, 16 general-purpose outputs ? software configurable stream size ? one 16-bit transmit stream and one 16-bit receive stream ? two parallel 8-bit transmit streams a nd two parallel 8-bi t receive streams ? software configurable clock ( ppm_tclk) based on system clock ? software selectable clock modes ? serial peripheral interface (spi) mode ? time division multiplexing (tdm) mode ? software selectable operation modes ? continuous mode ? continuously tr ansmit/receive data through ppm ? start-transmit-receive (str) mode ? tran smit/receive only when str mode selected ? software configurable internal modul e shorting of the following signals: ? toucan_a[a_cnrx0, a_cntx 0] to toucan_b[b_cnrx0, b_cntx0] and/or toucan_c[c_cnrx0, c_cntx0] ? toucan_b[b_cnrx0, b_ cntx0] to toucan_c[c_cnrx0, c_cntx0] ? a_tpuch0 to b_tpuch0 ? a_tpuch1 to b_tpuch1 ? a_tpuch15 to etrig1 ? b_tpuch15 to etrig2 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-2 freescale semiconductor ? a_t2clk to b_t2clk figure 18-1. n-signal i/o compared with ppm i/o 18.2 programming model the ppm occupies 100 bytes of address space, arranged as 50 16-bit entries. all registers must be read or written through half-word (16-bit) ac cesses. reserved register addre sses return zeros when read and cannot be written to. table 18-1 shows the memory map for the ppm module. table 18-1. ppm memory map access register name address usage s 1 ppmmcr 0x30 5c00 module configuration register t 2 ppmtcr 0x30 5c02 test co nfiguration register s/u 3 ppmpcr 0x30 5c04 ppm control register s 1 tx_config_1 0x30 5c06 tx output configuration s 1 tx_config_2 0x30 5c08 tx output configuration ? reserved 0x30 5c0a ? 0x30 5c0c ? s 1 rx_config_1 0x30 5c0e rx input configuration s 1 rx_config_2 0x30 5c10 rx input configuration ? reserved 0x30 5c12 ? ? reserved 0x30 5c14 ? s/u 3 rx_data 0x30 5c16 receives data from rx_shifter on samp[0:2] update rate ? reserved 0x30 5c18 ? mpc555 external n data signals external 6 signals (maximum 4 data signals) tclk tsync tx1 rx1 0 1 n=31 parallel tx/rx protocol tx0 rx0 mpc561/ mpc563 ppm tx/rx protocol device device peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-3 18.3 functional description in order to reduce the number of si gnals on the devices, many signals ha ve multiple func tions and each signal must be configured for access to any of thes e functions. the ppm module is designed to increase the availability of mpc561/mpc563 signal multip lexed functions. it can do this is two ways: ? by implementing a parallel-to-s erial communication protocol, ? by implementing internal signal shorting. 18.3.1 ppm parallel-to-serial communication protocol the ppm communication sub-modules, ppm_mux and ppm_shifter, transfer data between the mpc561/mpc563 and external devices . the ppm reduces the number of connections between devices by allowing certain internal modules of the mcu to transmit and receive data serially, where without ppm those internal modules would have to transmit and receive data in parallel. data is routed through the ppm using internal multiplexers. communi cation between the intern al modules and the pp m remains a parallel connection, but the ppm conn ects to external devices by a serial link. the ppm can be configured for different data transfer rates and data formats. s/u 3 rx_shifter 0x30 5c1a data is shi fted in from signals ppm_rx[0:1] ? reserved 0x30 5c1c ? s/u 3 tx_data 0x30 5c1e data to be transmitted on ppm_tx[0:1] ? reserved 0x30 5c20 ? s/u 3 gpdo 0x30 5c22 general purpose data out s/u 3 gpdi 0x30 5c24 general purpose data in s/u 3 short_reg 0x30 5c26 enables shorting of internal signals s/u 3 short_ch_reg 0x30 5c28 enables shorting of transmit data channels s/u 3 scale_tclk_reg 0x30 5c2a establishes frequency of tclk ? reserved 0x30 5c2c ? 0x30 5c7f ? 1 only accessible in supervisor mode. 2 this register is accessible in test mode only. reads/writes to this register when not in test mode will return tea (bus error access). 3 accessible in supervisor mode and user mode (when ppmmcr[supv]=0). table 18-1. ppm memory map (continued) access register name address usage peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-4 freescale semiconductor figure 18-2. block diagram of ppm module 18.3.1.1 internal multiplexing in the mpc561/mpc563 devices, the ppm module s upports multiplexing of four modules: tpu3_a, tpu3_b, mios and gpio registers, internal to the ppm. internal multiplexers route data between the mcu internal modules and the external device through the ppm. four configuration registers, tx_config_1, tx_config_2, rx_c onfig_1 and rx_config_2, control these internal multiplexers. by programming the c onfiguration registers the ppm mul tiplexers select which internal module will drive data out of the ppm a nd which will receive data from the ppm. the tx_config and rx_config registers allocate tw o bits to control each of the 16 internal multiplexers. during transmit operations, the tx_con fig registers determine which internal module?s data will be sampled and routed to the transmit sample-and-shift register, tx_data. during receive operations, data in the receive samp le-and-shift register, rx_shifter, is routed to the internal module specified by the value of th e rx_config registers, or in the case where gpdi is the de stination, data is routed directly from ppm_rx[0:1]. refer to figure 18-4 . ppm_regs imb3 interface tpu3_a gpio mios ppm_mux ppm_shifter ppm_tclk ppm_tsync ppm_tx[0:1] ppm_rx[0:1] channel_tx[15:0] channel_rx[15:0] clock generator sysclk sysclk clock ppm_short tpu3_b ppm module tclk and update generator clock (gpdo, gpdi) peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-5 figure 18-3. internal multiplexer mechanism for transmit data figure 18-4. internal multiple xer mechanism for received data 18.3.1.2 ppm clocks the ppm module generates and outputs two cl ock signals, ppm_tclk and ppm_tsync. the ppm_tclk and ppm_tsync clocks ar e the basis for all ppm communica tion functions; si ngle data bits are transmitted and received on ppm _tclk cycles, one ppm_tsync cloc k cycle defines a single 16-bit word transmit/receive cycle. the ppm can be configured to tr ansfer data in one of two clock modes, spi and tdm. figure 18-5 shows examples of ppm_tclk in sp i and tdm modes. the frequency of ppm_tclk is a function of the system cloc k (sysclk) and is programmable using the a_tpuch0 ch15 ch0 b_tpuch0 mpwm0 tx_config[ch15] tx_shifter tx_config[ch0] ppm_tx[0:1] gpdo15 a_tpuch15 b_tpuch15 mda14 gpdo0 ??? a_tpuch0 ch15 ch0 b_tpuch0 mpwm0 a_tpuch15 b_tpuch15 mda14 rx_config[ch15] rx_shifter rx_config[ch0] ppm_rx[0:1] ch15 ch0 ch15 ch0 ? rx_data ??? gpdi rx_config[chx] ??? ??? ? ? ? ??? peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-6 freescale semiconductor scale_tclk_reg. the transmit signals, ppm_tx, w ill stay high as long as ppm_tsync is high (equal to ?1? in figure 18-5 ). figure 18-5. ppm clocks and serial data signals complete transmit and receive cycles are based on the ppm_tsync clock. a cy cle begins on the rising edge of ppm_tsync, which goes high for one ppm_t clk cycle. the transmit signals, ppm_tx[0:1], will stay high as l ong as ppm_tsync is hi gh (equal to ?1? in figure 18-6 ). data bits start to transmit on the falling edge of ppm_tsync. in receive mode, valid data starts to shift into rx_shifter on the falling edge of ppm_tsync . ppm_tsync stays low until the conten ts of tx_data have been shifted out and/or 16 bits have been shifted into rx_shi fter. one data bit is transferred every ppm_tclk cycle. sysclk ppm_tclk1 ppm_tclk2 ppm_tclk2 ppm_tsync ppm_tx ppm_rx ?1? channel0 channel1 channel2 channel0 channel1 channel2 ppm_tclk1 ? tclk in tdm mode ppm_tclk2 ? tclk in spi mode ppm_clk2 ? tclk in spi mode, with inverted spi clock polarity enabled f tclk = (f sysclk /2* n ) where n is the value in scale_tclk_reg (see section 18.4.12, ? scale transmit clock register (scale_tclk_reg) shading of ppm_rx signifies value is unknown peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-7 figure 18-6. one transmit and receive cycle in spi mode 18.3.1.3 ppm control settings as data is transferred through the ppm module it must be sampled at a rate which guarantees its validity. this sample rate is a multiple of ppm_tclk a nd is defined by the samp[0:2] field of the ppmpcr register. for transmit operations, the sample rate is the rate at which tx_data receives data from the internal modules. for receive operati ons, it is the rate at which the internal modules read rx_shifter. the register rx_data is updated from rx_shif ter on completed receive (ppm_tsync) cycles. sysclk ppm_tclk ppm_tsync ppm_rx ppm_tx ch0 ch1 ch2 ch3 ch[k] ch0 ch1 ch2 ch3 ch0 ch[k] one cycle ch0 ?1? ?1? shading of ppm_rx signifies value is unknown peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-8 freescale semiconductor figure 18-7. examples of several tclk frequencies and sample rates the ppm module has two data tr ansmit signals, ppm_tx[0:1], a nd two data receive signals, ppm_rx[0:1]. the amount of data transferred on these signals depends on the setting in ppmpcr[op_16_8]. if the ppm is conf igured to transfer data in 16 ppm_tclk cycles per 16-bit word then all data in tx_data[0:15] is transmitted on the ppm_tx0 signal, and all data is received into rx_shifter[0:15] from ppm_rx0. if the ppm is configured to transfer data in eight ppm_tclk cycles per 16-bit word then the eight bits will transfer on each of the data transfer signals. note care must be taken when setting th e sample rate with respect to the op_16_8 bit setting. for example if the ppm is transferring data on an 8-clock cycle, then setting the sample rate to every 16 clocks will result in lost data. in spi mode the phase and polarity of ppm_tclk is selectable by programming bits in the ppmpcr register. ppm_tclk can have normal polarity (active high) or inverted polarity (active low). there are two clock phases available: valid data can be latched on the transition of ppm_tclk from its active edge to inactive edge, or valid data can be latched on th e transition of ppm_tclk from its inactive edge to active edge. see section 18.4.2, ?ppm cont rol register (ppmpcr) ? for more information on spi mode ppm_tclk settings. sysclk ppm_tclk(1) update(1) sysclk ppm_tclk(2) update(2) update(3) update(4) ppm_tclk(1) = sysclk/4 ppm_tclk(2) = sysclk/2 update(1) every ppm_tclk(1)clock update(2) every ppm_tclk(2) clock update(3) every second ppm_tclk(2) clock update(4) every fourth ppm_tclk(2) clock peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-9 18.3.2 ppm signal short functionality the mpc561/mpc563 devices have many modules that mu ltiplex their functions ont o shared signals. in order to access those functions, th e signals must be configured a ppropriately. however, choosing one function can be at the cost of a nother function. the ppm makes more functions available simultaneously by creating internal shorts that can activate functions that would otherwise requi re an external signal. internal signal shorts are enabled us ing the ppm short register, short_reg. 18.3.2.1 toucan shorting there are three toucan modules on the mpc561/mpc563 devices. usi ng the ppm it is possible to internally short the cnrx0 and cntx0 signals of these three modules to increase message buffer capacity. three bits of the short_reg register (sh_tcan[0:2]), are allocated to enable four combinations of s horting between the toucan modules. see table 18-8 for information on these bit descriptions. when one toucan module is shorted to another, the canrx signals and the cantx signals of both modules are shorted internally. both modules continue to operate as normal but all transmit and receive operations are done using only one pair of canrx and cantx signals. the canrx and cantx signals of the other module are no longer under the control of the toucan module. the c_toucan signals c_cntx0 and c_cnrx0 are multiplexed signals . when c_toucan is shorted with one or two other toucan modul es, c_toucan no longer has contro l of these signals and so they can be configured for another of the available functions. refer to chapter 2, ?signal descriptions ,? for more information. also see figure 18-24 . 18.3.2.2 tpu shorting there are two tpu3 modules on the mpc561/mpc563 devi ces. using the ppm, it is possible to internally short channel a_tpuch0 with b_tpuch0 and cha nnel a_tpuch1 with b_tpuch1. two bits of the short_ch register (sh_tpu[1:0]) control the intern al shorting. the input/output enable states of the tpu channels themselves determine the effect that the short bits ha ve on the tpu modules? operation. see table 18-9 for information on short_ch[sh_tpu] bit descriptions. the ppm only controls the internal shorting of tpu3 chan nels tpuch0 and tpuc h1. tpu channels are configured for input and output by the tpu rom functions defined for them. refer to appendix d, ?tpu3 rom functions ? for further information, and see figure 18-25 . if tpu_a and tpu_b channel 0 are shorted via short_ch[sh_tpu] and one is set to ouput while the other is set to input, then the data from the output channel will not appear on the pin of the input channel. this holds true if tpu_a and tpu_b channel 1 are shorted via short_ch[sh_tpu]. connect an external devi ce to the pin of the module that has the channel function set to output. 18.3.2.3 etrig1 and etrig2 each of the two qadc64e modules on the mpc561/mpc563 has an exte rnal trigger input signal that can be used to trigger analog to digital conversions. using the ppm, these external trigger inputs can be sourced internally. control for these short functions is found in short_reg[sh_et1] and peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-10 freescale semiconductor short_reg[sh_et2]. etrig1 can be shorted to a_tpuch15 and etrig2 can be shorted to b_tpuch15. since the etrig1 and etrig2 signals are shared wi th pcs6 and pcs7 respectively, the ppm shorting will allow both etrig and pcs functions to be available. by setting up a_tpuch15 and/or b_tpuch15 as output signals, enabling a short to etrig1 and/or etrig2 and sending a trigger signal from the tpu channels, the qadc64e can be successf ully triggered, leaving th e etrig signals free to be configured for pcs functions. 18.3.2.4 t2clk each of the two tpu modules has an input cloc k, t2clk. the a_t2clk and b_t2clk signals are shared with pcs4 and pcs5 re spectively. the t2clk signals can be shorted internally by short_reg[sh_t2clk] so that only one signal needs to be input to th e device, leaving the other signal free for pcs functionality. 18.3.3 ppm module pad configuration the ppm module has six pads associ ated with it, four i/o pads ppm _rx[0:1] and ppm_ tx[0:1] and two clock outputs ppm_tclk and ppm_tsy nc. all six ppm signals are mult iplexed with mios signals. in order to be able to acces s the ppm functions the signals must be configured appropriately. ppm pad control is done in the pdmcr2 register. as well as enabling signal functions , this register can configure the ppm pads for 2.6-v or 5-v operation. refer to chapter 2, ?signal descriptions ,? for more details. 18.4 ppm registers 18.4.1 module configurat ion register (ppmmcr) msb 0 1234567 8 91011121314 lsb 15 field stop reserved supv reserved sreset 0000_0000_0000_0000 addr 0x30 5c00 figure 18-8. module configuration register (ppmmcr) peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-11 18.4.1.1 entering stop mode the ppm module cannot, and should not, be put into stop mode while either the transmit or receive operation is enabled in ppmpcr[entx ] and/or ppmpcr[enrx]. furtherm ore, it should not be put into stop mode if it is operati ng in continuous mode. in th is case it should be switched to single transfer mode first. the following steps should be taken to ensure that st op mode is entered safely and without loss of data: 1. if the ppm is operating in continous mode ? switch to single transfer mode by clearing ppmpcr[cm]=0. 2. if the ppm is enabled for transmit or receive ? set ppmpcr[str] (tdm or spi mode) ? disable both ppmpcr[entx] and ppmpcr[enrx] ? wait until ppmpcr[str] is clear ed by the ppm module. this will be done when the next data frame has been sent or received. 3. if the ppm is not enabled for transmit or receive ? clear ppmpcr[str] if necessary 4. set ppmmcr[stop] when ppmmcr[stop] is set, the ppm module ente rs stop mode and the ppm module clocks will be stopped. while in stop mode, none of the ppm re gisters will be accessible, except for the ppmpcr register. if the stop bit is clear, stop mode is disabled. table 18-2. ppmmcr bit descriptions bits name description 0stop stop mode enable. when the stop bit is set and the ppm enters stop mode, the ppm module clocks will be stopped. the ppm will only respond to accesses to the ppmmcr register. the stop bit can only be set when the ppm is disabled, (i.e., ppmpcr[entx] = 0 and ppmpcr[enrx] = 0). writing to the stop bit while either tx or rx is enabled will result in a tea (bus error access). 0 ppm clocks enabled 1 ppm clock disabled ? ppm in stop mode. 1:7 ? reserved 8supv supervisor/user data space. the supv bit places the ppm registers in either supervisor or user data space. 0 access to ppmmcr, tx_config1/2, rx_config1 /2 is restricted to supervisor-only. access to all other ppm re gisters is unrestricted. 1 all ppm registers are accessible in supervisor-only data space. 9:15 ? reserved peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-12 freescale semiconductor 18.4.2 ppm control register (ppmpcr) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field samp[0:2] op_16_8 enrx entx spi str ci cp cm reserved sreset 0000_0000_0000_0000 addr 0x30 5c04 figure 18-9. ppm contro l register (ppmpcr) table 18-3. ppmpcr bit descriptions bits name description 0:2 samp[0:2] the sample rate is the rate at which the dat a registers are sampled, with respect to the frequency of tclk. for transmit, samp[0:2] is the rate at which data from the tx_data register is sampled. for receive, samp[0:2] is the rate at which data is sampled from rx_data. refer to table 18-4 for samp[0:2] settings. 3 op_16_8 this bit describes how the 16 data bits will be transmitted and received. both transmit and receive are effected by this bit setting. 0 16 tclk cycles per word. all 16 bits of tx _data[0:15] will transmit on ppm_tx0. all 16 bits of rx_shifter[0:15] are received from ppm_rx0. 1 8 tclk cycles per word. tx_data[0:7] wil l transmit on ppm_tx1, tx_data[8:15] will transmit on ppm_tx_0. rx_shifter[0:7] are received from ppm_rx1, rx_shifter[8:15] are re ceived from ppm_rx0. 4 enrx 1 ppm receive (rx) data enable. 0rx disabled 1 rx enabled 5 entx 2 ppm transmit (tx) data enable. 0 tx disabled 1 tx enabled 6 spi spi mode enable. 0 tdm mode enabled 1 spi mode enabled 7str start-transmit-receive bit. when this bit is set and spi mode is enabled, the ppm module will start to transmit and/or receive one frame of data. the str bit will then be cleared automatically by the ppm. refer to ta b l e 1 8 - 5 . 0 ppm has completed transmitting and/or receiving one data frame. 1 ppm will transmit and/or receive one data frame. 8ci clock invert. this bit defines the polarity of tclk clock in both spi and tdm modes. 0 normal clock polarity ? active high clocks selected 1 inverted clock ? active low clocks selected 9cp clock phase. this bit selects one of two fund amentally different transfer formats. refer to figures figure 18-12 and figure 18-13 . 0 valid data can be latched on the transition of tclk from inactive phase to active phase. 1 valid data can be latched on the transition of tclk from active phase to inactive phase. peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-13 10 cm continuous mode. 0 non-continuous mode (default). transmit and/ or receive one data frame when str = 1. (str will be automatically cleared by the ppm after the transfer of one data frame.) 1 data will continuously be transmitted and/or received as long as transmit and receive are enabled. refer to table 18-5 for more information. note: ensure ppmpcr[str]=0 wh en setting ppmpcr[cm]=1 11:15 ? reserved 1 enable rx. (a) if enrx is disabled, no data will shift into the ppm. (b) if enrx is asserted while entx=1, the first data bit rece ived will be the data that is transmitted from the ppm, and not rx0. see figure 18-10 . to receive the first data frame correctly, enrx and entx should be set simultaneously. 2 enable tx. (a) if entx is disabled, no data will shift out of the ppm and the ppm output signals, ppm_tx0 and ppm_tx1 will be high. (b) if entx is asserted while enrx = 1, the first data bits transmitted out of the ppm will be the data that was received into the ppm. see figure 18-11 . to transmit the first data frame corre ctly, set entx and enrx simultaneously. table 18-4. samp[0:2] bit settings samp[0:2] sample rate 000 every tclk 001 every 2 tclk 010 every 4 tclk 011 every 8 tclk 100 ? 111 every 16 tclk table 18-3. ppmpcr bit descriptions (continued) bits name description peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-14 freescale semiconductor figure 18-10. set enrx while entx = 1 . figure 18-11. set entx while enrx = 1 enrx ppm_tclk ppm_tsync ppm_rx ppm_tx ch0 ch1 ch2 ch3 ch[k] ch2 ch3 ch0 ch[k] one cycle ch0 ?1? ?1? entx ppm_tclk ppm_tsync ppm_rx ppm_tx ch2 ch3 ch[k] ch2 ch3 ch 0 ch[k] one cycle ch0 ?1? ?1? ch1 ch0 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-15 figure 18-12. spi transfer format with cp = 0 figure 18-13. spi transfer format with cp = 1 18.4.3 transmit configuration registers (tx_config_1 and tx_config_2) the two transmit configuration regi sters control which internal modules will transmit data through the ppm. each of the configuration register s contains eight separate 2-bit wide bit fields. each of the 16 fields controls a multiplexer that select s a 1-bit channel from an internal module to the ppm transmit data register. see table 18-6 for more information on channel cont rol and setting the channel values. table 18-5. ppmpcr[cm] and ppmpcr[str] bit operation ppmpcr[cm] ppmpcr[str] result 0 1 one data frame transmitted and/or received through ppm. 0 0 transfer of one data frame completed. 1 x continuously transmit and/or receive data frames through ppm. xx cm and str will only effect ppm transmit/receive when ppm is configured for spi mode. in tdm mode transmit/receive will be continuous regardless of the values of cm and str bits. ppm_tclk ppm_tclk data ppm_tsync ci = 0 ci = 1 ppm_tclk ppm_tclk data ppm_tsync ci = 0 ci = 1 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-16 freescale semiconductor tx_config_1 and tx_config_2 can only be written while ppm tr ansmit mode is disabled (ppmpcr[entx] = 0). while transmit is enabled these registers read as 0x00 and writing them will return tea (bus error access). 18.4.4 receive configuration registers (rx_config_1 and rx_config_2) the two receive configuration regist ers control which internal modules will receive data from the ppm. each of the configuration registers contains eight separate 2-bit wide bit fields. each of the 16 fields controls a multiplexer that selects a 1-bit channel from the ppm data receive register to an internal module. see table 18-6 for more information on channel cont rol and setting the channel values. rx_config_1 and rx_config_2 can only be wri tten while ppm receive mode is disabled (ppmpcr[enrx] = 0). while receive mode is enabled these register s read as 0x00 and wr iting them will return tea (bus error access). msb 0 1234567 8 91011121314 lsb 15 field ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sreset 0000_0000_0000_0000 addr 0x30 5c06 figure 18-14. transmit configuration register 1 (tx_config_1) msb 0 1234567 8 91011121314 lsb 15 field ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 sreset 0000_0000_0000_0000 addr 0x30 5c08 figure 18-15. transmit configuration register 2 (tx_config_2) msb 0 1234567 8 91011121314 lsb 15 field ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sreset 0000_0000_0000_0000 addr 0x30 5c0e figure 18-16. receive configuration register 1 (rx_config_1) peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-17 note channel 0 is transmitted first. channel 0 is received first. 18.4.5 receive data register (rx_data) rx_data receives data from the rx _shifter register. it is updated from rx_shifter at the end of a receive cycle (i.e., ri sing edge of ppm_tsync). msb 0 1234567 8 91011121314 lsb 15 field ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 sreset 0000_0000_0000_0000 addr 0x30 5c10 figure 18-17. receive configuration register 2 (rx_config_2) table 18-6. configuration register (tx and rx) channel settings tx/rx_config channel number channel values 00 01 10 11 0 gpio15 a_tpuch0 b_tpuch0 mpwm0 1 gpio14 a_tpuch1 b_tpuch1 mpwm1 2 gpio13 a_tpuch2 b_tpuch2 mpwm2 3 gpio12 a_tpuch3 b_tpuch3 mpwm3 4 gpio11 a_tpuch4 b_tpuch4 mpwm4 5 gpio10 a_tpuch5 b_tpuch5 mpwm5 6 gpio9 a_tpuch6 b_tpuch6 mpwm16 7 gpio8 a_tpuch7 b_tpuch7 mpwm17 8 gpio7 a_tpuch8 b_tpuch8 mpwm18 9 gpio6 a_tpuch9 b_tpuch9 mpwm19 10 gpio5 a_tpuch10 b_tpuch10 mpwm20 11 gpio4 a_tpuch11 b_tpuch11 mpwm21 12 gpio3 a_tpuch12 b_tpuch12 mda11 13 gpio2 a_tpuch13 b_tpuch13 mda12 14 gpio1 a_tpuch14 b_tpuch14 mda13 15 gpio0 a_tpuch15 b_tpuch15 mda14 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-18 freescale semiconductor 18.4.6 receive shift register (rx_shifter) rx_shifter receives data serially from the ppm input signals ppm _rx[0:1] (depending on the value of ppmpcr[op_16_8]). data bits ar e shifted in on every ppm_tclk cy cle. data in the rx_shifter register is delivered directly to the mpc561/ mpc563 internal modules with no wait time. 18.4.7 transmit data register (tx_data) tx_data contains data from the inte rnally multiplexed modul es that is to be tr ansmitted from the ppm module on the ppm_tx[1:0] signals (depending on th e value in ppmpcr[op_16_8]). data bits are transmitted serially (shifted out) on each ppm_tclk cy cle. the data is shifted out least significant bit (lsb) first, therefore tx_dat a15 first, tx_data0 last. 18.4.8 general-purpose data out (gpdo) gpdo is an internal register whose data can be transmitted serially through the ppm. by default, the transmit configuration registers are set to transmit from this register . the value in gpdo[0:15] is written into tx_data[0:15]. msb 0 1234567 8 91011121314 lsb 15 field rx_data sreset 0000_0000_0000_0000 addr 0x30 5c16 figure 18-18. receive data register (rx_data) msb 0 1234567 8 91011121314 lsb 15 field rx_shifter sreset 0000_0000_0000_0000 addr 0x30 5c1a figure 18-19. receive shifter register (rx_shifter) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field tx_data sreset 0000_0000_0000_0000 addr 0x30 5c1e figure 18-20. transmit data register (tx_data) peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-19 18.4.9 general-purpose data in (gpdi) gpdi is an internal register th at receives data directly from th e ppm input signals, ppm_tx[0:1]. by default, the receive configuration re gisters are set to direct received data from rx_data[0:15] to the gpdi[0:15] register. 18.4.10 short register (short_reg) short_reg allows the shorting of certain internal si gnals in the mpc561/mpc563 devices. this feature allows functions, whose internal signals are mul tiplexed on external sign als, to be accessible simultaneously. msb 0 1234567 8 91011121314 lsb 15 field gpdo sreset 0000_0000_0000_0000 addr 0x30 5c22 figure 18-21. general purpose data out register (gpdo) msb 0 1234567 8 91011121314 lsb 15 field gpdi sreset 0000_0000_0000_0000 addr 0x30 5c24 figure 18-22. general purpose data in register (gpdi) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field sh_tcan[2:0 ] sh_tpu[1:0] reserved sh_et1 sh_et2 sh_t2clk reserved sreset 0000_0000_0000_0000 addr 0x30 5c26 figure 18-23. short register (short_reg) peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-20 freescale semiconductor table 18-7. short_reg bit descriptions bits name description 0:2 sh_tcan[2:0] short toucan modules. these three bits determine which toucan modules are inter- nally shorted. see table 18-8 for a description of the effects of these bit settings. 3:4 sh_tpu[1:0] short tpu3 modules. the channels a_tp uch0 and b_tpuch0 can be internally shorted by the sh_tpu0. channels a_tpuch1 and b_tpuch1 can be internally shorted by sh_tpu1. the effect of the inte rnal shorts depends on the input/output en- able control for the tpu channels themselves. see table 18-9 for more information on bit settings for tpu shorting. 5?reserved 6sh_et1 short etrig1. this bit enables an internal short between etrig1 and a_tpuch15. 0 short disabled 1 short etrig1 to a_tpuch15 enabled 7sh_et2 short etrig2. this bit enables an internal short between etrig2 and b_tpuch15. 0 short disabled 1 short etrig2 to b_tpuch15 enabled 8 sh_t2clk short t2clk. this bit enables a short between a_t2clk and b_t2clk. 0 short disabled 1 short a_t2clk and b_t2clk enabled. a_t2clk then takes the input clock. 9:15 ? reserved table 18-8. short_reg[sh_tcan] bit settings sh_tcan2 sh_tcan1 sh_tcan0 effects on toucan modules 00 0no short 00 1no short 01 0no short 01 1 toucan_c[c_cnrx0, c_cntx0] shorted to toucan_b[b_cnrx0, b_cntx0] both modules communicate via b_cntx0, b_cnrx0. 10 0no short 10 1 toucan_c[c_cnrx0, c_cntx0] shorted to toucan_a[a_cnrx0, a_cntx0] both modules communicate via a_cntx0, a_cnrx0. peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-21 figure 18-24. example of toucan internal short with sh_tcan = 0b110 . 11 0 toucan_b[b_cnrx0, b_cntx0] shorted to toucan_a[a_cnrx0, a_cntx0]. both modules communicate via a_cntx0, a_cnrx0. see figure 18-24 for example of this bit setting 11 1 toucan_b[b_cnrx0, b_cntx0] and toucan_c[c_cnrx0, c_ cntx0] shorted to toucan_a[a_cnrx0, a_cntx0] all modules communicate via a_cntx0, a_cnrx0. table 18-9. short_reg[ sh_tpu] bit settings sh_tpu0 a_tpuch0 b_tpuch0 effect on tpu3 modules 1 input input data on pad a_tpuch0 will be the input to a_tpuch0 and b_tpuch0 1 input output output data on b_tpuch0 will be the input to a_tpuch0 1 output input output on a_tpuch0 will be the input data to b_tpuch0 1 output output no short 0x xno short table 18-8. short_reg[sh_tcan] bit settings sh_tcan2 sh_tcan1 sh_tcan0 effects on toucan modules toucan_a mpc561/mpc563 toucan_b a_cntx0 a_cnrx0 b_cntx0 b_cnrx0 can transceiver can transceiver peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-22 freescale semiconductor figure 18-25. short between tpu channels 18.4.11 short channels register (short_ch_reg) short_ch_reg allows the shorting of transmit channels from the ppm using the bit field short[7:0]. the ppm normally transmits da ta by right-shifting tx_d ata at the rate of one bit per ppm_tclk cycle, tx_data15 first. shorts can be enabled for transm it data bits tx_data[1, 3, 5, 7, 9, 11, 13, and 15]. where a short is enabled for any of th ese transmit data bits, that bit wi ll be transmitted for two ppm_tclk cycles, during its own bit time and the bit time of the fo llowing transmit data bit. example if short_ch x = 1, transmit tx_data x during tx_data x bit time and repeat tx_data x during tx_data[ x -1] bit time. sh_tpu1 a_tpuch1 b_tpuch1 effect on tpu3 modules 1 input input data on pad a_tpuch1 will be the input to a_tpuch1 and b_tpuch1 1 input output output data on b_tpuch1 will be the input to a_tpuch1 1 output input output on a_tpuch1 will be the input data to b_tpuch1 1 output output no short 0x xno short table 18-9. short_reg[ sh_tpu] bit settings pad pad a_ch b_ch a_tpuch b_tpuch tpu_a tpu_b mpc561/mpc563 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 18-23 msb 0 1 2 3 4 5 6 7 8 9 10 1112 1314 lsb 15 field reserved short_ch[7:0] sreset 0000_0000_0000_0000 addr 0x30 5c28 figure 18-26. short channels register (short_ch_reg) table 18-10. short_ch_reg bit descriptions bits name description 0:7 ? reserved 8:17 short_ch[7:0 ] each bit of this field will short a specified pair of channels. where a pair of channels are shorted, the data for the shorted channel will be transmitted twice. refer to table 18-11 for examples that illustrate the ef fects of enabling short_ch[7:0] bits. table 18-11. examples of the short_ch bits register name register contents comments example 1 short_ch_reg 0x0000 short_ch[7:0] = 0x00, therefore no shorts enabled tx_data[0:15] 0x1234 0b 0001 0010 0011 0100 data transmitted 0x1234 normal transmission. example 2 short_ch_reg 0x00f0 short_ch[7:4] = 1, therefore tx_data[1, 3, 5, 7] are enabled for re-transmission. tx_data[0:15] 0x1234 0b 0 0 0 1 0 0 1 0 0011 0100 underlines show bits to be re-transmitted bit channel shorted re -transmit (bit time) short_ch[x] = 0 no short ? short_ch7 = 1 tx_data1 to tx_data0 tx_data1 in tx_data0 short_ch6 = 1 tx_data3 to tx_data2 tx_data3 in tx_data2 short_ch5 = 1 tx_data5 to tx_data4 tx_data5 in tx_data4 short_ch4 = 1 tx_data7 to tx_data6 tx_data7 in tx_data6 short_ch3 = 1 tx_data9 to tx_data8 tx_data9 in tx_data8 short_ch2 = 1 tx_data11 to tx_d ata10 tx_data11 in tx_data10 short_ch1 = 1 tx_data13 to tx_d ata12 tx_data13 in tx_data12 short_ch0 = 1 tx_data15 to tx_d ata14 tx_data15 in tx_data14 peripheral pin multiplexing (ppm) module mpc561/mpc563 reference manual, rev. 1.2 18-24 freescale semiconductor 18.4.12 scale transmit clock register (scale_tclk_reg) scale_tclk_reg is used to set the rate of the pp m_tclk that provides the timing for data transfer into and out of the ppm module . the ppm_tclk frequency is deri ved from the system clock, f sysclk . ppm_tclk is software programmable using the following formula: f ppm_tclk = f sysclk / (2 * sct[6:0]) the range of ppm_tclk frequencies available is: data transmitted 0x3034 0b 0011 0000 0011 0100 example 3 short_ch_reg 0x00ff short_ch[7:0] = 1, therefore bits (tx_data[1, 3, 5, 7, 9, 11, 13, 15] are enabled for re-transmission. tx_data[0:15] 0x1234 0b 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 underlines show bits to be re-transmitted data transmitted 0x303c 0b 0011 0000 0011 1100 table 18-12. scale_tclk frequencies minimum maximum f sysclk /256 f sysclk /2 msb 0 1 234 5 678 9 1011121314 lsb 15 field reserved sct[6:0] sreset 0000_0000_0000_0000 addr 0x30 5c2a figure 18-27. scale transmit clock register (scale_tclk_reg) table 18-13. scale_tclk_reg bit descriptions bits name description 0:8 ? reserved 9:15 sct[6:0] determines t he frequency of ppm_tclk. sct[6:0] = 0 f sysclk /256 sct[6:0] = 1 to 127 f sysclk / (2 * sct[6:0]) writing to sct[6:0] while the ppm is enabled will cause an irregular ppm cycle to occur. table 18-11. examples of the short_ch bits (continued) register name register contents comments mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-1 chapter 19 time processor unit 3 the time processor unit 3 (tpu3), an enhanced ve rsion of the original tpu, is an intelligent, semi-autonomous microcontroll er designed for timin g control. the tpu3 is fully compatible to the tpu2. operating simultaneously with th e cpu, the two tpu3 m odules process micro-ins tructions, schedule and process real-time hardware events, perform input and output, and access sh ared data without cpu intervention. consequently, for each timer event, th e cpu setup and service times are minimized or eliminated. the mpc561/mpc563 contains two i ndependent tpu3s: tpu_a and tpu_b. these two tpu3 modules are memory mapped as shown in table 19-1 . . figure 19-1 is a simplified block diagram of a single tpu3. figure 19-1. tpu3 block diagram table 19-1. tpu memory map tpu address tpu_a 0x30 4000?0x30 43ff tpu_b 0x30 4400?0x30 47ff pins service requests data tcr1 tcr2 microengine control store execution unit imb3 host interface parameter ram channel control development support and system config scheduler control and data control timer channels channel 0 channel 1 channel 15 channel data t2clk te s t signal time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-2 freescale semiconductor 19.1 overview the tpu3 can be viewed as a special-purpose microcom puter that performs a pr ogrammable series of two operations, match and capture. each occurrence of either operation is called an event. a programmed series of events is called a func tion. tpu functions replace software functions that would require cpu interrupt service. the microcode rom tpu3 functions that are av ailable in the mpc561/m pc563 are described in appendix d, ?tpu3 rom functions .? 19.2 tpu3 components the tpu3 consists of two 16-bit time bases, 16 independent timer channels, a task scheduler, a microengine, and a host interface. in addition, a dual-ported parameter ra m (dptram) is used to pass parameters between th e module and the cpu. 19.2.1 time bases two 16-bit counters provide refere nce time bases for all output-com pare and input-capture events. prescalers for both time ba ses are controlled by the cp u via bit fields in the tpu3 module configuration register (tpumcr) and tpu modul e configuration register two (t pumcr2). timer count registers tcr1 and tcr2 provide access to the current coun ter values. tcr1 and tcr2 can be read by tpu microcode but are not directly availa ble to the cpu. the tcr1 clock is always derived from the system clock. the tcr2 clock can be derived from the system clock or from an external input via thet2clk clock pin. the duration betwee n active edges on the t2clk clock pin must be at least nine system clocks. 19.2.2 timer channels the tpu3 has 16 independent channels, each connect ed to an mcu pin. the channels have identical hardware and are functionall y equivalent in operation. each channel consists of an even t register and pin control logic. the event register c ontains a 16-bit capture register, a 16-bit compar e/match register, and a 16-bit greater-than-or-equal-to compar ator. the direction of each pin, eith er output or input, is determined by the tpu microengine. each channel can either use the same time base for match and capture, or can use one time base for match and the other for capture. 19.2.3 scheduler when a service request is receive d, the scheduler determines which tpu3 channel is serviced by the microengine. a channel can request se rvice for one of four reasons: for host service, for a link to another channel, for a match event, or for a capture event. th e host system assigns each active channel one of three priorities: high, middle, or low. when multiple service request s are received simultaneously, a priority-scheduling mechanism grants service based on channel number and assigned priority. time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-3 19.2.4 microengine the microengine is composed of a control store an d an execution unit. control-store rom holds the microcode for each factory-masked time function. when assigned to a channel by the scheduler, the execution unit executes microcode for a function assigne d to that channel by the cpu. microcode can also be executed from the dual-port ram (dptram) modul e instead of the contro l store. the dptram allows emulation and development of custom tpu mi crocode without the genera tion of a microcode rom mask. refer to section 19.3.6, ?emulation support ? for more information. 19.2.5 host interface the host interface registers allow communication betw een the cpu and the tpu3, both before and during execution of a time function. the re gisters are accessible from the im b through the tpu3 bus interface unit. refer to section 19.4, ?programming model ? for register bit/field defi nitions and address mapping. 19.2.6 parameter ram parameter ram occupies 256 bytes at the top of the system address map. channel parameters are organized as 128 16-bit words. chan nels zero through 15 each have eight parameters. th e parameter ram address map in section 19.4.15, ?tpu3 parameter ram ,? shows how parameter words are organized in memory. the cpu specifies function parameters by writing to the appropriate ram address. the tpu3 reads the ram to determine channel operation. the tpu3 can also store information to be read by the cpu in the parameter ram. detailed descriptions of the para meters required by each ti me function are beyond the scope of this manual. refer to the tpu reference manual (tpurm/ad), included in the tpu literature package (tpulitpak/d) for more information. 19.3 tpu operation all tpu3 functions are related to one of the two 16-bit time bases. f unctions are synthesized by combining sequences of match events and capt ure events. because the primitives are implemented in hardware, the tpu3 can determine precisely when a match or cap ture event occurs, and respond rapidly. an event register for each channel provides for simultaneous match/capture event occurrences on all channels. when a match or input capture event requiring servi ce occurs, the affected ch annel generates a service request to the scheduler. the scheduler determines the priority of the request a nd assigns the channel to the microengine at the first availa ble time. the microengine performs the function defined by the content of the control store or emulation ram, us ing parameters from the parameter ram. 19.3.1 event timing match and capture events are handled by independent channel hardware. this provides an event accuracy of one time-base clock period, regardless of the numbe r of channels that are active. an event normally causes a channel to request service. the time needed to respond to and service an event is determined by which channels and the number of channels requesting service, the relative priorities of the channels requesting service, and the microcode execution time of the active f unctions. worst-case event service time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-4 freescale semiconductor time (latency) determines tpu3 performance in a gi ven application. latency can be closely estimated. for more information, refer to the tpu reference manual (tpurm/ad). 19.3.2 channel orthogonality most timer systems are limi ted by the fixed number of functions assigned to each pin. all tpu3 channels contain identical hardware and are functionall y equivalent in operation, so that any channel can be configured to perform any time function. any function can operate on the calling channel, and, under program control, on another channel determined by the program or by a parameter. the user controls the combination of time functions. 19.3.3 interchannel communication the autonomy of the tpu3 is enhanced by the ability of a channel to affect th e operation of one or more other channels without cpu intervention. interchanne l communication can be accomplished by issuing a link service request to another channel, by contro lling another channel directly, or by accessing the parameter ram of another channel. 19.3.4 programmable channel service priority the tpu3 provides a programmable service priority le vel to each channel. three priority levels are available. when more than one channe l of a given priority requests servic e at the same time, arbitration is accomplished according to channel num ber. to prevent a single high-pr iority channel from permanently blocking other functions, other servic e requests of the same priority ar e performed in channel order after the lowest-numbered, highest-priority ch annel is serviced (i.e. round-robin). 19.3.5 coherency for data to be coherent, all availabl e portions of the data must be identi cal in age, or must be logically related. as an example, consider a 32-bit counter value that is read and written as two 16-bit words. the 32-bit value is read-coherent only if both 16-bit portions are updated at the same time , and write-coherent only if both portions take effect at the same time. parameter ram hard ware supports coherent access of two adjacent 16-bit parameters. th e host cpu must use a long-word op eration to guarantee coherency. 19.3.6 emulation support although factory-programmed time func tions can perform a wide variety of control tasks, they may not be ideal for all applications. the tpu3 provides emulation capability th at allows the development of new time functions. emulation mode is entered by setting the emu bit in tpumcr. in emulation mode, an auxiliary bus connection is made between the dptram and the tpu3, and access to dptram via the intermodule bus is disabled. a 9-bit address bus, a 32-bit data bus, and c ontrol lines transfer information between the modules. to ensure exact emulation, dp tram module access timing re mains consistent with access timing of the tpu micr ocode rom control store. to support changing tpu application requirements, freescale has established a tp u function library. the function library is a collection of tp u functions written for easy assembly in combination with each other time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-5 or with custom functions. refe r to freescale programming note, using the tpu function library and tpu emulation mode (tpupn00/d) for information about developing custom functions and accessing the tpu function library. refer to general tpu c functions for the mpc500 family (an2360/d) for more information about tpu f unctions in general and the t pu literature package (tpulitpak/d) for more information about specific functions. 19.3.7 tpu3 interrupts each of the tpu3 channels can gene rate an interrupt service request. in terrupts for each channel must be enabled by writing to the appropriate control bit in the channel interrupt enable register (cier). the channel interrupt status regi ster (cisr) contains one in terrupt status flag per ch annel. time functions set the flags. setting a flag bit causes the tpu3 to ma ke an interrupt service request if the corresponding channel interrupt enable bit is set. the tpu3 can generate one of 32 possible interrupt request levels on the imb3. the value driven onto irq [7:0] represents the interrupt level programmed in the irl field of the tpu interrupt configuration register (ticr). under the control of the ilbs bits in the icr, each inte rrupt request level is driven during one of four different time-multipl exed time slots, with eight leve ls communicated per time slot. no hardware priority is assigned to interrupts. furthe rmore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 19-2 displays the interrupt level scheme. figure 19-2. tpu3 interrupt levels 19.3.8 prescaler control for tcr1 timer count register 1 (tcr1) is clocked from the ou tput of a prescaler. th e following fields control tcr1: ? the psck and tcr1p fields in tpumcr ? the div2 field in tpumcr2 ? the epscke and epsck fields in tpumcr3. the rate at which tcr1 is increm ented is determined as follows: ? the user selects either the standard prescaler (by clearing the enhanced prescaler enable bit, epscke, in tpumcr3) or the enhan ced prescaler (by setting epscke). ? if the standard prescaler is selected (epscke = 0), then the psck bit determines whether the standard prescaler divides the system cl ock input by 32 (psck = 0) or 4 (psck = 1) imb3 clock ilbs[1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-6 freescale semiconductor ? if the enhanced prescaler is selected (epsck e = 1), the epsck bits select a value by which the system clock is di vided. the lowest freque ncy for tcr1 clock is system clock divided by 64x8. the highest frequency for tcr1 clock is system clock divided by two (2x1). see table 19-2 and table 19-3 . ? the output of either the standa rd prescaler or the enhanced pr escaler is then divided by 1, 2, 4, or 8, depending on the value of the tcr1p field in the tpumcr. ? if the tpumcr2[div2] bit is one, the tcr1 counter increments at a rate of the internal clock divided by two. if div2 is zero, the tcr1 increment rate is de fined by the output of the tcr1 prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler). figure 19-3 shows a diagram of the tcr1 prescaler control block. table 19-2. enhanced tcr1 prescaler divide values epsck value divide system clock by 0x00 2 0x01 4 0x02 6 0x03 8 0x04, 0x05,...0x1d 10,12,...60 0x1e 62 0x1f 64 table 19-3. tcr1 prescaler values tcr1p value divide by 0b00 1 0b01 2 0b10 4 0b11 8 time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-7 figure 19-3. tcr1 prescaler control 19.3.9 prescaler control for tcr2 timer count register 2 (tcr2), like tcr1, is cloc ked from the output of a prescaler. the t2cg (tcr2 clock/gate control) bit and the t2csl (tcr2 counter clock edge) bi t in tpumcr determine t2cr2 pin functions. refer to table 19-4 . the function of the t2cg bit is shown in figure 19-4 . when t2cg is set, the external t2 clk pin functions as a ga te of the div8 clock (t he tpu3 system clock divided by eight). in this case, when the external tcr2 pin is low, th e div8 clock is blocked, preventing it from incrementing tcr2. when th e external tcr2 pin is high, tcr2 is incremented at the frequency of the div8 clock. when t2cg is cleared, an ex ternal clock from the tcr2 pin, which has been synchronized and fed through a digita l filter, increments tcr2. the dur ation between acti ve edges on the t2clk clock pin must be at least nine system clocks. tpumcr3[tcr2psck2] and tpumcr[tcr2] determine how the clock source is divided to provide the output, see table 19-5 . figure 19-4 illustrates the tcr2 pre-di vider and pre-scaler control. table 19-4. tcr2 counter clock source t2csl t2cg tcr2 clock 0 0 rise transition t2clk 0 1 gated system clock 1 0 fall transition t2clk 1 1 rise and fall transition t2clk system prescaler psck mux tcr1 prescaler tcr1 div2 2,4,6,...64 prescaler 4, 32 1,2,4,8 epscke enhanced clock time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-8 freescale semiconductor figure 19-4. tcr2 prescaler control table 19-5 is a summary of prescaler output (assuming a divide-by-one value for the pre-divider prescaler). 19.4 programming model the tpu3 memory map contains three groups of registers: ? system configuration registers ? channel control and status registers ? development support and te st verification registers all registers except the channel inte rrupt status register (cisr) must be read or written by means of half-word (16-bit) or word (32-bit) accesses. the address space of the tpu3 memory map occupies 512 bytes. unused registers within the 512-byte address space return zeros when read. table 19-6 shows the tpu3 address map. table 19-5. tcr2 prescaler control tcr2 value internal clock divide ratio e xternal clock divide ratio tcr2psck2 = 0 tcr2psck2 = 1 tcr2psck2 = 0 tcr2psck2 = 1 0b008811 0b01 16 24 2 3 0b10 32 56 4 7 0b11 64 120 8 15 table 19-6. tpu3 register map address register 0x30 4000(tpu_a) 0x30 4400(tpu_b) tpu3 module configuration register (tpumcr) see ta bl e 1 9 - 7 for bit descriptions. 0x30 4002(tpu_a) 0x30 4402(tpu_b) tpu3 test configuration register (tcr) 0x30 4004(tpu_a) 0x30 4404(tpu_b) development support control register (dscr) see ta bl e 1 9 - 8 for bit descriptions. 0x30 4006(tpu_a) 0x30 4406(tpu_b) development support status register (dssr) see ta bl e 1 9 - 9 for bit descriptions. tcr2 prescaler tcr2 tcr2psck2 pre-divider clock source mux control tcr2 pin clock div8 prescaler time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-9 0x30 4008(tpu_a) 0x30 4408(tpu_b) tpu3 interrupt configuration register (ticr) see table 19-10 for bit descriptions. 0x30 400a(tpu_a) 0x30 440a(tpu_b) channel interrupt enable register (cier) see table 19-11 for bit descriptions. 0x30 400c(tpu_a) 0x30 440c(tpu_b) channel function selection register 0 (cfsr0) see table 19-12 for bit descriptions. 0x30 400e(tpu_a) 0x30 440e(tpu_b)) channel function selection register 1 (cfsr1) see table 19-12 for bit descriptions. 0x30 4010(tpu_a) 0x30 4410(tpu_b) channel function selection register 2 (cfsr2) see table 19-12 for bit descriptions. 0x30 4012(tpu_a) 0x30 4412(tpu_b) channel function selection register 3 (cfsr3) see table 19-12 for bit descriptions. 0x30 4014(tpu_a) 0x30 4414(tpu_b) host sequence register 0 (hsqr0) see table 19-13 for bit descriptions. 0x30 4016(tpu_a) 0x30 4416(tpu_b) host sequence register 1 (hsqr1) see table 19-13 for bit descriptions. 0x30 4018(tpu_a) 0x30 4418(tpu_b) host service request register 0 (hsrr0) see table 19-14 for bit descriptions. 0x30 401a(tpu_a) 0x30 441a(tpu_b)) host service request register 1 (hsrr1) see table 19-14 for bit descriptions. 0x30 401c(tpu_a) 0x30 441c(tpu_b) channel priority register 0 (cpr0) see table 19-15 for bit descriptions. 0x30 401e(tpu_a) 0x30 441e(tpu_b)) channel priority register 1 (cpr1) see table 19-15 for bit descriptions. 0x30 4020(tpu_a) 0x30 4420(tpu_b) channel interrupt status register (cisr) see table 19-17 for bit descriptions. 0x30 4022(tpu_a) 0x30 4422(tpu_b) link register (lr) 0x30 4024(tpu_a) 0x30 4424(tpu_b) service grant latch register (sglr) 0x30 4026(tpu_a) 0x30 4426(tpu_b) decoded channel number register (dcnr) 0x30 4028(tpu_a) 0x30 4428(tpu_b) tpu module configuration register 2 (tpumcr2) see table 19-18 for bit descriptions. 0x30 402a(tpu_a) 0x30 442a(tpu_b) tpu module configuration 3 (tpumcr3) see table 19-21 for bit descriptions. 0x30 402c(tpu_a) 0x30 442c(tpu_b) internal scan data register (isdr) 0x30 402e(tpu_a) 0x30 442e(tpu_b) internal scan control register (iscr) table 19-6. tpu3 register map (continued) address register time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-10 freescale semiconductor 0x30 4100 ? 0x30 410f(tpu_a) 0x30 4500 ? 0x30 450f(tpu_b) channel 0 parameter registers 0x30 4110 ? 0x30 411f(tpu_a) 0x30 4510 ? 0x30 451f(tpu_b) channel 1 parameter registers 0x30 4120 ? 0x30 412f(tpu_a) 0x30 4520 ? 0x30 452f(tpu_b) channel 2 parameter registers 0x30 4130 ? 0x30 413f(tpu_a) 0x30 4530 ? 0x30 453f(tpu_b) channel 3 parameter registers 0x30 4140 ? 0x30 414f(tpu_a) 0x30 4540 ? 0x30 454f(tpu_b) channel 4 parameter registers 0x30 4150 ? 0x30 415f(tpu_a) 0x30 4550 ? 0x30 455f(tpu_b) channel 5 parameter registers 0x30 4160 ? 0x30 416f(tpu_a) 0x30 4560 ? 0x30 456f(tpu_b) channel 6 parameter registers 0x30 4170 ? 0x30 417f(tpu_a) 0x30 4570 ? 0x30 457f(tpu_b) channel 7 parameter registers 0x30 4180 ? 0x30 418f(tpu_a) 0x30 4580 ? 0x30 458f(tpu_b) channel 8 parameter registers 0x30 4190 ? 0x30 419f(tpu_a) 0x30 4590 ? 0x30 459f(tpu_b) channel 9 parameter registers 0x30 41a0 ? 0x30 41af(tpu_a) 0x30 45a0 ? 0x30 45af(tpu_b) channel 10 parameter registers 0x30 41b0 ? 0x30 41bf(tpu_a) 0x30 45b0 ? 0x30 45bf(tpu_b) channel 11 parameter registers 0x30 41c0 ? 0x30 41cf(tpu_a) 0x30 45c0 ? 0x30 45cf(tpu_b) channel 12 parameter registers 0x30 41d0 ? 0x30 41df(tpu_a) 0x30 45d0 ? 0x30 45df(tpu_b) channel 13 parameter registers 0x30 41e0 ? 0x30 41ef(tpu_a) 0x30 45e0 ? 0x30 45ef(tpu_b) channel 14 parameter registers 0x30 41f0 ? 0x30 41ff(tpu_a) 0x30 45f0 ? 0x30 45ff(tpu_b) channel 15 parameter registers table 19-6. tpu3 register map (continued) address register time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-11 19.4.1 tpu module configur ation register (tpumcr) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field stop tcr1p tcr2p emu t2cg stf supv psck tpu3 t2csl ? sreset 0 00 00 000101 0 0000 addr 0x30 4000(tpu_a), 0x30 4400 (tpu_b) figure 19-5. tpumcr ? tpu module configuration register table 19-7. tpumcr bit description bits name description 0 stop low-power stop mode enable. if the stop bi t in tpumcr is set, the tpu3 shuts down its internal clocks, shutting down the internal micr oengine. tcr1 and tcr2 cease to increment and retain the last value before the stop condition wa s entered. the tpu3 asserts the stop flag (stf) in tpumcr to indicate that it has stopped. 0 enable tpu3 clocks 1 disable tpu3 clocks 1:2 tcr1p timer count register 1 presca ler control. tcr1 is clocked from the output of a prescaler. the prescaler divides its input by 1, 2, 4, or 8. this is a write-once field unless the pwod bit in tpumcr3 is set. 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8 refer to section 19.3.8, ?prescaler control for tcr1 ? for more information. 3:4 tcr2p timer count register 2 presca ler control. tcr2 is clocked from the output of a prescaler. the prescaler divides this input by 1, 2, 4, or 8. this is a write-once field unless the pwod bit in tpumcr3 is set. 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8 refer to section 19.3.9, ?prescaler control for tcr2 ? for more information. 5 emu emulation control. in emulation mode, the tpu3 executes microinstructions from dptram exclusively. access to the dptram via the imb3 is blocked, and the dptram is dedicated for use by the tpu3. after reset, this bit can be written only once. 0 tpu3 and dptram operate normally 1 tpu3 and dptram operate in emulation mode 1 6 t2cg tcr2 clock/gate control 0 tcr2 pin used as clock source for tcr2 1 tcr2 pin used as gate of div8 clock for tcr2 refer to section 19.3.9, ?prescaler control for tcr2 ? for more information. 7 stf stop flag. 0 tpu3 is operating normally 1 tpu3 is stopped (stop bit has been set) 8 supv supervisor data space 0 assignable registers are accessible from user or supervisor privilege level 1 assignable registers are accessible from supervisor privilege level only time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-12 freescale semiconductor 19.4.2 development support control register (dscr) this register is accessible only wh en the tpu is in test mode; see section 19.4.14, ?factory test registers .? 9 psck standard prescaler clock. note that this bit has no effect if the extended prescaler is selected (epscke = 1). 0f sys 32 is input to tcr1 prescaler, if standard prescaler is selected 1f sys 4 is input to tcr1 prescaler, if standard prescaler is selected 10 tpu3 tpu3 enable. the tpu3 enable bit provides co mpatibility with the tpu. if running tpu code on the tpu3, the microcode size should not be gr eater than 2 kbytes and the tpu3 enable bit should be cleared to zero. the tpu3 enable bit is write-once after reset. the reset value is one, meaning that the tpu3 will operate in tpu3 mode. 0 tpu mode; zero is the tpu reset value 1 tpu3 mode; one is the tpu3 reset value note: the programmer should not change this value unless necessary when developing custom tpu microcode. 11 t2csl tcr2 counter clock edge. this bit and the t2cg control bit determine the clock source for tcr2. refer to section 19.3.9, ?prescaler control for tcr2 ? for details. 12:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in tpu3 implementations that use har dware interrupt arbitration. 1 if all tpus connected to a dptram are stopped, the dptram is accessible. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field hot4 ? blc clks frz ccl bp bc bh bl bm bt sreset 0000_0000_0000_0000 addr 0x30 4004 (tpu_a), 0x30_4404 (tpu_b) figure 19-6. dscr ? developmen t support control register table 19-8. dscr bit descriptions bits name description 0 hot4 hang on t4 1 0 exit wait on t4 state caused by assertion of hot4 1 enter wait on t4 state 1:4 ? reserved 5 blc branch latch control 0 latch conditions into branch conditio n register before exiting halted state 1 do not latch conditions into branch condition r egister before exiting the halted state or during the time-slot transition period 6 clks stop clocks (to tcrs) 0 do not stop tcrs 1 stop tcrs during the halted state table 19-7. tpumcr bit description (continued) bits name description time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-13 19.4.3 development support status register (dssr) this register is accessible only wh en the tpu is in test mode; see section 19.4.14, ?factory test registers .? 7:8 frz freeze assertion response. the frz bits specify the tpu microengine response to the imb3 freeze signal 00 ignore freeze 01 reserved 10 freeze at end of current microcycle 11 freeze at next time-slot boundary 9 ccl channel conditions latch. ccl controls the latc hing of channel conditions match recognition latch (mrl) and transition detect latch (tdl) when the chan register is written. refer to the tpu reference manual (tpurm/ad) for further information. 0 only the pin state condition of the new channel is latched as a result of the write chan register microinstruction 1 pin state, mrl, and tdl conditions of the new channel are latched as a result of a write chan register microinstruction 10 bp breakpoint enable for microprogram counter ( pc) 0 breakpoint not enabled 1 break if pc equals pc breakpoint register 11 bc channel breakpoint enable 0 breakpoint not enabled 1 break if chan register equals channel breakpo int register at beginning of state or when chan is changed through microcode 12 bh host service breakpoint enable 0 breakpoint not enabled 1 break if host service latch is asserted at beginning of state 13 bl link service breakpoint enable 0 breakpoint not enabled 1 break if link service latch is asserted at beginning of state 14 bm mrl breakpoint enable 0 breakpoint not enabled 1 break if mrl is assert ed at beginning of state 15 bt tdl breakpoint enable 0 breakpoint not enabled 1 break if tdl is asserted at beginning of state 1 t4 is one of the four basic timers (t1, t2, t3 & t4) used for microengine timing. table 19-8. dscr bit d escriptions (continued) bits name description time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-14 freescale semiconductor 19.4.4 tpu3 interrupt conf iguration register (ticr) msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ? bkpt pcbk chbk srbk tpuf ? sreset 0000_0000_0000_0000 addr 0x30 4006 (tpu_a), 0x30 4406 (tpu_b) figure 19-7. dssr ? development support status register table 19-9. dssr bit descriptions bits name description 0:7 ? reserved 8 bkpt breakpoint asserted flag. if an internal breakpo int caused the tpu3 to enter the halted state, the tpu3 asserts the bkpt signal on the imb and sets the bkpt flag. bkpt remains set until the tpu3 recognizes a breakpoint acknowledge cycle, or until the imb freeze signal is asserted. 9 pcbk microprogram counter ( pc) breakpoint flag. pcbk is asserted if a breakpoint occurs because of a pc register match with the pc breakpoint register. pcbk is negated when the bkpt flag is cleared. 10 chbk channel register breakpoint flag. chbk is a sserted if a breakpoint occurs because of a chan register match with the chan register breakpoi nt register. chbk is ne gated when the bkpt flag is cleared. 11 srbk service request breakpoint flag. srbk is assert ed if a breakpoint occurs because of any of the service request latches being asserted along with their corresponding enable flag in the development support control register. srbk is negated when the bkpt flag is cleared. 12 tpuf tpu3 freeze flag. tpuf is set whenever the tpu3 is in a halted state as a result of freeze being asserted. this flag is automatically negate d when the tpu3 exits the halted state because of freeze being negated. 13:15 ? reserved msb 01234567891011121314 lsb 15 field ? cirl ilbs ? sreset 0000_0000_0000_0000 addr 0x30 4008 (tpu_a), 0x30 4408 (tpu_b) figure 19-8. ticr ? tpu3 inte rrupt configuration register time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-15 19.4.5 channel interrupt enable register (cier) the channel interrupt enable register (cier) allows th e cpu to enable or disabl e the ability of individual tpu3 channels to request in terrupt service. setting the appropriate bit in the register enables a channel to make an interrupt service request; cl earing a bit disables the interrupt. 19.4.6 channel function select registers (cfsr n ) encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be executed on the corresponding ch annel. encodings for predef ined functions are found in table d-1 and table d-2 . table 19-10. ticr bit description bits name description 0:4 ? reserved 5:7 cirl channel interrupt request level. this three-bi t field specifies the interrupt request level for all channels. this field is used in conjunction with the ilbs field to determine the request level of tpu3 interrupts. 8:9 ilbs interrupt level byte select. this field and the cirl field determine the level of tpu3 interrupt requests. 00 irq [0:7] selected 01 irq [8:15] selected 10 irq [16:23] selected 11 irq [24:31] selected 10:15 ? reserved. note that bits 10:11 represent channel interrupt base vector (cibv) bits in some tpu3 implementations. msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 400a (tpu_a), 0x30 440a (tpu_b) figure 19-9. cier ? channel interrupt enable register table 19-11. cier bit descriptions bits name description 0:15 ch[15:0] channel interrupt enable/disable 0 channel interrupts disabled 1 channel interrupts enabled note: the msb (bit 0) represents ch15, and the lsb (bit 15) represents ch0. time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-16 freescale semiconductor 19.4.7 host sequence registers (hsqr n ) the host sequence field selects the m ode of operation for the time func tion selected on a given channel. the meaning of the host sequence bits de pends on the time function specified. see appendix d, ?tpu3 rom functions ,? for definitions of the host service request bits for the predefin ed tpu rom functions. msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 sreset 0000_0000_0000_0000 addr 0x30 400c (tpu_a), 0x30 440c (tpu_b) figure 19-10. cfsr0 ? channel function select register 0 msb 01234567891011121314 lsb 15 field ch 11 ch 10 ch 9 ch 8 sreset 0000_0000_0000_0000 addr 0x30 400e (tpu_a), 0x30 440e (tpu_b) figure 19-11. cfsr1 ? channel function select register 1 msb 01234567891011121314 lsb 15 field ch 7 ch 6 ch 5 ch 4 sreset 0000_0000_0000_0000 addr 0x30 4010 (tpu_a), 0x30 4410 (tpu_b) figure 19-12. cfsr2 ? channel function select register 2 msb 01234567891011121314 lsb 15 field ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 4012 (tpu_a), 0x30 4412 (tpu_b) figure 19-13. cfsr3 ? channel function select register 3 table 19-12. cfsr n bit descriptions name description ch[15:0] encoded time function for each channel. encoded four-bit fields in the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-17 19.4.8 host service request registers (hsrr n ) the host service request fiel d selects the type of host service reque st for the time function selected on a given channel. the meaning of the host service request bits is determ ined by time function microcode. see appendix d, ?tpu3 rom functions ,? the tpu reference manual and the freescale tpu literature package for more information. msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 sreset 0000_0000_0000_0000 addr 0x30 4014 (tpu_a), 0x30 4414 (tpu_b) figure 19-14. hsqr0 ? host sequence register 0 msb 01234567891011121314 lsb 15 field ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 4016 (tpu_a), 0x30 4416 (tpu_b) figure 19-15. hsqr1 ? host sequence register 1 table 19-13. hsqr n bit descriptions name description ch[15:0] encoded host sequence. the host sequence field selects the mode of operati on for the time function selected on a given channel. the meaning of the host sequence bits depends on the time function specified. msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 sreset 0000_0000_0000_0000 addr 0x30 4018 (tpu_a), 0x30 4418 (tpu_b) figure 19-16. hsrr0 ? host service request register 0 msb 01234567891011121314 lsb 15 field ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 401a (tpu_a), 0x30 441a (tpu_b) figure 19-17. hsrr1 ? host service request register 1 time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-18 freescale semiconductor 19.4.9 channel priority registers (cprx) the channel priority registers (cpr1, cpr2) assign one of three priority levels to a channel or disable the channel. see appendix d, ?tpu3 rom functions ,? for more information. table 19-14. hssr n bit descriptions name description ch[15:0] encoded type of host service. the host service request field selects the type of host service request for the time function selected on a given channel. the meaning of the host service request bits depends on the time function specified. a host service request field cleared to 0b00 signal s the host that service is completed by the microengine on that channel. the host can request service on a channel by writing the corresponding host service request field to one of three non-zero states. the cpu must monitor the host service request register until the tpu3 clears the servic e request to 0b00 before any parameters are changed or a new service request is issued to the channel. msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 sreset 0000_0000_0000_0000 addr 0x30 401c (tpu_a), 0x30 441c (tpu_b) figure 19-18. cpr0 ? channel priority register 0 msb 01234567891011121314 lsb 15 field ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 401e (tpu_a), 0x30 441e (tpu_b) figure 19-19. cpr1 ? channel priority register 1 table 19-15. cpr n bit description name description ch[15:0] encoded channel priority levels. table 19-16 indicates the number of time slots guaranteed for each channel priority encoding. table 19-16. channel priorities chx[1:0] service guaranteed time slots 00 disabled ? 01 low 1 out of 7 10 middle 2 out of 7 11 high 4 out of 7 time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-19 19.4.10 channel interrupt status register (cisr) the channel interrupt status register (cisr) contains one inte rrupt status flag per channel. time functions specify via microcode when an interrupt flag is set. setting a flag causes the tp u3 to make an interrupt service request if the corres ponding cier bit is set. to clear a status flag, read cisr, then write a zero to the appropriate bit. note cisr is the only tpu3 register th at can be accessed on a byte basis. 19.4.11 tpu3 module configur ation register 2 (tpumcr2) msb 01234567891011121314 lsb 15 field ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 sreset 0000_0000_0000_0000 addr 0x30 4020 (tpu_a), 0x30 4420 (tpu_b) figure 19-20. cisr ? channel interrupt status register table 19-17. cisr bit descriptions bits name description 0:15 ch[15:0] channel interrupt status 0 channel interrupt not asserted 1 channel interrupt asserted msb 0123456 7 8 9 10 111213 14 lsb 15 field ? div2 softrst e tbank fpsck t2cf dtpu sreset 0000_0000_0000_0000 addr 0x30 4028 (tpu_a), 0x30 4428 (tpu_b) figure 19-21. tpumcr2 ? tpu modu le configuration register 2 table 19-18. tpumcr2 bit descriptions bits name description 0:6 ? reserved 7 div2 divide by 2 control. when asserted, the div2 bit, along with the tcr1p bit and the psck bit in the tpumcr, determines the rate of the tcr1 counter in the tpu3. if set, the tcr1 counter increments at a rate of two system clocks. if negated, tcr1 increments at the rate determined by control bits in the tcr1p and psck fields. 0 tcr1 increments at rate determined by contro l bits in the tcr1p and psck fields of the tpumcr register 1 causes tcr1 counter to increment at a rate of the system clock divided by two time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-20 freescale semiconductor 8 soft rst soft reset. the tpu3 performs an internal reset when both the soft rst bit in the tpumcr2 and the stop bit in tpumcr are set. the cpu must write zero to the soft rst bit to bring the tpu3 out of reset. the soft rst bit must be asserted for at least nine clocks. 0 normal operation 1 puts tpu3 in reset until bit is cleared note: do not attempt to access any other tpu3 registers when this bit is asserted. when this bit is asserted, it is the only accessible bit in the register. 9:10 etbank entry table bank select. this field determ ines the bank where the microcoded entry table is situated. after reset, this field is 0b00. this c ontrol bit field is write once after reset. etbank is used when the microcode contains entry tables no t located in the default bank 0. to execute the rom functions on this mcu, etbank[1:0] must be 00. refer to ta b l e 1 9 - 1 9 . note: this field should not be modified by th e programmer unless necessary because of custom microcode. 11:13 fpsck filter prescaler clock. th e filter prescaler clock control bit field determines the ratio between system clock frequency and minimum detectable pulses. the reset value of these bits is zero, defining the filter clock as fo ur system clocks. refer to table 19-20 . 14 t2cf t2clk pin filter control. wh en asserted, the t2clk input pin is filtered with the same filter clock that is supplied to the channels. this control bit is write once after reset. 0 uses fixed four-clock filter 1 t2clk input pin filtered with same filter clock that is supplied to the channels 15 dtpu disable tpu3 pins. when the disable tpu3 contro l pin is asserted, pin tp15 is configured as an input disable pin. when the tp15 pin value is zero, all tpu3 output pins are three-stated, regardless of the pins function. th e input is not synchronized. this control bit is write once after reset. 0 tp15 functions as normal tpu3 channel 1 tp15 pin configured as output disable pin. when tp15 pin is low, all tpu3 output pins are in a high-impedance state, regardless of the pin function. table 19-19. entry table bank location etbank bank 00 0 01 1 10 2 11 3 table 19-20. system clock frequency/minimum guaranteed detected pulse filter control divide by 20 mhz 33 mhz 40 mhz 56 mhz 000 4 200 ns 121 ns 100 ns 71 ns 001 8 400 ns 242 ns 200 ns 143 ns 010 16 800 ns 485 ns 400 ns 286 ns 011 32 1.6 s 970 ns 800 ns 571 ns 100 64 3.2 s 1.94 s 1.60 s1.14 s table 19-18. tpumcr2 bit descriptions (continued) bits name description time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-21 19.4.12 tpu module configur ation register 3 (tpumcr3) 101 128 6.4 s 3.88 s 3.20 s2.29 s 110 256 12.8 s 7.76 s 6.40 s4.57 s 111 512 25.6 s 15.51 s 12.80 s9.14 s msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 field ? pwod tcr2psck2 epscke ? epsck sreset 0000_0000_0000_0000 addr 0x30 402a (tpu_a), 0x30 442a (tpu_b) figure 19-22. tpumcr3 ? tpu modu le configuration register 3 table 19-21. tpumcr3 bit descriptions bits name description 0:6 ? reserved 7 pwod prescaler write-once disable bit. the pwod bit does not lock the epsck field and the epscke bit. 0 prescaler fields in mcr are write-once 1 prescaler fields in mcr can be written anytime 8 tcr2psck 2 tcr2 prescaler 2 0 prescaler clock source is divided by one. 1 prescaler clock is divided. see divider definitions in ta bl e 1 9 - 5 . 9 epscke enhanced pre-scaler enable 0 disable enhanced prescaler (use standard prescaler) 1 enable enhanced prescaler. system clock will be divided by the value in epsck field. 10 ? reserved 11:15 epsck enhanced prescaler value that will be lo aded into the enhanced prescaler counter. prescaler value(epsck + 1) x 2. refer to section 19.3.8, ?prescaler control for tcr1 ,? for details. table 19-20. system clock frequency/minimum guaranteed detected pulse time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-22 freescale semiconductor 19.4.13 siu test register (siutst) 19.4.14 factory test registers table 19-23 shows registers that are used for factory test only.the tpu developmen t support registers are also used by tpu debuggers. they can only be us ed if the tpu is put into its test mode. msb 0 123456789101112131415 field tpu_dbg ? sreset 0000_0000_0000_0000 addr 0x2f_c3fc 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 19-23. siutst ? siu test register table 19-22. siutst bit descriptions bits name description 0 tpu_dbg this enables the test features of the tpu for use by tpu debuggers. it should only be enabled while debugging tpu microcode. 0 tpu debugging is disabled 1 tpu debug is enabled 1:31 ? reserved, always clear to 0. table 19-23. registers used for factory test only name address tpu_a tpu_b link register (lr) 0x30 4022 0x30 4422 service grant latch register (sglr) 0x30 4024 0x30 4424 decoded channel number register (dcnr) 0x30 4026 0x30 4426 internal scan data register (isdr) 0x30 402c 0x30 442c internal scan control register (iscr) 0x30 402e 0x30 442e tpu3 test configuration register (tcr) 0x30 4002 0x30 4402 development support control register (dscr) 0x30 4004 0x30_4404 development support status register (dssr) 0x30 4006 0x30 4406 time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 19-23 19.4.15 tpu3 parameter ram the channel parameter registers are organized as one hundred 16-bit word s of ram. channels 0 to 15 have eight parameters. the para meter registers constitute a shared wo rk space for communication between the cpu and the tpu3. the tpu3 can only access data in the parameter ram. refer to table 19-24 . 19.5 time functions descriptions of the mpc 561/mpc563 pre-programmed time functions are shown in appendix d, ?tpu3 rom functions .? table 19-24. parameter ram address offset map channe l number parameter 01234567 0 0x30 4100(a) 0x30 4500(b)) 0x30 4102a(a) 0x30 4502(b) 0x30 4104(a) 0x30 4504(b) 0x30 4106(a) 0x30 4506(b) 0x30 4108(a) 0x30 4508(b) 0x30 410a(a) 0x30 450a(b) 0x30 410c(a) 0x30 450c(b) 0x30 410e(a) 0x30 450e(b) 1 0x30 4110(a) 0x30 4510(b) 0x30 4112(a) 0x30 4512(b) 0x30 4114(a) 0x30 4514(b) 0x30 4116(a) 0x30 4516(b) 0x30 4118(a) 0x30 4518(b) 0x30 411a(a) 0x30 451a(b) 0x30 411c(a) 0x30 451c(b) 0x30 411e(a) 0x30 451e(b) 2 0x30 4120(a) 0x30 4520(b) 0x30 4122(a) 0x30 4522(b) 0x30 4124(a) 0x30 4524(b) 0x30 4126(a) 0x30 4526(b) 0x30 4128(a) 0x30 4528(b) 0x30 412a(a) 0x30 452a(b) 0x30 412c(a) 0x30 452c(b)) 0x30 412e(a) 0x30 452e(b) 3 0x30 4130(a) 0x30 4530(b) 0x30 4132(a) 0x30 4532(b) 0x30 4134(a) 0x30 4534(b) 0x30 4136(a) 0x30 4536(b) 0x30 4138(a) 0x30 4538(b) 0x30 413a(a) 0x30 453a(b) 0x30 413c(a) 0x30 453c(b) 0x30 413e(a) 0x30 453e(b) 4 0x30 4140(a) 0x30 4540(b) 0x30 4142(a) 0x30 4542(b) 0x30 4144(a) 0x30 4544(b) 0x30 4146(a) 0x30 4546(b) 0x30 4148(a) 0x30 4548(b) 0x30 414a(a) 0x30 454a(b) 0x30 414c(a) 0x30 454c(b) 0x30 414e(a) 0x30 454e(b) 5 0x30 4150(a) 0x30 4550(b) 0x30 4152(a) 0x30 4552(b) 0x30 4154(a) 0x30 4554(b) 0x30 4156(a) 0x30 4556(b) 0x30 4158(a) 0x30 4558(b) 0x30 415a(a) 0x30 455a(b) 0x30 415c(a) 0x30 455c(b) 0x30 415e(a) 0x30 455e(b) 6 0x30 4160(a) 0x30 4560(b) 0x30 4162(a) 0x30 4562(b) 0x30 4164(a) 0x30 4564(b) 0x30 4166(a) 0x30 4566(b) 0x30 4168(a) 0x30 4568(b) 0x30 416a(a) 0x30 456a(b) 0x30 416c(a) 0x30 456c(b) 0x30 416e(a) 0x30 456e(b) 7 0x30 4170(a) 0x30 4570(b) 0x30 4172(a) 0x30 4572(b) 0x30 4174(a) 0x30 4574(b) 0x30 4176(a) 0x30 4576(b) 0x30 4178(a) 0x30 4578(b) 0x30 417a(a) 0x30 457a(b) 0x30 417c(a) 0x30 457c(b) 0x30 417e(a) 0x30 457e(b) 8 0x30 4180(a) 0x30 4580(b) 0x30 4182(a) 0x30 4582(b) 0x30 4184(a) 0x30 4585(b) 0x30 4186(a) 0x30 4586(b) 0x30 4188(a) 0x30 4588(b) 0x30 418a(a) 0x30 458a(b) 0x30 418c(a) 0x30 458c(b) 0x30 418e(a) 0x30 458e(b) 9 0x30 4190(a) 0x30 4590(b) 0x30 4192(a) 0x30 4592(b) 0x30 4194(a) 0x30 4594(b) 0x30 4196(a) 0x30 4596(b) 0x30 4198(a) 0x30 4598(b) 0x30 419a(a) 0x30 459a(b) 0x30 419c(a) 0x30 459c(b) 0x30 419e(a) 0x30 459e(b) 10 0x30 41a0(a) 0x30 45a0(b) 0x30 41a2(a) 0x30 45a2(b) 0x30 41a4(a) 0x30 45a4(b) 0x30 41a6(a) 0x30 45a6(b) 0x30 41a8(a) 0x30 45a8(b) 0x30 41aa(a) 0x30 45aa(b) 0x30 41ac(a) 0x30 45ac(b) 0x30 41ae(a) 0x30 45ae(b) 11 0x30 41b0(a) 0x30 45b0(b) 0x30 41b2(a) 0x30 45b2(b) 0x30 41b4(a) 0x30 45b4(b) 0x30 41b6(a) 0x30 45b6(b) 0x30 41b8(a) 0x30 45b8(b) 0x30 41ba(a) 0x30 45ba(b) 0x30 41bc(a) 0x30 45bc(b) 0x30 41be(a) 0x30 45be(b) 12 0x30 41c0(a) 0x30 45c0(b) 0x30 41c2(a) 0x30 45c2(b) 0x30 41c4(a) 0x30 45c4(b) 0x30 41c6(a) 0x30 45c6(b) 0x30 41c8(a) 0x30 45c8(b) 0x30 41ca(a) 0x30 45ca(b) 0x30 41cc(a) 0x30 45cc(b) 0x30 41ce(a) 0x30 45ce(b) 13 0x30 41d0(a) 0x30 45d0(b) 0x30 41d2(a) 0x30 45d2(b) 0x30 41d4(a) 0x30 45d4(b) 0x30 41d6(a) 0x30 45d6(b) 0x30 41d8(a) 0x30 45d8(b) 0x30 41da(a) 0x30 45da(b) 0x30 41dc(a) 0x30 45dc(b) 0x30 41de(a) 0x30 45de(b) 14 0x30 41e0(a) 0x30 45e0(b) 0x30 41e2(a) 0x30 45e2(b) 0x30 41e4(a) 0x30 45e4(b) 0x30 41e6(a) 0x30 45e6(b) 0x30 41e8(a) 0x30 45e8(b) 0x30 41ea(a) 0x30 45ea(b) 0x30 41ec(a) 0x30 45ec(b) 0x30 41ee(a) 0x30 45ee(b) 15 0x30 41f0(a) 0x30 45f0(b) 0x30 41f2(a) 0x30 45f2(b) 0x30 41f4(a) 0x30 45f4(b) 0x30 41f6(a) 0x30 45f6(b) 0x30 41f8(a) 0x30 45f8(b) 0x30 41fa(a) 0x30 45fa(b) 0x30 41fc(a) 0x30 45fc(b) 0x30 41fe(a) 0x30 45fe(b) time processor unit 3 mpc561/mpc563 reference manual, rev. 1.2 19-24 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 20-1 chapter 20 dual-port tpu3 ram (dptram) the dual-port ram (dptram) module with tpu3 microcode storage support consists of a control register block and an 8-kbyte array of static ram, which can be used either as a microcode storage for tpu3 or as a general-purpose memory. the mpc 561/mpc563 has one dptram module. the module serves two tpu3 modules (a and b). the dptram module acts as a common memory on the imb3 and allows th e transfer of da ta to the two tpu3 modules. therefore, the dptram interface includes an imb3 bus interface and two tpu3 interfaces. when the dptram is be ing used in microcode mode, the a rray is only accessi ble to the tpu3 via a separate local bus, and not via the imb3. in the mpc561/mpc563, the dptram base address register (rambar) must be set to a particular value to fit into the imb memory map of th e part. the dptram rambar register must be programmed to 0xffa0. the dptram module is powered by v dd in normal operation. the entire array may be used as standby ram if standby power is supplied via the iramst by pin of the mpc561/mpc563. iramstby must be supplied by an external source. the dptram may also be used as the microcode control store for up to two tpu3 modules when placed in a special emulation mode. in this mode the dptr am array may only be accessed by either or both of the tpu3 units simultaneously via separate emulation bu ses, and not via the imb3. the dptram contains a multiple input signature ca lculator (misc) in order to provide ram data corruption checking. the misc reads the dptram address and generates a 32-bit data-dependent signature. this signature can then be checked by the host. note the rcpu cannot perform instructi on fetches from any module on the imb3 (including the dptram). only data accesses are permitted. 20.1 features ? eight kbytes of static ram ? accessible by the cpu only if neither tpu3 is in emulation mode ? low-power stop operation ? entered by setting the stop bit in the dptmcr ? does not enter low-power state while in tpu3 emulation mode for protection ? tpu3 microcode mode dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 20-2 freescale semiconductor ? the dptram array acts as a microcode storage for the tpu3 module. this pr ovides a means of executing tpu3 code out of dptram instead of tpu3 rom. ? includes built in check logic which scans the ar ray contents and calculat es the dptram signature ? imb3 bus interface ? two tpu3 interface units ? byte, half-word, or word accessible 20.2 dptram configuration block diagram figure 20-1. dptram configuration 20.3 programming model the dptram module consists of two separately addressable sections. th e first is a set of memory-mapped control and status registers used for configura tion (dptmcr, rambar, misrh, misrl, miscnt) and testing (dpttcr) of the dptram array. the second secti on is the array itself. all dptram module control and status registers are located in supervisor data space. user read or write attempts will result in a bus error. when the tpu3 is using the ram a rray for microcode control storage, none of these cont rol registers has any effect on the operation of the ram array. all addresses within the 64-byte control block wi ll respond when accessed properly. unimplemented addresses will return zeros for read accesses. likewi se, unimplemented bits with in registers will return zero when read and will not be affected by write operations. table 20-1 shows the dptram control and status register s. the addresses shown are offsets from the internal system base address (see section 6.2.2.1.2, ?internal memo ry map register (immr) ?). refer to figure 1-3 to locate the dptram control bloc k in the mpc561/mpc563 address map. imb3 tpu3 emulation mode tpu3 tpu3 local bus local bus ram mode dptram tpu3 tpu3 dptram imb3 imb3 imb3 dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 20-3 the dptram array occupies an 8- kbyte block. in the mpc561/mpc563, th e array must be located at the address 0x30 2000. refer to figure 1-3 and figure 20-2 . figure 20-2. dptram memory map 20.3.1 dptram module config uration register (dptmcr) this register defines the basic c onfiguration of the dptram module. the dptmcr contains bits to configure the dptram module for stop operation and for proper access privileges to the array. the register also contains the misc control bits. table 20-1. dptram register map r/w access address register reset value supervisor r/w 0x30 0000 dpt ram modul e configuration register (dptrmcr) see ta bl e 2 0 - 2 for bit descriptions. 0x0100 test 0x30 0002 test configuration register (dpttcr) 0x0000 supervisor r/w 0x30 0004 ram base address register (rambar) see ta bl e 2 0 - 3 for bit descriptions. 0x0001 supervisor read only 0x30 0006 multiple input signature register high (misrh) see section 20.3.4, ?misr high (misrh) and misr low registers (misrl) ? for bit descriptions. 0x0000 supervisor read only 0x30 0008 multiple input signat ure register low (misrl) see section 20.3.4, ?misr high (misrh) and misr low registers (misrl) ? for bit descriptions. 0x0000 supervisor read only 0x30 000a multiple input signature counter (miscnt) see section 20.3.5, ?misc counter (miscnt) ? for bit descriptions. last memory address msb 0 1 2 3 4 5 6 7 8 9 1011121314 lsb 15 field stop ? misf misen rasp ? sreset 0 undefined 0 0 1 0000_0000 addr 0x30 0000 figure 20-3. dpt module configuration register (dptmcr) dptram array 0x30 2000 0x30 3fff (8 kbytes) dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 20-4 freescale semiconductor 20.3.2 dptram test register (dpttcr) dpttcr (test register, address 0x30 0002) is used only during factory testi ng of the mpc561/mpc563, and, if written, will generate a bus error. 20.3.3 ram base address register (rambar) the rambar register is used to specify the 16 msbs of the starting dptram array location in the memory map. in order to be accessible in the mpc561/mpc563 memory map, this register must be programed to 0xffa0. this register can be writ ten only once after a reset. this prevents runaway software from inadvertently re-mapping the array. since the locking mechanism is triggered by the first writ e after reset, the base table 20-2. dptmcr bit settings bits name description 0 stop low power stop (sleep) mode 0 dptram clocks running 1 dptram clocks shut down only the stop bit in the dptmcr may be access ed while the stop bit is asserted. accesses to other dptram registers may result in unpredi ctable behavior. note also that the stop bit should be set and cleared independently of the ot her control bits in this register to guarantee proper operation. changing the st ate of other bits while changing the state of the stop bit may result in unpredictable behavior. refer to section 20.4.4, ?stop operation ? for more information. 1:4 ? reserved 5 misf multiple input signature flag. misf is readable at any time. this flag bit should be polled by the host to determine if the misc has completed re ading the dptram. if mi sf is set, the host should read the misrh and misrl registers to obtain the dptram signature. 0 first signature not ready 1 misc has read entire dptram. signature is la tched in misrh and misrl and is ready to be read. 6 misen multiple input signature enable. misen is rea dable and writable at any time. the misc will only operate when this bit is set and the mpc561/mpc563 is in tpu3 emulation mode. when enabled, the misc will continuously cycle thro ugh the dptram addresses, reading each and adding the contents to the misr. in order to save power, the misc can be disabled by clearing the misen bit. 0misc disabled 1 misc enabled 7 rasp ram area supervisor/user program/data. the dptram array may be placed in supervisor or unrestricted space. when pl aced in supervisor space, (r asp = 1), only a supervisor may access the array. if a supervisor program is acce ssing the array, normal read/write operation will occur. if a user program is attempting to access the array, the access will be ignored and the address may be decoded externally. 0 both supervisor and user access to dptram allowed 1 supervisor access only to dptram allowed 8:15 ? reserved. these bits are used for the ia rb (interrupt arbitration id) field in tpu3 implementations that use hard ware interrupt arbitration. dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 20-5 address of the array should be writ ten in a single operation. writing only one half of the register will prevent the other half from being written. 20.3.4 misr high (misrh) and misr low registers (misrl) the misrh and misrl together contain the 32-bi t ram signature calculated by the misc. these registers are read-only and should be read by the host when the misf bit in the mcr is set. exiting tpu3 emulation mode results in the reset of both misrh and misrl. msb 0 1234567891011121314 lsb 15 field a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 ? ramds sreset 0000_0000_0000_000 1 addr 0x30 0004 figure 20-4. ram array base address register (rambar) table 20-3. rambar bit settings bits name description 0:11 a[8:19] dptram array base address. these bits specify the 11 high-order bits of the 24-bit base address of the dptram array. this allows t he array to be placed on a 8-kbyte boundary anywhere in the memory map. do not overlap the dptram array memory map with other modules on the chip. on the mpc561/mpc563 the value 0xffa0 must be used for dptram 6 kbyte. 12:14 ? reserved. (bit 12 represents a[20] in dptram implementations that require it.) 15 ramds ram disabled. ramds is a read-only status bit. the dptram array is disabled after a master reset because the rambar regist er may be incorrect. when the array is disabled, it will not respond to any addresses on the imb3. access to the dptram control register block is not affected when the array is disabled. ramds is cleared by the dptram module when a base address is written to the array address field of rambar. ramds = 0: dptram enabled ramds = 1: dptram disabled msb 0 1234567891011121314 lsb 15 field d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 sreset 0000_0000_0000_0000 addr 0x30 0006 figure 20-5. multiple input signature register high (misrh) dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 20-6 freescale semiconductor 20.3.5 misc co unter (miscnt) the miscnt contains the address of the current misc memory access. th is register is read-only. note that the naming of the a[31:0] bits represents little-e ndian bit encoding. exiting tpu3 emulation mode or clearing the misen bit in the dptmcr results in the reset of this register. 20.4 dptram operation the dptram module has several modes of opera tion. the following secti ons describe dptram operation in each of these modes. 20.4.1 normal operation in normal operation, read or write data accesses of 8-, 16-, or 32-bits are supported. also, in normal operation, neither tpu3 accesses the array, nor do they have any eff ect on the operation of the dptram module. 20.4.2 standby operation the dptram array uses a separate power supply ir amstby to provide power to the dptram array during a power-down phase. in order to guarantee valid dptr am data during power- down, external low voltage inhibit circuitry (external to the mpc561/mpc563) must be designe d to force the reset pin of the mpc561/mpc563 into the active state before v dd drops below its normal limit. this is necessary to inhibit spurious writes to the dptram during power-down. msb 0 1234567891011121314 lsb 15 fieldd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 sreset 0000_0000_0000_0000 addr 0x30 0008 figure 20-6. multiple input signature register low (misrl) msb 01234567891011121314 lsb 15 field ? a12a11a10a9a8a7a6a5a4a3a2a1 a0 sreset last memory address addr 0x30 000a figure 20-7. misc counter (miscnt) dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 20-7 20.4.3 reset operation when a synchronous reset occurs, a bus master is allowed to complete th e current access. thus a write bus cycle (byte, half word, or word) th at is in progress when a synchronous reset occurs will be completed without error. once a writ e already in progress has been complete d, further writes to the dptram array are inhibited. if a reset is generated by an async hronous reset such as the loss of cl ocks or software watchdog time-out, the contents of the dptram arra y are not guaranteed. (refer to chapter 7, ?reset ? for a description of mpc561/mpc563 reset sources, ope ration, control, and status.) reset will also reconfigure some of the fields and bi ts in the dptram control registers to their default reset state. see the description of the control registers to determine th e effect of reset on these registers. 20.4.4 stop operation setting dptmcr[stop] causes the module to enter its lowest power-consuming state. the dptmcr can still be written to allow the st op control bit to be cleared. in stop mode, the dptram array cannot be read or written. all data in the array is retained the biu continues operating to allow the cpu to access the st op bit in the dptmcr. th e system clock remains stopped until the stop bi t is cleared or the dptram module is reset. the stop bit is initialized to logi cal zero during reset. only the st op bit in the dp tmcr can be accessed while the stop bit is asserted. accesses to other dptram registers may result in unpredictable behavior. the dptram will not enter stop mode if one of the tpus is in emulation mode using dptram (i.e., tpumcr[emu] = 1) 20.4.5 freeze operation the freeze line on the imb3 has no effect on the dp tram module. when the fr eeze line is set, the dptram module will operate in its current mode of operation. if the dptram module is not disabled, (ramds = 0), it may be accessed via the imb3. if the dptram array is being used by the tpu3 in emulation mode, the dptram will still be ab le to be accessed by the tpu3 microengine. 20.4.6 tpu3 emulation mode operation to emulate tpu3 time functions, store in the ram array the microinstructions required for all time functions. storing microins tructions must be done with the dp tram in its normal operating mode and accessible from the imb3. af ter the time functions are stored in th e array, place one or both of the tpu3 units in emulation mode. the ram ar ray is then controlled by the tpu3 units and disconnected from the imb3. to use the dptram for microcode accesses, se t the emu bit in the corresponding tpu3 module configuration register. through the auxiliary buses, the tpu3 units can access word instructions simultaneously at a rate of up to 56 mhz. dual-port tpu3 ram (dptram) mpc561/mpc563 reference manual, rev. 1.2 20-8 freescale semiconductor when the dptram array is being used by one or tw o of the tpu3 units, all accesses via the imb3 are disabled. the control registers have no effect on the ram array. the contents of the ram ar e validated using a multiple input signatu re calculator (misc). misc reads of the ram are performed only when the mpc561/mpc563 is in emulation mode and the misc is enabled (misen = 1 in the dptmcr). refer to section 19.3.6, ?emulation support ? for more information in tp u3 and dptram operation in emulation mode. 20.5 multiple input signat ure calculator (misc) the integrity of the dptram data is ensured through the use of a misc. the dptram data is read in reverse address order and a unique 32- bit signature is generated based on the output of these reads. misc reads are performed when one of the tpu3 modules does not request back-t o-back accesses to the dptram provided that the misen bit in the dptmcr is set. the misc generates the dptram signa ture based on the following polynomial: eqn. 20-1 after the entire dptram has been re ad and a signature has been calcul ated, the misc sets the misf bit in the dptmcr. the host should poll this bit and enter a handling routine when the bit is found to be set. the signature should then be read from the misrh and misrl register s and the host determines if it matches the predetermined signature. the misrh and misrl regi sters are updated each time the misc completes reading the entire dptram regardless of whether or not the previous signature ha s been read or not. this en sures that the host reads the most recently generated signature. the misc can be disabled by clearing the misen bit in the dptmcr. note the reset state of the dp tmcr[misen] is disabled. gx () 1xx 2 x 22 x 31 ++ + + = mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-1 chapter 21 cdr3 flash (uc3f) eeprom the mpc563 u-bus cdr3 (uc3f) eeprom module is designed for use in embedded microcontroller (mcu) applications targeted for hi gh-speed read performance and hi gh-density byte count requirements. the mpc563 has one flash module of 512 kbytes but th e mpc561 has no internal flash; this chapter, therefore, applies only to the mpc563. the uc3f arra y uses a single transistor flash bit cell and is configured for a module of 512 kbytes (524,288 bytes) of non-volatil e memory (nvm). the uc3f module is divided into eight 64-k byte (65,536-byte) array blocks. tw o blocks of the uc3f module memory map may be subdivided into two smaller blocks: a 48-kbyte (49,152-by te) block and a 16-kbyte (16,384-byte) block, or a 16-kbyt e block and a 48-kbyte block. the primary function of the uc3f ee prom module is to serve as elec trically programmable and erasable nvm to store program instructions and/or data. it is a class of non-volatile so lid state silicon memory device consisting of an arra y of isolated elements, an electrical means for selectively adding and removing charge to the elements, and a means of selectively sensing the stored ch arge in the elements. when power is removed from the device, the stored charge of the isolated elements will be retained. the uc3f eeprom module is arranged into two major sections as shown in figure 21-1 . the first section is the uc3f array used to store sy stem program and data. th e second section is the memory interface (mi) that controls operation of the uc3f array. the mi also serves as the interface between the uc3f array and a bus interface unit (biu) which conne cts the uc3f array to the u-bus. note if the flash arrays are disabled in the immr register (flen=0), then neither the uc3f array or the uc3f control registers are accessible. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-2 freescale semiconductor figure 21-1. block diagram for a 51 2 kbyte uc3f module configuration the uc3f eeprom module array is divided into array blocks to allo w for independent erase, address attributes restrictions, a nd protection from program and erase for each array block. the size of a large array block in the uc3f module is fixed at 64 kbytes. the size of a subdivide d large block becomes the original large array block size minus 16 kbyt es (64 kbytes ? 16 kbyt es = 48 kbytes). the si ze of the small block, which is the remainder of the large block, is al ways 16 kbytes. the total uc3f eeprom array is distributed into eight large blocks, two of which cont ain small blocks. informati on is transferred to the uc3f eeprom by long-word (64 bits), word (32 bi ts), half-word (16 bits), or byte (8 bits). to improve system performance, ea ch array read access retrieves 32 byt es of information. these 32 bytes may be copied into one of two read page buffers al igned to the low order addresses. the two read page buffers are independently updated by page management logic contained in the biu which interfaces to the uc3f eeprom module. block 0 (16 kbytes + 48 kbytes) block 1 (48 kbytes + 16 kbytes) block 2 (64 kbytes) block 3 (64 kbytes) block 4 (64 kbytes) block 5 (64 kbytes) block 6 (64 kbytes) block 7 (64 kbytes) column decode row decode pgm data latch address latch read page buffer 0 read page buffer 1 data mux program/erase control program/erase voltage generation read control internal timer register block memory interface (mi) uc3f array core vssf vddf vflash bus interface unit (biu) u-bus epee b0epee cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-3 to prevent unnecessary page accesses from the array, the uc3f memory interface (mi) monitors the incoming address to determine if the required informat ion is in one of the two read page buffers. this strategy allows the uc3f array to have an off pa ge access and an on page a ccess. in normal operation, write accesses to the uc3f array are not recogni zed except during program and erase operations. the uc3f eeprom uses an embedded hardware algorithm to program and erase the uc3f array. special control logic is included to guard against accident al program or erase by requiri ng a specific series of read and write accesses to the uc3f c ontrol registers. external input s provide a hardware protection mechanism to prevent accidental program and erase of uc3f array blocks. the hardware algorithm automatically performs all necessary applications of high voltage pulses and verify reads of the uc3f array to ensure that all bi ts are programmed and erased with sufficie nt margin to guarant ee data integrity and reliability. 21.0.1 features of the cdr3 flash eeprom (uc3f) ? high density single tran sistor flash bit cell ? -40 to 125 c ambient temperature operating range ? -40 to 85 c on the suffix c device ? 2.5-v to 2.7-v v ddf operating range and 4.75-v to 5.25-v v flash operating range ? shadow information stored in sp ecial flash nvm shadow locations ? 512 kbytes using 64-kbyte blocks ? two 16-kbyte small blocks ? array block restriction cont rol for small and large blocks ? erase by array blocks ? array protection for program and erase operations ? array block assignment of supe rvisor or supervisor/user space ? array block assignment of da ta or instruction/data space ? internal 64-bit data path architecture ? page mode read ? retains two independent read page buffers ? read page size of 32 bytes (8 words). ? word (32-bit) programming ? embedded hardware program and erase algorithm ? uses internal oscillator to time program and erase pulses. pulses are timed independently of system clock frequency ? automatically perf orms margin reads ? external flash program or eras e enable inputs for block 0 or entire flash array (b0epee and epee) ? low power disable via an extern al signal or uc3f register bit ? censor mode for flash memory array access restri ction with a user bypass for unrestricted array access cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-4 freescale semiconductor 21.1 uc3f interface the uc3f module contains a memory in terface (mi) and an array core. the mi controls access of the array core and register bloc k in the uc3f module. the interface signals to the uc3f m odule consist of address i nputs, data inputs, data outputs, a simple set of control signals for read and write operations, a set of register selects, and a set of register outputs which are used by the biu. three require d supply pins power the module: v ddf , v ssf , and v flash . the uc3f module is a fully asynchronous module and does not require a clock input for operation. all required clocks are generated internally using an internal oscillator, exte rnal test clock input, or internal delay circuits. 21.1.1 external interface the uc3f eeprom module uses external pins to provide power supplies. th ese pins are listed in table 21-1 . . table 21-1. uc3f external interface signals mnemoni c i/o type description comments v ddf power pin uc3f power supply to reduce noise in the read path no other circuits should be connected to the uc3f v ddf supply pin.this v dd pin must be isolated from all other v dd pins inside the device. the specified voltage range during operation is 2.6 v 0.1 v. v ssf ground pin uc3f ground to reduce noise in the read path no other circuits should be connected to the uc3f v ssf supply. this v ss pin must be isolated from all other v ss pins inside the device. vflash power pin uc3f 5-v power supply vflash provides a 5-v supply to the uc3f module which is used for read, program, and erase operations. vflash must be in the range of 4.75 v to 5.25 v (5 v 5%) during operation. epee external program/eras e epee pin status the epee bit monitors the state of the external program/erase enable (epee) input. the uc3f module samples the epee input when ehv is asserted and holds that sampled state until ehv is negated. b0epee block 0 external program/eras e block 0 epee pin status the b0em bit monitors the stat e of block 0 epee, b0epee, input. the uc3f module samples the b0epee input when ehv is asserted and holds that sampled value until ehv is negated. if b0em = 1 when ehv is asserted, high voltage operations such as program or erase are enabled for either small block 0 or the lowest numbered block of the uc3 f array regardless of the state of epee. if b0em = 0 when ehv is asserted, high voltage operations are disabled for small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-5 21.2 programming model the uc3f eeprom module consists of a control regi ster block, an addressable shadow row implemented in flash, and an addressable main flash memory ar ray. the control registers are used to configure, program, erase and exercise the uc 3f shadow row and flash array. 21.2.1 uc3f eeprom control registers these supervisor-level control re gisters are used to control uc3f eeprom module operation. on reset, the registers are loaded with default reset informat ion. several bits of the uc 3f control registers are special flash nvm registers which retain their state when power is removed from the uc3f eeprom. these special nvm registers are identified in the i ndividual register field and control bit descriptions. 21.2.1.1 register addressing the uc3f module control registers, shown in table 21-2 , are selected with indi vidual register selects generated from the biu. as suc h, each flash module that is designe d using the uc3f eeprom module may uniquely define the addressing of the control register block. 21.2.1.2 uc3f eeprom configur ation register (uc3fmcr) the uc3f module configuration regist er is used to configure the opera tion and access restrictions of the uc3f array and shadow row. table 21-2. uc3f register programming model address register 0x2f c800 module configuration (uc3fmcr) 0x2f c804 extended module configuration (uc3fmcre) 0x2f c808 high voltage control (uc3fctl) 0x2f c80c reserved msb 01234 5 6789101112131415 field stop lock ? fic sie access censor supv hreset 01000 01 1 1 1 11111111 addr 0x2f c800 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field data protect hreset 0 0 0 0 0 0 0011111111 1 reset state determined by nvm registers. thes e bits will be set to 01 by the factory. figure 21-2. uc3f eeprom conf iguration register (uc3fmcr) cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-6 freescale semiconductor table 21-3. uc3fmcr bit descriptions bits name description 0 stop array stop control. writes to the stop bit have no effect while in program or erase operation (ses = 1). the stop bit is always readabl e whenever the registers are enabled. when stop = 1, the reset state of stop is 1 and the uc3f array is disabled; internal circuits are switched into a low power stat e. the stop bit may be used to implement low power standby modes or power management schemes. the uc3 fmcr remains readable and writable when stop = 1 so that the stop bit ma y be deasserted. attempts to program or erase the array while stop = 1 have no effect. ses cannot be set to 1 when stop = 1. when stop = 0, the reset state of stop is 0 and the uc3f array is enabled for accesses. all registers that were disabled with stop = 1 are now enabled. a stop recovery time of 1 s is required for biases in the uc3f array to reach t heir appropriate states to resume normal operation. operations to the uc3f array should be delayed for at least 1 s after clearing the stop bit. 0 = uc3f array is enabled 1 = uc3f array is disabled (low-power mode) 1lock 1 lock control. the default reset state of lock is 1. this enables writing of all fields in the flash registers. once the lock bit has been asserted (lock = 0) in normal operating mode, the write-lock can only be disabled again by a reset. when the device is in background debug mode and csc = 0, the lock bit may be written from a 0 to a 1. when the lock control bit is cleared to 0, the write-locked register bits: fic, supv, sbsupv[0:1], data, sbdata, protect, sbprotect, and sben[0:1] are locked. writes to these bits while lock = 0 will have no effect. lock can be written to 0 once after reset when uc3fctl[csc] = 0 to allow protection of the write-locked register bits after initialization. warning: if the lock protection mechanism is enabled (lock = 0) before protect and sbprotect are cleared, the device mu st use background debug mode to program or erase the uc3f eeprom. 2?reserved 3 fic force information censorship. the default rese t state of fic is normal censorship operation (fic = 0). the fic bit is wr ite protected by the lock bit and the uc3fctl[csc] bit. writes will have no effect if lock = 0 or csc = 1. once fic is set (fic = 1), it cannot be cleared except by a reset. the fic bit can be read whenever the registers are enabled. the fic bit is a censorship emulation mode used to aid in the development of custom techniques for controlling the access bit with out setting censor[0:1] to the information cens orship state. using fic to force information censorship allows testing of the hardware and software for setting access without setting censor[0:1] = 11 and ri sk permanently setting the device into an unusable information censorship state. 0 = normal uc3f censorship operation 1 = forces the uc3f into information censorship mode 4 sie shadow information enable. the default reset stat e of sie is 0. the sie bit is write protected in program operation (ses = 1 and pe = 0). the si e bit can be read whene ver the registers are enabled. when sie = 1, normal array accesses are disabled, and the two shadow information rows are enabled. array accesses are directed to the shado w row while sie = 1. when an array location is read in this mode, only the lower 6 address bits are used to select which 64 bytes of the 512-byte shadow row are read. the upper address bits are not used for shadow row decoding. the read page buffer address monitor is reset whenever sie is modified making the next uc3f array access an off page access. 0 = normal array access 1 = disables normal array access an d selects the shadow information rows cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-7 5 access enable uncensored access. a censored a ccess to the uc3f eeprom is any access where the device is in the censored mode. the default reset state is access is a 0 so t hat fic and censor[0:1] control the state of censorship to the uc3f eeprom array. all a ccesses to the uc3f eeprom array is allowed if access = 1. access can be read whenever the registers are enabled. access provides a method to bypass the uc3f eeprom module censorship. 0 censored - uc3f array access allowed only if the censorship state is no censorship 1 allows all uc3f array access 6:7 censor censor accesses. the censor[0:1] bits are im plemented using non-volatile register bits or cam cells. the reset state of censor[0:1] is user def ined by the contents stored in the nvm register bits. censor is not writable but the nvm register?s da ta can be set or cleared to the desired reset state. reading censor while setting or clearing with the high voltage applied (csc = 1 and hvs = 1) will return 0?s. 00 cleared censorship, uc3f array access allowed only if device is in uncensored mode 01 no censorship, all uc3f array accesses allowed 10 no censorship, all uc3f array accesses allowed 11 information censorship, uc3f array access allowed only if device is in uncensored mode 8:15 supv supervisor space. the supv bits are used to a ssign supervisor space restrictions for each block of the uc3f array. the index for the supv bit field is used to determine block assignment. for example, supv[0] is used for the supervisor spac e assignment of array block 0, while supv[4] is used for array block 4 supervisor space assignment. array block m is mapped into supervisor address space when supv[m] = 1, and only supervisor accesses are allowed to array block m. if su pv[m] = 0, then array block m is mapped into unrestricted address space which allows both supervisor and user accesses to array block m. the supv bits are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to uc3f array on a blockwise basis. the block addresses are decoded in the biu to determine which array block is selected, and the selected block?s supv bit is compared with the address space attributes to determine validity of an array access. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the supv bit corresponding to the a rray block containing that small block. this particular small block is controlled by the appropriate sbsupv bit while the remainder of that array block is controlled by its supv bit. 0 array block m is placed in unrestricted address space 1 array block m is placed in supervisor address space table 21-3. uc3fmcr bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-8 freescale semiconductor 21.2.1.3 uc3f eeprom extended c onfiguration regi ster (uc3fmcre) the uc3fmcre is an extended module configuration register used for conf iguring the small block functions. in addition, 16 bits of the uc3fmcre are used to provide a source for module identification. 16:23 data data space. the data bits are write protected by lock and csc. writes to data have no effect if lock = 0 or csc = 1. the data bits may be read whenever the registers are enabled. each array block of the uc3f eeprom may be m apped into data or data and instruction address space. when array block m is mapped into data address space (data[m] = 1), only data accesses will be allowed. when array block m is mapped into both data and instruction address space (data[m] = 0), both data and instruction accesses will be allowed. the data bits are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to uc3f array on a blockwise basis. the block addresses are decoded in the biu to determine which array block is selected, and the selected block?s data bit is compared with the address space attributes to determine validity of an array access. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the data bit corresponding to the array block containing that small block. this particular small block is controlled by the appropriate sbdata bit while the remainder of that array block is controlled by its data bit. 0 array block m is placed in both data and instruction address spaces 1 array block m is placed in data address space 24:31 protect block protect. each array block of the uc3f eeprom can be individually protected from program or erase operation. the contents of array block m are protected from progra m or erase by setting protect[m] = 1. the uc3f will perform all program and erase interlocks and complete the program or erase sequence, but the program and er ase voltages are not applied to locations within the protected array block(s), blocks whose corre sponding protect bit is set to 1. by setting protect[m] = 0, array block m is enabled for program and erase operation, and its contents may be altered by programming or erasing. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the protect bit corresponding to the array block containing that small block. this particular small block is controlled by the appropriate sbprotect bit while the remainder of that array block is controlled by its protect bit. 0 array block m is unprotected 1 array block m is protected 1 note that the lock bit is in a different bit location on t he mpc563 than in the mpc555. it was at bit 0 of cmfmcr. table 21-3. uc3fmcr bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-9 msb 0123456789101112131415 field sben sbsupv sbdata sbprotect ? biu hreset 0011001111 00_0000 addr 0x2f c804 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field memsiz blk map sblkl flashid 1 hreset 1011010 0_0000 _0000 1 the value of flashid could change to show a revision of the uc3f module. figure 21-3. uc3fmcre? uc3f eeprom extended configuration register table 21-4. uc3fmcre bit descriptions bits name description 0:1 sben small block enable. when sben[m]=0, the corres ponding small block m behaves logically as if the small block is still part of the larger host block. in addition, the small block protect bit (sbprotect[m]), the small block supervisor bit (sbsupv[m]), the small block data bit (sbdata[m]), and the small block block bit (sbblock[m]) corresponding to small block m have no effect. the corresponding small block is controlled by the same protect, supervisor, data, and block bits that control its host block. when sben[m] = 1, the corresponding sma ll block m can be programmed and erased independently of its host block. the correspondi ng small block protect bit, the small block supervisor bit, the small block data bit, an d the small block bit are enabled by sben. for example: when sben[0] = 0, small block 0 (16 kbytes) and the residual block (48 kbytes) contained in the host block of small block 0 are programmed and erased as if the two blocks are one large array block (64 kbytes). when sben[0 ] = 1, small block 0 and the residual block contained in the host block of small block 0 behave as two separate blocks, i.e. small block 0 and the residual block in small block 0?s host bloc k can be programmed and erased independently of each other. 0 small block m behaves as part of the host block 1 small block m functions independent of host block 2:3 sbsupv small block supervisor space. each sm all array block of the uc3f eeprom may be mapped into supervisor or unrestricted address space. when small array block m is mapped into supervisor address space, sbsupv[ m] = 1, only supervisor acce sses are allowed. when small block m is mapped to unrestricted address s pace, sbsupv[m] = 0, both supervisor and user accesses are allowed. if sben[m] = 0, the correspondi ng small block m is logically part of the host block and sbsupv[m] has no effect. instead, the corresponding supv[m] bit will be used to determine if the small block is mapped to supervisor or unrestricted address space. like the supv[0:7] bits, the sbsupv bits are not actually used in the uc3f eeprom module but are used by the biu to determine access restri ctions to the uc3f array. block addresses are decoded in the biu to determine which small array block is selected, and the selected small block?s sbsupv bit is compared with the address space attributes to determine validity of an array access. 0 small block m is placed in unrestricted address space 1 small block m is placed in supervisor address space cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-10 freescale semiconductor 4:5 sbdata small block data space. each small array block of the uc3f eeprom may be mapped into data or both data and instruction address space. w hen a small array block is mapped into data address space, sbdata[m] = 1, only data accesses will be allowed. when a small array block is mapped into both data and instruction addr ess space, sbdata[m] = 0, both data and instruction accesses will be allowed. if sben[m] = 0, the correspondi ng small block m is logically part of the host block and sbdata[m] has no effect. instead, the corresp onding data[m] bit will be used to determine if the small block is mapped to data or to both data and instruction address space. like the data bits, the sbdata bits are not ac tually used in the uc3f eeprom module but are used by the biu to determine access restrictions to the uc3f array. block addresses are decoded in the biu to determine which small array block is selected, and the selected small block?s sbdata bit is compared with the address sp ace attributes to determine validity of an array access. 0 small block m is placed in both data and instruction address spaces 1 small block m is placed in data address space 6:7 sbprotec t small block protect. each small block of the uc3f eeprom can be individually protected from program or erase operation. the uc3f will perform all program and erase interlocks and even complete the program or erase sequence, but the program and erase voltages are not applied to locations within the protected small block(s). 0 small block m is unprotected 1 small block m is protected 8:9 ? reserved 10:15 biu biu configuration bits. these register bits are reserved for biu functionality and are strictly outputs from the uc3f eeprom. 16:18 memsiz memory size. the memsiz fi eld is used to indicate the uc3f array size. the memsiz bits are read only and writes have no effect. 000 uc3f array is 64 kbytes 001 uc3f array is 128 kbytes 010 uc3f array is 192 kbytes 011 uc3f array is 256 kbytes 100 unused 101 uc3f array is 512 kbytes 110 unused 111 unused the flash module on the mpc563 is 512 kbytes. 19 blk block size. the blk bit is used to indicate the array block size used in the uc3f array. the blk bit is read only and writes have no effect. 0 array block size is 32 kbytes 1 block size is 64 kbytes note: all blocks are 64 kbytes (i.e. blk is always set) 20 map array address mapping. the map bit is used to indicate the uc3f array address mapping within a 2 n address space. the map bit is read only and writes have no effect. the map bit is more useful when the uc3f array is a non-2 n size. when map = 0, the uc3f array is mapped to the bottom (starting at address 0) of the 2 n space in which the array resides. for modules with 2 n array sizes, the map bit is always set to 0. when map = 1, the uc3f array is mapped to th e top (ending at address all $f?s) of the 2 n space in which the array resides. 0 uc3f array is mapped to bottom of 2 n address space 1 uc3f array is mapped to top of 2 n address space table 21-4. uc3fmcre bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-11 21.2.1.4 uc3f eeprom high voltag e control register (uc3fctl) the uc3f eeprom high voltage control register is us ed to control the program and erase operations of the uc3f eeprom module. 21:22 sblkl small block location code. there are three po ssible locations for the small blocks: 1) a small block may be placed in the lowest numbered host block and the highest numbered host blocks, 2) a small block may be placed in the lowest numbered host block and the second lowest numbered host block, and 3) a small block may be placed in the second highest numbered host block and the highest numbered host block. 00 unused 01 small blocks are part of the two highest numbered blocks of the uc3f array 10 small blocks are part of the two lowest numbered blocks of the uc3f array 11 small blocks are part of the lowest and highest numbered blocks of the uc3f array 23:31 flashid flash module identification code. the flashid value is assigned by freescale and used internally for tracking purposes. the flashid field is read only and writes have no effect. msb 0 1 2 3 4 56789101112131415 field hvs pegood pefi epee b0em ? sbblock hreset 000x 1 x 2 000_0000_0000 addr 0x2f c808 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field block ? csc ? hsus pe ses ehv hreset 0000_0000_0000_0000 1 value is set by the curr ent status of the epee pin. 2 value is set by the current status of the b0epee pin. figure 21-4. uc3f eeprom high volt age control register (uc3fctl) table 21-5. uc3fctl bit descriptions bits name description 0 hvs high voltage status. the hvs bit is for status only, and writes to hvs have no effect. during a program or erase operation, hvs is set (hvs = 1) to indicate when high voltage operations are in progress. the hvs bit will negate itself when the program or erase operation completes successfully, ehv negates during program or eras e to terminate the program/erase operation, hsus is asserted to suspend the program/erase op eration, resetting the module, or the internal hardware program/erase controller times out. 0 no program or erase of the uc3f array or shadow information or censor bits in progress 1 program or erase of the uc3f array or shadow information or censor bits in progress table 21-4. uc3fmcre bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-12 freescale semiconductor 1 pegood program/erase operation re sult. the pegood bit is for status only. at the completion of a program or erase operation using the embedded hardware algorithm, the hardware algorithm will change the state of the pegood bit to reflect whether or not the program or erase operation was successful. note: pegood will be set under the following conditions: no failure occurred no program or erase operation was requested (i.e., the flash was protected) the pegood bit is only valid after the hardware program/erase algorithm has cleared hvs. pegood is reset when either ehv is asserted or ses is cleared. see figure 21-5 for a timing diagram of when pegood is valid. 0 program or erase operation failed 1 program or erase operation was successful 2 pefi program/erase fail indicator. the pefi bit is a status qualifier for the pegood bit and is valid for the same times that pegood is valid. in the event of an erase failure which returns pegood = 0, the pefi bit provides diagnostic in formation for the cause of the erase failure. if pefi = 0, the erase failure occurred during the preprogramming step of t he erase operation. if pefi = 1, the erase failure occurred during th e actual erase or apde steps of the erase operation. in the event of a program failure which return s pegood = 0, the pefi bit indicates a program failure by reading as a 0. the pefi bit should never return a 1 for a program failure. note: the pefi bit is meaningful only while pegood is valid and pegood = 0. pefi is valid after hvs negates and prior to the assertion of ehv or negation of ses. 0 program operation failed if pegood = 0 1 erase operation failed if pegood = 0 3 epee epee pin status. the epee bit monitors the state of the external program/erase enable (epee) input. the uc3f module samples the epee input when ehv is asserted and holds that sampled state until ehv is negated. 0 high voltage operations are not possible 1 high voltage operations are possible 4 b0em block 0 epee pin status. the b0em bit monitors the state of the block 0 epee, b0epee, input. the uc3f module samples the b0 epee input when ehv is assert ed and holds that sampled value until ehv is negated. if b0em = 1 when ehv is asserted, high voltage operations such as program or erase are enabled for either small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. if b0em = 0 when ehv is asserted, high voltage operations are disabled for small block 0 or the lowest numbered block of the uc3f ar ray regardless of the state of epee. 0 high voltage operations are not possible for block 0 or lowest numbered block 1 high voltage operations are possible for block 0 or lowest numbered block. 5:13 ? reserved 14:15 sbblock small block program and erase select. th e sbblock bits are write- protected by the ses bit. sbblock selects the uc3f eeprom small array blocks for program and erase operation. when programming, only those blocks intended to be enabled for programming should have their corresponding block[m] or sbblock[m] bit set. 0 small block m is not selected for program or erase 1 small block m is selected for program or erase table 21-5. uc3fctl bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-13 16:23 block block program and erase select. the bloc k bits are write protected by the ses bit. block selects the uc3f eeprom array blocks for progra m and erase operation. all the blocks may be selected for program or erase operation at once. the uc3f eeprom configuration along with block determine which array blocks that may be programmed. the uc3f eeprom array blocks that are enabled to be programmed by the program operation are the blocks whose corresponding block bit is set to 1. for example, if array blocks 2 and 5 are enabled for programming, block[2] and block[5] must be set to 1 while block[0], block[1], bl ock[3], block[4], block[6], and block[7] are set to 0. the uc3f eeprom configuration along with bloc k determine the blocks that will be erased simultaneously. all array blocks whose corresponding block bits are set will be erased during the erase operation. for example, if block = 001 00111, then array blocks 2, 5, 6, and 7 get erased when an erase operation is performed. 0 array block m is not selected for program or erase 1 array block m is selected for program or erase 24 ? reserved 25 csc censor set or clear. the csc bit is write protected by the ses bit. csc configures the uc3f eeprom for setting or clearing censor. if csc = 1 then censor is configured for setting if pe = 0 or clearing if pe = 1. when the csc bit is set, the following bits in the uc3fmcr register are write-locked: lock , fic, access, supv, data, and protect. 0 configure for normal operation 1 configure to set or clear the censor bits 26:27 ? reserved 28 hsus program/erase suspend. setting the hsus bit during an embedded hardware algorithm program or erase operation will force the uc3f eeprom to suspend the current program or erase. the uc3f eeprom will maintain all information necessary to resume the suspended operation. array reads are possible while hsus = 1. however, array reads must be done to locations that are not being affected by the program/erase oper ation that is currently being suspended. the uc3f eeprom will not prevent read accesses to those locations. reads to those locations will result in unknown data. writes to the hsus bit only have effect while ehv = 1. the hsus bit is write locked by ehv = 0. 0 hardware program/erase behaves normally 1 any current hardware program/erase is suspended 29 pe program or erase select. the pe bit is write protected by the ses bit. pe configures the uc3f eeprom for programming or erasing. when pe = 0, the array is confi gured for programming and if ses = 1 the sie bit will be write locked. w hen pe = 1, the array is configured for erasing and ses will not write lock the sie bit. 0 configure for program operation 1 configure for erase operation table 21-5. uc3fctl bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-14 freescale semiconductor figure 21-5. pegood valid time 30 ses start-end program or erase sequence. the ses bit is write protected by the stop, hvs, and ehv bits. the ses bit is used to signal the start and end of a program or erase sequence. at the start of a program or er ase sequence, ses is set. this will lock stop, protect, sbprotect, block, sbblock, sben, csc, and pe. if pe = 0 and ses = 1, sie will be write locked. at this point, the uc3f eeprom is ready to receive either the programming writes or the erase interlock write. note: the erase interlock write is a write to any uc3f eeprom array location after ses is set and pe = 1. if pe = 0 and ses = 1, writes to the uc3f arra y are programming writes. the first programming write sets the address of the location to be prog rammed, and the data wri tten is captured into the program data latch for programming into the uc3f array. all progra mming writes after the first programming write update the program data latch but do not change the address to be programmed. at the end of the program or er ase operation, the ses bit must be cleared to return to normal operation and re lease the stop, protect, sbprotect, block, sbblock, csc, sben, and pe bits. 0 uc3f eeprom not configured fo r program or erase operation 1 configure uc3f eeprom for program or erase operation 31 ehv enable high voltage. ehv can be asserted only after the ses bit has been asserted and a valid programming write(s) or erase hardware interlock write has occurred. if an attempt is made to assert ehv when ses is negated, or if a valid programming write or erase hardware interlock write has not occurred since ses was asserted, ehv will remain negated. the external program or erase enable pin (epee) and ehv are used to control the application of the program or erase voltage to the uc3f ee prom module. high voltage operations to the uc3f eeprom array, special shadow locations or flash nvm registers can occur only if ehv = 1 and epee = 1. only after the correct hardware and software interlocks have been applied to the uc3f eeprom can ehv be set. once ehv is set, ses cannot be changed and a ttempts to read the array will not be acknowledged. clearing ehv during a program or erase operation will safely terminate the high voltage operation. if ehv is cleared while using the embedded hardware program/erase algorithm, the program/erase routine will abort the operation and exit normally. 0 program or erase pulse disabled 1 program or erase pulse enabled table 21-5. uc3fctl bit descriptions (continued) bits name description pegood valid time pegood valid time pegood hvs ehv ses cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-15 21.2.2 uc3f eeprom array addressing the uc3f array is divided into eight blocks, 64 kbytes in size, which may be independently erased. two blocks are host to a 16-kbyte small block. seventeen bits of address are used to decode locations in the uc3f ar ray. the read control logic in the uc3f eeprom module decodes the upper 14 bits of that address to determine if the desired data is currently stored in one of the two read page buffers. if the data is already present in one of the two read page buffers, a read operation is not completed to the uc3f array core, a nd 64 bits of data are transferred from the appropriate read page buffer to the biu. th is type of array read access is an on-page read. in the event that the read control logic determines that the desired data is not contained within one of the read page buffers, a read access to the uc3f array core is completed and 32 bytes of data are transferred from the array core. only the addressed 64 bits of data will be transferred to the biu. this type of array read access is an off-page read. the biu contains logic to implement the read page buffer update and replacement scheme to transfer the 32 bytes of data in to the appropriate read page buffer. if the read page update and replacement scheme contai ns a random access mode that does not update the read page buffers, the 32 bytes of data retrieved from th e uc3f array core will not be transf erred into either read page buffer. the biu is expected to contain pa ge update logic for controlling the updating of the read page buffers. write accesses to the uc3f array have no ef fect except during program and erase operation. 21.2.3 uc3f eeprom shadow row the uc3f eeprom module contains a special shadow row that is used to hold reset configuration data and user data. see figure 21-6 . the shadow row is accessed by setting uc3fmcr[si e] = 1 and performing normal array accesses. upon transitioning sie (a 1-to-0 or 0-to-1 transition), the read page match decode circuit is reset so that the next array access is an off-page access. the shadow row contains 512 bytes which are addres sed for read accesses using the low order row and read page addresses. the shadow row is implemented in the lowest numbered block of the ar ray. in the case of a uc3f array configuration which also has a small block in the lowe st numbered block of the a rray, the shadow row is contained in the small block. if sben[0] = 1 in this ar ray configuration, the shadow row is treated as part of small block 0. sbprotect[0] a nd sbblock[0] are used to contro l program and erase operation of the shadow row. if sben[0] = 0 in th is array configuration, the shadow ro w is treated as part of the host block. the corresponding protect and block bits are used to control program and erase operation of the shadow row. note a module cannot read its own shadow row. on the mpc563 the program accessing the flash shadow row must be executing from external memory or from internal sram. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-16 freescale semiconductor figure 21-6. shadow information 21.2.3.1 reset configuration word (uc3fcfig) the uc3f eeprom reset c onfiguration word is implemented in th e first word (addr[23:29] = 0x00) of the special shadow locations. the re set configuration word along with th e rest of the shadow information words is located in supervisor data address space. the purpose of the reset configur ation word is to provide the system with an alternative internal source for the reset configuration. note that with the exception of bit 20, the bits in the uc3fcfig are id entical to those in the usiu hard reset configuration word. the reset state of uc3fcfig is user programmable. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field earb ip bdrv bdis bps[0:1] ? d bgc[0:1] ? atwc ebdf[0:1] iws reset unchanged 1 addr 0x0 3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field prpm sc etre hc en_comp 2 exc_comp 2 ? oerc ? isb dme reset unchanged 1 1 programmed by the user. 2 available only on the mpc564 3 when uc3fmcr[sie] = 1, uc3fcfig is the first word of the shadow row. figure 21-7. hard reset configuration word (uc3fcfig) 0x00 0x1ff 0x10 0x0f reset configuration word general-use shadow information reserved for future applications 0x04 0x03 cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-17 table 21-6. rcw bit descriptions bits name description 0 earb external arbitration ? refer to section 9.5.7, ?arbitration phase ? for a detailed description of bus arbitration. the default value is that internal arbitration hardware is used. 0 internal arbitration is performed 1 external arbitration is assumed 1 ip initial interrupt prefix ? this bit defines the init ial value of the msr[ip] immediately after reset. the msr[ip] bit defines the interrupt table location. 0 msr[ip] = 0 after reset 1 msr[ip] = 1 after reset the default value is 0. see ta b l e 3 - 1 1 for more information. 2 bdrv bus pins drive strength ? this bit determines the bus pins? (address, data, and control) driving capability to be either full or reduced drive. the bu s default drive strength is fu ll; upon default, it also causes the clkout drive strength to be full. see ta b l e 6 - 7 for more information. bdrv controls the default state of co m[1] in the siumcr. 0 full drive 1 reduced drive 3 bdis boot disable ? if the bdis bit is set, then memory cont roller is not activated after reset. if it is cleared then the memory controller bank 0 is active immediatel y after reset such that it matches any addresses. if a write to the or0 register occurs after reset this bit definition is ignored. the default value is that the memory controller is enabled to control the boot with the cs 0 pin. see section 10.7, ?global (boot) chip-select operation ? for more information. 0 memory controller bank 0 is active and ma tches all addresses immediately after reset 1 memory controller is not activated after reset. 4:5 bps boot port size ? this field defines the port size of the boot device on reset (br0[ps]). if a write to the or0 register occurs after reset this field definition is ignored. see table 10-5 and table 10-8 for more information. 00 32-bit port (default) 01 8-bit port 10 16-bit port 11 reserved 6:8 ? reserved. these bits must not be high in the reset configuration word. 9:10 dbgc[0:1] debug pins configuration ? see section 6.2.2.1.1, ?siu module configuration register (siumcr) ? for this field definition. the default value is that these pins func tion as: vfls[0:1], bi , br , bg and bb . see ta b l e 6 - 8 . 11 ? reserved. 12 atwc address type write enable configuration ? the default value is that these pins function as we pins. 0we [0:3]/be [0:3]/at[0:3] functions as we [0:3]/be [0:3] 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] see ta b l e 6 - 7 . 13:14 ebdf external bus division factor ? this field defines the initial value of the external bus frequency. the default value is that clkout frequency is equal to that of the internal clock (no division). see ta bl e 8 - 9 . 15 iws interlock write select ? this bit determines which interlock write operation should be used during the clear censorship operation. iws always comes from the uc3fcfig, it will neve r use the external reset configuration word (rstconf=0) or the default internal rese t configuration word (rstconf=1 and hc =1). 0 interlock write is a write to any uc3f array location 1 interlock write is a write to the uc3fmcr register. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-18 freescale semiconductor during reset, the has configuration bit (hc ) and the usiu configure the uc3f eeprom module to provide uc3fcfig. if hc = 0 and the usiu requests internal configuration during reset the reset configuration word will be provided by uc3fcfig. the default reset state of the uc3fcf ig after an erase operation of th e uc3f module is no configuration word available (hc = 1). 16 prpm peripheral mode enable ? this bit determines if the chip is in peripheral mode. a detailed description is in ta b l e 6 - 1 3 . the default value is no peripheral mode enabled. 17:18 sc single chip select ? this field defines the mode of the mpc563. 00 extended chip, 32 bits data 01 extended chip, 16 bits data 10 single chip and show cycles (address) 11 single chip see ta b l e 6 - 1 0 . 19 etre exception table relocation enable ? this field defines whether the exception table relocation feature in the bbc is enabled or disabled. the default state for this field is disabled. for more details, see ta b l e 4 - 4 . 20 hc has configuration ? this bit determines if th e flash reset configuration word is valid. 0 the flash shadow row contains a valid reset configuration word 1 the flash shadow row does not contain a valid reset configuration word 21 en_comp 1 enable compression ? this bit enables the operation of the mpc564 with compressed code. see ta b l e 4 - 4 . 22 exc_comp 1 exception compression ? this bit determines t he operation of the mpc564 with exceptions. 0 indicates the exceptions are all non-compressed. see ta bl e 4 - 4 . 1 the mpc564 assumes that all the except ion routines are in compressed code. 23 ? reserved. this bit must be programm ed low in the reset configuration word. 24:25 oerc other exceptions relocation control ? these bits effect only if etre was enabled. relocation offset: 00 offset 0 01 offset 64 kbytes 10 offset 512 kbytes 11 offset to 0x003f e000 see ta b l e 4 - 2 . 26:27 ? reserved 28:30 isb internal space base select ? this field defines t he initial value of the isb field in the immr register. a detailed description is in ta bl e 6 - 1 2 . the default state is that the internal memory map is mapped to start at address 0x0000_0000. this bit must not be high in the reset configuration word. 31 dme dual mapping enable ? this bit determines whether dual mapping of the internal flash is enabled. for a detailed description refer to ta b l e 1 0 - 1 1 . the default state is that dual mapping is disabled. 0 dual mapping disabled 1 dual mapping enabled 1 this bit is available only on the mpc564. table 21-6. rcw bit descriptions (continued) bits name description cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-19 21.2.4 uc3f eeprom 512-kbyte array configuration figure 21-8 , the array configuration diagram, shows th e uc3f configuration for the mpc563 512-kbyte arrays. figure 21-8. 512-kbyte array configuration 21.3 uc3f operation the following sections describe the operation of the uc3f eeprom du ring various operational modes. the primary function of the uc3f ee prom module is to serve as elec trically erasable and programmable non-volatile memory for embedded a pplication in microcontrollers. 21.3.1 reset the device signals a reset to the uc3f eeprom by as serting the reset signal. a reset is the highest priority operation for the uc3f eeprom and terminat es all other operations. the uc3f eeprom module uses reset to initialize regist er bits to their default reset value. if the uc3f eepr om is in program or erase operation (uc3fctl[ehv] = 1 and uc3fctl[ses] = 1) and a reset is issued, the module will perform the needed interlocks to disable the high vol tage without damage to the high voltage circuits. reset terminates any other mode of operation and forces the uc3f eeprom module to a state ready to receive accesses. small block 0 block 4 16 kbytes small block 1 48 kbytes block 7 64 kbytes block 6 block 5 block 0 64 kbytes block 1 64 kbytes block 2 64 kbytes block 3 64 kbytes 16 kbytes* 48 kbytes 64 kbytes uc3f note: the shading indicates the shadow row. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-20 freescale semiconductor during power up and power down peri ods, it is assumed that the rese t signal is asserted to prevent accidental program/erase di sturb of the uc3f array. 21.3.2 register read and write operation the uc3f eeprom control registers are accessible fo r read or write operation at all times while the device is powered up and en abled except during reset. 21.3.3 array read operation the uc3f eeprom array is available for a read operation under most conditions while the device is powered up. reads of the array are not allowed in the following instances: ? during reset?when in information or cleared censorship with access = 0 ? while the uc3f eep rom is disabled?see section 21.3.10, ?disabled ,? for more information on disabling the uc3f eeprom ? while the uc3f eeprom is in stop mode?see section 21.3.9, ?stop operation ,? for more information on stop mode ? while high voltage is applied to the array during program and erase operation ?hvs = 1 or ehv = 1 and not suspended the address of an incoming read acces s is compared to the address for wh ich data is currently held in the read page buffers. if the data corres ponding to the read address is currently held in one of th e two read page buffers, the data is fetched from the appropriate read page buffer. a data fetch from a read page buffer is an on-page r ead operation section 21.3.3.1, ?array on -page read operation .? if the data is not contained in one of the read page buffers, 32 bytes of information is fetched from the uc3f ar ray, and the addressed data is driven onto the data bus. a data fetch fr om the uc3f array is an off-page read operation. note after setting/clearing uc3fctl[hsus], reset, programming writes, erase interlock write, setting ehv, clearing ses or setting/clea ring sie, the page buffers may not contain valid informat ion. the uc3f forces an off-page read before an on-page r ead can be accomplished to ensure data coherency. for information regarding how the tw o read page buffers in the uc3f eeprom are associated to array blocks, refer to section 21.2.2, ?uc3f eeprom array addressing .? the uc3f module is configured as a page mode me mory. the uc3f module uses an internal address comparator to monitor incoming addresses to determine if the addressed informati on is stored in a read page buffer. when the address comparat or determines that the requested in formation is not stored in a read page buffer, an array off-page read operation retrieves 32 bytes of data from the fl ash array and transfers the addressed data to the data bus. in the mpc563, the uc3f module cont ains two 32-byte read page buffers . in the module, one buffer is dedicated to the most recently acce ssed instruction fetches and the other read page buffer is dedicated to the most recently loaded data access. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-21 21.3.3.1 array on-page read operation an internal address comparator is used to determine if addressed info rmation is stored in a read page buffer. if the address of a re ad access matches data contained in a read page buffer, that addressed data is transferred from the read page buffer to the data bus . an off-page read access to transfer data from the flash array to the data bus is not performed in this case. 21.3.4 shadow row select read operation the normal array is accessed when th e sie register bit in the uc3fmc r = 0. when sie = 1, reads to the array access the shadow information row. 21.3.5 array program/erase interlock write operation the only valid writes to the uc3f array are program or erase interlock writes. in the case of program interlock writes, the addres s of the write determines the location to be programmed whil e the data written is transferred to the program data latches to be progr ammed into the array. addr ess and data written during an erase interlock write is a ?don?t care? and is not stored anywhere. 21.3.6 high voltage operations there are two fundamental high voltage operations, program and erase. program changes a uc3f array bitcell from a logic 1 state to a l ogic 0 state and is a selective opera tion performed on up to 32 bits at a time. erase changes a uc3f array bitcell from a logi c 0 state to a logic 1 state and is a bulk operation performed on one block or multip le blocks of the uc3f array. 21.3.6.1 overview of program/erase operation the embedded hardware program/era se algorithm relies on an intern al state machine to perform the program and erase sequences. the embe dded hardware algorithm uses an in ternal oscillator to control the high voltage pulse duration and hardware control l ogic. the embedded hardware algorithm is also responsible for performing all margin reads and a pplying high voltage pulses to ensure each bit is programmed or erased with sufficient margin. upon successful program or erase operation, the program/erase hardware control l ogic terminates the program or er ase operation with a pass status (pegood = 1). the program/e rase control logic will ti me out in the event that the maximum program or erase time is exceeded and retu rn a fail status (pegood = 0). 21.3.7 programming to modify the charge stored in an isolated element of the uc 3f bit from a logic 1 st ate to a logic 0 state, a programming operation is required. this programming operation applies the required voltages to change the charge state of the selected bits without changing the logic state of any other bits in the uc3f array. the program operation cannot change the logic 0 state to a logic 1 state; this transition must be done by the erase operation. programming uses a program data latch to store the data to be programmed and an address latch to store the word address to be programmed. the uc3f array may be pr ogrammed by byte (8 bits), half-word (16 bits), or word (32 bits). cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-22 freescale semiconductor blocks of the uc3f eeprom that are protected (protec t[m] = 1, sben[n] = 1 and sbprotect[n] = 1) will not be programme d. also, if epee = 0, no progr amming voltages will be a pplied to the array. if b0epee = 0, no programming voltages wi ll be applied to block 0 or sm all block 0 depending on the state of sben[0] and the configuration of the array. 21.3.7.1 program sequence the uc3f eeprom module requires a sequence of writes to the high volta ge control register (uc3fctl) and to the program data latch in order to enable the high voltage to the array or shadow information for program operation. the requi red hardware program sequence follows. 1. write protect[0:7] and sbpro tect[0:1] to disable protecti on on blocks to be programmed. 2. write block[0:7] and sbblock[0: 1] to select the array blocks to be programmed, ses = 1 and pe = 0 in the uc3fctl register. note block[0:7] and sbblock[0:1] in conjunction with sben[0:1] determine which blocks/s mall blocks in the array are enabled for programming operation. just becaus e a block or sbblock bit is enabled (set to 1), no programmi ng can occur in the corresponding block/small block unless the programm ing operation specifi cally targets an address location within that block/sm all block to program. if block or sbblock is not set to 1, no address lo cations in that corresponding block or small block ca n be programmed. 3. programming write ? a successful write to th e array location to be programmed. this write updates the program data latch with the informat ion to be programmed. in addition, the addressof the first programming write is latched in the uc3f memory interface block. all accesses of the array after the first write are to the same addr ess regardless of the address provided. thus the locations accessed after the firs t programming write are limited to the locati on to be programmed. the last write to the program da ta latch is saved for programming. note if a byte of the pr ogram data latch has not rece ived a programming write, no programming voltages will be applied to the corresponding byte in the array. once ehv has been set, writes to the program data latch are disabled until ehv is cleared to 0. 4. write ehv = 1 in the uc3fctl register. note the values of the epee and b0epee i nputs are latched with the assertion of ehv to determine the array protec tion state for the program operation. it is assumed that the epee and b0epee i nputs are setup prior to the assertion of ehv. 5. read the uc3fctl register until hvs = 0. 6. read the uc3fctl, confirm pegood = 1. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-23 7. write ehv = 0. warning writing ehv = 0 before hvs = 0 causes the current program sequence to abort. the location for which the pr ogram sequence was aborted may not have been programmed with sufficient margins. the block containing that location must be erased and reprogram med before that bl ock of the uc3f array may be used reliably. 8. if more information needs to be programmed go to step 3. 9. write ses = 0 in the uc3fctl register. figure 21-9. program state diagram table 21-7. program interlock state descriptions state mode next state transition requirement s1 normal operation: normal array reads and register accesses. the block protect information can be modified. s2 t2 write pe = 0, ses = 1. s1 t1 t2 t3 s2 s4 t4 s3 t5 t6 reset t7 s5 t8 t9 t10 cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-24 freescale semiconductor 21.3.7.2 program shadow information programming the shadow information uses the same procedure as progr amming the array except that sie must be set to a 1 prior to initiating the programming sequence. only the lowermost addresses are used to encode words that get programmed in the shadow row. the shadow information is physically located in s2 first program hardware interlock write: normal read operation still occurs. the array will accept programming writes. accesses to the registers are normal register accesses. a write to uc3fctl cannot change ehv at this time.if the write is to a register no data will be stored in the program data latch and the uc3f remains in state s2. s1 t1 write ses = 0 or a reset. s3 t3 hardware interloc k. a successful write to any uc3f array location. this programming write will latch the selected word of data into the program data latch and the address is latched to select the location that will be programmed. once a bit has been written then it remains in the program data latch until another write over-writes that data or a write of ses = 0. if the write is to a register no data will be stored in the program data latch and the uc3f remains in state s2. s3 expanded program hardware interlock operation: programming writes are accepted so that data may be programmed. these writes may be to any uc3f array location. the location to be programmed is determined from the address initially written to on the first program interlock write. the program data latch may be updated on any program interlock writes which occur in this state. accesses to the registers are normal register accesses. a write to uc3fctl can change ehv. if the write is to a register no data will be stored in the program data latch. s1 t6 write ses = 0 or a reset. s4 t4 write ehv = 1. s4 program operation: high voltage is applied to the array or shadow information to program the uc3f bit cells, and program margin reads are automatically performed by the internal program control logic. no further programming writes will be accepted. during programming, the array will not respond to any access. accesses to the registers are allowed. a write to uc3fctl can change ehv or hsus only. s1 t5 reset. s2 t7 write ehv = 0. s5 t8 write hsus = 1 or disable the uc3f module. s5 program suspend operation: the program operation is suspended to either read the array or disable the module. once hvs reads as a 0, the program operation is suspended. normal reads to the array can be performed if the module is enabled; read accesses to the location being programmed returns indeterminate data. s1 t10 reset. s4 t9 write hsus = 0 or re-enable the uc3f module. table 21-7. program interlock state descriptions (continued) state mode next state transition requirement cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-25 lowest numbered block and wi ll also be located in sm all block 0 if the lowest numbered block hosts a small block in the implemented configuration. 21.3.7.3 program suspend the program operation may be suspended to allow read accesses to the array. setting the hsus bit in the uc3fctl to a 1 while pe = 0, ehv = 1, and hvs = 1 forces the array in to a program suspend state. the deassertion of the hvs bit (hvs = 0) signifies that the program operation has been successfully suspended. the hvs bit should negate within 10 s of asserting the hsus bit. while in program suspend mode, nor mal read accesses may be performed to the uc3f array or shadow information words. reads to the array location target ed for program return indeterminate data since only a partial programming operation may have been performed. the program operation may be resumed by setting hsus = 0. note repeated suspending of a program oper ation to fetch a rray contents may extend the program operation. the inte rnal program hardware may only resume the program operation at predef ined steps of the internal program hardware sequence; inte rrupting the program ope ration on a high frequency basis may cause the internal program hardware to delay completion of the current step and delay advancement to th e next step of the internal program hardware sequence. frequent suspe nd/resume operations (more than approximately once per millisecond) may also cause program or erase timeouts, and are not recommended. 21.3.8 erasing to modify the charge stored in an isolated element of the uc 3f bit from a logic 0 st ate to a logic 1 state, an erase operation is require d. in the uc3f eeprom, eras e is a bulk operatblockion that affects the stored charge of all the isolated elements in an array bloc k. to make the uc3f modul e block-erasable, the array is divided into blocks that are physically isolated from each other. each of the ar ray blocks may be erased in isolation or in any combination. the uc3f array bl ock size is fixed for all blocks in the module at 64 kbytes and the module is comprised of eight blocks. two of these bloc ks may be further subdivided into two small blocks. array blocks of the uc3f eeprom that are protecte d (protect[m] = 1 or (sben[m] = 1 & sbprotect[m] = 1) ) will not be erased. also, if epee = 0 or b0epee = 0, no erase voltages will be applied to the array or the block co rresponding to block 0 or sm all block 0 if sben[0] = 1. the embedded program/erase algorithm first pre-programs all bits in blocks selected for erase prior to actually erasing the selected blocks. the array blocks selected for erase operation are determined by block[0:7], sbblock[0:1] in conjunction with sben[0:1], and the array configuration. if multiple bl ocks are selected for erase, the embedded erase hardware algorithm seri ally erases each array block until all of the selected blocks are erased. for instance, if block[0:7] = 0x78 and sben[0:1] = 0b00, then blocks 1, 2, 3, a nd 4 are selected for erase. the embedded erase hardwa re algorithm first erases block 1 and then erases block 2 followed cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-26 freescale semiconductor by blocks 3 and 4. the total er ase time for this example is the block erase time, t erase , multiplied by four since four blocks are eras ed. in addition, the preprogr amming time to program all locations in blocks 1, 2, 3, and 4 to a ?0? state need s to be considered when determining the total eras e time. the preprogramming time is dependent on the data al ready stored in the flash array before beginning the erase operation. 21.3.8.1 erase sequence the uc3f eeprom module requires a sequence of writes to the high volta ge control register (uc3fctl) and an erase interlock write in order to enable high voltage to the array and shadow information for erase operation. the required hardware algorithm erase sequence follows. 1. write protect[0:7] and sbpro tect[0:1] to disable protect fo r the blocks to be erased. 2. write block[0:7] and sbblock[0:1] to select th e blocks to be erased, pe = 1 and ses = 1 in the uc3fctl register. note block[0:7] and sbblock[0:1] in conjunction with sben[0:1] determine which blocks are selected for erase. blocks whose block bits or enabled small blocks w hose sbblock bits are set (equal to 1) get erased when an erase operation is performed. 3. execute an erase interlock wr ite to any uc3f array location. 4. write ehv = 1 in the uc3fctl register. note the values of the epee and b0epee i nputs are latched with the assertion of ehv to determine the array protecti on state for the erase operation. it is assumed that the epee and b0epee input s are setup prior to the assertion of ehv. 5. read the uc3fctl register until hvs = 0. warning writing ehv = 0 before hvs = 0 causes the current erase sequence to abort. all blocks being erased mu st go through another erase sequence before the uc3f eeprom can be used reliably. 6. read the uc3fctl register. confirm pegood =1. 7. write ehv = 0 in the uc3fctl register. 8. write ses =0 in the uc3fctl register. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-27 figure 21-10. erase state diagram table 21-8. erase interlock state descriptions state mode next state transition requirement s1 normal operation: normal array reads and register accesses. the block protect information can be modified. s2 t2 write pe = 1, ses = 1. s2 erase hardware interlock write: normal read operation still occurs. the uc3f will accept the erase hardware interlock write. this write may be to any uc3f array location. accesses to the register s are normal register accesses. a write to uc3fctl cannot set ehv at this time. a write to the register is not an erase hardware interlock write and the uc3f remains in state s2. s1 t1 write ses = 0 or a reset. s3 t3 hardware interlock a successful write to any uc3f array location is the erase interlock write. if the write is to a register the erase hardware interlock write has not been done and the uc3f remains in state s2. s3 high voltage write enable accesses to the register s are normal register accesses. a write to uc3fctl can change ses or ehv. s1 t6 write ses = 0 or a reset. s4 t4 write ehv = 1. s4 erase operation: high voltage is applied to the array blocks to erase the uc3f bit cells, and erase margin reads are automatically performed by the embedded erase control logic. during erase the array will not respond to any address. a ccesses to the registers are allowed. a write to uc3fctl can change ehv or hsus only. s1 t5 reset. s2 t7 write ehv = 0. s5 t8 write hsus = 1 or disable the uc3f module. s1 t1 t2 t3 s2 s4 t4 s3 t5 t6 reset s5 t8 t9 t10 t7 cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-28 freescale semiconductor 21.3.8.2 erasing shadow information words the shadow information words are erased with e ither the lowest numbered block or small block 0, depending on the array configur ation and the state of sb en[0]. if the lowest numbered block in the array does not host a small block, then th e shadow information words are er ased with the lowest numbered block. if the lowest numbered block hosts a small block, then the shadow information words may get erased with small block 0. if sben[0 ] = 0 for this array configuration, then the shadow information words get erased with the lowest numbered block. if sben[0 ] = 1 for this same array configuration, then the shadow information words get er ased with small block 0 only. 21.3.8.3 erase suspend the erase operation may be suspended to allow read accesses to the array. setting the hsus bit in the uc3fctl to a 1 while ehv=1 and hvs=1 forces the ar ray into an erase suspe nd state. the deassertion of the hvs bit (hvs = 0) signifies that the erase operation has been successfully suspended. the hvs bit should negate within 10 ms of asserting the hsus bit. while in erase suspend mode, normal read accesses may be performed to the uc3f array or shadow information words. reads to the array block or blocks targeted for erase return indeterminate data since only a partial erase operation has been performed. the erase operation may be re sumed by setting hsus = 0. note repeated suspending of an erase ope ration to fetch array contents may severely extend the erase operation. th e internal erase hardware may only resume the erase operation at predefined steps of the internal erase hardware sequence; interrupting the erase ope ration on a high frequency basis may cause the internal erase hardware to de lay completion of the current step and delay advancement to the ne xt step of the internal erase hardware sequence. 21.3.9 stop operation the uc3f eeprom goes into a low power operation, or stop operation, wh ile stop = 1. when the stop bit is set, only the control regi sters can be accessed on the uc3f eeprom module. the uc3f eeprom array may not be programmed, er ased or read while stop = 1. s5 erase suspend operation: the erase operation is suspended to either read the array or disable the module. once hvs reads as a 0, the erase operation is suspended. normal reads to the array can be performed if the module is enabled; read accesse s to locations in blocks being erased return indeterminate data. s1 t10 reset. s4 t9 write hsus = 0 or re-enable the uc3f module. table 21-8. erase interlock state descriptions (continued) state mode next state transition requirement cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-29 with stop = 1, the uc3f module enters a low power state by shutting down inte rnal timers and bias generators. a stop r ecovery time of 1 s is required when clearing the st op bit to exit stop operation. the biu should allow 1 s following the negation of the stop bit so that internal bias generators used by the array may recover to normal levels prio r to initiating any uc3f array accesses. note the uc3f cannot be stopped while the ar ray is being programmed or erased since the stop bit is write locked by ses = 1. 21.3.10 disabled the uc3f module can be disabled by clearing the flen bit in the immr register (see section 6.2.2, ?system configuration a nd protection registers ?). while disabled, the uc3f module is completely shut down. the register block and array ar e not accessible in this mode, and all circuits which draw any dc power are disabled to elim inate power consumption. in addition,the module can be disabled by setting the stop bit in the uc3fmcr register (see section 21.2.1.2, ?uc3f eeprom configuration register (uc3fmcr) ?). if the uc3f module is disabled wh ile programming or erasi ng, the hsus bit in the uc3fctl register is asserted (hsus = 1) to suspend the current progr am or erase operation. wh en the uc3f module is re-enabled, the suspended program or erase operation may be resume d by writing the hsus bit to a 0. note while there should be no ha rmful side effects result ing from disabling the uc3f module while in program or er ase operation, it is not recommended that program or erase operation be suspended in this manner. when disabled, the power used by th e uc3f is reduced to leakage leve ls; otherwise, the uc3f module is enabled for accesses. for example, r ecovering from a stop operation (stop = 1), there is a recovery time of 1 s for internal biases to reach to operating levels. 21.3.11 censored accesses an d non-censored accesses the uc3f eeprom has a censorship mechanism whic h provides for several censorship states. the censorship mechanism is used to increase restricti ons in accessing flash data. four bits in uc3fmcr are used to configure the uc3f censorship state. these bits are: ? access?enables a uc3f eeprom to bypass the censorship. ? fic?overrides censor[0:1] to force information censorship. ? censor[0:1]?determine the ce nsorship state of the uc3f. the device has two relevant modes used by the uc3f eepr om to select the type of censorship. the first mode, which is uncensored mode, provides no censorship. in uncensored mode the access and censor[0:1] bits are irrelevant . the second mode, censored mode, enables the uc3f eeprom to exercise censorship based on the state of access, fic, and censor [0:1]. the device will enter censored mode only if one of following events occurs: ? booting from external memory cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-30 freescale semiconductor ? operating in peripheral mode or upon any access by an external master ? operating in debug mode (bdm or nexus) ? booting from internal sram in censored mode, a uc3f eeprom may disallow accesse s to the array. if cens ored mode is entered by any means then the uc3f eeprom will exercise censorship according to table 21-9 . . while the device remains in the uncensored mode, a ccess may be set to allow the device to enter censored mode and still access the uc3f array. access may not be set while the device is in censored mode but may be cleared. table 21-9. censorship states access fic censor[0:1] description 0 0 11 information censorship, no uc3f array accesses allowed. 0 0 01 or 10 no censorship, uc3f array accesses allowed. 0 0 00 cleared censorship, no uc3f array accesses allowed. 0 1 xx emulated censorship, no uc3f array accesses allowed. 1 x xx no censorship, uc3f array accesses allowed. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-31 . the only way censor[0:1] can be changed is by se tting or clearing the flash nvm fuses. in the information censorship state, censor[0:1] must be cleared to the cleared censorship state before censor[0:1] can be put into the no censorship state. while clearing censor[0:1 ] the entire uc3f array is erased. thus the information st ored in the uc3f array is made invalid while clearing censor[0:1]. 21.3.11.1 setting a nd clearing censor the value of each bit in censor[0:1] is determin ed by the state of an nvm cam cell. the nvm cam cell is not writable but instead ma y be set or cleared. read ing censor[0:1] while se tting or clearing with the high voltage applied (csc = 1 and ehv = 1) will return 0?s. table 21-10. censorship modes and censorship status mode censored uncensored access 0 1 0 1 fic 0 1 010101 censor[0:1] 00 01 or 10 11 00, 01, or 10 11 00, 01, 10 or 11 uc3f eeprom status #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 indicates that the uc3f array cannot be accessed. 1. access cannot be changed. fic can be se t. uc3f array cannot be accessed. censor[0:1] can be set. ce nsor[0:1] cannot be cleared. 2. access cannot be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be set. censor[0:1] can be cleared. 3. access cannot be changed. fic can be se t. uc3f array cannot be accessed. censor[0:1] cannot be cleared unless iws = 1. 4. access cannot be changed. fic cannot be changed. uc3f array cannot be accessed. censor[0:1] can be set. censor[0:1] cannot be cleared unless iws = 1. 5. access cannot be changed. fic cannot be changed. uc3f array cannot be accessed. censor[0:1] cannot be cleared unless iws = 1. 6. access can be cleared. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 7. access can be cleared. fic cannot be changed. uc3f array can be accessed. censor[0:1] can be changed. 8. access can be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 9. access can be changed. fic cannot be changed. uc3f array can be accessed. censor[0:1] cannot be changed unless iws = 1. 10. access can be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 11. access can be changed. fic cannot be changed. uc3f array can be accessed. censor[0:1] can be changed. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-32 freescale semiconductor 21.3.11.2 setting censor the set operation changes the state in an nvm cam ce ll from a 0 to a 1. this set operation can be done without changing the contents of the uc3f array. th e required sequence to set one or both of the bits in censor[0:1] follows. 1. write csc = 1, pe = 0 and ses = 1 in the uc3fctl register 2. write a 1 to the censor bit(s) to be set 3. write ehv = 1 in the uc3fctl register 4. read the uc3fctl register until hvs = 0 5. read the uc3fctl register. confirm pegood = 1 6. write ehv = 0 in the uc3fctl register 7. write ses = 0 and csc = 0 21.3.11.3 clearing censor the clear operation changes the state of the censor[0:1 ] bits from a 1 to a 0 by erasing the cam cells. this clear operation can be done only while erasing the entire uc3f array a nd shadow information. the required sequence to clear censor follows. clear censor[0:1] 1. write protect[0:7] = 0x00 to enable the enti re array for erase. if sben[m] = 1, then sbprotect[m] must also be cleared to 0. 2. write block[0:7] = 0xff, csc = 1, pe = 1 and ses = 1 in the uc3fctl register. if sben[m] = 1, then sbblock[m] must also be set to 1. 3. do an erase interlock write. on the uc3f module, the erase interlock write ca n be performed in one of two ways, depending on the value of the uc3fcfig bit 15, iws. if iws = 0, a valid erase in terlock write is a write to any valid array location. this is subject to any censorship conditions that might apply. if iws = 1, a valid erase interlock write can be a wr ite to any valid array lo cation or a write to the uc3fcmcr register. when the iws = 1, the censor[0:1] bits can al ways be cleared in the uc3f flash eeprom status states #3, #4 and #5 from table 21-10 . the erase interlock write is only valid if all bloc ks of the array are selected for erase and not protected. block[0:7] and sbblock[0:1] se t to 1, as well as protect[0:7] and sbprotect[0:1] set to 0, are re quired for a valid erase interloc k write during the clear censor operation. 4. write ehv = 1 in the uc3fctl register. cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 21-33 note the values of the epee and b0epee i nputs are latched with the assertion of ehv to determine the array pr otection state for the clear censor operation. it is assumed that the ep ee and b0epee inputs are setup prior to the assertion of ehv. if epee and b0epee are not enabled for erase, the censor[0:1] bits may not be cleared. 5. read the uc3fctl register until hvs = 0. 6. read the uc3fctl register. confirm pegood = 1. 7. write ehv = 0 in the uc3fctl register. 8. write ses = 0 and csc = 0. 21.3.11.4 switching the uc3f eeprom censorship there are three states of censorship that censor [0:1] can select. these are?cleared censorship, no censorship (two states) a nd information censorship. these three stat es, state values, tr ansitions, and state of censorship are shown in figure 21-11 . figure 21-11. censorship states and transitions censor[0:1] = 10 censor[0:1] = 00 t1 t2 t3 no censorship cleared censorship information censorship censor[0:1] = 11 data data data data data data data unknown t3 t4 t3 censor[0:1] = 01 cdr3 flash (uc3f) eeprom mpc561/mpc563 reference manual, rev. 1.2 21-34 freescale semiconductor censor[0:1] transitions are listed as follows: 1. cleared censorship to no censorship, t1 set censor[0] or censor[1]. 2. no censorship to information censorship, t2 set censor[0] and censor[1]. 3. information censorship, no censorshi p or unknown to cleared censorship, t3 clear censor[0:1]. this is done only wh ile the entire uc3f array is erased. 4. cleared censorship to information censorship, t4 set both censor[0] and censor[1]. 21.3.12 background debug mode or freeze operation while in background debug mode, the uc3f shoul d respond normally to accesses except that lock is writable. see the lock bit in table 21-3 . mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-1 chapter 22 calram operation the calibration static random access memory (cal ram) module provides the mpc561/mpc563 with a general purpose memory that may be read from or wr itten to as either bytes, half-words, or words. in addition to this, a portion of th e calram, called the overlay regi on, can be used for calibration. calibration in this context is defined as overlayi ng portions of the u-bus fl ash with a portion of the calram array. during normal flash access, the risc central processi ng unit (rpcu) reads data from u-bus flash (through l-bus and l2u) as shown in figure 22-1 . during calibration acce ss, instead of flash providing the data, the overlay regions of calram provide the data to the rpcu. 22.1 features standard calram features are listed below: ? one-clock accesses ? two-cycle access for power savings ? byte, half-word (16-bits), or wo rd (32-bit) read/write accesses ? each 8-kbyte block has indivi dual protection control bits. ? low power standby operation for data retention special overlay features are: ? eight overlay regions; each can be programmed to be 4-, 16-, 32-, 64- , 128-, 256-, or 512-bytes long ? each overlay region size can be forced to 4 bytes long ? data driven from the calram module for overla y access has the same timing as the data that would have come from the u-bus flash ? overlay is for data read from the u-bus flash space and does not affect in struction fetches from the flash ? overlay block is naturally aligned ? for example, 128-byte block is 128-byte aligned ? normal access to overlaid portion of calram array can be made to generate an error (machine check) if so configured calram operation mpc561/mpc563 reference manual, rev. 1.2 22-2 freescale semiconductor 22.2 calram block diagram figure 22-1. system block diagram 22.3 calram memory map the mpc561/mpc563 chip internal memory map is shown in figure 22-2 . the calram module is divided into two sections. ? control section: ? includes all the register s in the calram module ? array sub-region: ? contains memory arrays thempc561/mpc563 contains one calram module ? a 32-kbyte me mory at address 0x3f 8000 ? 0x3f ffff as shown in figure 22-1 and figure 22-2 . in addition, the module is assigned 16 32-bi t register address spaces: 12 implemented and f our unimplemented registers. the 12 implemented registers are: one module configuration regist er (crammcr), one register reserved for factor y test, eight region base address (cram_rbax) registers, one overlay configuration re gister (cramovlcr), and one ownership trace register (calram_otr) to suppo rt a separate module called readi. refer to chapter 24, ?readi module .? e-bus rpcu l-bus u-bus + fp usiu flash 32-kbytes calram interface l2u interface uimb readi jtag 4-kbyte overlay 28-kbyte sram (non overlay) bbc calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-3 figure 22-2. mpc561/mpc563 memory map with calram address ranges when the normal device power (vdd) is off, portions of the calram array can be powered by separate power supply sources (iramstby) as shown in figure 22-3 , thus allowing the data to be retained. 0x38 0000 0x37 ffff 0x07 ffff 0x3f ffff 0x3f 8000 0x3f 6fff 0x00 0000 0x38 003f calram registers calram (32 kbytes) uc3f a flash 1 512 kbytes 1 note: available on mpc563 only calram operation mpc561/mpc563 reference manual, rev. 1.2 22-4 freescale semiconductor figure 22-3. standby power supply configuration for calram array 22.4 modes of operation the calram module has the fo llowing modes of operation: ?reset ? one-cycle ?two-cycle ? standby ?stop ?overlay 0x3f 8000 0x3f 9000 0x3f a000 0x3f b000 0x3f c000 0x3f d000 0x3f e000 0x3f f000 0x3f ffff ram 4k a8 ram 4k a7 ram 4k a6 ram 4k a5 ram 4k a4 ram 4k a3 ram 4k a2 ram 4k a1 calram iramstby (overlay portion of (non-overlay standby ram) standby ram) iramstby calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-5 22.4.1 reset reset configures the calram module and resets some of the bits in the calram registers to their default reset state. some register b its are unaffected by reset. see section section 22.5, ?programming model .? 22.4.2 one-cycle mode the calram registers and array may be accessed for reads or writes as byte, (aligned) half-word, or word. this mode is the default mode of operation and, as th e name suggests, the access time to the array and the internal registers for reads and writes is one cycle. thus the one-cycle mode is used for high performance although it consumes more power than the two cycle mode. 22.4.2.1 calram access/privilege violations each 8-kbyte calram array can be assigned read-only, data-only, or supervisor-only privilege if data relocate (dr) bit in the msr is set. all calram registers are assigned supe rvisor-only and data-only privilege. a privilege violati on causes an error. see section section 22.5.1, ?calram module configuration register (crammcr) .? an attempt to access any of the four unimplemented reserved registers (of the 16 register spaces) causes an error and returns 0?s on the data bus for a read access. if an error condition occurs due to privilege violation or an attempt to access uni mplemented portions of array or regi ster space, then the type of the error generated depends on whether the access generating the error was initiated by the rcpu core or by a non-rcpu bus master. if the error causing access was initiated by the rcpu core, a data storage interrupt (dsi) is generated. if the access was initiated by a non- rcpu bus master, a machine check exception is generated. also, a write access that generate s an error does not corrupt the data in an array or a register. similarly, a read access that generates an error does not drive the data on the l-bus from the array or the register, instead it driv es 0?s. also, aborted accesses mainta in data integrity. aborted writes do not corrupt data in register/array, and aborte d reads do not drive the requested data on l-bus. 22.4.3 two-cycle mode in this mode, the calram module ta kes two cycles to complete an acces s and consumes less power than in one-cycle mode. it follows the normal one-cyc le mode operation except that the accesses are completed one cycle later. this mode is selected by setting the 2cy bit in the crammcr register. 22.4.4 standby operation/keep-alive power the registers and contro l logic for the calram module are powered by vdd . the memory array is also supplied by vdd during normal operation; however, when the vdd is off, the calram array is backed up by a switched source (iramstby) th at is also known as standby power. calram operation mpc561/mpc563 reference manual, rev. 1.2 22-6 freescale semiconductor 22.4.5 stop operation the low power stop mode for this module is entere d by setting the disable bit (dis) in the crammcr register. reads from and writes to the array duri ng this mode will generate an error. when the disable bit (dis) is cleare d, the module returns to normal function. 22.4.6 overlay mode operation for a microcontroller used as a c ontroller for an engine (or other electromechanical device), various parameters stored in the flash memory may need to be changed in order to properly tune (calibrate) the engine. because flash memory ma y not be readily programmed duri ng normal operation of an embedded controller, portions of the calram array can be overlayed onto the u-bus flash memory. by allowing the calram module to overl ay portions of flash memory, paramete rs normally stored in the flash may be tweaked and changed w ith a development tool both during norm al operation and pr ior to programming a final, more precise version of the flash memory. the overlay is for read-onl y data and does not affect instruction fe tches from the flash. the data for any l-bus address which falls in the ove rlay region of the u-bus flash will be driven by the calram on the l-bus. the calram also indicates to the l2u to bloc k the data from the flash to be driven onto the l-bus. as far as the rcpu core is concerned, the timing of data coming from the calram appears to be the same as that from the flash. 22.4.6.1 overlay mode configuration each calram module contains eight overlay regions, each of which is 512 bytes long as shown in figure 22-4 . all overlay regions of a modul e are contiguous and each starts at the least significant address of the region and can in crement all the way up to 512 bytes as shown in figure 22-5 . as described in section section 22.5.2, ?calram region base address registers (cram_rbax) ?, cram_rbax registers allow the programming of the base addres ses rba[11:29] of the u-bus flash regions and the rgn_size[0:4] to be overlaid. note that each region can also be indi vidually disabled by writing 0000 to rgn_size[0:3]. if the programmed ba se address is not naturally aligne d with respect to the rgn_size field, the least significant bits of th e base address fields can be consider ed 0?s in order to make the starting address naturally aligned. in an rba register, rgn_size[0:3] ={0101} se lect the size to be 128 bytes, and even if cram_rbax [25:29] are not all 0?s, they will be considered as 0?s so that the address becomes 128-byte na turally aligned. calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-7 figure 22-4. calram array when programming the cram_rba x registers, the calram can be put in overla y mode by setting the ovl bit in the calram overlay configuration register (cramovl) as described in section section 22.5.3, ?calram overlay confi guration register (cram_ovlcr) .? for example, figure 22-5 shows that overlay regions 0, 4, and 5 have their entire regi on of 512 bytes mapped to regions in the flash as specified by cram_rba0, cram _rba4, and cram_rba5. ov erlay region 1 is partially mapped to a region in fl ash as specified by the cram_rba 1. if the region size of 256 bytes is selected for overlay region 1, for example, then the enable d portion of overlay regi on 1 will occupy address 0x3f f200 to 0x3f f2ff. the rest of overlay region 1 from 0x3f f300 to 0x3f f3ff is available for normal (non-overlay) array access. overlay regions 2, 3, 6, and 7 are disabled for overlay and hence can be used, in their entirety, for normal (non-overlay ) array accesses. 0x3f 8000 0x3f f000 0x3f f400 0x3f fc00 0x3f f800 0x3f ffff overlay 0 overlay 6 overlay 4 overlay 2 overlay 7 overlay 5 overlay 3 overlay 1 overlay region 4-kbyte non-overlay region 28 kbytes calram operation mpc561/mpc563 reference manual, rev. 1.2 22-8 freescale semiconductor figure 22-5. calram module overlay map of flash (clps = 0) figure 22-6 illustrates the address sp aces occupied by the two ca lram modules available in mpc561/mpc563. 0x3f 8000 0x3f f000 0x3f f400 0x3f fc00 0x3f f800 0x3f ffff overlay 6 overlay 2 overlay 7 overlay 3 overlay region 4-kbyte 0x07 ffff 0x00 0000 u-bus flash 1-mbyte overlay 4 overlay 5 uc3f flash 512 kbytes non-overlay region calram normal array access calram overlay access u-bus flash overlay 0 overlay 1 overlay 4 overlay 5 28 kbytes calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-9 figure 22-6. calram address map (clps = 0) if the clps bit in ovlcr regi ster is set, then each of the eight region sizes is forced to be 4 bytes long as shown in figure 22-7 , regardless of the value programmed in the rgn_size field. these 32 bytes occupy contiguous address space in calram, for example, from 0x3f ffe0 to 0x3f ffff. the remainder (4 kbytes ? 32 bytes) is not only available for normal array access but also c ontiguous with a 28-kbyte non-overlay array. 0x3f ffff 0x3f 8000 calram 0x3f f000 (28-kbyte 32-kbyte calram non-overlay area) calram 4-kbyte overlay area calram operation mpc561/mpc563 reference manual, rev. 1.2 22-10 freescale semiconductor figure 22-7. calram module overlay map of flash (clps = 1) figure 22-8 shows the overlay regions when the clps bit is set for calram in mpc561/mpc563. u-bus flash non-overlay region calram normal array access calram overlay access u-bus flash l-bus calram array 28 kbytes overlay 7 overlay 0 (4 kbytes ? 32 bytes) available for non-overlay use overlay of 32 bytes (each is 4 bytes long) overlay region 4-kbyte (each overlay is 4 bytes long and must be 4-byte aligned) calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-11 figure 22-8. calram address map (clps = 1) the values programmed in the rbax re gisters are unaffected by reset. see section 22.5.2, ?calram region base address re gisters (cram_rbax) ? for details. on reset, it is not necessary to reprogram the rabx registers. in such cases, the calibration m ode can be re-entered simp ly by setting the ovl bit. 22.4.6.2 priority of overlay regions when the address matches to more than one enabled portion of the overlay regi on, the effective region is the region with the highest priority. priority is de termined by the region number; the highest priority assigned to the lowest region number. the benefit from this priority featur e is that by storing the parameters in eight overl ay regions, it overlays all eight regions onto the same 512- byte flash region, and enables th e overlay feature. upon observing system performance with a set of parameters, the ne xt set of parameters can be selected by simply disabling the highest priority regi on. this ?observing and disabling the highest priority region? loop can continue until all regions are disabled. this allows moving from one set of para meters to another with 0x3f ffff 0x3f 8000 calram 0x3f f000 (28-kbyte 32-kbyte calram non-overlay area) 32-byte overlay area (0x3f ffe0 ? 0x3f ffff) 4 kbytes ? 32 bytes available for non- overlay use calram operation mpc561/mpc563 reference manual, rev. 1.2 22-12 freescale semiconductor minimal amount of reprogramming efforts. 22.4.6.3 normal (non-overlay) access to overlay regions if overlay is enabled and cramovlcr[derr] is set, then any normal l-bus array access that falls within any of the eight enabled overlay regions gene rates a machine-check excep tion; otherwise the access terminates normally without asserting data error. th e l-bus write accesses cause the data to be written regardless of whether the derr bit is set or not. for example, if overlay region 1 is programmed such that it is enabled and its region size is 256 bytes, then any l-bus access to address in th e range of 0x3f f200 ? 0x3f f2ff ge nerates machine check exception if the derr bit is set in cramovlcr register. the other portion of region 1 from 0x3f f300 to 0x3f f3ff can be used as normal (non-overlay) array. 22.4.6.4 calibration write cycle flow write accesses to the overlaid u- bus flash regions are ignored co mpletely by the calram module. 22.5 programming model the following section describes the calram programmer?s model. the calram has one register (crammcr) for configuring the calr am array and one regist er dedicated to fact ory test. in addition, there are eight 32-bit region ba se address registers for calibra tion purposes and a 32-bit overlay configuration register. the region base address regi sters hold the base address for the flash region and region size that need to be overlaid by the calram . the overlay configurati on register provides three bits (ovl, derr, and clsp) that are needed for overlay configuration. the calram ownership trace register (cram_otr) is provided to support a separate module called a readi module. access to all calram registers requires the bus ma ster to be in supervisor data mode. on a privilege violation, the register is not accessed and the access generates an error. table 22-2 shows the register addres s map for the mpc561/mpc563. table 22-1. priorities of overlay regions module/region number priority calram/region 0 highest calram/region 1 . calram/region 2 . calram/region 3 . calram/region 4 . calram/region 5 . calram/region 6 . calram/region 7 lowest calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-13 any unimplemented bits in calram registers return 0?s on a read and writes to these bits are ignored. 22.5.1 calram module config uration register (crammcr) the module configuration re gister (crammcr) contains bits that allow the ca lram to be configured for normal ram accesses. a brief description of each bit is provided in table 22-3 table 22-2. calram control registers address register 0x38 0000 crammcr 0x38 0004 for factory test 0x38 0008 cram_rba0 0x38 000c cram_rba1 0x38 0010 cram_rba2 0x38 0014 cram_rba3 0x38 0018 cram_rba4 0x38 001c cram_rba5 0x38 0020 cram_rba6 0x38 0024 cram_rba7 0x38 0028 cramovlcr 0x38 002c cramotr /readi_otr 0x38 0030 reserved 0x38 0034 reserved 0x38 0038 reserved 0x38 003c reserved msb 0123456789101112131415 field lck dis 2cy ? sreset 0000_0000_0000_0000 addr 0x38 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? r0 d0 s0 r1 d1 s1 r2 d2 s2 r3 d3 s3 sreset 0000_0000_0000_0000 figure 22-9. calram module conf iguration register (crammcr) calram operation mpc561/mpc563 reference manual, rev. 1.2 22-14 freescale semiconductor table 22-3. crammcr bit descriptions bits name description 0 lck write protection ? this bit is designed to lo ck out writes to the crammcr. while lck = 0 the register can be written repe atedly without restriction. if lck = 1, the register does not accept writes (i.e., the value of the register remains unchanged, but the cycle terminates normally.) in normal mode, this bit can only be set once and can only be cleared by reset. 0 writes to the crammcr are unrestricted 1 writes to the crammcr are ignored in freeze mode, only the lck bit may be written to zero if it was previously set. 1 dis array disable ? when set, this bit disables the calram array. in this mode, all reads and writes to the calr am array are ignored and a bus error is generated. the calram responds to re gister access while dis = 1. this is a low power mode for the module, since all internal functions will be disabled. the module can be re-enabled by writing the dis bit back to a zero. reset will also re-enable the module. 0 calram module array access is enabled 1 calram module array access is disabled 2 2cy two cycle mode ? when set, this bit puts the calram into a two cycle access mode operation for calram register accesses as well as array accesses. this mode provides power savings by using the first cycle to decode any l-bus access for an address match to where the array resides. 0 calram module in one-cycle operation 1 calram module in two-cycle operation 3:19 ? reserved 20 r0 read-only/read-write privilege ? if the data relo cate (dr) bit is set in machine status register (msr in rcpu) and r0 is also set, then write accesses are terminated with an error. if dr bit is 0, both reads and writes to the array block is allowed regardless of the value programmed in r0. this bit controls the highest 8-kbyte block (low est address) of calram in the associated array. likewise, r1, r2, and r3 control three other 8-kbyte blocks in the same manner. see ta b l e 2 2 - 4 for control bit address ranges. r0 = 0 and dr = 0 readable and writable (array 8-kbyte block) r0 = 0 and dr = 1 readable and writable (array 8-kbyte block) r0 = 1and dr = 0 readable and writable (array 8-kbyte block) r0 = 1 and dr = 1 read only (array 8-kbyte block) 21 d0 data-only/data-instruction privilege (data type assignment) ? if the data relocate (dr) bit is set in machine status register (msr) and d0 is also set, then any access attempting to fetch an instruction from the array block g enerates an error. if dr bit is 0, both data read and instruction fetch from the array block is allowed, regardless of the value programmed in d0. this bit controls the highest 8-kbyte block (lowest address) of calram in the associated array. likewise, d1, d2, and d3 control three other 8-kbyte blocks in the same manner. see ta b l e 2 2 - 4 for control bit address ranges. d0 = 0 and dr = 0 data and/or instruction (array 8-kbyte block) d0 = 0 and dr = 1 data and/or instruction (array 8-kbyte block) d0 = 1 and dr = 0 data and/or instruction (array 8-kbyte block) d0 = 1 and dr = 1 data only (array 8-kbyte block) calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-15 22.5.2 calram region base ad dress registers (cram_rbax) the region base address register de fines the base address of a region on the u-bus flash memory space that will be overlaid by a portion of the calram memory space a nd the region size. because eight such regions in the flash can be overlaid by the calram, eight such registers (x = 0, 1, 2, 7) are provided. the cram_rbax[11:29] provides the ba se address (starting a ddress) of the of the u-bus flash region to be overlaid and the cram_rbax[0:3] provi des size corresponding to the region. see table 22-6 for details. the rgn_size[0] is rese rved and should never be program med to a one, because the mpc563 has only 512 kbytes of flash, and cram_rba x[11] and cram_rbax[ 12] should never be programmed to a one. also, note that if cram_ovlcr[cl ps] is set, each of the eight sizes are forced 22 s0 supervisor-only/supervisor-user privilege (space assignment) ? if the data relocate (dr) bit is set in machine status register (msr) and s0 is also set, then any access to the array block by a user program generates an error. if dr bit is 0, both user and supervisor program can access the array block, regardless of the value programmed in s0. the calram array may be placed in supervisor or unrestricted space. this bit controls the highest 8-kbyte block (lowest address) of calram in the associated array. likewise, s1, s2, and s3 control other three blocks in the same manner. see ta bl e 2 2 - 4 for control bit address ranges. s0 = 0 and dr = 0 both user and supervisor access allowed (array 8-kbyte block) s0 = 0 and dr = 1 both user and supervisor access allowed (array 8-kbyte block) s0 = 1 and dr = 0 both user and supervisor access allowed (array 8-kbyte block) s0 = 1 and dr = 1 only supervisor access allowed (array 8-kbyte block) 23 r1 same as r0 except for address ranges shown on ta b l e 2 2 - 4 . 24 d1 same as d0 except for address ranges shown on ta b l e 2 2 - 4 . 25 s1 same as s0 except for address ranges shown on table 22-4 . 26 r2 same as r0 except for address ranges shown on ta b l e 2 2 - 4 . 27 d2 same as d0 except for address ranges shown on ta b l e 2 2 - 4 . 28 s2 same as s0 except for address ranges shown on table 22-4 . 29 r3 same as r0 except for address ranges shown on ta b l e 2 2 - 4 . 30 d3 same as d0 except for address ranges shown on ta b l e 2 2 - 4 . 31 s3 same as s0 except for address ranges shown on table 22-4 . table 22-4. crammcr privilege bit assignment for 8-kbyte array blocks bit selection address block (relative) r0, d0, and s0 0xxxxx 0000 ? 0xxxxx 1fff r1, d1, and s1 0xxxxx 2000 ? 0xxxxx 3fff r2, d2, and s2 0xxxxx 4000 ? 0xxxxx 5fff r3, d3, and s3 0xxxxx 6000 ? 0xxxxx 7fff table 22-3. crammcr bit descriptions (continued) bits name description calram operation mpc561/mpc563 reference manual, rev. 1.2 22-16 freescale semiconductor to be four bytes, regardless of the valu e programmed in the rgn_size[0:3] field. see section 22.5.3, ?calram overlay configurat ion register (cram_ovlcr) ? for details. the implemented bits of cram_rba x bits are unaffected by reset (har d reset). the diagram below shows one such register, cram_rba0, which provide s the base address of overlay region 0. msb 0123456789101112131415 field rgn_size ? rba sreset unaffected 0000_000 unaffected addr 0x38 0008?0x38 0024 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field rba ? sreset unaffected 00 figure 22-10. calram region base address register (cram_rbax) table 22-5. cram_rbax bit descriptions bits name description 0:3 rgn_siz e these bits define the size of the overlay region. see ta b l e 2 2 - 6 for sizes. 4:10 ? reserved 11:29 rba the region base address defines the star ting address of the memory to be overlayed. 1 1 the overlay match address will include isb in its comparison. the overlay can only be in the range of the isb internal space. 30:31 ? reserved table 22-6. rgn_size encoding rgn_size number of overlay bytes 0000 overlay block disabled 0001 overlay block is 4 bytes 0010 overlay block is 16 bytes 0011 overlay block is 32 bytes 0100 overlay block is 64 bytes 0101 overlay block is 128 bytes 0110 overlay block is 256 bytes 0111 overlay block is 512 bytes 1xxx reserved note: the overlay size of 8 bytes cannot be selected calram operation mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 22-17 22.5.3 calram overlay configur ation register (cram_ovlcr) 22.5.4 calram ownership trace register (cram_otr) this register is provided to support a separate module called readi. refer to chapter 24, ?readi module .? the reads from this register will return 0?s. note cram_otr is also defined as readi_otr. see section 24.6.1.1, ?user-mapped register (otr) .? msb 0 1 2 3456789101112131415 field ovl derr clps ? sreset 0000_0000_0000_0000 addr 0x38 0028 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? sreset 0000_0000_0000_0000 figure 22-11. calram overlay configuration register (cram_ovlcr) table 22-7. cramovlcr bit descriptions bits name description 0 ovl overlay enable ? when set, the calram overlay mode operation is enabled. in this mode calram allows eight programmable sections (four to 512 bytes) of the on-chip u-bus flash memory module to be overlaid by sections of the calram. 0 calram module overlay is disabled 1 calram module overlay is enabled 1 derr data error 0 calram module will not generate machine check exception due to normal l-bus array access to the enabled portion overlay region even if overlay is enabled 1 calram module will generate machine check exception due to normal l-bus array access to the enabled portion of overlay region even if overlay is enabled 2 clps collapse the total overlay region from 4 kbytes to 32 bytes; that is, the size is forced to be four bytes for each for the eight regions regardless of the values programmed in cram_rbax[0:3]; these bits are also referred to as rgn_size[0:3]. 0 overlay region of four kbytes; region size as specified by cram_rbax[0:3]. 1 overlay region of 32 bytes; each region size is four bytes long regardless of the values in cram_rbax[0:3]. 3:31 ? reserved calram operation mpc561/mpc563 reference manual, rev. 1.2 22-18 freescale semiconductor msb 0123456789101112131415 field ownership trace register sreset 0000_0000_0000_0000 addr 0x38 002c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ownership trace register sreset 0000_0000_0000_0000 figure 22-12. calram ownership trace register (cram_otr) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-1 chapter 23 development support the visibility and controllability requi rements of emulators an d bus analyzers are in opposition to the trend of modern microcomputers and micropr ocessors where many bus cycles are directed to internal resources and are not visible externally. in order to enhance the development tool visibility and controllability, some of the development support functions are implemented in silic on. these functions include program flow tracking, internal watchpoint, breakpoint generation, and em ulation while in debug mode. this section covers program flow tracking support, break point/watchpoint support, development system interface support (debug mode) and software monitor debugger support. these features allow efficiency in debugging systems based on the mpc561/mpc563. 23.1 program flow tracking the mechanism described in this section allows tr acking of program instruct ion flow with almost no performance degradation. the information provided may be compressed and captured externally and then parsed by a post-processing program usi ng the microarchitecture defined below. the program instructions flow is visible on the external bus when the mpc561/mpc563 is programmed to operate in serial mode and sh ow all fetch cycles on the external bus. this mode is selected by programming the isct_ser (instruction fetch show cy cle control) field in the i-bus support control register (ictrl), as shown in table 23-26 . in this mode, the processor is fetch serialized, and all internal fetch cycles appear on the extern al bus. processor performance is, therefore, much lower than when working in regular mode. these features, together with the fact that most fetch cycles are performed internally (e.g., from the i-cache), increase performance but make it very difficult to provide the real program trace. in order to reconstruct a program trace, the program code and the fo llowing additional information from the mcu are needed: ? a description of the last fetched instruction (stall , sequential, branch not ta ken, branch direct taken, branch indirect ta ken, exception taken) ? the addresses of the targets of al l indirect flow change. indirect flow changes include all branches using the link and count registers as the target address, all exceptions, and rfi, mtmsr and mtspr (to some registers) because they may cause a context switch. ? the number of instructions canceled each clock instructions are fetched sequentially until branches (direct or indirect) or exceptions appear in the program flow or some stall in execution causes the machine not to fetch the next addres s. instructions may be architecturally executed, or they may be canceled in some st age of the machine pipeline. development support mpc561/mpc563 reference manual, rev. 1.2 23-2 freescale semiconductor the following sections define how th is information is generated and how it should be used to reconstruct the program trace. the issue of da ta compression that could reduce th e amount of memory needed by the debug system is also mentioned. 23.1.1 program trace cycle to allow visibility of the events happening in the ma chine a few dedicated pins are used and a special bus cycle attribute, program trace cycle, is defined. the program trace cycle attribute is at tached to all fetch cycles resultin g from indirect flow changes. when program trace recording is needed, make sure these cycles are visible on the external bus. the vsync indication, when asserted, forces all fe tch cycles marked with the program trace cycle attribute to be visible on the external bus even if their data is f ound in one of the internal devices. to enable the external hardware to properly synchronize with the internal activ ity of the cpu, the assertion and negation of vsync forces the machin e to synchronize. the first fetch af ter this synchronization is marked as a program trace cycle and is visible on the external bus. for more information on the activity of the external hardware during program trace refer to section 23.1.4, ?external hardware .? in order to keep the pin count of the chip as low as possible, vsync is not implemented as one of the chip?s external pins. it is asserted and negated using the serial interface implemented in the development port. for more information on this interface refer to section 23.4, ?development port .? forcing the cpu to show all fetch cycles marked with the program trace cycle attr ibute can be done either by asserting the vsync pin (as mentioned above) or by programming the fetch show cycle bits in the instruction support control register, ic trl. for more information refer to section 23.1.5, ?instruction fetch show cycle control .? when the vsync indication is asserte d, all fetch cycles marked with th e program trace cy cle attribute are made visible on the external bus. these cycles can ge nerate regular bus cycles (address phase and data phase) when the instructions reside only in one of the external devices. or, they can generate address-only cycles when the instructions reside in one of the internal devices (internal memory, etc.). when vsync is asserted, some perf ormance degradation is expected due to the additional external bus cycles. however, since this performance degradation is e xpected to be very small, it is possible to program the machine to show all indi rect flow changes. in this way, the machine will always pe rform the additional external bus cycles and maintain exactly the same be havior both when vsync is asserted and when it is negated. for more information refer to section 23.6.10, ?l-bus support control register 2 .? the status pins are divided into two groups and one special case listed in the following sections. 23.1.1.1 instruction queue st atus pins ? vf [0:2] instruction queue status pins denote th e type of the last fetched instruct ion or how many in structions were flushed from the instruction queue. these status pins are used for both functions because queue flushes only happen in clocks that there is no fetch type information to be reported. possible instruction types are defined in table 23-1 . development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-3 table 23-2 shows vf[0:2] encodings for inst ruction queue flush information. 23.1.1.2 history buffer flushe s status pins? vfls [0:1] the history buffer flushes status pins denote how many instructions are flus hed from the history buffer this clock due to an exception. table 23-3 shows vfls encodings. table 23-1. vf pins instruction encodings vf[0:2] instruction type vf next clock will hold 000 none more instruction type information 001 sequential more instruction type information 010 branch (direct or indirect) not ta ken more instruction type information 011 vsync was asserted/negated and therefore the next instruction will be marked with the indirect change-of-flow attribute more instruction type information 100 exception taken ? the target will be marked with the indirect change-of-flow attribute queue flush information 1 1 unless next clock vf=111. see below. 101 branch indirect taken, rfi, mtmsr, isync and in some cases mtspr to cmpa-f, ictrl, ecr, or der ? the target will be marked with the indirect change-of-flow attribute 2 2 the sequential instructions listed here af fect the machine in a manner similar to indirect branch instructions. refer to section 23.1.3, ?sequential instru ctions marked as indirect branch .? queue flush information 1 110 branch direct taken queue flush information 1 111 branch (direct or indirect) not taken queue flush information 1 table 23-2. vf pins queue flush encodings vf[0:2] queue flush information 000 0 instructions flushed from instruction queue 001 1 instruction flushed from instruction queue 010 2 instructions flushed from instruction queue 011 3 instructions flushed from instruction queue 100 4 instructions flushed from instruction queue 101 5 instructions flushed from instruction queue 110 reserved 111 instruction type information 1 1 refer to table 23-1 . development support mpc561/mpc563 reference manual, rev. 1.2 23-4 freescale semiconductor 23.1.1.3 queue flush in formation special case there is one special case when although queue flush information is expected on the vf pins, (according to the last value on the vf pins), regular instruction type information is reported. the only instruction type information that can appear in this case is vf = 111, branch (direct or indi rect) not taken. since the maximum queue flushes possible is five, it is easy to identify this special case. 23.1.2 program trace when in debug mode when entering debug mode an interrupt/exception take n is reported on the vf pi ns, (vf = 100) and a cycle marked with the program trace cycle is made visible externally. when the cpu is in debug mode, the vf pins equa l ?000? and the vfls pins equal ?11?. for more information on debug mode refer to section 23.3, ?development system interface .? if vsync is asserted/negated while the cpu is in debug mode, this inform ation is reported as the first vf pins report when the cpu returns to regular mode. if vsync was not changed while in debug mode. the first vf pins report will be of an indirect branch taken (vf = 101), suitab le for the rfi instruction that is being issued. in both cases the first instruction fetc h after debug mode is marked with the program trace cycle attribute and therefore is visible externally. 23.1.3 sequential instructions marked as indirect branch there are cases when non-branch (se quential) instructions may effect the machine in a manner similar to indirect branch instructions. these instructions include rfi, mtmsr, isync and mtspr to cmpa-f, ictrl, ecr and der. these instructions are marked by the cpu as indirect branch instru ctions (vf = 101) and the following instruction address is marked with the same program trac e cycle attribute as if it were an indirect branch target. therefore, when one of these special instruct ions is detected in the cpu, the address of the following instruction is visible externally. in this way the reconstructing softwa re is able to evaluate correctly the effect of these instructions. 23.1.4 external hardware when program trace is needed, the external hardware needs to sample the status pins (vf and vfls) each clock cycle and the address of all cycles ma rked with the program trace cycle attribute. table 23-3. vfls pin encodings vfls[0:1] history buff er flush information 00 0 instructions flushed from history queue 01 1 instruction flushed from history queue 10 2 instructions flushed from history queue 11 used for debug mode indication (freeze). program trace external hardware should ignore this setting. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-5 program trace can be used in various ways. below ar e two examples of how pr ogram trace can be used: ? back trace ? back tr ace is useful when a reco rd of the program trace be fore some event occurred is needed. an example of such an event is some system failure. in case back trace is needed the external hardwa re should start sampling the status pins (vf and vfls) and the address of all cycles marked with the program trace cycl e attribute immediately when reset is negated. if show cycles is programme d out of reset to show all, all cycles marked with program trace cycle attri bute are visible on the external bus. vsync should be asserted sometime after reset and negated when the progr ammed event occurs. if no show is programmed for show cycles, make sure vsync is asserted before the instruct ion show cycles programming is changed from show all. note that in case the ti ming of the programmed even t is unknown it is possibl e to use cyclic buffers. after vsync is negated the trace buffer will c ontain the program flow trace of the program executed before the programmed event occurred. ? window trace ? window trace is us eful when a record of the program trace between two events is needed. in case window trac e is needed the vsync pin should be asserted between these two events. after the vsync pin is negated the trace buffer wi ll contain information describing the program trace of the program executed between the two events. 23.1.4.1 synchronizing the trace wi ndow to the cpu internal events the assertion/negation of vs ync is done using the seri al interface implemented in the development port. in order to synchronize the assertion/ negation of vsync to an internal ev ent of the cpu, it is possible to use the internal breakpoint s together with debug mode. this met hod is available only when debug mode is enabled. for more inform ation on debug mode refer to section 23.3, ?developme nt system interface .? the following is an exampl e of steps that enable s ynchronization of the trace window to the cpu internal events: 1. enter debug mode, either immediately out of reset or using the debug mode request 2. program the hardware to break on the event th at marks the start of the trace window using the control registers defined in section 23.2, ?watchpoints and breakpoints support ? 3. enable debug mode entry for the programmed brea kpoint in the debug enable register (der). see section 23.6.13, ?development port data register (dpdr) ?) 4. return to the regular code run (see section 23.3.1.6, ?exiting debug mode ?) 5. the hardware generates a breakpoint when the programmed event is dete cted and the machine enters debug mode (see section 23.3.1.2, ?entering debug mode ?) 6. program the hardware to break on the ev ent that marks the end of the trace window 7. assert vsync 8. return to the regular code run. the first report on the vf pins is a vsync (vf = 011). 9. the external hardware starts sampling the pr ogram trace information upon the report on the vf pins of vsync 10. the hardware generates a breakpoint when the programmed event is dete cted and the machine enters debug mode development support mpc561/mpc563 reference manual, rev. 1.2 23-6 freescale semiconductor 11. negate vsync 12. return to the regular code run (issue an rfi). the first report on the vf pins is a vsync (vf = 011) 13. the external hardware stops sampling the pr ogram trace information upon the report on the vf pins of vsync 23.1.4.2 detecting the tr ace window start address when using back trace, latching the va lue of the status pins (vf and vfls ), and the address of the cycles marked as program trace cycle, should start immediatel y after the negation of reset. the start address is the first address in the program trace cycle buffer. when using window trace, latching the value of the st atus pins (vf and vfls), and the address of the cycles marked as program trace cycle, should start i mmediately after the first vsync is reported on the vf pins. the start address of the trace window should be calcu lated according to first two vf pins reports. assuming that vf1 and vf2 are the tw o first vf pins reports and t1 a nd t2 are the two addresses of the first two cycles marked with the pr ogram trace cycle attribute that were latched in the trace buffer, use the following table to calculate the trace window start address. 23.1.4.3 detecting the asse rtion/negation of vsync since the vf pins are used for re porting both instruction type inform ation and queue flush information, the external hardware must take special care when trying to detect the asse rtion/negation of vsync. when vf = 011 it is a vsync assertion/negation report only if the previous vf pi ns value was one of the following values: 000, 001, or 010. 23.1.4.4 detecting the trace window end address the information on the status pins that describes the last fetched instruction a nd the last queue/history buffer flushes, changes every clock. cycles marked as program trace cycle are generated on the external bus only when possible (when the siu wins the arbitration over the exte rnal bus). therefore, there is some delay between the informati on reported on the status pins that a cycl e marked as program trace cycle will be performed on the external bus and the actual time th at this cycle can be detected on the external bus. when vsync is negated (through the serial interface of the developmen t port), the cpu delays the report of the of the assertion/negation of vsync on the vf pins (vf = 011) until all a ddresses marked with the program trace cycle attri bute were visible externally. therefore, the external hardware should stop table 23-4. detecting the trace buffer start point vf1 vf2 starting point description 011 vsync 001 sequential t1 vsync asserted followed by a sequential instruction. the start address is t1 011 vsync 110 branch direct taken t1 - 4 + offset (t1 - 4) vsync asserted followed by a taken direct branch. the start address is the target of the direct branch 011 vsync 101 branch indirect taken t2 vsync asserted followed by a taken indirect branch. the start address is the target of the indirect branch development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-7 sampling the value of the status pins (vf and vfls), and the address of the cycles marked as program trace cycle immediately after the vsync report on the vf pins. the last two instructions reported on the vf pins are not always valid. therefore at the last stage of the reconstruction software, the last two instructio ns should be ignored. 23.1.4.5 compress in order to store all the information generated on th e pins during program trace (five bits per clock + 30 bits per show cycle) a large memory buffer may be needed. however, since this information includes events that were canceled, compression can be very effe ctive. external hardware can be added to eliminate all canceled instructions and report only on branches (t aken and not taken), indir ect flow change, and the number of sequential instructions after the last flow change. 23.1.5 instruction fetch show cycle control instruction fetch show cycles are controlled by the bits in the ic trl and the state of vsync. the following table defines the level of fetch show cycles generated by th e cpu. for information on the fetch show cycles contro l bits refer to table 23-5 . note a cycle marked with the program trace cycle attribute is generated for any change in the vsync stat e (assertion or negation). 23.2 watchpoints and breakpoints support watchpoints, when detected, are reported to the ex ternal world on dedicated pi ns but do not change the timing and the flow of the machine. breakpoints, wh en detected, force the machine to branch to the appropriate exception handler. th e rcpu supports internal watchpoints, internal breakpoints, and external breakpoints. internal watchpoints are generated when a user pr ogrammable set of conditi ons are met. internal breakpoints can be programmed to be ge nerated either as an immediate resu lt of the assertion of one of the internal watchpoints, or after an internal watchpoi nt is asserted for a user programmable times. programming a certain internal watc hpoint to generate an internal breakpoint can be done either in table 23-5. fetch show cycles control vsync isctl instruction fetch show cycle control bits show cycles generated x 00 all fetch cycles x 01 all change of flow (direct & indirect) x 10 all indirect change of flow 0 11 no show cycles are performed 1 11 all indirect change of flow development support mpc561/mpc563 reference manual, rev. 1.2 23-8 freescale semiconductor software, by setting the corr esponding software trap enable bit, or on the fly using the serial interface implemented in the development port to set the corresponding development port trap enable bit. external breakpoints can be genera ted by any of the peripherals of the system, including those found on the mpc561/mpc563 or externally, and also by an exte rnal development system. peripherals found on the external bus use the serial interface of the deve lopment port to assert the external breakpoint. in the rcpu, as in other risc processors, saving/ restoring machine state on the stack during exception handling, is done mostly in software . when the software is in the middl e of saving/restoring machine state, msr[ri] is cleared. exceptions that occur and that are handled by the rcpu when msr[ri] is clear result in a non-restartable mach ine state. for more information refer to section 3.13.4, ?exceptions .? in general, breakpoints are recognized in the rcpu is only when msr[ri] is set, which guarantees machine restartability after a brea kpoint. in this working mode breakpoi nts are said to be masked. there are cases when it is desired to en able breakpoints even when msr[ri] is clear, with the possible risk of causing a non-restartable machine state. therefor e internal breakpoints ha ve also a programmable non-masked mode, and an external de velopment system can also choose to assert a non-maskable external breakpoint. watchpoints are not masked and ther efore always reported on the external pins, regardless of the value of msr[ri]. the counters, although count ing watchpoints, are part of the internal breakpoints logic and therefore are not decremented when the rcpu is oper ating in the masked mode and msr[ri] is clear. figure 23-1 shows the watchpoint and br eakpoint support of the rcpu. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-9 figure 23-1. watchpoint and breakpoint support in the cpu 23.2.1 internal watchp oints and breakpoints this section describes the intern al breakpoints and watchpoints suppor t of the rcpu. for information on external breakpoints support refer to section 23.3, ?development system interface .? internal breakpoint and watchpoint support is based on eight comparators comparing information on instruction and load/store cycles, two counters, and two and-or logic structures. the comparators perform compare on the instruction address (i-address), on the load/sto re address (l-address) and on the load/store data (l-data). the comparators are able to detect the following c onditions: equal, not equal, greater than, less than (greater than or equal and less than or equal ar e easily obtained from these four conditions; for more information refer to section 23.2.1.6, ?generating six compare types ?). using the and-or logic structures ?in range? and ?out of range? detections (on address a nd on data) are supported. using the counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined number of times. the l-data comparators can operate on fix point data of load or stor e. when operating on fix point data the l-data comparators are able to perform compare on bytes , half-words and words and can treat numbers either as signed or as unsigned values. breakpoint non-maskable breakpoint msr[ri] watchpoints to watchpoint maskable breakpoint development port trap enable bits counters (non-masked control bit) internal watchpoints logic development port lctrl2 msr software trap enable bits to cpu development system or external peripherals internal peripherals x x bit wise and bit wise or x x pins development support mpc561/mpc563 reference manual, rev. 1.2 23-10 freescale semiconductor the comparators generate match even ts. the match events enter the in struction and-or logic where the instruction watchpoints and breakpoint are generated. the instruction watchpoints, when asserted, may generate the instruction breakpoint . two of them may decrement one of the counters. if one of the instruction watchpoints expires in a counter that is counting, the in struction breakpoint is asserted. the instruction watchpoints and the load/store matc h events (address and data) enter the load/store and-or logic where the load/store watchpoints and breakpoint are generated. the load/store watchpoints, when asserted, may generate the load/s tore breakpoint or they may decrement one of the counters. when a counter that is counting one of the load/store watchpoints expires, the load/store breakpoint is asserted. watchpoints progress in the machin e and are reported on retirement. in ternal breakpoints progress in the machine until they reach the top of the history buf fer when the machine branches to the breakpoint exception routine. in order to enable the use of the br eakpoint features without adding restrictions on th e software, the address of the load/store cycle that generated the load/store breakpoint is not stored in the dar (data address register), like other load/store t ype exceptions. in case of a load/store breakpoint, the address of the load/store cycle that generated the breakpoint is stored in an implemen tation-dependent register called the bar (breakpoint address register). key features of internal watc hpoint and breakpoint support are: ? four i-address comparators (each supports equal, not equal, greater than, less than) ? two l-address comparators (each s upports equal, not equal, greater than, less than) including least significant bits masking according to the size of the bus cycle for the byte and half-word working modes. refer to section 23.2.1.2, ?byte and ha lf-word working modes .? ? two l-data comparators (each supports equal, not equal, greater than, less than) including byte, half-word and word operating modes and four byte ma sk bits for each comparator. can be used for fix point data. match is detected on ly on the valid part of the data bus (according to the cycle?s size and the two address least significant bits). ? no internal breakpoint/watchpoint matchi ng support for unaligned words and half-words ? the l-data comparators can be programmed to tr eat fix point numbers as signed values or as unsigned values ? combine comparator pairs to detect in and out of range conditions (inc luding either signed or unsigned values on the l-data) ? a programmable and-or logic st ructure between the four instru ction comparators results with five outputs, four instruction watc hpoints and one instruction breakpoint ? a programmable and-or logic st ructure between the four instru ction watchpoints and the four load/store comparators results with three outputs , two load/store watchpoints and one load/store breakpoint ? five watchpoint pins, three for the in struction and two for the load/store ? two dedicated 16-bit down counters. each can be programmed to count either an instruction watchpoint or an load/store wa tchpoint. only architecturally ex ecuted events are counted, (count up is performed in case of recovery). development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-11 ? on the fly trap enable programming of the different internal breakpo ints using the serial interface of the development port (refer to section 23.4, ?development port ?). software control is also available. ? watchpoints do not change the timing of the machine ? internal breakpoints and watchpoi nts are detected on the instru ction during instruction fetch ? internal breakpoints and watchpoint s are detected on the load/store during load/store bus cycles ? both instruction and load/store breakpoint s and watchpoints are handled and reported on retirement. breakpoints and watchpoints on recovere d instructions (as a result of exceptions, interrupts or miss prediction) are not reported and do not change the timing of the machine. ? instructions with instruction br eakpoints are not executed. the mach ine branches to the breakpoint exception routine before it executes the instruction. ? instructions with load/store breakpoints are ex ecuted. the machine branches to the breakpoint exception routine after it executes the instruction. the address of the access is placed in the bar (breakpoint address register). ? load/store multiple and string instru ctions with load/store breakpoints first finish execution (all of it) and then the machine branches to the breakpoint exception routine. ? load/store data compare is done on the load/sto re, after swap in store accesses and before swap in load accesses (as the data appears on the bus). ? internal breakpoints may opera te either in masked mode or in non-masked mode. ? both ?go to x? and ?continue? working mode s are supported for the instruction breakpoints. 23.2.1.1 restrictions there are cases when the same watc hpoint can be detected more than once during the exec ution of a single instruction, e.g. a load/store watchpoint is detected on more than one transfer wh en executing a load/store multiple/string or a load/store watchpoint is detect ed on more than one byte when working in byte mode. in all these cases only one watchpoint of the same type is reported for a sing le instruction. similarly, only one watchpoint of the sa me type can be counted in the counters for a single instruction. because watchpoint events are reported upon the retireme nt of the instruction that caused the event, and more than one instruction can retire from the machine in one clock, consequent even ts may be reported in the same clock. moreover the same event, if detected on more than one instruct ion (e.g., tight loops, range detection), in some cases wi ll be reported only once. note that the in ternal counters count correctly in these cases. do not put a breakpoint on an mtsp r instruction that accesses the ictr l register when ictrl[ifm] = 1 because this causes unpr edictable behavior. 23.2.1.2 byte and hal f-word working modes the cpu watchpoints and br eakpoints support enables de tection of matches on byte s and half-words even when accessed using a load/store instruction of larger data widths, for example when loading a table of bytes using a series of load word in structions. in order to use this feat ure, program the byte mask for each of the l-data comparators and to write the needed match value to the correct half-word of the data development support mpc561/mpc563 reference manual, rev. 1.2 23-12 freescale semiconductor comparator when working in half-word mode and to the correct bytes of the data comparator when working in byte mode. since bytes and half-words can be accessed using a larger data width instruction, it is impossible to predict the exact value of the l-address li nes when the requested byte/half-wor d is accessed, (e.g., if the matched byte is byte two of the word and it is accessed using a load word instruct ion), the l-address value will be of the word (byte zero). therefore, the cpu mask s the two least-significant bits of the l-address comparators whenever a word access is performed a nd the least-significant bit whenever a half-word access is performed. address range is supported only when al igned according to the access size. (see section 23.2.1.3, ?examples ?). 23.2.1.3 examples ? a fully supported scenario: ? looking for: data size: byte address: 0x00000003 data value: greater than 0x07 and less than 0x0c ? programming options: one l-address comparator = 0x00000003 and program for equal one l-data comparator = 0x00000007 and program for greater than one l-data comparator = 0x0000000c and program for less than both byte masks = 0xe both l-data comparators program to byte mode ? result: the event will be correctly detected regardless of the load/store instruction the compiler chooses for this access ? a fully supported scenario: ? looking for: data size: half-word address: greater than 0x00000000 and less than 0x0000000c data value: greater than 0x4e204e20 and less than 0x9c409c40 ? programming option: one l-address comparator = 0x00000000 and program for greater than one l-address comparator = 0x0000000c and program for less than one l-data comparator = 0x4e204e 20 and program for greater than one l-data comparator = 0x9c409c40 and program for less than both byte masks = 0x0 both l-data comparators program to half-word mode ? result: the event will be correctly detect ed as long as the compiler does not use a load/store instruction with data size of byte. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-13 ? a partially supported scenario: ? looking for: data size: half-word address: greater than or equal 0x00000002 and less than 0x0000000e data value: greater than 0x4e204e20 and less than 0x9c409c40 ? programming option: one l-address comparator = 0x00000001 and program for greater than one l-address comparator = 0x0000000e and program for less than one l-data comparator = 0x4e204e 20 and program for greater than one l-data comparator = 0x9c409c40 and program for less than both byte masks = 0x0 both l-data comparators program to half-word mode or to word mode ? result: the event will be correctly detected if the compil er chooses a load/store instruction with data size of half-word. if the compiler chooses load/s tore instructions with data size greater than half-word (word, multiple), there might be some false detections. these can be ignored only by the so ftware that handles the breakpoint s. the following figure illustrates this partially supported scenario. figure 23-2. partially supported watchpoint/breakpoint example 23.2.1.4 context dependent filter the cpu can be programmed to either recognize internal breakpoints onl y when the recove rable interrupt bit in the msr is set (masked mode) or it can be programmed to always rec ognize internal breakpoints (non-masked mode). when the cpu is programmed to rec ognize internal breakpoints only when msr[ri] = 1, it is possible to debug all parts of the code except when the machine status save/resto re registers (srr0 and srr1), dar (data address register) and dsisr (data storage interrupt status register ) are busy and, th erefore, msr[ri] = 0, (in the prologues and epilogues of interrupt/exception handlers). when the cpu is programmed always to recognize intern al breakpoints, it is possi ble to debug all parts of the code. however, if an internal breakpoint is recognized when msr[ri] = 0 (srr0 and srr1 are busy), the machine enters into a non-restartable state. for more information refer to section 3.13.4, ?exceptions .? possible false detect on these half -words when using word/multiple 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000c 0x0000_0010 development support mpc561/mpc563 reference manual, rev. 1.2 23-14 freescale semiconductor when working in the masked mode, all internal breakpoints detected when msr[ri] = 0 are lost. watchpoints detected in this case are not counted by the debug counters. watchpoints detect ed are always reported on the external pins, rega rdless of the value of msr[ri]. out of reset, the cpu is in ma sked mode. programming the cpu to be in non-masked mode is done by setting the brknomsk bit in th e lctrl2 register. refer to section 23.6.10, ?l-bus support control register 2 .? the brknomsk bit controls all internal breakpoints (i-b reakpoints and l-breakpoints). 23.2.1.5 ignore first match in order to facilitate th e debugger utilities ?continue? and ?go from x?, the ignore first match option is supported for instruction breakpoints. when an instruct ion breakpoint is first enabled (as a result of the first write to the instruction support control register or as a result of the assertion of msr[ri] when operating in the masked mode), the first instruction wi ll not cause an instruction breakpoint if the ignore first match (ifm) bit in the instru ction support control register (ict rl) is set (used for ?continue?). when the ifm bit is clear, every matched instructi on can cause an instruction breakpoint (used for ?go from x?). this bit is set by the so ftware and cleared by the hardware af ter the first instruction breakpoint match is ignored. load/store breakpoints and all count er generated breakpoints (i nstruction and load/store) are not affected by this mode. 23.2.1.6 generating six compare types using the four compare types mentione d above (equal, not equal, greater than, less than) it is possible to generate also two more compare types: grea ter than or equal and less than or equal. ? generating the greater than or equal compare t ype can be done by using th e greater than compare type and programming the comparator to the needed value minus 1. ? generating the less than or e qual compare type can be done by using the less than compare type and programming the comparator to the needed value plus 1. this method does not work for the following boundary cases: ? less than or equal of the largest unsigned number (1111...1) ? greater than or equal of the smallest unsigned number (0000...0) ? less than or equal of the maximum positive number when in signed mode (0111...1) ? greater than or equal of the maximum negative number when in signed mode (1000...) these boundary cases need no special support because th ey all mean ?always true? and can be programmed using the ignore option of the load/sto re watchpoint programming (refer to section 23.2, ?watchpoints and breakpoints support ?). 23.2.2 instruction support there are four instruction address comparators a,b,c, and d. each is 30 bits long, generating two output signals: equal and less than. th ese signals are used to ge nerate one of the followi ng four events: equal, not equal, greater than, less than. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-15 the instruction watchpoints and brea kpoint are generated using these events and according to user programming. note that using the or opt ion enables ?out of range? detect. figure 23-3. instruction support general structure table 23-6. instruction watchpoints programming options name description programming options iwp0 first instruction watchpoint comparator a comparators (a&b) iwp1 second instruction watchpoint comparator b comparator (a | b) iwp2 third instruction watchpoint comparator c comparators (c&d) iwp3 fourth instruction watchpoint comparator d comparator (c | d) comparator a eq lt compare type comparator b eq lt comparator c eq lt comparator d eq lt events generator and-or logic control bits a b (a & b) (a | b) c d (c & d) (c | d) i-watchpoint 0 i-watchpoint 1 i-breakpoint i-watchpoint 2 i-watchpoint 3 compare type logic compare type logic compare type logic compare type logic development support mpc561/mpc563 reference manual, rev. 1.2 23-16 freescale semiconductor 23.2.2.1 load/store support there are two load/store address comp arators e, and f. each compares the 32 address bits and the cycle?s attributes (read/write). the two l east-significant bits are masked (i gnored) whenever a word is accessed and the least-significant bit is masked whenever a ha lf-word is accessed. (for mo re information refer to section 23.2.1.2, ?byte and ha lf-word working modes ?). each comparator generates two output signals: equal and less than. these signals ar e used to generate one of the foll owing four events (one from each comparator): equal, not equa l, greater than, less than. there are two load/store data compar ators (comparators g,h) each is 32 bits wide and can be programmed to treat numbers either as signed va lues or as unsigned values. each da ta comparator operates as four independent byte comparators. each byte comparator has a mask bit and gene rates two output signals: equal and less than, if the mask bit is not set. th erefore, each 32 bit comparat or has eight output signals. these signals are used to generate the ?equal a nd less than? signals according to the compare size programmed (byte, half-word, word). when operating in byte mode all signals are significant, when operating in half-word mode only four signals from each 32 bit comparat or are significant . when operating in word mode only two signals from each 32 bit comparator are significant. from the new ?equal and less than ? signals and according to the co mpare type programmed one of the following four match events are gene rated: equal, not equal, greater th an, less than. therefore, from the two 32-bit comparators eight match indications are generated: gmatch[0:3], hmatch[0:3]. according to the lower bits of the address and the si ze of the cycle, only match indications that were detected on bytes that have valid in formation are validated, the rest ar e negated. note that if the cycle executed has a smaller size than the compare size (e .g., a byte access when the compare size is word or half-word) no match indi cation will be asserted. using the match indication signals four load/store data events ar e generated in the following way. the four load/store data events t ogether with the match events of th e load/store address comparators and the instruction watchpoints are used to generate the load/s tore watchpoints and brea kpoint according to the programming. table 23-7. load/store data events event name event function 1 1 ?&? denotes a logical and, ?|? denotes a logical or g (gmatch0 | gmatch1 | gmatch2 | gmatch3) h (hmatch0 | hmatch1 | hmatch2 | hmatch3) (g&h) ((gmatch0 & hmatch0) | (gma tch1 & hmatch1) | (gmatch2 & hmatch2) | (gmatch3 & hmatch3)) (g | h) ((gmatch0 | hmatch0) | (gmatch1 | hmatch1) | (gmatch2 | hmatch2) | (gmatch3 | hmatch3)) development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-17 note that when programming the load /store watchpoints to ignore l-addr events and l-data events, it does not reduce the load/store watchpoints detection logic to be instruction watchpoint detecti on logic since the instruction must be a load/store instruction for the load/store watc hpoint event to trigger. table 23-8. load/store watchpoints programming options name description instruction events programming options l-address events programming options l-data events programming options lwp0 first load/store watchpoint iwp0, iwp1, iwp2, iwp3, ignore instruction events comparator e comparator f comparators (e&f) comparators (e | f) ignore l-addr events comparator g comparator h comparators (g&h) comparators (g | h) ignore l-data events lwp1 second load/store watchpoint iwp0, iwp1, iwp2, iwp3, ignore instruction events comparator e comparator f comparators (e&f) comparators (e | f) ignore i-addr events comparator g comparator h comparators (g&h) comparators (g | h) ignore l-data events development support mpc561/mpc563 reference manual, rev. 1.2 23-18 freescale semiconductor figure 23-4. load/store support general structure comparator g byte 0 eq lt compare size compare type byte 1 eq lt byte 2 eq lt byte 3 eq lt eq lt eq lt eq lt eq lt comparator h byte 0 eq lt byte 1 eq lt byte 2 eq lt byte 3 eq lt eq lt eq lt eq lt eq lt add(30:31) data cycle size compare size valid 0 valid 1 valid 2 valid 3 g h (g&h) (g | h) instruction watchpoints l-watchpoint 0 l-watchpoint 1 l-breakpoint size logic compare byte qualifier logic events generator and-or logic size logic byte qualifier logic control bits e f (e&f) (e | f) comparator e type logic events generator lt eq comparator f type logic lt eq compare type type logic compare type logic byte mask byte mask development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-19 23.2.3 watchpoint counters there are two 16-bit watchpoint counters. each counter is able to c ount one of the instruction watchpoints or one of the load/store watchpoint s. both generate the correspondi ng breakpoint when they reach zero. when working in the masked mode, the counters do not count watchpoints det ected when msr[ri] = 0. see section 23.2.1.4, ?context dependent filter .? the counters value when counting watchpoints programmed on the actual instructions that alter the counters, are not predictable. re ading values from the counters wh en they are active, must be synchronized by inserting a sync instructi on before the actual read is performed. note when programmed to count instruction watchpoints, the last instruction which decrements the count er to zero is treated li ke any other instruction breakpoint in the sense that it is not executed and the machine branches to the breakpoint exception routine before it executes this instruction. as a side effect of this behavior, the valu e of the counter inside the breakpoint exception routine equals one and not zero as might be expected. when programmed to count load/store watchpoints, the last instruction which de crements the counter to zero is treated like any other load /store breakpoint in the sense that it is executed and the machine branches to the breakpoint exception routine after it executes this instruction. therefore, the value of the counter inside the breakpoint exception routin e equals zero. 23.2.3.1 trap enable programming the trap enable bits can be programmed by regular software (only if msr[ pr] = 0) using the mtspr instruction or ?on the fly? using the special develo pment port interface. for more information refer to section section 23.4.6.5, ?development port serial communications ? trap enable mode .? the value used by the breakpoints genera tion logic is the bit wise or of th e software trap enable bits, (the bits written using the mtspr) and the development port tr ap enable bits (the bits serially shifted using the development port). all bits, the software trap enable bits and the development port trap enable bits, can be read from ictrl and the lctrl2 using mfspr. for th e exact bits placement refer to section 23.6.10, ?l-bus support control register 2 ? and to section 23.6.10, ?l-bus suppor t control register 2 .? 23.3 development system interface when debugging an existing system, it is sometimes desirable to be able to do so without the need to insert any changes in the existing system. in some cases it is not desired, or even impossi ble, to add load to the lines connected to the existing sy stem. the development system inte rface of the cpu supports such a configuration. the development system interface of the cpu uses a dedicated serial port (the development port) and, therefore, does not need any of the regular system in terfaces. controlling the activity of the system from the development port is done when the cpu is in the debug mode. the developm ent port is a relatively development support mpc561/mpc563 reference manual, rev. 1.2 23-20 freescale semiconductor economical interface (three pins) that allows the development system to operate in a lower frequency than the frequency of the cpu. note that it is also possible to debug the cpu using monitor debugger software, for more information refer to section 23.5, ?software monitor debugger support .? debug mode is a state where the cpu fetches all instructions from the de velopment port. in addition, when in debug mode, data can be read from the developmen t port and written to the development port. this allows memory and registers to be read and modified by a development tool (emu lator) connected to the development port. for protection purposes, two possible working modes ar e defined: debug mode enable and debug mode disable. these working modes are selected only during reset. for more information refer to section 23.3.1.1, ?debug mode enable vs. debug mode disable .? the user can work in debug mode starting from reset or the cpu can be programmed to enter debug mode as a result of a predefined list of events. these even ts include all possible inte rrupts and exceptions in the cpu system, including the internal breakpoints, togeth er with two levels of development port requests (masked and non-masked) and one peripheral breakpoint request that can be gene rated by any one of the peripherals of the system (including internal and exte rnal modules). each event can be programmed either to be treated as a regular in terrupt that causes the machine to branch to its interrupt vector, or to be treated as a special interrupt that causes debug mode entry. when in debug mode an rfi instruction will return the machine to its regular work mode. the debugger tool should issue an isync instruction to the debug port prior to any other instructions when the cpu enters debug mode after running code. the relationship between the de bug mode logic to the rest of the cpu chip is shown in figure 23-5 . development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-21 figure 23-5. functional diagram of mpc561/mpc563 debug mode support the development port provides a full duplex serial interface for communications between the internal development support logic of the cpu and an exte rnal development tool. the development port can operate in two working modes: the tr ap enable mode and the debug mode. the trap enable mode is used in order to shift into the cpu internal development support logic the following control signals: 1. instruction trap enable bits, used for on the fly programming of the instruction breakpoint 2. load/store trap enable bits, used for on the fly programming of the load/store breakpoint 3. non-maskable breakpoint, used to a ssert the non-maskable external breakpoint 4. maskable breakpoint, used to asse rt the maskable external breakpoint 5. vsync, used to assert and negate vsync in debug mode the development port controls also the debug mode features of the cpu. for more information section 23.4, ?development port .? 23.3.1 debug mode support the debug mode of the cpu provides the developmen t system with the following basic functions: 32 development port development port 32 35 ecr der cpu core dpir dpdr 9 tecr control logic shift register dsdo vfls, frz ext bus bkpt, te, vsync dsdi dsck development support logic port internal bus siu/ ebi development support mpc561/mpc563 reference manual, rev. 1.2 23-22 freescale semiconductor ? gives an ability to control the execution of th e processor and maintain control on it under all circumstances. the development por t is able to force the cpu to enter to the debug mode even when external interrupts are disabled. ? it is possible to enter debug mode immediatel y out of reset thus allo wing debugging of a rom-less system. ? it is possible to selectively define, using an enable register, the events that will cause the machine to enter into the debug mode. ? when in debug mode detect th e reason upon which the machine en tered debug mode by reading a cause register. ? entering into the debug mode in all regular cases is restartable in the sense that it is possible to continue to run the regular program from the location where it entered the debug mode. ? when in debug mode all instructio ns are fetched from the developm ent port but load /store accesses are performed on the r eal system memory. ? data register of the developmen t port is accessed using mtspr and mfspr instructions via special load/store cycles. (this feature together with the last one enables easy memory dump & load). ? upon entering debug mode, the processor gets into the privileged state (msr[pr] = 0). this allows execution of any instruction, and access to any storage location. ? an or signal of all exception cause register (e cr) bits (ecr_or) enables the development port to detect pending events while already in de bug mode. an example is the ability of the development port to detect a debug mode access to a non existing memory space. figure 23-6 illustrates the debug mode l ogic implemented in the cpu. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-23 figure 23-6. debug mode logic 23.3.1.1 debug mode enable vs. debug mode disable for protection purposes two possible working modes ar e defined: debug mode enable and debug mode disable. these working modes are selected only during reset. see figure 23-7 for bdm mode selection. debug mode is enabled by asserting dsck during reset. 5 event valid event set reset ecr_or freeze rfi decoder exception cause register debug enable register q (ecr) (der) debug mode enable internal debug mode signal 0 32 0 32 ... . ... . ... . ... . ... . ... . ... . ... . ... . ... . ... . ... . development support mpc561/mpc563 reference manual, rev. 1.2 23-24 freescale semiconductor the debug interface is enabled by: ? holding jcomp/rsti low while hreset is asserted and then entering bdm (dsck=high at hreset negation) or ? configuring readi to be disabled (evti =high at rsti negation) and then entering bdm (dsck=high at hreset negation) the state of this pin is sampled thr ee clocks before the negation of sreset . note because sreset negation is done by an exte rnal pull up resistor any reference here to sreset negation time refers to the time the mpc561/mpc563 releases sreset . if the actual negati on is slow due to a large resistor, set up time for the debug port signals should be set accordingly. if the dsck pin is sampled negated, debug mode is disabled until a subsequent re set when the dsck pin is sampled in the asserted state. when debug mode is disabled the inte rnal watchpoint/breakpoint hardware will still be operational and may be used by a software monitor program for debugging purposes. when debug mode is disabled, all deve lopment support registers (see list in table 23-14 ) are accessible to the supervisor code (msr[pr] = 0) and can be used by a monitor debugger software. however, the processor never enters debug mode and, therefore, the exception cause register (ecr) and the debug enable register (der) are used onl y for asserting and negating the freez e signal. for more information on the software monitor debugger support refer to section 23.5, ?software m onitor debugger support .? when debug mode is enabled, all development support re gisters are accessi ble only when the cpu is in debug mode. therefore, even superv isor code that may be still under debug cannot prevent the cpu from entering debug mode. the development system has full control of all development s upport features of the cpu through the development port. refer to table 23-16 . figure 23-7. bdm mode selection 23.3.1.2 entering debug mode entering debug mode can be a result of a number of ev ents. all events have a pr ogrammable enable bit to selectively decide which events result in debug m ode entry and which in re gular interrupt handling. poreset jcomp/rsti configuration (low) readi disabled/ bdm can be enabled/entered jtag disabled t development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-25 entering debug mode is also possible immediately out of reset, thus allowing the debugging of even a rom-less system. using this featur e is possible by special programmi ng of the development port during reset. if the dsck pi n continues to be asse rted following sreset negation (after enabling debug mode) the processor will take a breakpoint exception and go directly to debug m ode instead of fetching the reset vector. to avoid entering debug mode following reset, the dsck pin must be negated no later than seven clock cycles after sreset negates. in this case, the processor wi ll jump to the reset vector and begin normal execution. when entering debug mode immediately after reset, bi t 31 (development port interrupt) of the exception cause register (ecr) is set. figure 23-8. debug mode reset configuration when debug mode is disabled all events result in regular interrupt handling. the internal freeze signal is asserted whenever an enabled event occurs, regardless if debug mode is enabled or disabled. the internal fr eeze signal is connected to all releva nt internal modules. these modules can be programmed to stop all opera tions in response to the asserti on of the freeze signal. refer to section 23.5.1, ?freeze indication .? the freeze indication is negated when exiting debug mode. refer to section 23.3.1.6, ?exiting debug mode .? the following list contains the events that can cause the cpu to enter debug mode. each event results in debug mode entry if debug m ode is enabled and the corresponding enable bit is set. the reset values of the enable bits allow, in most cases, the use of the debug mode features without the need to program the debug enable register (der). for more information refer to section 23.6.13, ?development port data register (dpdr) .? ? nmi exception as a result of the assertion of the irq0_b pin. for more information refer to section 3.15.4.1, ?system reset exception and nmi (0x0100) .? ? check stop. refer to section 23.3.1.3, ?check stop state and debug mode ,? for more information. ? machine check exception ? implementation specific in struction protection error dsck out clk sreset dsck asserts high while sreset is asserted to enab le debug mode operation. 012345891011121314151617 dsck asserts high following sreset negation to enable debug mode immediately. development support mpc561/mpc563 reference manual, rev. 1.2 23-26 freescale semiconductor ? implementation specific data protection error ? external interrupt, reco gnized when msr[ee] = 1 ? alignment interrupt ? program interrupt ? floating point unavailable exception ? floating point assist exception ? decrementer exception, recognized when msr[ee] = 1 ? system call exception ? trace, asserted when in si ngle trace mode or when in br anch trace mode (refer to section 3.15.4.11, ?trace exception (0x0d00) ?) ? implementation dependent so ftware emulation exception ? instruction breakpoint, when breakpoints are mask ed (brknomsk bit in the lctrl2 is clear) recognized only when msr[ri] = 1, when breakpoi nts are not masked (brknomsk bit in the lctrl2 is set) always recognized ? load/store breakpoint, when brea kpoints are masked (brknomsk bit in the lctrl2 is cleared) recognized only when msr[ri] = 1, when breakpoi nts are not masked (brknomsk bit in the lctrl2 is set) always recognized ? peripherals breakpoint, from the development port, internal and external modules. are recognized only when msr[ri] = 1. ? development port non-maskable interrupt, as a resu lt of a debug station request. useful in some catastrophic events like an endl ess loop when msr[ri] = 0. as a result of this event the machine may enter a non-restartable state, for more information refer to section 3.13.4, ?exceptions .? the processor enters into the debug mode state when at least one of the bits in the exception cause register (ecr) is set, the corresponding bit in the debug enable register (der ) is enabled and debug mode is enabled. when debug mode is enable d and an enabled event occurs, the processor waits unt il its pipeline is empty and then starts fetching th e next instructions from the deve lopment port. for information on the exact value of machine status save/resto re registers (srr0 and srr1) refer to section 3.13.4, ?exceptions .? when the processor is in debug mode the freeze indication is asserted t hus allowing any peripheral that is programmed to do so to stop. the fact that the cpu is in debug mode is al so broadcast to the external world using the value b11 on the vfls pins. note the freeze signal can be as serted by software when debug mode is disabled. the development port should read the value of the excep tion cause register (ecr) in order to get the cause of the debug mode entry. reading the excepti on cause register (ecr) clears all its bits. 23.3.1.3 check stop state and debug mode the cpu enters the check stop state if the machin e check interrupt is disabled (msr[me] = 0) and a machine check interrupt is detected. however, if a machine check interrupt is detected when msr[me] = development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-27 0, debug mode is enabled and the chec k stop enable bit in the debug enable register (der) is set, the cpu enters debug mode rather then the check stop state. the different actions taken by the cpu when a machin e check interrupt is detected are shown in the following table. 23.3.1.4 saving machine state upon entering debug mode if entering debug mode was as a re sult of any load/store type ex ception, and therefore the dar (data address register) and dsisr (data stor age interrupt status register) have some significant value, these two registers must be saved before any other operation is performe d. failing to save thes e registers may result in loss of their value in case of another load/sto re type exception inside the development software. since exceptions are treated differen tly when in debug mode (refer to section 23.3.1.5, ?running in debug mode ?), there is no need to save machine status save /restore zero register (srr0) and machine status save/restore one register (srr1). 23.3.1.5 running in debug mode when running in debug mode all fetch cycles access the development port regardless of the actual address of the cycle. all load/store cycles access the real memory sy stem according to the cycl e?s address. the data register of the development port is mapped as a special control register therefore it is ac cessed using mtspr and mfspr instructions via specia l load/store cycles (refer to section 23.6.13, ?development port data register (dpdr) ?). exceptions are treated differen tly when running in debug mode. when already in debug mode, upon recognition of an exception, the exception cause regist er (ecr) is updated according to the event that caused the exception, a special erro r indication (ecr_or) is asserted fo r one clock cycle to report to the development port that an exception occurred and execution continues in debug mode without any change in srr0 and srr1. ecr_or is asserted before the ne xt fetch occurs to allow the development system to detect the excepting instruction. table 23-9. check stop state and debug mode msr[me] debug mode enable chstpe 1 1 check stop enable bit in the debug enable register (der) mcie 2 2 machine check interrupt enable bit in the debug enable register (der) action performed by the cpu when detecting a machine check interrupt exception cause register (ecr) value 0 0 x x enter the check stop state 0x2000_0000 1 0 x x branch to the machine check interrupt 0x1000_0000 0 1 0 x enter the check stop state 0x2000_0000 0 1 1 x enter debug mode 0x2000_0000 1 1 x 0 branch to the machine check interrupt 0x1000_0000 1 1 x 1 enter debug mode 0x1000_0000 development support mpc561/mpc563 reference manual, rev. 1.2 23-28 freescale semiconductor not all exceptions are recognized when in debug m ode. breakpoints and watchpoints are not generated by the hardware when in debug mode (regardless of the value of msr[ri]). upon entering debug mode msr[ee] is cleared by the hardware thus forcing the hardware to ignore ex ternal and decrementer interrupts. warning setting the msr[ee] bit while in debu g mode, (by the debug software), is strictly forbidden. the reason for this rest riction is that the external interrupt event is a level signal, and since the cpu only reports exceptions while in debug mode but do not tr eat them, the cpu does not clear the msr[ee] bit and, therefore, this even t, if enabled, is recognized again every clock cycle. when the ecr_or signal is asserted the development station should invest igate the exception cause register (ecr) in order to find out the event that caused the exception. since the values in srr0 and srr1 do not change if an exception is recognized while already in debug mode, they only change once when entering debug m ode, saving them when entering debug mode is not necessary. 23.3.1.6 exiting debug mode the rfi instruction is used to exit from debug mode in order to return to the normal processor operation and to negate the freeze indication. the development system may monitor the freeze status to make sure the mpc561/mpc563 is out of debug mode. it is the responsibility of the soft ware to read the exception cause register (ecr) before performing the rfi. failing to do so will force th e cpu to immediately re-enter to debug mode and to re-assert the freeze indication in cas e an asserted bit in the interrupt cause register (ecr) has a corresponding enable bit se t in the debug enable register (der). 23.4 development port the development port provides a full duplex serial interface for communications between the internal development support logic including debug mode and an external development tool. the relationship of the development support logic to the rest of the cpu chip is shown in figure 23-5 . the development port support logic is shown as a separate block for clarity. it is implemented as part of the siu module. 23.4.1 development port pins the following development por t pin functions are provided: 1. development serial clock (dsck) 2. development serial data in (dsdi) 3. development serial data out (dsdo) development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-29 23.4.2 development serial clock the development serial clock (dsck) is used to sh ift data into and out of the development port shift register. at the same time, the new most significa nt bit of the shift register is presented at the dsdo pin. in all further discussions references to the dsck si gnal imply the internal sync hronized value of the clock. the dsck input must be driven either high or low at all times and not allowed to float. a typical target environment would pull this input low with a resistor. the clock may be implemented as a free running clock or as gated clock. as discussed in section section 23.4.6.5, ?development port serial communications ? trap enable mode ? and section section 23.4.6.8, ?development port se rial communications ? debug mode ,? the shifting of data is controlled by ready and star t signals so the clock does not need to be gated with the serial transmissions. the dsck pin is also used at reset to enable de bug mode and immediately foll owing reset to optionally cause immediate entry into debug mode following reset. 23.4.3 development serial data in data to be transferred into the development port shift register is presented at the development serial data in (dsdi) pin by external logic. to be sure that the correct value is used internally. when driven asynchronous (synchronous) with the system clock, the data presented to dsdi must be stable a setup time before the rising edge of dsck (clkout) and a hold time after the rising edge of dsck (clkout). the dsdi pin is also used at reset to control the overall chip configuration mode and to determine the development port clock mode. see section section 23.4.6.4, ?development port serial communications ? clock mode selection ? for more information. 23.4.4 development serial data out the debug mode logic shifts data out of the developm ent port shift register usi ng the development serial data out (dsdo) pin. all transitions on dsdo ar e synchronous with dsck or clkout depending on the clock mode. data will be valid a setup time before the rising edge of the clock and will remain valid a hold time after the rising edge of the clock. refer to table 23-12 for dsdo data meaning. 23.4.5 freeze signal the freeze indication means that the processor is in debug mode (i.e., nor mal processor exec ution of user code is frozen). on the mpc561/mpc563, the freeze st ate can be indicated by th ree different pins. the frz signal is generated synchronously with the system clock. this indication ma y be used to halt any off-chip device while in debug mode as well as a handshake means between the debug tool and the debug port. the internal freeze status can also be monitored through status in the data shifted out of the debug port. development support mpc561/mpc563 reference manual, rev. 1.2 23-30 freescale semiconductor 23.4.5.1 sgpio6/frz/ptr signal the sgpioc6/frz/ptr signal powers up as the ptr function and its function is controlled by the gpc bits in the siumcr. 23.4.5.2 iwp[0:1]/vfls[0:1] signals the power-up state of iwp[0:1]/vfls[0:1] is controlled by setting the siumcr[dbgc]; see table 6-8 . they can also be set via the reset configuration word (see section 7.5.2, ?hard reset configuration word (rcw) ?). the frz state is indicated by the value 0b11 on the vfls[0:1] signals. 23.4.5.3 vfls[0:1]/mp io32b[3:4] signals the vfls[0:1]/mpio32b[3:4] signals power up as the mpio32b[3:4] f unction and their function can be changed via the vfls bit in the mios14tpcr regist er. the frz state is indicated by the value 0b11 on the vfls[0:1] signals. 23.4.6 development port registers the development port consists logically of the thre e registers: development port instruction register (dpir), development port data register (dpdr), and trap enable control register (tecr). these registers are physically implemented as two re gisters, development port shift re gister and trap enable control register. the development port shif t register acts as both the dpir and dpdr depending on the operation being performed. it is also used as a temporary holding re gister for data to be st ored into the tecr. these registers are discussed below in more detail. 23.4.6.1 development port shift register the development port shift register is a 35-bit shift register. instructions an d data are shifted into it serially from dsdi using dsck (or clkout dependi ng on the debug port clock mode, refer to section 23.4.6.4, ?development port serial communi cations ? clock mode selection ? ) as the shift clock. these instructions or data are then transf erred in parallel to the cpu, the tr ap enable control register (tecr). when the processor enters debug mode it fetches inst ructions from the dpir which causes an access to the development port shift register. thes e instructions are serially loaded into the shift register from dsdi using dsck (or clkout) as the shif t clock. in a similar way, data is transferred to the cpu by moving it into the shift register which th e processor reads as the result of executing a ?move from special purpose register dpdr? instruction. data is also parallel-loaded into the devel opment port shift register from the cpu by executing a ?move to sp ecial purpose register dpdr? instruction. it is then shifted out serially to dsdo using dsck (or clkout) as the shift clock. 23.4.6.2 trap enable control register the trap enable control register is a 9-bit register th at is loaded from the deve lopment port shift register. the contents of the control register are used to drive the six trap enable signals , the two breakpoint signals, and the vsync signal to the cpu. the ?transfer data to trap enable control regi ster? commands will cause the appropriate bits to be transferred to the control register. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-31 the trap enable control register is not accessed by the cpu, but instea d supplies signals to the cpu. the trap enable bits, vsync bit, and the breakpoint bits of this register are loaded from the development port shift register as the result of trap enable mode tran smissions. the trap enable b its are reflected in ictrl and lctrl2 special registers. see section 23.6.10, ?l-bus support control register 2 ? and section 23.6.10, ?l-bus suppor t control register 2 .? 23.4.6.3 development port registers decode the development port shift register is selected when the cpu accesses dpir or dpdr. accesses to these two special purpose registers occur in debug mode and appear on the internal bus as an address and the assertion of an address at tribute signal indicating that a special purpose register is being accessed. the dpir register is read by the cpu to fetch all instru ctions when in debug mode and the dpdr register is read and written to transf er data between the cpu and external development tools. the dpir and dpdr are pseudo registers. decoding either of these regi sters will cause the developmen t port shift register to be accessed. the debug mode logic knows whether the cpu is fetching instructions or reading or writing data. if what the cpu is expecting and what the re gister receives from the serial port do not match (instruction instead of data ) the mismatch is used to signal a seque nce error to the external development tool. 23.4.6.4 development port serial comm unications ? cloc k mode selection all of the serial transmissions are clock transmissions and are th erefore synchronous communications. however, the transmission clock may be either synchronous or asynchronous with the system clock (clkout). the development port allows the sel ection of two methods for clocking the serial transmissions. the first method allows the transmis sion to occur without bei ng externally synchronized with clkout, in this mode a serial clock dsck must be supplied to the mpc561/mpc563. the other communication method requires a data to be externally synchronized with clkout. the first clock mode is called ?as ynchronous clock? since the input cl ock (dsck) is asynchronous with clkout. to be sure that data on ds di is sampled correctly, transitions on dsdi must occur a setup time ahead and a hold time after the rising edge of dsck . this clock mode allows communications with the port from a development tool which does not have access to the clkout signal or where the clkout signal has been delayed or skewed. refer to the timing diagram in figure 23-9 . the second clock mode is called ?s ynchronous self clock?. it does not re quire an input clock. instead the port is timed by the system clock. the dsdi input is required to meet setup and hold time requirements with respect to clkout risi ng edge. the data rate for this mode is always the same as the system clock. refer to the timing diagram in figure 23-10 . the selection of clock or self clock mode is made at reset. the state of the ds di input is latched eight clocks after sreset negates. if it is latched low, asynchronous clock mode is enabled. if it is latched high then synchronous self cl ock mode is enabled. since dsdi is used to select th e development port clocking scheme , it is necessary to prevent any transitions on dsdi during this time from being recognized as the start of a seri al transmission. the port will not begin scanning for the star t bit of a serial transmission unt il 16 clocks after the negation of sreset . if dsdi is asserted 16 clocks after sreset negation, the port will wait until dsdi is negated to begin scanning for the start bit. development support mpc561/mpc563 reference manual, rev. 1.2 23-32 freescale semiconductor note: dsck and dsdi transitions are not requ ired to be synchronous with clkout. figure 23-9. asynchronous clock serial communications figure 23-10. synchronous self clock serial communication mode cntrl di<0> s<0> s<1> do<0> start ready debug port drives ?ready? bit onto ds do when ready for a new transmission. debug port detects the ?sta rt? bit on dsdi and follows the ?ready? bit with two status bi ts and 7 or 32 output data bits. development tool drives the ?start? bit on dsdi (after detecting ?ready? bit on dsdo when in debug mode). the ?start? bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits. di di di development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-33 figure 23-11. enabling clock mode following reset 23.4.6.5 development port serial co mmunications ? trap enable mode when not in debug mode the development port starts communications by setting dsdo (the msb of the 35-bit development port shift registe r) low to indicate that all activity re lated to the previous transmission are complete and that a new trans mission may begin. the start of a seri al transmission from an external development tool to the de velopment port is signaled by a start bit. a mode bit in the transmission defines the transmission as either a trap enable mode transmissi on or a debug mode transm ission. if the mode bit is set the transmission will only be 10 bits long and onl y seven data bits will be shifted into the shift register. these seven bits will be latched into the tecr. a control bit determines whether the data is latched into the trap enable and vsync bits of the tecr or into the breakpoints bits of the tecr. 23.4.6.6 serial data into devel opment port ? trap enable mode the development port shift register is 35 bits wide but trap enable mode transmissions only use the start/ready bit, a mode/status bit, a c ontrol/status bit, and the seven leas t significant data bits. the encoding of data shifted into the deve lopment port shift register (thr ough the dsdi pin) is shown in table 23-10 and table 23-11 below: dsdi clkout sreset dsdi negates following sreset negation clken internal clock enabl e signal asserts 8 clocks after sreset negation if dsdi is negated. this enables clocked mode. 0123456789101112131415 first start bit detected after dsdi negation (self clocked mode) to enable clocked mode. development support mpc561/mpc563 reference manual, rev. 1.2 23-34 freescale semiconductor the watchpoint trap enables and vsync functions are described in section section 23.2, ?watchpoints and breakpoints support ? and section section 23.1, ?program flow tracking .? the debug port command function allows the developmen t tool to either assert or negate breakpoint requests, reset the processor, activate or deactivate the fast down-load procedure. 23.4.6.7 serial data out of develo pment port ? trap enable mode in trap enable mode the only response out of the development port is ?sequencing error.? data that can come out of th e development port is shown in table 23-12 . ?valid data from cpu? and ?cpu interrupt? status cannot occu r in trap enable mode. table 23-10. trap enable data shifted into development port shift register start mode contro l 1st 2nd 3rd 4th 1st 2nd vsync function - - - - - - instruction- - - - - - - - data- - watchpoint trap enables 1 1 0 0 = disabled; 1 = enabled transfer data to trap enable control register table 23-11. debug port command shifted into development port shift register start mode contro l extended opcode major opcode function 1 1 1 x x 00000 nop 00001 hard reset request 00010 soft reset request 0 x 00011 reserved 1 0 00011 end download procedure 1 1 00011 start download procedure x x 00100... 11110 reserved x 0 11111 negate maskable breakpoint. x 1 11111 assert maskable breakpoint. 0 x 11111 negate non maskable breakpoint. 1 x 11111 assert non maskable breakpoint. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-35 when not in debug mode the sequenc ing error encoding indicates that th e transmission from the external development tool was a debug mode transmission. when a sequencing er ror occurs the development port will ignore the data shifted in while the sequencing error was shifting out. it wi ll be treated as a nop function. finally, the null output encoding is used to indicat e that the previous transmission did not have any associated errors. when not in debug mode, ready will be asserted at the end of each transmissi on. if debug mode is not enabled and transmission errors can be guaranteed not to occur, the status output is not needed. 23.4.6.8 development port serial communications ? debug mode when in debug mode the development port starts comm unications by setting dsdo low to indicate that the cpu is trying to read an instruction from dpir or data from dpdr. when the cpu writes data to the port to be shifted out the r eady bit is not set. the port waits for the cpu to read th e next instruction before asserting ready. this allows duple x operation of the serial port whil e allowing the port to control all transmissions from the external development tool. after detecting this ready status the external development tool begins the transm ission to the development port with a start bit (logic high) on the dsdi pin. 23.4.6.9 serial data in to development port in debug mode the 35 bits of the development port shif t register are interpreted as a start/ready bit, a mode/status bit, a control/status bi t, and 32 bits of data. all instructions and data for the cpu are transmitted with the mode bit cleared indicating a 32-bit data field. the encoding of data shifted into the development port shift register (through the dsdi pin) is shown below in table 23-13 . table 23-12. status / data shifted out of development port shift register ready status [0:1] data function bit 0 bit 1 bits 2:31 or 2:6 ? (depending on input mode) (0) 0 0 data valid data from cpu (0) 0 1 freeze status 1 1 the ?freeze? status is set to (1) when the cpu is in debug mode and to (0) otherwise. download procedure in progress 2 2 the ?download procedure in progress? status is assert ed (0) when debug port in the download procedure and is negated (1) otherwise. 1?s sequencing error (0) 1 0 1?s cpu interrupt (0) 1 1 1?s null development support mpc561/mpc563 reference manual, rev. 1.2 23-36 freescale semiconductor data values in the last two functions other than those specified are reserved. all transmissions from the debug port on dsdo begin with a ?0? or ?ready? bit. this indicates that the cpu is trying to read an instruction or data from th e port. the external development tool must wait until it sees dsdo go low to begi n sending the next transmission. the control bit differentiates between instructions and data and allows the development port to detect that an instruction was entered when the cpu was expecting data a nd vice versa. if this occurs a sequence error indication is shifted out in the next serial transmission. the trap enable function allows the development tool to transfer data to the trap enable control register. the debug port command function allows the development tool to either negate breakpoint requests, reset the processor, activate or deactiv ate the fast down load procedure. the nop function provides a null operation for use when th ere is data or a response to be shifted out of the data register and the appropriate next instruction or command will be determined by the value of the response or data shifted out. 23.4.6.10 serial data ou t of development port the encoding of data shifted out of the developmen t port shift register in debug mode (through the dsdo pin) is the same as for trap enable mode and is shown in table 23-12 . valid data encoding is used when data has been tr ansferred from the cpu to the development port shift register. this is the result of an instruction to move the contents of a general purpose register to the debug port data register (dpdr). the valid data encoding has the highest priori ty of all status outputs and will be reported even if an interrupt occurs at the same time. since it is not possible for a sequencing error to occur and also have valid data ther e is no priority conflict with th e sequencing error status. also, any interrupt that is recognized at the sa me time that there is valid data is not related to the execution of an table 23-13. debug instructions / data shifted into development port shift register start mode control instruction / data (32 bits) function bits 0:6 bits 7:31 1 0 0 cpu instruction transfer instruction to cpu 1 0 1 cpu data transfer data to cpu 1 1 0 trap enable 1 1 refer to ta b l e 2 3 - 1 0 does not exist transfer data to trap enable control register 1 1 1 0011111 does not exist negate breakpoint requests to the cpu. 1 1 1 0 does not exist nop development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-37 instruction. therefore, a valid data st atus will be output and the interrupt status will be saved for the next transmission. the sequencing error encoding indicates that the inputs from the external development tool are not what the development port and/or the cpu was expe cting. two cases could cause this error: 1. the processor was trying to read instructions and there was data sh ifted into the development port, or 2. the processor was trying to read data and there was instruction sh ifted into the development port. the port will terminate the read cycle with a bus error. this bus error will cause the cpu to signal that an interrupt (exception) occurred. since a status of sequencing error has a higher priority than exception, the port will repor t the sequencing error first, and the cpu interrupt on the next transmission. the deve lopment port will ignore the command, instruction, or data shifted in while the sequenc ing error or cpu interrupt is shif ted out. the next transmission after all error status is reported to the port should be a new instruct ion, trap enable or command (possibly the one that was in progress when the sequencing error occurred). the interrupt-occurred encoding is used to indicate that the cpu encountered an interrupt during the execution of the previous instruction in debug mode. interrupts may occur as th e result of instruction execution (such as unimplemented opcode or arithmetic error) , because of a memory access fault, or from an unmasked external inte rrupt. when an interrupt occurs the de velopment port will ignore the command, instruction, or data shifted in whil e the interrupt encoding was shifting out. the next transmission to the port should be a new instruction, trap enable or debug port command. finally, the null encoding is used to indicate that no data has been transferred from the cpu to the development port shift register. 23.4.6.11 fast download procedure the download procedure is used to download a block of data from the debug tool into system memory. this procedure can be accomplished by repeating th e following sequence of transactions from the development tool to the debug port for the number of data words to be down loaded: figure 23-12. download procedure code example init: save rx, ry ry <- memory block address- 4 ... repeat: mfspr rx, dpdr data word to be moved to memory stwu rx, 0x4(ry) until here ... restore rx,ry development support mpc561/mpc563 reference manual, rev. 1.2 23-38 freescale semiconductor for large blocks of data this sequence may take significant time to complete. the ?fast download procedure? of the debug port may be used to reduce this time. this time reduction is achieved by eliminating the need to transfer th e instructions in the loop to the debug port. the only transactions needed are those required to transfer the data to be placed in system memory. figure 23-13 and figure 23-14 illustrate the time benefit of the ?fast download procedure?. figure 23-13. slow download procedure loop figure 23-14. fast download procedure loop the sequence of the instructions used in the ?f ast download procedure? is the one illustrated in figure 23-12 with rx = r31 and ry = r30. this sequence is repeated infinitely until the ?end download procedure? command is issued to the debug port. note that, the internal general pur pose register 31 is used for tempor ary storage data value. before beginning the ?fast download procedur e? by the ?start download proce dure command?, the value of the first memory block address, ? 4, must be written to the general purpose register 30. to end a download procedure, an ?end download pr ocedure? command should be issued to the debug port, and then, additional data transaction should be sent by the development tool. th is data word will not be placed into the system memory, but it is needed to stop the procedure gracefully. 23.5 software monitor debugger support when in debug mode disable, a soft ware monitor debugger can make use of all of the development support features defined in the cpu. when debug mode is disabled all events result in regular interrupt handling, i.e. the processor resumes execution in the correspo nding interrupt handler. the exception cause register (ecr) and the debug enable register (der) only influence the asserti on and negation of the freeze signal. 23.5.1 freeze indication the internal freeze si gnal is connected to all relevant internal modules. these modules can be programmed to stop all operations in response to th e assertion of the freeze signal. in order to enab le a software monitor debugger to broadcast the fact that th e debug software is now executed, it is possible to assert and negate the internal freeze signal also when debug mode is disabled. external mfspr data stwu transaction internal activity external data transaction internal activity development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-39 the assertion and negation of the fr eeze signal when in debug mode disabl e is controlled by the exception cause register (ecr) and the debug enab le register (der) as described in figure 23-6 . in order to assert the freeze signal the software needs to program the rele vant bits in the debug enab le register (der). in order to negate the freeze line the software needs to read the ex ception cause register (ecr) in order to clear it and perform an rfi instruction. if the exception cause register (ecr ) is not cleared before the rfi is performed the freeze signal is not negated. therefore it is possible to nest inside a software monitor de bugger without affecting the value of the freeze line although rfi may be perf ormed a few times. only before th e last rfi the software needs to clear the exception cause register (ecr). the above mechanism enables the software to accura tely control the assertion and the negation of the freeze signal. 23.6 development support registers table 23-14 lists the registers used for development s upport in spr number order, and the register sections, section 23.6.2, ?comparator a?d value registers (cmpa?cmpd) ? through section 23.6.13, ?development port data register (dpdr) ,? follow the same spr order. the registers are accessed with the mtspr and mfspr instructions. table 23-14. development support programming model spr number (decimal) name 144 comparator a value register (cmpa) see table 23-17 for bit descriptions. 145 comparator b value register (cmpb) see table 23-17 for bit descriptions. 146 comparator c value register (cmpc) see table 23-17 for bit descriptions. 147 comparator d value register (cmpd) see table 23-17 for bit descriptions. 148 exception cause register (ecr) see table 23-18 for bit descriptions. 149 debug enable register (der) see table 23-19 for bit descriptions. 150 breakpoint counter a value and control register (counta) see table 23-20 for bit descriptions. 151 breakpoint counter b value and control register (countb) see table 23-21 for bit descriptions. 152 comparator e value register (cmpe) see table 23-22 for bit descriptions. 153 comparator f value register (cmpf) see table 23-22 for bit descriptions. development support mpc561/mpc563 reference manual, rev. 1.2 23-40 freescale semiconductor 23.6.1 register protection table 23-15 and table 23-16 summarize protection feat ures of development suppor t registers during read and write accesse s, respectively. 154 comparator g value register (cmpg) see table 23-23 for bit descriptions. 155 comparator h value register (cmph) see table 23-23 for bit descriptions. 156 l-bus support control register 1 (lctrl1) see table 23-24 for bit descriptions. 157 l-bus support control register 2 (lctrl2) see table 23-25 for bit descriptions. 158 i-bus support control register (ictrl) see table 23-26 for bit descriptions. 159 breakpoint address register (bar) see table 23-28 for bit descriptions. 630 development port data register (dpdr) see section 23.6.13, ?development port data register (dpdr) ? for bit descriptions. table 23-15. development support registers read access protection msr[pr] debug mode enable in debug mode result 0 0 x read is performed. ecr is cleared when read. reading dpdr yields indeterminate data. 0 1 0 read is performed. ecr is not cleared when read. reading dpdr yields indeterminate data. 0 1 1 read is performed. ecr is cleared when read. 1 x x program exception is generated. read is not performed. ecr is not cleared when read. table 23-14. development support programming model (continued) spr number (decimal) name development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-41 23.6.2 comparator a?d value registers (cmpa?cmpd) note: these registers are unaffected by reset. 23.6.3 exception cause register (ecr) the ecr indicates the cause of entr y into debug mode. all bi ts are set by the hardware and cleared when the register is read when debug mode is disabled, or if the processor is in debug mode. at tempts to write to this register are ignored. when th e hardware sets a bit in this regi ster, debug mode is entered only if debug mode is enabled and the correspond ing mask bit in the der is set. all bits are cleared to zero following reset. table 23-16. development support registers write access protection msr[pr] debug mode enable in debug mode result 0 0 x write is performed. write to ecr is ignored. writing to dpdr is ignored. 0 1 0 write is not performed. writing to dpdr is ignored. 0 1 1 write is performed. write to ecr is ignored. 1 x x write is not performed. program exception is generated. msb 0123456789101112131415 field cmpa-d reset unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field cmpad reset unaffected addr spr144?spr147 figure 23-15. comparator a?d value register (cmpa?cmpd) table 23-17. cmpa-cmpd bit descriptions bits mnemonic description 0:31 cmpa-d address bits to be compared development support mpc561/mpc563 reference manual, rev. 1.2 23-42 freescale semiconductor msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ? rst chstp mce ? exti ale pre fpuve dece ? syse tr fpase sreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? see ? itlber ? dtlber ? lbrk ibrk ebrk dpi sreset 0000_0000_0000_0000 addr spr 148 figure 23-16. exception cause register (ecr) table 23-18. ecr bit descriptions bits name description 0?reserved 1 rst reset interrupt bit. this bit is se t when the system rese t pin is asserted. 2 chstp checkstop bit. set when the processor enters checkstop state. 3 mce machine check interrupt bit. set when a machine check exception (other than one caused by a data storage or instruction storage error) is asserted. 4:5 ? reserved 6 exti external interrupt bit. set when the external interrupt is asserted. 7 ale alignment exception bit. set when the alignment exception is asserted. 8 pre program exception bit. set when the program exception is asserted. 9 fpuve floating point unavailable exception bit. set when the program exception is asserted. 10 dece decrementer exception bit. set when the decrementer exception is asserted. 11:12 ? reserved 13 syse system call exception bit. set when the system ca ll exception is asserted. 14 tr trace exception bit. set when in single-step mode or when in branch trace mode. 15 fpase floating point assist exception bit. set when the floating point assist exception occurs. 16 ? reserved 17 see software emulation exception. set when th e software emulation exception is asserted. 18 ? reserved 19 itlber implementation specific instruction protection error this bit is set as a result of an instruction protec tion error. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 20 ? reserved 21 dtlber implementation specific data protection error this bit is set as a result of an data protection error. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-43 23.6.4 debug enable register (der) this register enables selectively ma sking the events that may cause the processor to enter into debug mode. 22:27 ? reserved 28 lbrk l-bus breakpoint exception bit. this bit is set as a result of the assertion of a load/store breakpoint. results in debug mode entry if debu g mode is enabled and the corresponding enable bit is set. 29 ibrk i-bus breakpoint exception bit. this bit is se t as a result of the assertion of an instruction breakpoint. results in debug mode entry if debu g mode is enabled and the corresponding enable bit is set. 30 ebrk external breakpoint exception bit. set when an external breakpoint is asserted (by an on-chip imb or l-bus module, or by an external device or development system through the development port). this bit is set as a result of the asserti on of an external breakpoint. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 31 dpi development port interrupt bit. set by the development port as a result of a debug station non-maskable request or when debug mode is entered immediately out of reset. msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ? rste chstpe mcee ? extie alee pree fpuvee decee ? sysee tre fpase sreset 0 0 1 0 0000_0000_0 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? seee ? itlbere ? dtlbere ? lbrke ibrke ebrke dpie sreset 0000_0000_0000 1 1 1 1 addr spr 149 figure 23-17. debug enable register (der) table 23-19. der bit descriptions bits name description 0:1 ? reserved 1 rste reset enable 0 debug entry is disabled (reset value) 1 debug entry is enabled 2 chstpe checkstop enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 3 mcee machine check exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled table 23-18. ecr bit descriptions (continued) bits name description development support mpc561/mpc563 reference manual, rev. 1.2 23-44 freescale semiconductor 4:5 ? reserved 6 extie external interrupt enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 7 alee alignment exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 8 pree program exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 9 fpuvee floating point unavailable exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 10 decee decrementer exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 11:12 ? reserved 13 sysee system call exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 14 tre trace exception enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 15 fpasee floating point assist exception enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 16 ? reserved 17 seee software emulation exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 18 ? reserved 19 itlbere implementation specific inst ruction protection error enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 20 ? reserved 21 dtlbere implementation specific data protection error enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 22:27 ? reserved 28 lbrke load/store breakpoint enable bit. 0 debug mode entry disabled 1 debug mode entry enabled (reset value) table 23-19. der bit descriptions (continued) bits name description development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-45 23.6.5 breakpoint counter a value and control register note: counta[16:31] are cleared following rese t; counta[0:15] are unaffected by reset. 29 ibrke instruction breakpoint interrupt enable bit. 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 30 ebrke external breakpoint interrupt enable bit (development port, internal or external modules). 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 31 dpie development port interrupt enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) msb 0123456789101112131415 field cntv sreset unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? cntc sreset 0000_0000_0000_0000 addr spr 150 figure 23-18. breakpoint counter a value and control register (counta) table 23-20. breakpoint counter a value and control register (counta) bits name description 0:15 cntv counter preset value 16:29 ? reserved 30:31 cntc counter source select 00 not active (reset value) 01 i-bus first watchpoint 10 l-bus first watchpoint 11 reserved table 23-19. der bit descriptions (continued) bits name description development support mpc561/mpc563 reference manual, rev. 1.2 23-46 freescale semiconductor 23.6.6 breakpoint counter b value and control register note: countb[16:31] are cleared following reset; countb[0:15] are unaffected by reset. 23.6.7 comparator e?f valu e registers (cmpe?cmpf) note: these registers are unaffected by reset. msb 0123456789101112131415 field cntv sreset unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field ? cntc sreset 0000_0000_0000_0000 addr spr 151 figure 23-19. breakpoint counter b value and control register (countb) table 23-21. breakpoint counter b value and control register (countb) bits name description 0:15 cntv counter preset value 16:29 ? reserved 30:31 cntc counter source select 00 not active (reset value) 01 i-bus second watchpoint 10 l-bus second watchpoint 11reserved msb 0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 lsb 31 field cmpe-f sreset unaffected addr spr 152, spr 153 figure 23-20. comparator e?f value registers (cmpe?cmpf) table 23-22. cmpe?cmpf bit descriptions bits mnemonic description 0:31 cmpe-f address bits to be compared development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-47 23.6.8 comparator g?h value registers (cmpg?cmph) note: these registers are unaffected by reset. 23.6.9 l-bus support control register 1 msb 0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 lsb 31 field cmpg-h sreset unaffected addr spr 154, spr 155 figure 23-21. comparator g?h value registers (cmpg?cmph) table 23-23. cmpg-cmph bit descriptions bits mnemonic description 0:31 cmpg-h data bits to be compared msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field cte ctf ctg cth crwe crwf sreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field csg csh susg sush cgbmsk chbmsk unused sreset 0000_0000_0000_0000 addr spr 156 figure 23-22. l-bus support control register 1 (lctrl) table 23-24. lctrl1 bit descriptions bits mnemonic description function 0:2 cte compare type, comparator e 0xx not active (reset value) 100 equal 101 less than 110 greater than 111 not equal 3:5 ctf compare type, comparator f 6:8 ctg compare type, comparator g 9:11 cth compare type, comparator h 12:13 crwe select match on read/write of comparator e 0x don?t care (reset value) 10 match on read 11 match on write 14:15 crwf select match on read/write of comparator f development support mpc561/mpc563 reference manual, rev. 1.2 23-48 freescale semiconductor note: lctrl1 is cleared following reset. 23.6.10 l-bus support control register 2 16:17 csg compare size, comparator g 00 reserved 01 word 10 half word 11 byte (must be programmed to word for floating point compares) 18:19 csh compare size, comparator h 20 susg signed/unsigned operating mode for comparator g 0 unsigned 1signed (must be programmed to signed for floating point compares) 21 sush signed/unsigned operating mode for comparator h 22:25 cgbmsk byte mask for 1st l-data comparator 0000 all bytes are not masked 0001 the last byte of the word is masked . . . 1111 all bytes are masked 26:29 chbmsk byte mask for 2nd l-data comparator 30:31 ? reserved ? msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field lw0en lw0ia lw0 iadc lw0la lw0 ladc lw0ld lw0 lddc lw1 en lw1ia lw1 iadc lw1la sreset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field lw1 ladc lw1ld lw1 lddc brk nomsk ?dlw0 en dlw1 en slw0 en slw1 en sreset 0000_0000_0000_0000 addr spr 157 figure 23-23. l-bus support control register 2 (lctrl2) table 23-24. lctrl1 bit descriptions (continued) bits mnemonic description function development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-49 table 23-25. lctrl2 bit descriptions bits name description 0 lw0en 1st l-bus watchpoint enable bit 0 watchpoint not enabled (reset value) 1 watchpoint enabled 1:2 lw0ia 1st l-bus watchpoint i-addr watchpoint selection 00 first i-bus watchpoint 01 second i-bus watchpoint 10 third i-bus watchpoint 11 fourth i-bus watchpoint 3 lw0iadc 1st l-bus watchpoint care/don?t care i-addr events 0 don?t care 1care 4:5 lw0la 1st l-bus watchpoint l-addr events selection 00 match from comparator e 01 match from comparator f 10 match from comparators (e&f) 11 match from comparators (e | f) 6 lw0ladc 1st l-bus watchpoint care/don?t care l-addr events 0 don?t care 1care 7:8 lw0ld 1st l-bus watchpoint l-data events selection 00 match from comparator g 01 match from comparator h 10 match from comparators (g&h) 11 match from comparators (g | h) 9 lw0lddc 1st l-bus watchpoint care/don?t care l-data events 0 don?t care 1care 10 lw1en 2nd l-bus watchpoint enable bit 0 watchpoint not enabled (reset value) 1 watchpoint enabled 11:12 lw1ia 2nd l-bus watchpoint i-addr watchpoint selection 00 first i-bus watchpoint 01 second i-bus watchpoint 10 third i-bus watchpoint 11 fourth i-bus watchpoint 13 lw1iadc 2nd l-bus watchpoint care/don?t care i-addr events 0 don?t care 1care development support mpc561/mpc563 reference manual, rev. 1.2 23-50 freescale semiconductor note: lctrl2 is cleared following reset. for each watchpoint, three control re gister fields (lwxia, lwxla, lwxld) must be programmed. for a watchpoint to be asserted, all th ree conditions must be detected. 14:15 lw1la 2nd l-bus watchpoint l-addr events selection 00 match from comparator e 01 match from comparator f 10 match from comparators (e&f) 11 match from comparators (e | f) 16 lw1ladc 2nd l-bus watchpoint care/don?t care l-addr events 0 don?t care 1care 17:18 lw1ld 2nd l-bus watchpoint l-data events selection 00 match from comparator g 01 match from comparator h 10 match from comparators (g&h) 11 match from comparator (g | h) 19 lw1lddc 2nd l-bus watchpoint care/don?t care l-data events 0 don?t care 1care 20 brknomsk internal breakpoints non-mask bit 0 masked mode; breakpoints are recognized only when msr[ri]=1 (reset value) 1 non-masked mode; breakpoints are always recognized 21:27 ? reserved 28 dlw0en development port trap enable selection of the 1st l-bus watchpoint (read only bit) 0 trap disabled (reset value) 1 trap enabled 29 dlw1en development port trap enable selection of the 2nd l-bus watchpoint (read only bit) 0 trap disabled (reset value) 1 trap enabled 30 slw0en software trap enable selection of the 1st l-bus watchpoint 0 trap disabled (reset value) 1 trap enabled 31 slw1en software trap enable selection of the 2nd l-bus watchpoint 0 trap disabled (reset value) 1 trap enabled table 23-25. lctrl2 bit descriptions (continued) bits name description development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-51 23.6.11 i-bus support co ntrol register (ictrl) if the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always visible on the external pins. program tr ace is not affected by this phenomenon. msb 0123 4 5 6 7 8 9 10 11 12131415 field cta ctb ctc ctd iwp0 iwp1 sreset 0000_0000_0000_0000 16 1 718 1 920 21 222324252627282930 lsb 31 field iwp2 iwp3 siwp0 en siwp1 en siwp2 en siwp3 en diwp0 en diwp1 en diwp2 en diwp3 en ifm isct_ser 1 1 changing the instruction show cycle prog ramming starts to take effect only fr om the second instruction after the actual mtspr to ictrl. sreset 0000_0000_0000_0000 addr spr 158 figure 23-24. i-bus support control register (ictrl) table 23-26. ictrl bit descriptions bits mnemonic description function non-compressed mode 1 compressed mode 2 0:2 cta compare type of comparator a 0xx = not active (reset value) 100 = equal 101 = less than 110 = greater than 111 = not equal 1xx = not active 000 = equal (reset value) 001 = less than 010 = greater than 011 = not equal 3:5 ctb compare type of comparator b 6:8 ctc compare type of comparator c 9:11 ctd compare type of comparator d 12:13 iwp0 i-bus 1st watchpoint programming 0x = not active (reset value) 10 = match from comparator a 11 = match from comparators (a&b) 14:15 w1 i-bus 2nd watchpoint programming 0x = not active (reset value) 10 = match from comparator b 11 = match from comparators (a | b) 16:17 iwp2 i-bus 3rd watchpoint programming 0x = not active (reset value) 10 = match from comparator c 11 = match from comparators (c&d) 18:19 iwp3 i-bus 4th watchpoint programming 0x = not active (reset value) 10 = match from comparator d 11 = match from comparators (c | d) 0x = not active (reset value) 10 = match from comparator d 11 = match from comparators (c | d) development support mpc561/mpc563 reference manual, rev. 1.2 23-52 freescale semiconductor 20 siwp0en software trap enable selection of the 1st i-bus watchpoint 0 = trap disabled (reset value) 1 = trap enabled 21 siwp1en software trap enable selection of the 2nd i-bus watchpoint 22 siwp2en software trap enable selection of the 3rd i-bus watchpoint 23 siwp3en software trap enable selection of the 4th i-bus watchpoint 24 diwp0en development port trap enable selection of the 1st i-bus watchpoint (read only bit) 0 = trap disabled (reset value) 1 = trap enabled 25 diwp1en development port trap enable selection of the 2nd i-bus watchpoint (read only bit) 26 diwp2en development port trap enable selection of the 3rd i-bus watchpoint (read only bit) 27 diwp3en development port trap enable selection of the 4th i-bus watchpoint (read only bit) 28 ifm ignore first match, only for i-bus breakpoints 0 = do not ignore first match, used for ?go to x? (reset value) 1 = ignore first match (used for ?continue?) 29:31 isct_ser rcpu serialize control and instruction fetch show cycle these bits control serialization and instruction fetch show cycles. see table 23-27 for the bit definitions. note: changing the instruction show cycle programming starts to take effect only fr om the second instruction after the actual mtspr to ictrl. 1 refer to appendix a, ?mpc562/mpc564 compression features ,? for code compression-specific functionality. 2 mpc562/mpc564 only. table 23-27. isct_ser bit descriptions serialize control (ser) instruction fetch (isctl) functions selected 0 00 rcpu is fully serialized and show cycles will be performed for all fetched instructions (reset value) 0 01 rcpu is fully serialized and show cycles will be performed for all changes in the program flow 0 10 rcpu is fully serialized and show cycles will be performed for all indirect changes in the program flow 0 11 rcpu is fully serialized and no show cycles will be performed for fetched instructions table 23-26. ictrl bit descriptions (continued) bits mnemonic description function non-compressed mode 1 compressed mode 2 development support mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 23-53 23.6.12 breakpoint address register (bar) 23.6.13 development port data register (dpdr) this 32-bit special purpose register physically resides in the development port logic. it is used for data interchange between the core and the development system . an access to this regi ster is initiated using mtspr and mfspr (spr 630) and implemented us ing a special bus cycle on the internal bus. 1 00 illegal. this mode should not be selected. 1 01 rcpu is not serialized (normal mode) and show cycles will be performed for all changes in the program flow 1 10 rcpu is not serialized (normal mode) and show cycles will be performed for all indirect changes in the program flow 1 11 rcpu is not serialized (nor mal mode) and no show cycles will be performed for fetched instructions msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field barv sreset unaffected addr spr 159 figure 23-25. breakpoint address register (bar) table 23-28. bar bit descriptions bits mnemonic description 0:31 barv[0:31] the address of the load/s tore cycle that generated the breakpoint msb 0 123456789101112131415161718192021222324252627282930 lsb 31 field data reset unaffected addr spr 630 figure 23-26. development port data register (dpdr) table 23-27. isct_ser bit descriptions serialize control (ser) instruction fetch (isctl) functions selected development support mpc561/mpc563 reference manual, rev. 1.2 23-54 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-1 chapter 24 readi module the readi module provides real-time development ca pabilities for rcpu-based mcus in compliance with the nexus ieee-isto 5001-1999. this module pr ovides development support capabilities for mcus in single chip mode, without requiring address and data signals for internal visibility. the development features supported are program trace , data trace, watchpoint trace, ownership trace, run-time access to the mcu?s internal memory map, and access to rcpu inte rnal registers during halt , via the auxiliary port. the auxiliary port, along with rcpu developmen t features (such as ba ckground debug mode and watchpoints) supports all software and hardware deve lopment in single chip mode. the auxiliary port, along with (on-chip) calibration ram, allows calibra tion variable acquisition a nd calibration constant tuning in single chip mode, for auto motive powertrain development systems. note in this section the bit numbering in th e register definitions of tool mapped registers follows the nexus ieee-isto 5001 - 1999 bit numbering convention of msb = bit 31 and lsb = bit 0, unlike the mpc500 standard (msb = bit 0 and lsb = bi t 31). the bit description tables list the bit numbering and nexus bit numbering. 24.1 features summary the readi module is compliant with class 3 of the ieee-isto 5001-1999. the following features are implemented: ? program trace via branch trace messaging (btm). branch trace me ssaging displays program flow discontinuities (direct and indirect branches, exceptions etc.), allowing the development tool to interpolate what transpires between the discont inuities. thus static code may be traced. ? data trace via data write messaging (dwm) and data read messaging (drm ). this provides the capability for the development tool to trace re ads and/or writes to (sel ected) internal memory resources. data trace also allows for calibrati on variable acquisition in automotive powertrain development systems. ? two data trace windows with pr ogrammable address range and a ccess attributes. data trace windowing reduces the requirements on the au xiliary port bandwidth by constraining the number of trace locations. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which pro cess id or operating system task is activated. an ownership trace message is transmitted to indicate when a new process/task is activat ed, allowing development tools to trace process/task flow. readi module mpc561/mpc563 reference manual, rev. 1.2 24-2 freescale semiconductor ? run-time access to on-chip memory map and mp c500 special purpose registers (sprs) via the readi read/write access protocol. this feature supports accesses fo r runtime internal visibility, calibration constant acquisition and tuning, and external rapid prototyping for powertrain automotive development systems. ? watchpoint messaging via the auxiliary port ? nine or 16 full-duplex auxiliary signal inte rface for medium and high visibility throughput ? one of two modes sele cted during reset: full port mode (fpm) and re duced port mode (rpm). ? fpm comprises 16 signals a nd rpm comprises nine signals ? auxiliary output port ? one mcko (message clock out) signal ? two or eight mdo (mes sage data out) signals ? one mseo (message start/end out) signal ? auxiliary input port ? one mcki (message clock in) signal ? one or two mdi (message data in) signals ? one msei (message start/end in) signal ? one evti (event in) signal ? one rsti (reset in) signal ? all features configurable and co ntrollable via the auxiliary port ? security features fo r production environment ? support of existing rcpu development acc ess protocol via the auxiliary port ? readi module can be reset i ndependent of system reset ? parametrics: ? two bits are downloaded per clock in full port mode. for example, with input clock running at 28 mhz, this translates to a download rate of 56 mbits/s. ? one bit is downloaded per clock in reduced port mode. for example, with input clock running at 28 mhz, this translates to a download rate of 28 mbits/s. ? eight bits are uploaded per clock in full port m ode. for example, with system clock running at 56 mhz, this translates to a upload rate of 448 mbits/s. ? two bits are uploaded per clock in reduced port mode. for example, with system clock running at 56 mhz, this translates to a upload rate of 112 mbits/s. 24.1.1 functional block diagram the functional block diagram of the readi module is shown in figure 24-1 . readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-3 figure 24-1. readi functional block diagram 24.2 modes of operation the various operating modes of the readi module are: 1. reset 2. secure 3. normal 4. disabled 24.2.1 reset configuration the readi reset configuration is explained in section 24.7.6, ?readi reset configuration .? u-bus snoop l-bus snoop l-bus master data trace encoding program encoding trace r/w access control registers message queues mdo[0:1] brkpt_ l-bus mcko watchpoint capture security signal interface message out formatter message in formatter mdi[0] or mcki rcpu evti rsti ownership rcpu development access usiu l-bus snoop l-bus l-bus trace encoding signal interface u-bus usiu mseo msei or mdo[0:7] mdo[0:1] out l-bus readi module mpc561/mpc563 reference manual, rev. 1.2 24-4 freescale semiconductor 24.2.2 security security is provided via the uc3f censorship mechanism. if a uc3f ar ray is in censored mode, reads or writes to the uc3f will not be allowed (rcpu will not be able to fetch instru ctions from the uc3f) once any of the following cases are detected: ? program trace and/or data trace are enabled ? read/write access is attempted (c an be to any address location) ? rcpu development access is enabled. 24.2.3 normal normal operation of the readi module allows for developement support fe atures to be available. these features include control of the devi ce, access to registers, and the abili ty to perform data or instruction trace. 24.2.4 disabled if evti is negated at negation of rsti , the readi module will be disa bled. no trace output will be provided, and output auxiliary port will be three-stated. any message sent by the tool is ignored. 24.3 parametrics with 32-deep message queues, thr oughput numbers were calculated fo r the following benchmark codes [assuming full port mode]: ? for an example benchmark whic h had 10.9% direct branches, 2.5% indirect branches, 10.4% data writes, and 19.3% data reads, approximately 20% of total data trace accesses will be traced. ? for another example benchmark which had 9.8% direct branches, 2.8% i ndirect branches, 6.6% data writes, and 18.3% data reads, approximately 27% of total data tr ace accesses will be traced. note the queue is only 16 messages deep on revisions prior to rev. d of the mpc561 and is 16 deep in rev. b and earlier versions of the mpc563. for reduced port mode, the data trace fe ature should not be used, or used sp aringly, so as not to cause queue overruns. 24.4 messages the readi module implements messaging via the a uxiliary port according to the ieee-isto 5001 - 1999. messaging will be implemented via transfer codes (tcodes) on the auxiliary port. the tcode number for the message identifies the tr ansfer format (the numb er and/or size of pack ets to be transferred) and the purpose of each packet. public messages outlined in table 24-1 are supported by readi. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-5 . table 24-1. public messages tcode number message name 1 device id. refer to section 24.6.1.3, ?devic e id register (did) .? 2 ownership trace message. refer to section 24.13.1, ?ownership trace messaging .? 3 program trace ? direct branch message. refer to section 24.8.2.1, ?direct branch messages .? 4 program trace ? indirect branch message. refer to section 24.8.2.2, ?indirect branch messages .? 5 data trace ? data write message. refer to section 24.9.2.1, ?data write message .? 6 data trace ? data read message. refer to section 24.9.2.2, ?data read message .? 8 error message. refer to table 24-20 . 10 (0x0a) program trace correction. refer to section 24.8.2.3, ?correction messages .? 11 (0x0b program trace ? direct branch synchronization message. refer to section 24.8.2.4.1, ?direct branch synchronization message .? 12 (0x0c) program trace ? indirect branch synchronization message. refer to section 24.8.2.4.2, ?indirect branch synchronization message .? 13 (0x0d) data trace ? data write synchronization message. refer to section 24.9.2.4, ?data write synchronization message .? 14 (0x0e) data trace ? data read synchronization message. refer to section 24.9.2.5, ?data read synchronization messaging .? 15 (0x0f) watchpoint message. refer to section 24.12.1, ?watchpoint messaging .? 16 (0x10) auxiliary access ? device ready for upload/download message. refer to section 24.6.2, ?accessing memory-mapped locations via the auxiliary port .? 17 (0x11) auxiliary access ? upload request (tool requests information) message. refer to section 24.6.3, ?accessing readi tool mapped registers via the auxiliary port .? 18 (0x12) auxiliary access ? download request (tool provides information) message. refer to section 24.6.2, ?accessing memory-mapped locations via the auxiliary port .? 19 (0x13) auxiliary access ? upload/download information (device/tool provides information) message. refer to section 24.6.3, ?accessing readi tool mapped registers via the auxiliary port .? 27 (0x1b) program trace 1 - resource full message. refer to section 24.8.2.4.5, ?resource full message .? 1 1 this message is not available on the mpc561 prior to revision d and is not available on the mpc563 revision b and earlier. table 24-2. vendor-defined messages tcode number message name 56 (0x38) rcpu development access ? dsdi data (tool provides information) message 57 (0x39) rcpu development access ? dsdo da ta (device provides information) message 58 (0x3a) rcpu development access ? bdm stat us (device provides information) message 59 (0x3b) program trace ? indirect branch message with compressed code. available in mpc562/mpc564 only. readi module mpc561/mpc563 reference manual, rev. 1.2 24-6 freescale semiconductor vendor-defined messages outlined in table 24-2 are also supported by readi. 24.5 terms and definitions 60 (0x3c) program trace ? direct branch synchronizat ion message with compressed code. available in mpc562/mpc564 only. 61 (0x3d) program trace ? indirect branch synchroniz ation message with compressed code. available in mpc562/mpc564 only. table 24-3. terms and definitions term description auxiliary port refers to ieee-isto 5001 auxiliary port. branch trace messaging (btm) external visibility of addresses for taken branches and exceptions, and the number of sequential instructions executed between each taken branch. bdm background debug mode. compressed code mode current instruction stream is fetching compre ssed code. available in mpc562/mpc564 only. calibration constants performance related constants which must be tuned for automotive powertrain and disk drive applications. calibration variables intermediate calculations which must be visible during the calibration or tuning process to enable accurate tuning of calibration constants. data read message (drm) external visibility of data reads to internal memory-mapped resources. data write message (dwm) external visibility of data writes to internal memory-mapped resources. data trace messaging (dtm) external visibility of how data flows thr ough the embedded system. may include drm and/or dwm. download tool sends information to the device field number of bits representing single piece of information fpm full port mode. this is the default full port mode for readi. ieee-isto 5001 ieee-isto 5001, formerly known as gl obal embedded processor debug interface standard. worldwide web documentation at http://www.nexus5001.org/. halt rcpu is in freeze state (typically in debug mode) instruction fetch the process of reading the instruction dat a received from the instruction memory. instruction issue the process of driving valid instruction bits in side the processor. the instruction is decoded by each execution unit, and the appropriate ex ecution unit prepares to execute the instruction during the next clock cycle. table 24-2. vendor-defined messages (continued) tcode number message name readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-7 instruction taken an instruction is taken after it has been iss ued and recognized by the appropriate execution unit. all resources to perform the instruction are ready, and the processor begins to execute it. instruction retire completion of the instruction issue, execution and writeback stages. an instruction is ready to be retired if it completes without generating an exception and all instructions ahead of it in history buffer have completed without generating an exception. ictrl instruction bus support control register (refer to table 23.6.11 ) ownership trace message (otm) visibility of process/function that is currently executing. public messages messages on the auxiliary signals for accomplishing common visibility and controllability requirements e.g. drm and dwm. rcpu processor that implements the powerpc-based architecture used in the freescale mpc500 family of microcontrollers. readi real time embedded applications development interface. readi signals refers to ieee-isto 5001 auxiliary port. rpm reduced port mode. this is the reduced port mode for readi. run-time rcpu is executing program code in normal mode sequential instruction any instruction other than a flow-control instruction or isync. snooping monitoring addresses driven by a bus master to detect the need for coherency actions. standard the phrase ?according to the standard? implies according the ieee-isto 5001 - 1999. superfield one or more message ?fields? delimited by mseo /msei assertion/negation. the information transmitted between ?s tart-message? and ?end-packet? states. show cycle an internal access (e.g., to an internal memory) reflected on the external bus using a special cycle (marked with a dedicated transfer co de). for an internal memory ?hit,? an address-only bus cycle is generated ; for an internal memory ?mi ss,? a complete bus cycle is generated. transfer code (tcode) message header that identifies the number and/or size of packets to be transferred, and how to interpret each of the packets. tck / dsck / mcki multiplexed signal: jtag clock or development port clock. mcki is a readi signal on the mpc561/mpc563 tdi / dsdi / mdi0 multiplexed signal: jtag data in or development port serial data in. mdi0 is a readi signal on the mpc561/mpc563. tdo / dsdo / mdo0 multiplexed signal: jtag data out or development port serial data out. mdo0 is a readi signal on the mpc561/mpc563 upload device sends information to the tool. vsync internal rcpu signal vf internal rcpu signal which indicates instruction queue status. vfls internal rcpu signal which indicates history buffer flush status. table 24-3. terms and definitions (continued) term description readi module mpc561/mpc563 reference manual, rev. 1.2 24-8 freescale semiconductor 24.6 programming model the readi registers do not follow the recommenda tions of the ieee-isto 5001 - 1999, but are loosely based on the 0.9 release of the standard. see http://www.nexus5001.org/ . readi registers are classified in to two categories: user-mapped re gister and tool-mapped registers. user-mapped register (a memory-mapped register): ? ownership trace register tool-mapped registers (registers which can be acces sed only through the development tool and are not memory mapped): ? device id register ? development control register ? mode control register 4-bit ? user base address register ? read/write access register ? upload/download info rmation register ? data trace attributes register 1 ? data trace attributes register 2 24.6.1 register map readi registers are accessible via the auxiliary port. they can be classified into two categories: user-mapped registers a nd tool-mapped registers. 24.6.1.1 user-mapped register (otr) the operating system writes the id for the current task/process in the single user-mapped register, the readi ownership trace (otr) register. table 24-4 shows the location of the re gister bits. their functions are explained below. the current task/process (ctp) fiel d is updated by the operating system software to provide task/process id information. the otr register ca n only be accessed by supervisor data attribut es. only cpu writes to this register will be transmitted. this register is not accessible via the aux iliary port download request message. note this is the only readi register that is reset by hreset . readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-9 24.6.1.2 tool-mapped registers table 24-5 defines readi registers that are not memo ry mapped and can only be accessed through the development tool. their correspondi ng access opcodes are also defined. . 24.6.1.3 device id register (did) accessing the did register provides key attributes to the developmen t tool concerning the mcu. this information is also transmitte d via the auxiliary output port upon exit of readi reset (rsti ), if evti is asserted at rsti negation. table 24-6 gives the bit descriptions. msb 0123456789101112131415 field current task process (ctp) hreset 0000_0000_0000_0000 addr 0x38 002c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field current task process (ctp) hreset 0000_0000_0000_0000 figure 24-2. readi ownership trace register (otr) table 24-4. otr bit descriptions bits name description 0:31 ctp readi ownership trace register, write only. table 24-5. tool-mapped register space access opcode register access type 8 (0x08) device id register (did) read only 10 (0x0a) development control register (dc) read only 11(0x0b) mode control register (mc) 1 read/write 1 1 not available on all revisions. refer to the device errata for the version of silicon in use. 13 (0x0d) user base address register (uba) read only 15 (0x0f) read/write access register (rwa) read/write 16 (0x10) upload/download information register (udi) read/write 20 (0x14) data trace attributes register 1 (dta1) read/write 21 (0x15) data trace attributes register 2 (dta2) read/write readi module mpc561/mpc563 reference manual, rev. 1.2 24-10 freescale semiconductor 24.6.1.4 development control register (dc) the dc register is used for basic development control of the readi module. table 24-7 shows the location of register bits. msb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field rev mdc pn rsti ? 1 0000_10 00_0011 addr 0x08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 field pn mid ? rsti 0xxx 2 0000_0001_110 1 1 the default value depends on the revision of the device. 2 xxx = 0b101 for mpc561/mpc562 and xxx = 0b110 for mpc563/mpc564. figure 24-3. readi device id register table 24-6. did bit descriptions rcpu bits nexus bits name description 0:3 31:28 rev readi version number. this field contains the revision level of the device. 4:9 27:22 mdc 1 1 the ieee-isto 5001-19 99 defines these two fields as a single combined field. readi manufacturer design center. this fi eld identifies the manufacturer?s design center. the mpc561/mpc563 has a value of 0x02. 10:19 21:12 pn 1 readi part number. this part number identification field. the mpc561/mpc562 field value is 0x35, and mpc563/mpc564 value is 0x36. 20:30 11:1 mid readi manufacturer id. this fiel d identifies the manufact urer of the device, freescale?s id is 0x0e. the value of this register for the mpc561 prior to revision d silicon is 0x1c, and the value for the mpc563 prior to revision b and earlier silicon is 0x1c. 31 0 ? reserved msb 7654321 lsb 0 field dor dme ? tm ec rsti 0000_0000 address 0x0a figure 24-4. readi development control (dc) register readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-11 table 24-8 describes the dc register fields with the m ode configurations for rcpu development access. 24.6.1.5 mode control register (mc) the mc register is used to select different modes of the readi module. table 24-7 shows the location of register bits. table 24-7. dc bit descriptions rcpu bits nexus bits name description 07dor 1 1 the dor and dme fields in the dc register can only be modi fied when system reset is asserted, or reset (to default state) when the readi module is reset by the assertion of rsti . readi debug mode entry out-of-reset field can be configured to enable or disable debug mode entry out of reset. 0 debug mode not entered out-of-reset 1 debug mode entered out-of-reset 16dme 1 readi debug mode enable field can be configured to enable or disable debug mode. 0 debug mode disabled 1 debug mode enabled 25 dpareserved 3:5 4:2 tm readi trace mode field can be configured to enable btm, dtm, and otm. any or all types of trace may be enabled. 000 no trace 1xx btm branch trace messaging enabled x1x dtm data trace messaging enabled xx1 otm ownership trace messaging enabled 6:7 1:0 ec readi evti control field can be configured for synchronization and breakpoint generation. if the ec is equal to 0b00, asserting evti will cause the next program and data trace message to be a synchronization message (providing program and data trace are enabled). if the ec field is equal to 0b01, a breakpoint will be generated. if the field is configured to one of the reserv ed states, its action reverts to that of the default state. note: the evti signal is level sensitive when ec is configured for breakpoint generation. this implies that as long as evti assertion is continued (with ec set to 0b01), the readi module will continue reque sting a breakpoint. the user must detect breakpoint generation and negate the evti signal appropriately. 00 evti for program and data trace synchronization 01 evti for breakpoint generation 1x no action table 24-8. rcpu development access modes dor dme rcpu development access through readi x 0 non-debug mode access of rcpu development through readi. 0 1 debug mode is enabled through readi (rcpu is still in normal mode, out of reset) 1 1 debug mode is enabled through readi and entered out-of-reset. debug mode entry causes rcpu to halt. readi module mpc561/mpc563 reference manual, rev. 1.2 24-12 freescale semiconductor note the mc register is not available prior to revisi on d of the mpc561 and is not available in revisi on b and earlier versions of the mpc563. prior revisions have only th e default features. 24.6.1.6 user base addr ess register (uba) the uba register defines the memory map address for the ot register. table 24-10 gives a description of the register bits. msb 7 6543 2 1 lsb 0 field qtst ? ptm qfm ptsm rsti 0000_0000 address 0x0b figure 24-5. readi mode control (mc) register table 24-9. mc bit descriptions rcpu bits nexus bits name description 0 7 qtst enables a factory test mode for structur al testing of the queue. this bit can only be written in factory test mode. when set, no trace messages are queued. users should always write this bit as a 0. 5 2 ptm the program trace mode (ptm) bit enabl es an enhanced method of program trace. this mode allows program trace to work with the isctl bits of the ictrl register set to any value except 3. the value of 2 is recommended for optimal processor performance. the drawback of this mode is direct branch messages are never syncronizing so sync requests must be held until the next indirect branch. 0 legacy program trace mode 1 enhanced program trace mode 6 1 qfm the queue flush mode (qfm) bit selects if information in the queue is discarded or transmitted at the time of an overrun. discarding information allows trace to resume quicker after an overrun, but makes it difficult to find the cause of the overrun. 0 information in the queue is removed 1 trace is stopped until the queue empties. 7 0 ptsm the program trace sync mode (ptsm) indicates if the program trace messages contain the i-cnt packet. 0 program trace message do not contain the i-cnt packet. 1 program trace message contain the i-cnt packet. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-13 24.6.1.7 read/write a ccess register (rwa) the rwa register provides dma-like access to memory-mapped locations, mpc500 special purpose registers, and readi t ool mapped registers. table 24-11 shows the location of register bits. msb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field uba rsti 0000_0000_0011_1000 addr 0x0d 151413121110987654321 lsb 0 field uba rsti 0000_0000_0010_1100 figure 24-6. readi user base address register table 24-10. uba bit descriptions rcpu bits nexus bits name description 0:31 31:0 uba the user base address (uba) field defines the memory map address for the ot register. the mpc561/mpc563 user base address is 0x38002c. the uba register is read-only by the development tool. readi module mpc561/mpc563 reference manual, rev. 1.2 24-14 freescale semiconductor msb 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 field sc rwad rsti 0000_0000_0000_0000 addr 0x0f 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 field rwad rw sz wd rsti 0000_0000_0000_0000 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 field wd rsti 0000_0000_0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field wd prv map rsti 0000_0000_0000_0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 field cnt rsti 0000_0000_0000_0000 figure 24-7. readi read/write access register table 24-11. rwa read/write access bit descriptions rcpu bits nexus bits name description 0 79 sc the start complete (sc) field is set when a read or write access is initiated. the device will clear the sc bit once the read or write access completes. during a block access, if the sc bit is reset, the access will terminate. 0 access complete 1 start access 1:25 78:54 rwad read/write address (rwad) bits are used to identify the address of internal memory-mapped resources to be accessed, or the lowest address (i.e., lowest unsigned value) for a block move (cnt > 0). the address range for a block move is from rwad to rwad + cnt. note: the rwd field of the udi register is shared with the wd field of the rwa register. 26 53 rw the read/write (rw) field can be configured to allow selection of a read or a write access. 0 read access 1 write access readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-15 24.6.1.8 upload/download information register (udi) the udi register, a 34-bit register, is used to store the data to be written for block write access, and the data read for read (si ngle and block) accesses. table 24-12 gives a description of the register bits. 27:28 52:51 sz the word size (sz) field can be config ured to allow 32-bit, 16-bit, or 8-bit read/write accesses. if the field is configured to one of the reserved states, its action reverts to that of the default state. 00 32-bit 01 16-bit 10 8-bit 11 reserved 29:60 50:19 wd write data (wd) bits co ntain the data to be written. for a read access, the data stored is a don?t care. 61:62 18:17 prv the privilege attribute field can be configured to select different read/write access attributes. 00 user data 01 user instruction 10 supervisor data 11 supervisor instruction 63 16 map the map select field can be configured to allow access to multiple memory maps. the primary processor memory map (map equal to 0b0) is designated as the default. the secondary memory map (map equal to 0b1) can be set to select the mpc500 special purpose registers. 0 primary memory map 1 secondary memory map (ppc special purpose registers) 64:79 15:0 cnt the access count field can be configur ed to indicate the number of accesses of word size (defined in sz field). the cnt value is used to increment the specified address in the rwad field for block read/write accesses. for a single read/write access, the cnt value should equal to 0x0000. a 64-kbyte block read/write access can be performed by configuring the cnt bits as 0xffff. if a user wants to terminate a block read or write access which has not completed, the cnt bits should be reset. table 24-11. rwa read/write access bit descriptions (continued) rcpu bits nexus bits name description readi module mpc561/mpc563 reference manual, rev. 1.2 24-16 freescale semiconductor msb 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 field rwd rsti 0000_0000_0000_0000_0 addr 0x10 16151413121110987654321 lsb 0 field rwd err dv rsti 000_0000_0000_0000 0 0 figure 24-8. readi upload/download information register table 24-12. udi bit descriptions rcpu bits nexus bits name description 0:31 33:2 rwd the read/write data field is used to store data for read accesses and block write accesses. it can contain three sizes of data. refer to table 24-13 , table 24-14 and table 24-9 for details. 32 1 err the error field is used to determine the st atus of the read or write access. refer to table 24-13 and ta b l e 2 4 - 1 4 for details. 0 read or write access has not been completed. 1 read or write access has completed. note: the err field is read-only. 33 0 dv the data valid field is used to determine the status of the read or write access. refer to ta b l e 2 4 - 1 3 and table 24-14 for details. 0 no error has occurred. 1 access error occurred. note: the dv field is read-only. table 24-13. read access status err dv status 0 0 read access has not yet completed 0 1 read access has completed and no access error occurred 1 0 access error occurred 11not allowed table 24-14. write access status err dv status 0 0 write access has completed and no access error occurred 1 0 write access error occurred (error message sent out) 0 1 write access has not yet completed 11not allowed readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-17 . note the rwd field of the udi register is shared with the wd field of the rwa register. 24.6.1.9 data trace attributes 1 and 2 registers (dta1 and dta2) the dta1 and dta2 registers allow da ta trace messaging (dtm) to be rest ricted to reads, writes or both for a user programmable address ra nge. two dta registers allow two address ranges to be selected for dtm. refer to table 24-15 for register bit descriptions. lsb 8 bit reserved ? read as zeros ls byte err dv 16 bit reserved ? read as zeros ms byte ls byte err dv 32 bit ms byte ls byte err dv figure 24-9. rwd field configuration msb 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 field dtea rsti 0000_0000_0000_0000 addr 0x14 (dta1), 0x15 (dta2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field dtea dtsa rsti 0000_0000_0000_0000 151413121110987654321 lsb 0 field dtsa ta rsti 0000_0000_0000_00 00 figure 24-10. readi data trace attributes 1 register (dta1) readi data trace attributes 2 register (dta2) table 24-15. dta 1 and 2 bit descriptions rcpu bits nexus bits name description 0:22 47:25 dtea 1 the read/write end field defines the end address for the address range. refer to table 24-16 . readi module mpc561/mpc563 reference manual, rev. 1.2 24-18 freescale semiconductor note there is no way to distinguish betw een off-core mpc500 special purpose register (spr) map and normal memo ry map accesses via the defined address range control. if data trace ra nges are set up such that the off-core mpc500 spr map falls within active ranges, then accesses to these off-core mpc500 sprs will be traced, and the me ssages will not be distinguishable from accesses to normal memory map space. off-core mpc500 sprs typically exist in the 8- to 16-kbyte lowest memory block (0x2000 ? 0x3ff0). if data or peripherals are mapped to this space, load/stores to mpc500 sprs will be indistinguishable from data or peripheral accesses. 24.6.2 accessing memory-mapped locations via the auxiliary port the control and status information is accessed via the four auxiliary access public messages: device ready for upload/download, upload request (tool request s information), download request (tool provides information), and upload/download informat ion (device/tool provides information). to write control or status to memory-mapped locations the following se quence would be required. 1. the tool confirms that the devi ce is ready (so as to not cancel an ongoing read write access). the tool transmits the download reque st public message (tcode 18) wh ich contains write attributes, write data, and target address. 2. the tool waits for device read y for upload/download (tcode 16) message before initiating next access. 23:45 24:2 dtsa 1 the read/write start field defines the starting address for the address range. refer to table 24-16 . 46:47 1:0 ta the read/write trace field can be configured to allow enabling or disabling data read and/or data write traces. 00 disable data read and data write trace x1 enable data read trace 1x enable data write trace 1 data trace range start and end addresses must be word-aligned. table 24-16. data trace values programmed values range selected dtsa < dtea dtsa dtea dtsa > dtea invalid range dtsa = dtea word at dtsa table 24-15. dta 1 and 2 bi t descriptions (continued) rcpu bits nexus bits name description readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-19 to read control or status from memory-mapped locations the following sequence would be required. 1. the tool confirms that the device is ready. th e tool transmits the downl oad request public message (tcode 18) which contains read attributes and target address. 2. when device reads data it transmits uploa d/download information message (tcode 19) containing read data. device is now ready for next access. for a block write to memory-mapped locations the following sequence would be required. 1. the tool confirms that the device is ready. th e tool transmits the downl oad request public message (tcode 18) which contains bl ock write attributes, first wr ite data, and target address. 2. the tool waits for devi ce ready for upload/downl oad message (tcode 16). when it is transmitted by device, tool transmits uploa d/download information message (tcode 19) containing next write data. this step is repeat ed until all data is written for a block read from memory-mapped locati ons the following sequence would be required. 1. the tool confirms that the device is ready. th e tool transmits the downl oad request public message (tcode 18) which contains block re ad attributes and target address. 2. the tool waits for upload/download informat ion message (tcode 19) from device, which contains read data. this step is repeated until all data is read. refer to section 24.10, ?read/write access ,? for more details on read/write access protocol. 24.6.3 accessing readi tool mapped registers via the auxiliary port to write control or status data to readi tool mapped registers the following sequence would be required. 1. the tool confirms that the device is ready. the tool transmits the download request message (tcode 18) which contains wr ite data, and register opcode. 2. the tool waits for device read y for upload/download message (tco de 16) before initiating next access. to read control or status from readi tool mapped registers the following sequence would be required 1. the tool confirms that the devi ce is ready. the tool transmits the upload re quest message (tcode 17) which contains the target opcode. 2. when device reads data it transmits uploa d/download information message (tcode 19) containing read data. device is now ready for next access. refer to section 24.10, ?read/write access ,? for more details on read/write access protocol. 24.6.4 partial register updates registers may be updated via the auxiliary port usi ng the download request message with the message containing only n (where n is less than register width) most-significant bits of the register. in such cases the bits not transmitted will be reset to 0b0. the bits transmitted will be aligne d such that the last bit transmitted will be the most significan t bit of the register. th erefore a message size th at is divisible by the input port size shoul d be transmitted. readi module mpc561/mpc563 reference manual, rev. 1.2 24-20 freescale semiconductor 24.6.5 programming considerations the following programing guidelines are reco mmended for users of the readi features. 24.6.5.1 program trace guidelines program trace via btm is not supported during bdm. for program trace synchroni zation to work, the ictrl register (refer to table 23.6.11 )must be programmed such that show cycles will be performed for all changes in the program flow (isctl field = 0b01) or the ptm bit in the readi mc register must be set and the isctl fiel d in the ictrl register must not equal 0b11. note the user must program the ictrl for ch ange of flow show cycles or the ptm bit in the readi mc register ea rly in the reset vector, before any branches, otherwise trace is not guaranteed. if bdm is enabled, the ictrl regist er cannot be modified through the program and can only be modified through rcpu development access. to get the best performance from the system, ptm shou ld be set to 1 and isctl should be set to 0b10. it is also recommended that the usiu be programmed to ignore instruction show cycl es (so as to not impact u-bus performance). see section 6.2.2.1.1, ?siu module confi guration register (siumcr) .? to correctly trace program execution using btm, the readi module must be enab led prior to release of system reset. if the read i module is enabled (evti asserted, rsti negated) after th e rcpu has started execution of the program, the trace cannot be guaranteed. refer to figure 24-16 for further details. 24.6.5.2 compressed code mode guidelines to display data on instruction show cycles, the bbc must be enable d. bbcmcr[decomp_sc_en] (refer to section 4.6.2.1, ?bbc module conf iguration register (bbcmcr) ?) must be set when decompression is enabled. this will allo w readi to track the compressed code. bbcmcr[decomp_sc_en] should not be se t if there is no intention to use compressed code, as it will degrade u-bus performance. refer to appendix a, ?mpc562/mpc564 compression features ? for mpc562/mpc564 compression information. the ictrl register must be programmed such that a s how cycle will be performe d for all changes in the program flow (isctl field = 0b01), or the ptm bit must be set and isctl must be set to a value other than 0b11. (see table 23-26 .) 24.7 signal interface this section details information regardi ng the readi signals and signal protocol. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-21 24.7.1 functional description the readi signal interface provides the function of transmitting messages from the message queues to the external tools. the signal interface also provide s the control for timing and logic for formatting the messages. 24.7.1.1 signals implemented the readi module implements one mcko, mcki, evti , rsti , mseo , and msei signal. it also implements one or two mdi and two or eight mdo signals. the input signals are synchr onized to the mcki input clock and the output signals are synchronized to the free running mcko output clock. the mcki input clock should be synchr onised to the mcko ouput clock to en sure correct message reception. the readi signal definition is outlined in table 24-17 . note mcki clock frequency has to be less than or equa l to one half of mcko clock frequency. table 24-17. description of readi signals ieee-isto 5001 signal name input/ output description of signal mcko output message clock-out (mcko) is a free-running output clock to development tools for timing of mdo and mseo signal functions. mcko is the same as the mcu system clock. mdo[7:0] or mdo[1:0] output message data out (mdo[7:0] or mdo[1:0]) are output signal s used for uploading otm, btm, dtm, and read/write accesses. external latc hing of mdo will occur on rising edge of mcko. eight signals are implemented. mdo[7:0] are used in full port mode, mdo[1:0] are used in reduced port mode. mseo output message start/end out (mseo ) is an output signal which indicates when a message on the mdo signals has started, when a variable length packet has ended, and when the message has ended. 1 mseo signal is implemented. external latching of mseo will occur on rising edge of mcko. mcki input message clock-in (mcki) is a input clock from development tools for timing of mdi and msei signal functions. mcki frequency has to be less than or equal to one half of mcko frequency. mdi[1:0] or mdi0 input message data in (mdi[1:0] or mdi[0]) are input signals used for downloading configuration information, writes to user resources, etc. inte rnal latching of mdi will occur on rising edge of mcki. two signals are implemented on the mpc561 /mpc563. mdi[1:0] are used in full port mode, mdi[0] only is used in reduced port mode. mse i input message start/end in (msei ) is an input signal which indicates when a message on the mdi signals has started, when a variable length packet has ended, and when the message has ended. 1 msei signal is implemented. internal latching of msei will occur on rising edge of mcki. evti input event in (evti ) ? the evti signal is level sensitive when configured for breakpoint generation, otherwise it is edge sensitive. rsti input reset in (rsti ). readi module mpc561/mpc563 reference manual, rev. 1.2 24-22 freescale semiconductor 24.7.2 functional block diagram figure 24-11 depicts the functional block di agram of the signal interface. . figure 24-11. functional diagram of signal interface the signal interface is responsible for handshaking wi th the message queue and registers. it is also responsible for requesting new messa ges from the message queue. a me ssage is always requested from the message queue if the me ssage queue is not empty, the message buffer is availa ble and a higher priority message is not requesting to be transmitted. the rate at which data is removed from the queue depends on the average message length, the number of mdo signals, and the mcko clocking rate. 24.7.3 message priority message formatting is performed in the signal in terface block. the following priority scheme is implemented for messages sent to th e signal output formatter block, with 1 being the highest priority and 5 being the lowest priority: 1. invalid message 2. readi register access handshakes (device ready/download information) 3. watchpoint messages 4. read/write access message 5. rcpu development access message control unit signal interface trace messages from queue data to readi output formatter input formatter mdo[7:0] mdi[1:0] mcko mseo msei mcki rsti evti mux buf buf auxiliary messages watchpoint message rcpu dev. port message data control invalid message r/w access message registers readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-23 6. queued messages (program trace, data trace, and ownership trace) 24.7.4 signal protocol the protocol for the mcu receiv ing and transmitting messages via the auxiliary signals will be accomplished with the msei and mseo signal functions re spectively. the msei signal will provide the protocol for the mcu receiving messages, and the mseo signal will provide the protocol for the mcu transmitting messages. the msei /mseo protocol is illustrated in table 24-18 . msei /mseo are used to signal the end of variable-length packets and messag es. they are not required to indicate end of fixed length packets. msei /mseo are sampled on the rising edge of mcki and mcko respectively. fixed width fields can be c oncatenated before variable length fields without regard to th e individual fields starting or endi ng at message n bit boundaries. variable width fi elds must end at message n bit boundaries (where n is mdi/mdo signals). figure 24-12 shows the basic relation between the mdo and mseo signals, and packet structure. mdo and mseo are sampled on the rising edge of mcko. figure 24-12. auxiliary signal packet structure for program trace indirect branch message table 24-18. msei /mseo protocol operation mseo /msei state idle ?1?s at all clocks start two ?1?s followed by one ?0? active ?0?s at all clocks during transmission of a message end of variable length packet ?0? followed by ?1? end of packet and message ?0? followed by two or more ?1?s tcode = 4 number of sequential instructi ons since last taken branch = 4 relative address = 0x534 don?t care data (idle clock) mcko mseo mdo[7:0] 00000100 00000001 00110100 00000101 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 24-24 freescale semiconductor figure 24-13 illustrates the state diagram for msei /mseo transfers. in the end message state, data on mdi/o is ignored. figure 24-13. msei /mseo transfers 24.7.5 messages public messages outlined in table 24-19 are supported by readi. table 24-19. public messages supported message name minimum packet size (bits) maximu m packet size (bits) packet type packet description direction device id 6 6 fixed tcode number = 1 from device 32 32 fixed device id information ownership trace message 6 6 fixed tcode number = 2 from device 32 32 fixed task/process id tag idle start message normal transfer end message mse =1 mse =1 mse =0 mse =0 mse =1 mse =1 mse =0 mse =0 mse =0 mse =1 mdi/o: ignored mdi/o: data on end packet mse represents msei / mseo mdi/o represents mdo/mdi mdi/o: valid mdi/o: valid mdi/o: valid readi reset mdi/o is ignored readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-25 program trace ? direct branch message 6 6 fixed tcode number = 3 from device 1 8 variable number of sequential instructions executed since last taken branch program trace ? indirect branch message 6 6 fixed tcode number = 4 from device 1 8 variable number of sequential instructions executed since last taken branch 1 23 variable unique portion of the target address for taken branches and exceptions data trace ? data write message 6 6 fixed tcode number = 5 from device 1 25 variable unique portion of the data write address 8 32 variable data write value (8, 16, 32 bits) data trace ? data read message 6 6 fixed tcode number = 6 from device 1 25 variable unique portion of the data read address 8 32 variable data read value (8, 16, 32 bits) error message 1 6 6 fixed tcode number = 8 from device 5 5 fixed error code program trace correction message 6 6 fixed tcode number = 10 (0xa) from device 1 8 variable correcting the number of instructions in the trace program trace ? direct branch synchronization message (ptsm = 0) 6 6 fixed tcode number = 11 (0xb) from device 1 1 variable number of program trace messages cancelled 1 23 variable full target address program trace ? direct branch synchronization 2 message (ptsm = 1) 6 6 fixed tcode number = 11 (0xb) from device 1 8 variable number of sequential instructions executed since last taken branch 1 23 variable full target address program trace ? indirect branch synchronization message (ptsm = 0) 6 6 fixed tcode number = 12 (0xc) from device 1 1 variable number of program trace messages cancelled 1 23 variable full target address table 24-19. public messages supported (continued) message name minimum packet size (bits) maximu m packet size (bits) packet type packet description direction readi module mpc561/mpc563 reference manual, rev. 1.2 24-26 freescale semiconductor program trace ? indirect branch synchronization 2 message (ptsm = 1) 6 6 fixed tcode number = 12 (0xc) from device 1 8 variable number of sequential instructions executed since last taken branch 1 23 variable full target address data trace ? data write synchronization message 6 6 fixed tcode number = 13 (0xd) from device 1 1 variable number of messages canceled 1 25 variable full target address 8 32 variable data write value (8, 16, 32 bits) data trace ? data read synchronization message 6 6 fixed tcode number = 14 (0xe) from device 1 1 variable number of messages canceled 1 25 variable full target address 8 32 variable data read value (8, 16, 32 bits) watchpoint message 6 6 fixed tcode number = 15 (0xf) from device 6 6 fixed number indicating watchpoint source auxiliary access ? device ready for upload/download message 6 6 fixed tcode number = 16 (0x10) from device auxiliary access ? upload request message 6 6 fixed tcode number = 17 (0x11) from to o l 8 8 fixed opcode to enable selected configuration, status or data upload from mcu auxiliary access ? download request message 6 6 fixed tcode number = 18 (0x12) from to o l 8 8 fixed opcode to enable selected configuration or data download to mcu 8 80 variable depending upon opcode selected for download, information to be downloaded to device will vary. auxiliary access ? upload/download information message 6 6 fixed tcode number = 19 (0x13) from device / to o l 8 80 variable 1). for an access, depending on word size selected (sz field in rwa register), variable-length packets of information (10, 18, or 34 bits) will be uploaded/downloaded from/to device. 2). depending upon opcode selected for upload from internal readi registers, information to be uploaded to the device will vary. table 24-19. public messages supported (continued) message name minimum packet size (bits) maximu m packet size (bits) packet type packet description direction readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-27 vendor-defined messages outlined in table 24-21 are also supported by readi. resource full message 2 6 6 fixed tcode number = 27 (0x1b) from device 1 4 variable resource code 1 refer to table 24-20 for the error message codes. 2 not available on the mpc561 prior to revision d and not available on mpc563 revision b and earlier. table 24-20. error message codes error code description 00000 ownership trace overrun 1 1 this error message is not available on the mpc561 prior to revision d and is not available on the mpc563 revision b and earlier. 00001 program trace overrun 1 00010 data trace overrun 1 00011 read/write access error 00100 invalid message 00101 invalid access opcode 00110 watchpoint overrun 00111 program/data/ownership trace overrun 01000-10111 reserved 11000-11111 vendor defined table 24-21. vendor-defined messages supported tcode name minimum packet size (bits) maximum packet size (bits) packet type packet description direction dev port access ? dsdi data message 6 6 fixed tcode number = 56 (0x38) from tool 10 35 variable bdm development serial data in (dsdi) dev port access ?dsdo data message 6 6 fixed tcode number = 57 (0x39) from device 10 35 variable bdm development serial data out (dsdo) dev port access ? bdm status message 6 6 fixed tcode number = 58 (0x3a) from device 11fixedbdm status table 24-19. public messages supported (continued) message name minimum packet size (bits) maximu m packet size (bits) packet type packet description direction readi module mpc561/mpc563 reference manual, rev. 1.2 24-28 freescale semiconductor 24.7.5.1 message formats message formatting is perf ormed in the signal interf ace block. raw messages read from the message queue are independent of the number of mdo signals implemented. table 24-22 shows the various message formats that the signal interface formatter has to encounter. program trace ? indirect branch message with compressed code 1 6 6 fixed tcode number = 59 (0x3b) from device 1 8 variable number of sequential instructions executed since last taken branch 6 6 fixed bit address 1 23 variable unique portion of the target address for taken branches and exceptions (compressed code) program trace ? direct branch synchronization message with compressed code 1 (ptsm = 0) 6 6 fixed tcode number = 60 (0x3c) from device 6 6 fixed bit address 1 23 variable current instruction address program trace ? direct branch synchronization message with compressed code 1 (ptsm = 1) 6 6 fixed tcode number = 60 (0x3c) from device 1 8 variable number of sequential instructions executed since last taken branch 6 6 fixed bit address 1 23 variable current instruction address program trace ? indirect branch synchronization message with compressed code 1 (ptsm = 0) 6 6 fixed tcode number = 61 (0x3d) from device 6 6 fixed bit address 1 23 variable current instruction address program trace ? direct branch synchronization message with compressed code (ptsm = 1) 6 6 fixed tcode number = 61 (0x3d) from device 1 8 variable number of sequential instructions executed since last taken branch 6 6 fixed bit address 1 23 variable current instruction address 1 this message is provided only for the mpc562/mpc564. table 24-21. vendor-defined messages supported (continued) tcode name minimum packet size (bits) maximum packet size (bits) packet type packet description direction readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-29 note for variable length fields, the transmitte d size of the field is determined as the bits from the least si gnificant bit to the most significant non-zero valued bit, (i.e., most significant 0 va lue bits are not transmitted). table 24-22. message field sizes 1,2 message tcode field # 1 field # 2 field # 3 max size 3 min. size 4 device id 1 fixed = 32 na na 38 bits 38 bits ownership trace message 2 fixed = 32 na na 38 bits 38 bits program trace ? direct branch message 3variable max = 8 min = 1 na na 14 bits 7 bits program trace ? indirect branch message 4variable max = 8 min = 1 variable max = 23 min = 1 na 37 bits 8 bits data trace ? data write message 5variable max = 25 min = 1 variable max = 32 min = 8 na 63 bits 15 bits data trace ? data read message 6variable max = 25 min = 1 variable max = 32 min = 8 na 63 bits 15 bits error message 5 8 fixed = 5 na na 11 bits 11 bits program trace correction message 10 (0xa) variable max = 8 min = 1 na na 14 bits 7 bits program trace ? direct branch synchronization message (ptsm = 0) 11 (0xb) variable max = 1 min = 1 variable max = 23 min = 1 na 30 bits 8 bits program trace ? direct branch synchronization message (ptsm = 1) 11 (0xb) variable max = 8 min = 1 variable max = 23 min = 1 na 37 bits 8 bits program trace ? indirect branch synchronization message (ptsm = 0) 12 (0xc) variable max = 1 min = 1 variable max = 23 min = 1 na 30 bits 8 bits program trace ? indirect branch synchronization message (ptsm = 1) 12 (0xc) variable max = 8 min = 1 variable max = 23 min = 1 na 37 bits 8 bits readi module mpc561/mpc563 reference manual, rev. 1.2 24-30 freescale semiconductor data trace ? data write synchronization message 13 (0xd) variable max = 1 min = 1 variable max = 25 min = 1 variable max = 32 min = 8 64 bits 16 bits data trace ? data read synchronization message 14 (0xe) variable max = 1 min = 1 variable max = 25 min = 1 variable max = 32 min = 8 64 bits 16 bits watchpoint message 15 (0xf) fixed = 6 na na 12 bits 12 bits auxiliary access ? device ready for upload/download message 16 (0x10) na na na 6 bits 6 bits auxiliary access ? upload request (tool requests information) message 17 (0x11) fixed = 8 na na 14 bits 14 bits auxiliary access ?download request (tool provides information) message 18 (0x12) fixed = 8 variable max = 80 min = 8 na 94 bits 22 bits auxiliary access ? upload/download information (device/tool provides information) message 19 (0x13) variable max = 80 min = 8 na na 86 bits 14 bits resource full message 6 27 (0x1b) variable max = 4 min =1 na na 10 bits 7 bits dev port access ? dsdi data (tool provides information) message 56 (0x38) variable max = 35 min = 10 na na 41 bits 16 bits dev port access ? dsdo data (device provides information) message 57 (0x39) variable max = 35 min = 10 na na 41 bits 16 bits dev port access ?bdm status (device provides information) message 58 (0x3a) fixed = 1 na na 7 bits 7 bits program trace ? indirect branch message with compressed code 59 (0x3b) variable max = 8 min = 1 fixed = 6 variable min = 1 max = 23 43 bits 14 bits program trace ? direct branch synchronization message with compressed code (ptsm = 0) 7 60 (0x3c) fixed = 6 variable max = 23 min = 1 na 35 bits 13 bits table 24-22. message field sizes 1,2 (continued) message tcode field # 1 field # 2 field # 3 max size 3 min. size 4 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-31 the maximum message length is 94 bi ts. the maximum number of fields is three, excluding the tcode itself. 24.7.5.2 rules of messages ? a variable sized field within a message must end on a port boundary. ? a variable sized field may star t within a port boundary only when following a fixed length packet. ? super fields must end on a port boundary (2-, 4-, or 8-bit boundaries depending on whether the device receives or sends message s, and the port size configured). ? when a variable length field is sized such that it does not end on a port boundary, it is necessary to extend and zero fill the remaining bits after the highest-order bit so th at it can end on a port boundary. ? a data field within a data trace messag e must be 8, 16, 24, or 32 bits in length. the field containing the tcode number is always transf erred out first, followed by subsequent fields of information. within a field, the lowest si gnificant bits are shifted out first. figure 24-14 shows the transmission sequence of a message which is made up of a tcode (a fi xed-length field) and a variable length field (field 1), together ma king a super field. every instance of a fixed length field followed by a variable field is a super field. figure 24-14 , for example, shows two supe r fields. the only exception to program trace ? direct branch synchronization message with compressed code (ptsm = 1) 5 60 (0x3c) variable max = 8 min = 1 fixed = 6 variable min = 1 max = 23 43 bits 14 bits program trace? indirect branch synchronization message with compressed code (ptsm = 0) 5 61 (0x3d) fixed = 6 variable max = 23 min = 1 na 35 bits 13 bits program trace? indirect branch synchronization message with compressed code (ptsm = 1) 5 61 (0x3d) variable max = 8 min = 1 fixed = 6 variable min = 1 max = 23 43 bits 14 bits 1 the double edges indicate that mseo /msei is asserted to indicate the start of a message or negated to indicate the end of a message. refer to figure 24-14 . 2 the shaded edges indicate super fields t hat can hold information delimited via mseo /msei assertion followed by mseo /msei negation. 3 maximum information size. the actual number of bits transmitted is dependant on the number of mdo signals. 4 minimum information size. the actual number of bits transmitted is dependent on the number of mdo signals. 5 refer to table 24-20 . 6 not available prior to rev. d of the mpc561 and is not available in rev. b and earlier versions of the mpc563 7 only available on mpc562/mpc564 table 24-22. message field sizes 1,2 (continued) message tcode field # 1 field # 2 field # 3 max size 3 min. size 4 readi module mpc561/mpc563 reference manual, rev. 1.2 24-32 freescale semiconductor this rule are the developm ent port access messages. see section 24.14.1, ?rcpu de velopment access messaging ,? for further details. figure 24-14. transmission sequence of messages 24.7.5.3 branch trace message examples the following are examples of branch trace messages. 24.7.5.3.1 example of in direct branch message table 24-23 illustrates an example of how the indirect branch public messa ge is transmitted. the example uses a 4-bit output port. note that t0, i0, and a0 are the least significant bits where: tx = tcode number (fixed) ix = number of sequentia l instructions (variable) ax = unique portion of the address (variable) note during clock 7, the tool shoul d ignore data on mdo signals. 123 msb lsb msb lsb msb lsb lsb msb 4 mse x super field super field tcode (6 bits) field #1 (var) field #2 field #3 (var) readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-33 24.7.5.3.2 example of direct branch message table 24-24 is an example of the minimum transmission of any message containing a variable length field (three clocks). the example uses a 4-bit output port. note that t0, and i0 are the least significant bits where: tx = tcode number (fixed) ix = number of sequential instructions (variable) note during clock 3, the tool shoul d ignore data on mdo signals. 24.7.5.4 non-temporal ordering of transmitted messages trace messages sent out may not be in the sequence they actually occurred. the traces are monitored on the internal buses and these traces are captured as th ey occur and are sent out in the order they were captured and processed. btms are in sequence and dtms are in sequence, ho wever, temporal order of dtms interleaved with btms may not be accurate with rega rd to logical flow of code. table 24-23. indirect branch message clock mdo[3:0] mseo 3210 1 idle 0 xxxx 1 idle (or end of last message) 1 t3t2t1t0 0 start message 2i1i0t5t4 0 normal transfer 3 i5i4i3i2 0 normal transfer 400i7i6 1 end packet 5 a3a2a1a0 0 normal transfer 6 a7a6a5a4 1 end packet 7 0000 1 end message 8 t3t2t1t0 0 start message table 24-24. direct branch message clock mdo[3:0] mseo 3210 1 idle 1 t3t2t1t0 0 start message 2i1i0t5t4 1 end packet 3 0000 1 end message readi module mpc561/mpc563 reference manual, rev. 1.2 24-34 freescale semiconductor 24.7.6 readi reset configuration the readi reset configuration in formation is received via evti and mdi0 to enable or disable the readi module and select the port size. evti and mdi0 are sampled sync hronously at the negation of rsti. reset configuration inform ation must be valid on evti and mdi0 at least four clocks prior to the negation of rsti . if evti is sampled asserted at negation of rsti , the readi module will be enab led. this is illustrated in figure 24-15 . readi control and status information will be reset and the a uxiliary output port will be three-stated, when rsti is asserted. system reset will not reset the readi control and stat us information and not three-state the auxiliary output port. port size configuration is selected via th e value of mdi0 at the negation of rsti . table 24-25 describes the readi reset configuration options. rsti has a pull-down resistor in the pa ds. if the auxiliary port is not connected to a tool, readi module will be in reset state and not drive the auxiliary output port. figure 24-15. readi module enabled table 24-25. readi reset configuration options evti mdi [0] configuration 1 x module disabled. all outputs three-stated. 0 1 module enabled, default full port configuration 2 mdi, 8 mdo 0 0 module enabled, reduced port configuration 1 mdi, 2 mdo rsti evti evti is sampled at the negation of rsti . because evti is asserted, the readi module is enabled. reset configuration information must be valid on evti at least 4 system clocks prior to rsti negation. system clock readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-35 hreset rsti msei mdi mseo mdo (tool drives) (tool drives) evti (tool drives) 1 evti must be asserted 4 system clocks prior to the readi module. did message dc message 2 device sends out did message after 3 tool sends in dc message with desired program trace mode enabled. (bdm can also be enabled through. 16 clocks after receiving the device will start executing the reset instruction sequence user program. in this user program, if background debug mode (bdm) is enabled, the ictrl register cannot be modified through user program. this register can only be accessed through the development port. 4 dc register configur ation. see note.) note: set the isctl field = 0b01 in the ictrl register. also the usiu should be programmed to ignore instruction showcycles to avoid impacting u-bus performance. negation of rsti to enable after the hreset negation, tool negates hreset negation of rsti device ready tcode=1 tcode=16 tcode=18 device ready message. do not send an input message is received from the readi module. enabled, or wait until the did message until at least 2 mcki after readi is readi module mpc561/mpc563 reference manual, rev. 1.2 24-36 freescale semiconductor figure 24-16. enabling program trace out of system reset 24.7.7 readi signals the readi signals support nexus (ieee-isto 5001-1999) auxiliary por t interface for debug. there are two modes available, full port mode and reduced por t mode. reduced port mode allows for a 1 bit input stream and a 2 bit output stream. full port mode allows for a 2 bit input stream and an 8 bit output stream. see figure 24-11 for readi mode selection. steps to enter readi (nexus) mode: 1. negate poreset while holding jcomp/rsti low. 2. configure tms/evti and tdi/dsdi/mdi[0 ] while jcomp/rsti is low. (evti = low to enable nexus) 3. negate jcomp/rsti . 4. if mdi[0] is high at jcomp/rsti negation, then full port mode is enabled otherwise reduced mode is selected. to exit readi mode: 1. reassert jcomp/rsti to disable readi. figure 24-17. readi mode selection 24.7.7.1 reset configuration for debug mode to enable rcpu development access via the readi signals, the reset sequence outlined below should be used: ? assert readi reset (rsti ), event-in (evti ) and system reset (hreset ) ? negate rsti ? upon negation of rsti , tool should configure th e dor, dme, and dpa fields in the dc register to desired setting. ? tool negates hreset at least 16 system clocks after receiving the device ready message refer to figure 24-84 for further details. poreset jcomp/rsti tms /evti mdi0 readi-config jtag disabled readi readi-config readi t readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-37 24.7.7.2 reset configurat ion for non-debug mode refer to section 24.7.7.1, ?reset configuration for debug mode ,? for details on reset configuration for non-debug mode. the only difference between non-debug m ode reset configurati on and debug mode reset configuration are the values of the dor and dme fields in the dc register. 24.7.7.3 secure mode refer to section 24.2.2, ?security ,? for further details. 24.7.7.4 disabled mode if evti is negated at negation of rsti , the readi module will be disa bled. no trace output will be provided, and output auxiliary signals will be three-stated. this is illustrated in figure 24-18 . figure 24-18. read i module disabled 24.7.7.5 guidelines for tr ansmitting input messages ? an error message is sent out when an invalid tcode is detected by the signal input formatter. refer to section 24.10.8.2, ?invalid message ,? for further details. ? an error message is sent out when an invalid acce ss opcode is detected in auxiliary input messages by the signal input formatter. refer to section 24.10.8.3, ?invalid access opcode ,? for further details. ? if the tcode is valid, then readi will expect that the correct number of packets have been received and no further checking wi ll be performed. if the number of packets received by readi is not correct, readi response is not defined, unless the message is a download request message (refer to section 24.6.4, ?partial register updates ,? for further details). system rsti evti reset configuration information must be valid on evti at least 4 clocks prior to rsti negation. evti is sampled at the negation of rsti . since evti is negated, the readi module is disabled. clock readi module mpc561/mpc563 reference manual, rev. 1.2 24-38 freescale semiconductor 24.8 program trace this section details the program trace mechanism supported by readi for the rcpu. program trace is implemented via branch trace messaging (b tm) as per the ieee-isto 5001-1999 definition. 24.8.1 branch trace messaging branch trace messaging facilitates program trace by providing the followi ng types of information: ? messaging for taken direct bran ches includes how many sequential instructions were executed since the last taken branch or exception. direct (or indirect) branches not taken are counted as sequential instructions. ? messaging for taken indi rect branches and exceptions include s how many sequential instructions were executed since the last taken branch or exce ption and the unique portion of the branch target address or exception vector address. ? for some mispredicted branches and excepti on occurrences, program trace correction messages correct the number of instructions since last ta ken branch as transmitte d in prior btm message. 24.8.1.1 rcpu instructions that cause btm messages the following rcpu instructions, when executed, cause indirect branch messages to be encoded: 1. taken branch relative to link or counter registers 2. context switching se quential instructions 3. exception taken (error/interrupts) the following rcpu instruction, wh en executed, causes direct br anch messages to be encoded: 1. taken direct branch instructions 24.8.2 btm message formats btm messages are of five types ? direct, i ndirect, correction, synchronization, and error. 24.8.2.1 direct branch messages direct branches (conditional or uncondi tional) are all taken branches w hose destination is fixed in the instruction opcode. the program trace direct branch message has the following format: figure 24-19. direct branch message format tcode (3) sequence count [1 - 8 bits] max length = 14 bits [6 bits] min length = 7 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-39 24.8.2.2 indirect branch messages indirect branches include interrupts, exceptions, and all taken branches whose destination is determined at run time. for the rcpu, certain se quential instructions are tagged wi th the indirect change-of-flow attribute because these instruction affect the machine in a similar manner to true indirect change-of-flow instructions. these instructions are the rfi, isync , mtmsr and certain mtspr (to cmpa ? cmpf, ictrl, ecr and der) the program trace indirect branch message has the following format: figure 24-20. indirect branch message format for compressed code support, six addi tional bits indicate the starting bi t address within the word of the compressed instruction. the program trace indirect bran ch with compressed code messa ge has the format shown in figure 24-21 . the format of the bit address field is shown in figure 24-22 . the bit definitions are shown in table 24-26 . note on the mpc562/mpc564, the bit pointer should be multiplied by 2 (shift left on bit) for the actual starting bit position. figure 24-21. indirect branch message format with compressed code figure 24-22. bit pointer fo rmat with compressed code table 24-26. bit pointer format rcpu bits nexus bits name description 4:5 0:1 ? reserved (unused) 0:3 2:5 bp bit pointer. this value is 1/2 of the actual bit position on which the instru ction starts. tcode (4) sequence count relative address [1 - 8 bits] [1 - 23 bits] max length = 37 bits [6 bits] min length = 8 bits tcode (59) sequence count bit pointer relative address [6 bits] [1-8 bits] [6 bits] [1-23 bits] max length = 40 bits min length = 14 bits 543210 reserved bit pointer msb lsb readi module mpc561/mpc563 reference manual, rev. 1.2 24-40 freescale semiconductor 24.8.2.3 correction messages in case of a mispredicted branch or an exception, a program trace correction me ssage may also be sent indicating a number which corrects the number of instructions (not messages) in the trace. in the case of a synchronizing branch trace message getting corrected due to a misprediction or an exception, the next branch trace message will be a synchronizing message. table 24-27 illustrates an example of a program trace correct ion message in case of a mispredicted branch. note in case of a mispredicted branch, the correction count is always 1 and the sequential instruction count is reset to 1 (to denote the not-taken branch as a sequential instruction), after the progr am trace correction message is sent. this is because a mispredicted branch is considered to be a sequential instruction. table 24-28 illustrates an example of a program trace correction messa ge in case of an exception. note in case of an exception, the sequential in struction count is reset to 0, after the program trace correction message is sent. table 24-27. program trace correction due to a mispredicted branch time processor state message sent 1 sequential instruction 2 sequential instruction 3 sequential instruction 4 sequential instruction 5 sequential instruction 6 direct branch instruct ion direct branch message tcode = 3 number of sequential instructions executed since last taken branch = 5 7 sequential instruction 8 sequential instruction 9 sequential instruction 10 sequential instruction 11 indirect bran ch instruction (mispredicted taken) indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 4 unique portion of the target address 12 sequential instruction 13 sequential instruction readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-41 14 sequential instruction 15 branch correction program trace correction message tcode = 10 number of instructions to rewind from trace = 1 16 sequential instruction 17 sequential instruction 18 indirect bran ch instruction (predicted taken) indirect branch message tcode = 4 number of sequential instructions executed since last valid taken branch = 3 unique portion of the target address at time 11, the indirect br anch is mispredicted taken. at time 15, branch correction occurs due to the mi spredicted branch which was taken at time 11. a program trace correction message is sent out correcti ng the number of instruct ions in the trace (1). sequential instruction which occurred at time 12, 13, and 14 respectively are not included in the correction count because the tool is not aware that they occurred (they were not transmitted out). at time 18, the indirect branch message indicates that 3 sequential instructions were executed since trace correction (this includes the mispredicted branch instruction which is considered to be a sequential instruction). table 24-28. program trace correction due to an exception time processor state message sent 1 sequential instruction 2 sequential instruction 3 sequential instruction 4 direct branch instruction direct branch message tcode = 3 number of sequential instructions executed since last taken branch = 3 5 sequential instruction 6 sequential instruction 7 sequential instruction 8 sequential instruction 9 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 4 unique portion of the target address 10 sequential instruction 11 sequential instruction table 24-27. program trace correction due to a mispredicted branch (continued) time processor state message sent readi module mpc561/mpc563 reference manual, rev. 1.2 24-42 freescale semiconductor the program trace correction mess age has the following format: figure 24-23. program trace correction message format 24.8.2.4 synchronization messages a program trace synchronization message is transmitted via the auxiliar y port (provided program trace is enabled) for the following conditions: ? initial program trace message upon exit of any system reset will be a synchronization message. ? upon exit of sleep, deep-sleep and low power down mode , the first btm will be a synchronization message. ? initial program trace message upon exit of background debug mode. upon exiting bdm, the next btm will be a synchronization message. ? when btm is enabled, the first btm will be a synchronization message. ? after 255 program trace messages have been que ued without synchronizati on, the next btm will be a synchronization message. 12 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 2 unique portion of the target address 13 sequential instruction 14 exception due to instruction at time 8 program trace correction message tcode = 10 number of instructions to rewind from trace = 5 16 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 0 unique portion of the target address at time 8, the sequential instruction that causes an exception is issued. at time 14, the instruction iss ued at time 8 causes an exception. a program trace correction message is sent out correct ing the number of instructions in the trace (5). the sequential instruction that occurred at time 13 is not included in the co rrection count because the to ol is not aware that it occurred (it was not transmitted out). note: the sequential instruction at time 8 did not retire and is included in the correction number. table 24-28. program trace correction due to an exception (continued) time processor state message sent tcode (10) [6 bits] number of instructions to rewind from trace [1 - 8 bits] max length = 14 bits min length = 7 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-43 ? upon assertion of an event in (evti ) signal. if the readi module is not disabled, an evti assertion will cause the next btm to be a sync hronization message (provi ded the ec field is 0b00 in the dc register). ? upon occurrence of a watchpoint, the next btm will be a synchronization message (provided program trace is enabled). ? occurrence of queue overrun. a program trace ove rrun error occurs when a trace message cannot be queued due to the queue being full. this causes the message que ue to be flushed, and an error message is placed as the first message in the que ue. the error code within the error message will indicate that program/data/ow nership trace overrun has occurred. the next btm will be a synchronization message. ? sequential instruction count overflow. when the sequential instruction counter reaches its maximum count (up to 256 sequentia l instructions may be executed), the next btm will be a program trace synchr onization message.the sequential instruction counter is reset. ? upon entering or exiting code compression m ode, the next btm will be a synchronization message. ? the next change-of-flow instru ction fetch following vsync wi ll be a synchronization message. program trace synchronizati on messages provide the fu ll address (without leadi ng zeros) and ensure that development tools fully synchronize with program tr ace regularly. synchronization messages provide a reference address for subsequent bt ms, in which only the un ique portion of the progr am trace address is transmitted. note for program trace synchronization to work, the ictrl register (refer to table 23.6.11 ) must be programmed such that show cycle will be performed for all changes in the program flow (i sctl field = 01) if the ptm bit is set to 0. if the ptm bit is set to 1, is ctl can be programmed to any value except no show cycles (isctl field = 11). it is also recommended that the usiu be programmed to ignore instruction show cycles so as to not impact u-bus performance; set siumcr[no show]. synchronization will only occur at changes in program flow boundaries, and cannot be forced by the readi module. synchronizat ions on errors, overflows, as well as periodic synchronizations will not be deterministic to the neares t instruction, but to the next taken change in program flow. the start of program trace (enabled via any mean s) will be also deferred to the next change in program flow. program trace synchronization messag es are of the following types: ? direct branch ? indirect branch ? direct branch with compressed code ? indirect branch with compressed code ? resource full readi module mpc561/mpc563 reference manual, rev. 1.2 24-44 freescale semiconductor 24.8.2.4.1 direct branch synchronization message the program trace direct branch synchronization me ssage has the following formats depending on how the ptsm bit in the mc register is configured: figure 24-24. direct branch synchronization message format (ptsm = 0) figure 24-25. direct branch synchronization message format (ptsm = 1) 24.8.2.4.2 indirect branch synchronization message the program trace indirect branch synchronization message has the fo llowing formats depending on the setting of mc[ptsm]: figure 24-26. indirect branch synchronization message format (ptsm = 0) figure 24-27. indirect branch synchronization message format (ptsm = 1) 24.8.2.4.3 direct branch synchroniza tion message with compressed code for compressed code support, six addi tional bits indicate the starting bi t address within the word of the compressed instruction. the program trace direct branch synchronization with compressed code message has the following formats dependi ng on the setting of mc[ptsm]: tcode (11) messages cancelled full target address [1 bit] [1 ? 23 bits] min length = 8 bits [6 bits] max length = 30 bits tcode (12) full target address [1 ? 23 bits] [6 bits] [1-8 bits] messages cancelled min length = 8 bits max length = 37 bits tcode (12) full target address [1 ? 23 bits] [6 bits] [1 bit] messages cancelled min length = 8 bits max length = 30 bits tcode (12) full target address [1 ? 23 bits] [6 bits] [1-8 bits] messages cancelled min length = 8 bits max length = 37 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-45 figure 24-28. direct branch synchronization message format with compressed code (ptsm = 0) figure 24-29. direct branch synchronization message format with compressed code (ptsm = 1) 24.8.2.4.4 indirect branch synchroniz ation message with compressed code for compressed code support, six addi tional bits indicate the starting bi t address within the word of the compressed instruction. th e program trace indirect branch s ynchronization with compressed code message has the following formats de pending on the setting of mc[ptsm]: : figure 24-30. indirect branch synchronization message format with compressed code (ptsm - 0) : figure 24-31. indirect branch synchronization message format with compressed code (ptsm = 1) bit pointer format is shown in figure 24-22 and bit address format is described in table 24-26 . 24.8.2.4.5 resource full message when more than 256 instructions have run without a branch being taken a pr ogram trace resource full message will be generated that indicates the maxi mum i-cnt value has been reached. the i-cnt field has a maximum width of 8 bits. tcode (60) bit address [1 ? 23 bits] [6 bits] max length = 35 bits full target address [6 bits] min length = 13 bits tcode (60) bit address [1 ? 23 bits] [6 bits] max length = 43 bits full target address [6 bits] min length = 14 bits sequence count [1-8 bits] tcode (61) full target address [1 ? 23 bits] [6 bits] [6 bits] bit pointer min length = 13 bits max length = 35 bits tcode (60) bit pointer [1 ? 23 bits] [6 bits] max length = 43 bits full target address [6 bits] min length = 14 bits sequence count [1-8 bits] readi module mpc561/mpc563 reference manual, rev. 1.2 24-46 freescale semiconductor the total instruction count can be found by adding 256 for each program trace full message received to the sequence count of the direct or indi rect branch trace message that follo ws the resource full message. the program trace full message has the following format: figure 24-32. program trace full message format at this time, the program trace seque ntial count full code is the only defined option for this message. 24.8.2.5 error messages branch trace error messages are expl ained within applicable functiona l areas, such as data trace, watchpoint, and program trace s ections of this chapter. 24.8.2.6 relative addressing the relative address feature is compliant with the ieee-isto 5001 - 1999 recommendations, and is designed to reduce the number of bits transmitte d for addresses of indirect branch messages. the address transmitted is relative to the address of the previous branch trace me ssage. it is generated by xoring the new address with the previous address, and then using only the results up to the most significant ?1? in the resu lt. to recreate this addres s, an xor of the (most-si gnificant 0-padded) message address with the previously decoded address gives the current address. figure 24-33 shows how a relative address is generated and how it can be used to recr eate the original address. table 24-29. resource codes error code description 0000 program trace sequential count full 0001-1111 vendor defined or reserved tcode (27) resource code [1 - 8 bits] max length = 10 bits [6 bits] min length = 7 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-47 figure 24-33. relative address generation and re-creation 24.8.3 queue overflow program trace error message a trace overrun error occurs when a trace message cannot be queued due to the que ue being full, provided program trace is enabled. the overrun error causes the message queue to be flushed, and an erro r message to be queued. the error code within the error message in dicates that either a program/dat a/ownership trace overrun error has occurred or that only a program trace overrun has occurred. the ne xt btm will be a synchronization message. refer to table 24-20 . the error message has the following format: figure 24-34. error message (queue overflow) format 24.8.4 branch trace message operation 24.8.4.1 btm capture a nd encoding algorithm btm is accomplished by capturing inst ruction fetch information from th e u-bus and instruction execution information from the rcpu (vf and vfls signals), and combining them to generate program trace messages. previous address (a1) = 0x0003 fc 01, new address (a2) = 0x0003 f365 a1 = 0000 0000 0000 0011 1111 1100 0000 0001 a2 = 0000 0000 0000 0011 1111 0011 0110 0101 address message (m1) = 1111 0110 0100 m1 = 0000 0000 0000 0000 0000 1111 0110 0100 a1 a1 = 0000 0000 0000 0011 1111 1 100 0000 0000 m1 = 0000 0000 0000 0000 0000 1111 0110 0100 a2 = 0000 0000 0000 0011 1111 0011 0110 0101 address re-creation: message generation: m1 = a2 + + + tcode (8) error code (0b0 0000, length = 11 bits [5 bits] [6 bits] 0b0 0001, 0b0 0010, 0b0 0111) readi module mpc561/mpc563 reference manual, rev. 1.2 24-48 freescale semiconductor 24.8.4.2 instructi on fetch snooping instruction fetches are snooped on the u-bus. there is a one-to-one corresponde nce between instruction fetches marked with the u-bus program trace attri bute and the indication of rcpu vf signal (only 3, 4, 5, and 6) between two s ynchronization events. since u-bus program trace attribute occurs after the i ndication of vf, it is latched and paired with the nearest (previous) unpaired vf (3, 4, 5, and 6) i ndication to determine th e instruction address. for all other vf indications , except 3, 4, 5, and 6, it is not possibl e to determine the instruction address. 24.8.4.3 instruction execution tracking instruction execution tracking is performed by capturing the rcpu vf and vfls signals, and decoding them to infer the state of the processor. the rcpu vf signals indicate two classi fications of information: ? the current instruction type which is being load ed into the rcpu instruction queue. for further details refer to the rcpu reference manual . ? the number of instructions which are currentl y being flushed from the rcpu instruction queue. for further details refer to the rcpu reference manual . 24.8.4.4 instruction flush cases the various conditions under which th e rcpu may signal instruction flus hes of the rcpu prefetch queue or rcpu history buffer are: 1. a taken branch (direct, indirect , interrupt or exception) will ca use the instruction prefetch queue (which contains instructions from the now old st ream) to be flushed, and fetching will start from the branch target stream. the sequential instru ction count will be updated to reflect this. 2. a mispredicted branch will cause instructions fetched from the new stream to be flushed, and fetching will resume from the old stream. it wi ll also require a program trace message to be cancelled and the tra ce to be corrected. 3. an exception can cause cancel lation of multiple taken branches which may require cancelling multiple program trace messages. 24.8.5 branch trace message queueing readi implements a queue 16 or 32 messages deep (depending on the sili con version) for program trace, data trace, and ownership trace me ssages. messages that enter the que ue are transmitte d via the output auxiliary port in the order in which they are queued. note if multiple trace messages need to be queued at the same time, program trace messages will have the highest priority unless the data trac e buffers are full, in which case the data trace messages are given temporary higher priority than the program trace messages. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-49 24.8.6 btm timing diagrams figure 24-35. direct branch message figure 24-36. indirect branch message figure 24-37. indirect branch message with compressed code mcko mseo mdo[7:0] 00000011 0010 00000000 tcode = 3 number of sequential instructio ns since last taken branch = 72 don?t care data (idle clock) 0001 don?t care data (idle clock) tcode = 4 number of sequential instructi ons since last taken branch = 4 relative address = 0x534 mcko mseo mdo[7:0] 00000100 00000001 00110100 00000101 00000000 tcode = 59 (0x3b) bit address = 3 relative address = 0x432 don?t care data (idle clock) number of sequential instructions since last taken branch = 4 mcko mseo mdo[7:0] 00111011 00000001 10000011 00001100 00000001 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 24-50 freescale semiconductor figure 24-38. program trace correction message figure 24-39. error message (program/data/ownership trace overrun) figure 24-40. direct branch synchronization message tcode = 10 (0xa) number of instructions corrected in trace= 65 don?t care data (idle clock) mcko mseo mdo[7:0] 01001010 00010000 00000000 tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 tcode = 11 (0xb) number of messages cancelled = 0 full target address = 0x654320 don?t care data (idle clock) mcko mseo mdo[7:0] 00001011 00000000 00100000 01000011 01100101 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-51 figure 24-41. indirect branch synchronization message figure 24-42. direct branch synchronization message with compressed code figure 24-43. indirect branch synchronization message with compressed code 24.8.7 program trace guidelines refer to section 24.6.5.1, ?program trace guidelines ,? for further details. tcode = 12 (0xc) number messages cancelled = 0 full target address = 0x654320 don?t care data (idle clock) mcko mseo mdo[7:0] 00001100 00000000 00100000 01000011 01100101 00000000 tcode = 60 (0x5c) bit address = 9 full target address = 0xca864 don?t care data (idle clock) mcko mseo mdo[7:0] 01111100 01000010 10000110 11001010 00000000 tcode = 61 (0x5d) bit address = 9 full target address = 0xca864 don?t care data (idle clock) mcko mseo mdo[7:0] 01111101 01000010 10000110 11001010 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 24-52 freescale semiconductor 24.9 data trace this section details the data trac e mechanism supported by readi. data trace is implemented via data write messaging (dwm) and data read messa ging (drm), as per the ieee-isto 5001 - 1999. 24.9.1 data trace for the load/store bus (l-bus) the l-bus allows the rcpu to perform loads and stores, and the l2u to read and write the l-bus resources. snooping for data trace on the l-bus requires the readi m odule to handle the full range of l-bus cycles. this includes various ca ses of pipelining and aborted cycles. data trace requires snooping the l-bus cycles, and st oring the information for qualifying accesses (based on enabled features and matching target addresses). th e readi module traces all data accesses that meet the selected range and attributes. this includes all rcpu initiated accesse s and all l-bus accesses. l-bus data cycles can have data sizes of 8, 16, or 32 bits.the readi module supports all three data sizes. in full port mode, 16-bit accesses shift out 24 bits of data so the tool can diff erentiate them from 8-bit accesses. note in early versions of the readi module, 8-bit data cannot be differentiated from 16-bit data when the 8 msbs are set to zero. see the device mask set errata list for customer information. 24.9.2 data trace message formats data trace messages are of five types: ? data write ? data read ? data write synchronization ? data read synchronization ? error message 24.9.2.1 data write message the data write message contains the data write value and the address of the target location, relative to the previous data trace message. the data write message has the following format: figure 24-44. data write message format tcode (5) relative address [1 to 25 bits] max length = 63 bits [8, 16, or 32 bits] data value [6 bits] min length = 15 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-53 24.9.2.2 data read message the data read message contains the data read value a nd the address of the target location, relative to the previous data trace message. the data read message has the following format: figure 24-45. data read message format 24.9.2.3 data trace synchronization messages a data trace synchronization message shall be transmitted via the auxili ary port (provided data trace is enabled) for the following conditions: ? initial data trace message upon exit of any syst em reset will be a synchronization message. ? upon exit of sleep, deep-sleep and low power dow n mode, the first data trace message will be a synchronization message. ? initial data trace me ssage upon exit of background debug mode . upon exiting bdm, the next data trace message will be a synchronization message. ? when data trace is enabled, the first data tr ace message will be a synchronization message. ? after 255 data trace messages have been queued without sync hronization, the next data trace message will be a synchronization message. ? upon assertion of an event in (evti ) signal. if the readi module is not disabled at reset, when evti asserts, if the ec field is 0b00 in the dc register, the next data trace message will be a synchronization message. ? upon occurrence of a watchpoint, the next data tr ace message will be a synchronization message. ? occurrence of queue overrun. a data trace overrun error occurs when a trace message cannot be queued due to the queue being full (provided data trace is enabled) . this causes the message queue to be flushed, and an error message is placed as the first message in th e queue. the error code within the error message indicates that progra m/data/ownership trace overrun has occurred. the next data trace message will be a synchronization message. data trace synchronization messages provide the full address (without leading zeros) and ensure that development tools fully synchronize with data tr ace regularly. synchroniza tion messages provide a reference address for subsequent dtms, in which onl y the unique portion of the data trace address is transmitted. data trace synchronization messages are of two types: ? data write ? data read tcode (6) relative address [1 to 25 bits] max length = 63 bits [8, 16, 24, or 32 bits] data value [6 bits] min length = 15 bits readi module mpc561/mpc563 reference manual, rev. 1.2 24-54 freescale semiconductor 24.9.2.4 data write synchronization message the data write synchronization me ssage has the following format: figure 24-46. data write synchronization message format 24.9.2.5 data read synchronization messaging the data read synchronization me ssage has the following format: figure 24-47. data read synchronization message format 24.9.2.6 relative addressing refer to section 24.9.2.6, ?relative addressing ,? for further details. 24.9.3 queue overflow data trace error message a program/data/ownership trace overrun error or data trace error occurs when a trace message cannot be queued due to the queue being full, provided data trace is enabled. the overrun error causes the message queue to be flushed, and an erro r message to be queued. the error code within the error message indicates that a pr ogram/data/ownership trace ove rrun error has occurred. the next dtm will be a sync hronization message. refer to table 24-20 . the error message has the following format: figure 24-48. error message (queue overflow) format 24.9.4 data trace operation data trace is performed by snooping the l-bus for read or write cycles. data tr ace functions are enabled by setting the appropriate fields in the dc register and the dta register s. for details on field configuration, tcode (13) data value [1 to 25 bits] max length = 64 bits [8, 16, or 32 bits] messages cancelled [1 bit] [6 bits] min length = 16 bits full target address tcode (14) data value [1 to 25 bits] max length = 64 bits [8, 16, or 32 bits] messages cancelled [1 bit] [6 bits] min length = 16 bits full target address tcode (8) error code (0b0 0000, length = 11 bits [5 bits] [6 bits] 0b0 0001, 0b0 0010, 0b0 0111) readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-55 refer to section 24.6.1.4, ?development control register (dc) ,? and section 24.6.1.9, ?data trace attributes 1 and 2 registers (dta1 and dta2) ,? respectively. data trace flow is depicted in figure 24-49 . figure 24-49. data trace flow diagram for non-pipelined access idle data read/write detected store address cancelled queue message cycle no yes address in either wait for data phase store data no ? range data error ? yes reset readi module mpc561/mpc563 reference manual, rev. 1.2 24-56 freescale semiconductor 24.9.5 data trace windowing data trace windowing is achieved via the address ra nge within the dtea and th e dtsa fields of the dta registers. all l-bus accesses which fall within thes e two address ranges, provided the address ranges are enabled in either dta register, are candidates to be transmit ted. data read and/or da ta write trace may be enabled via the ta field of the data trace attributes registers (dta). note data trace ranges are word aligned. therefore, the address range fields (dtea and dtsa) of the dta registers are only 23 bits wide and, as such, should be assigned by the tool with the 23 most significant bits of the intended 25-bit range address, i.e. th e 2 lsb of the address are not used.) note the off-core mpc500 special purpose register (spr) map cannot be distinguished from the normal memo ry map accesses via the defined address range control. if data trace ra nges are set up such that the off-core mpc500 spr map falls within active ranges, then accesses to these off-core mpc500 sprs will be traced, and the me ssages will not be distinguishable from accesses to normal memory map space. off-core mpc500 sprs typically exist in the 8-kbyte ? 16-kbyte lowest memory block (0x2000 - 0x3ff0). if data or peripherals are mapped to this space, load/stores to mpc500 sprs will be indistinguishable from data or peripheral accesses. 24.9.6 special l-bus cases special l-bus cases are ha ndled as described in table 24-30 . 24.9.7 data trace queuing for queuing program trace, data trace, and ownership tr ace messages, readi implements a queue 32 messages deep (the queue is 16 messa ges deep on some versions; refer to device errata). messages that enter the queue are transmitted vi a the output auxiliary port in the order in which they are queued. table 24-30. special l-bus case handling special case action l-bus cycle aborted cycle ignored l-bus cycle with data error message discarded l-bus cycle terminated due to address error cycle ignored l-bus cycle completed without error cycle captured and transmitted l-bus cycle initiated by readi (read/write access) cycle ignored l-bus cycle is an instruction fetch cycle ignored data storage interrupt cycle ignored system reset cycle ignored readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-57 note if multiple trace messages need to be queued at the same time, program trace messages have a higher priority for que ue entry than data trace messages, unless the data trace buffers are full, in which case the data trace messages are given temporary higher priority than the program trace messages. 24.9.8 throughput and latency 24.9.8.1 assumptions fo r throughput analysis ? all accesses are data trace only ? 56-mhz operation ? output signals are always free (not in middle of transmission) when requested ? relative address field for da ta trace messages is 20 bits ? data field for data tr ace messages is 32 bits ? one idle clock between data trace messages 24.9.8.2 throughput calculations the data (read or write) trace message is 58 bits (6 [tcode] + 20 [relativ e address] + 32 [data]). data trace messages are transmitted out via the mdo si gnals. hence it will take eight clocks (58 bits/8 mdo signals) to send a message. there will be one idle clock before th e next data trace message can be sent. at 56 mhz, it will take 161ns ((8+ 1) x 17.8) to transmit the message. therefore, the average number of da ta trace messages that can be tran smitted out is 6.2 million (1/161ns) per second, or 24.8 million bytes of read/write data per second. 24.9.9 data timing diagrams figure 24-50. date write message tcode = 5 relative address = 0x318 data = 0x4a don?t care data (idle clock) mcko mseo mdo[7:0] 00000101 11000110 01001010 00000000 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 24-58 freescale semiconductor figure 24-51. data read message figure 24-52. data write synchronization message figure 24-53. data read synchronization message relative address = 0x1d0a9 don?t care data (idle clock) mcko mseo mdo[7:0] tcode = 6 data = 0x1234 01000110 00101010 01110100 00110100 00010010 00000000 don?t care data (idle clock) tcode = 13 (0xd) number of messages cancelled = 0 full target address = 0x1468ace data = 0xbe mcko mseo mdo[7:0] 00001101 00000000 11001110 10001010 01000110 00000001 10111110 00000000 00000000 don?t care data (idle clock) tcode = 14 (0xe) number of messages cancelled = 0 full target address = 0x1468ace data = 0x5c mcko mseo mdo[7:0] 00001110 00000000 11001110 10001010 01000110 00000001 01011100 00000000 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-59 figure 24-54. error message (program/data/ownership trace overrun) 24.10 read/write access the read/write access feature allows access to inte rnal memory-mapped space via the auxiliary port. read/write mechanism supports si ngle and block, reads and writes. 24.10.1 functional description the readi module is capable of bus mastership on the l-bus and for setting up and reading data and status. all accesses are setup and initiated to the read /write access register (r wa) and upload/download information register (udi) via the four auxi liary access public messages: device ready for upload/download, upload request (tool requests in formation), download re quest (tool provides information), upload/download information (device/tool provides information). read/write access features are enab led by setting the appropria te fields in the rwa register. for details on field configuration, refer to section 24.6.1.7, ?read/write access register (rwa) .? the functional flow for read/write access to memory-mapped locations and mpc500 registers is depicted in figure 24-59 . figure 24-55. target ready message figure 24-56. read register message tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 tcode (16) max length = 6 bits [6 bits] min length = 6 bits tcode (17) opcode [8 bits] max length = 14 bits [6 bits] min length = 14 bits readi module mpc561/mpc563 reference manual, rev. 1.2 24-60 freescale semiconductor figure 24-57. write register message figure 24-58. read/write response message tcode (18) opcode [8 bits] max length = 94 bits [8-80 bits] register value [6 bits] min length = 22 bits tcode (19) return value [8-80 bits] max length = 86 bits [6 bits] min length = 14 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-61 figure 24-59. read/write access flow diagram 24.10.2 write operation to memory-m apped locations and spr registers 24.10.2.1 single write operation for a single write access to memory-mapped locations and spr registers, the following sequence of operations need to be perf ormed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmitti ng download request public message (tcode=18). download request public cnt= 0 decrement cnt no read/write ? message (tcode 18) tool sends to device idle module read/write device ready for upload/ (tcode 16) latch data download public message device sends to tool upload/download (tcode 19) information public message tool sends to device write read ? read/write ? upload/download (tcode 19) information public message device sends to tool write read sc = 0 yes reset increment address readi module mpc561/mpc563 reference manual, rev. 1.2 24-62 freescale semiconductor 2. the download request publ ic message contains: a) tcode(18) b) access opcode 0xf which signals th at subsequent data needs to be stored in the rwa register. c) configure the rwa register fields as follows: ? start/complete (1 to i ndicate start access) -> sc ? read/write address (write address) -> rwad ? read/write (1 to indicate a write access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (write data) -> wd ? privilege (user data/instruction, s upervisor data/instruction) -> prv ? map select (select memo ry map, 0b0 or 0b1) -> map 0 = normal memory access 1 = secondary memory map (spr) ? access count (0 to indica te single access) -> cnt 3. after completion of the write operation, the de vice ready for upload/download public message (tcode=16) is transmitted to the tool indicat ing that the device is ready for next access. 4. the sc bit is cleared to indicate that the write access is complete. 24.10.2.2 block write operation for a block write access to memory -mapped locations, the following se quence of operations need to be performed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmitti ng download request public message (tcode = 18). 2. the download request publ ic message contains: a) tcode(18) b) access opcode 0xf which signals th at subsequent data needs to be stored in the rwa register. c) configure the rwa register fields as follows ? start/complete (1 to i ndicate start access) -> sc ? read/write address (starting wr ite address of block) -> rwad ? read/write (1 to indicate a write access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (write data) -> wd ? privilege (user data/instruction, s upervisor data/instruction) -> prv ? map select (select memory map 0b0) -> map ? access count (non zero number to indica te size of block access) -> cnt 3. after completion of this write operation, the device ready for upload/ download public message (tcode = 16) is transmitted to the tool indi cating that the device is ready for next access. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-63 4. the specified address (s tored in rwad field) is incremented to the next word size and the number in the cnt field is decremente d. the sc field is not cleared. 5. the tool transmits the next upload/downloa d information public message (tcode = 19). 6. the upload/download informati on public message contains: a) tcode(19) b) write data (write data -> udi) 7. after the completion of this write operation, the device ready fo r upload/download public message (tcode = 16) is transmitted to the tool indi cating that the device is ready for next access. 8. the specified address (in rwad field) is incremen ted to the next word si ze and the number in the cnt field is decremented. th e sc field is not cleared. 9. steps 5 through 8 are repeated unt il the count value in the cnt fiel d of rwa register equals zero. the sc bit is cleared to indicat e end of the block write access. note for downloading write data to the de vice for block write operation, the download request public message (tco de = 18) should not be used to write subsequent data to the udi regist er. data written to the udi register (via download request message, tcode 18) is not used by the device for any read/write operation. 24.10.3 read operation to memory-m apped locations and spr registers 24.10.3.1 single read operation for a single read access to memory-mapped locatio ns and spr registers, the following sequence of operations need to be perf ormed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmitti ng download request public message (tcode = 18). 2. the download request publ ic message contains: a) tcode(18) b) access opcode 0xf which signals th at subsequent data needs to be stored in the rwa register. c) configure the rwa fields as follows: ? start/complete (1 to i ndicate start access) -> sc ? read/write address (read address) -> rwad ? read/write (0 to indicate a read access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (0xxxxxxxx x-> wd [don?t care]) ? privilege (user data/instruction, s upervisor data/instruction) > prv ? map select (select memory map, 00 or 01) -> map ? access count (0 to indicate single access) -> cnt 3. data read from the specified addr ess is stored in the udi register. readi module mpc561/mpc563 reference manual, rev. 1.2 24-64 freescale semiconductor 4. once the read access is completed, the upload/ download information public message (tcode = 19) is transmitted to the tool along with the data read from the udi register. this message also indicates that the device is ready for next access. 5. the sc field in the rwa register is cleared. 24.10.3.2 block read operation for a block read access to memory-mapped locations and spr registers, the following sequence of operations need to be perf ormed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmitti ng download request public message (tcode = 18). 2. the download request publ ic message contains: a) tcode(18) b) access opcode 0xf which signals th at subsequent data needs to be stored in the rwa register. c) configure the rwa fields as follows: ? start/complete (1 to i ndicate start access) -> sc ? read/write address (starting r ead address of block) -> rwad ? read/write (0 to indicate a read access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (0xxxxxxxx x-> wd [don?t care]) ? privilege (user data/instruction, s upervisor data/instruction) > prv ? map select (select memory map 0b0) -> map ? access count (non-zero number to indicate block access) -> cnt 3. data read from the specified addr ess is stored in the udi register. 4. after the completion of this read operation, the upload/download info rmation public message (tcode=19) is transmitted to the tool along with the data read from the udi register. this message also indicates that the device is ready to perf orm the next read operation. 5. the specified address (in rwad field) is incremen ted to the next word si ze and the number in the cnt field is decremented. th e sc field is not cleared. 6. the data read from the new addre ss is stored in the udi register. 7. steps 4 through 7 are repeated unt il the count value in the cnt fiel d of rwa register equals zero. the sc bit is cleared to indicate end of the block read access. 24.10.4 read/write access to internal readi registers 24.10.4.1 write operation for a write access to intern al readi registers, the following sequenc e of operations need to be performed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmitti ng download request public message (tcode = 18). readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-65 2. the download request publ ic message contains: a) tcode(18) b) access opcode, which specifies th e register where data needs to be written, (e.g., access opcode 0x14 indicates that dta1 regist er is the target register). c) data to be written to the register. 3. after the data has been written to the targeted register, the device rea dy for upload/download public message (tcode = 16) is tr ansmitted to the tool indicating that the device is ready for next access. 24.10.4.2 read operation for a read access to internal readi registers, the fo llowing sequence of operatio ns need to be performed via the auxiliary port: 1. the tool confirms that the de vice is ready before transmit ting upload request public message (tcode = 17). 2. the upload request public message contains: a) tcode(17) b) access opcode, which specifies the register wher e data needs to be read from, (for example, access opcode 0x14 indicates that dta1 register is the target register). 3. the upload/download information public message (tcode=19) is transmitted to the tool along with the data read from the targeted register indi cating that the device is ready for next access. 24.10.5 error handling the readi module handles the various error conditions in the manner shown in the following sections. 24.10.5.1 access alignment the readi module will force address alignment based on the word size field (sz) va lue. if the sz field indicates word (32-bit) access, the least significant two bits of the re ad/write address field (rwad) are ignored. if the sz field indicates ha lf-word (16-bit) access, the least signi ficant bit of the read/write address field (rwad) is ignored. 24.10.5.2 l-bus address error an address error occurs on the l-bus when the addre ss phase of a cycle is not completed normally. this could occur because of address not being valid or the address map not being valid. in such cases: 1. the access is terminated without retrying. 2. the sc bit of the rwa is rese t. block accesses do not continue. 3. the error message (tcode = 8) is tr ansmitted (error code 0b00011). refer to table 24-20 . 24.10.5.3 l-bus data error l-bus data error is signalled due to: readi module mpc561/mpc563 reference manual, rev. 1.2 24-66 freescale semiconductor ? l-bus data phase error. ? u-bus address phase error (f or a l-bus to u-bus cycle). ? u-bus data phase error (for a l-bus to u-bus cycle). l-bus data error conditions are signa lled along with the transfer acknow ledge for the access. l-bus data error conditions may occur be cause of privilege violati ons, access to prot ected memory, etc. in such cases, for a read access, the err bit of the udi is set, and the dv bit in the udi is reset at the termination of the access. for a write access, an error public message (tcode = 8) is transmitted (error code 0b00011). 24.10.6 exception sequences the following cases are defined for se quences of the read/write protocol that differ from those described in the above sections: 1. if the sc bit is set to start readi read/write accesses, without valid values in the rwad, then an l-bus address error may occur, whic h is handled as described above. 2. if a block access is in progress with all the cy cles not yet completed, and the rwa is written to again, (with or without modifications), then the block access is terminated at the boundary of the nearest completed access. the resulting data is discarded and not written to the udi. if a new access has been programmed in the rwa register, then that access wi ll start once the controller has recovered. 3. when a block access is in progress with all the cy cles not yet completed, writing the sc bit to 0 in rwa register will terminate the block access and device will send out device ready for upload/download message. 4. if a any type (single/block) of access is in prog ress with the cycles not yet completed, and system reset occurs, the device will send out an error message. the access wi ll be terminated and the sc bit will be reset. refer to table 24-20 . 5. if any type of (single/block) of access is requested while system is in reset, the device will send out an error message. the access will not be started and the sc bit will be reset. 24.10.7 secure mode for details refer to section 24.2.2, ?security .? 24.10.8 error messages 24.10.8.1 read/write access error an error message is sent out when an l-bus access erro r or data error on a write access occurs. the error code within the error message indicates that an l-bus address or l-bus data error occurred. for other error handling, see section 24.10.5, ?error handling .? for a list of error codes, refer to table 24-20 . readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-67 the error message has the following format: figure 24-60. error message (read/write access error) format 24.10.8.2 invalid message an error message is sent out when an invalid mess age is received by readi. the error code within the error message indicates that an in valid tcode was detected in the auxiliary inpu t messages by the signal input formatter. refer to table 24-20 . the error message has the following format: figure 24-61. error message (invalid message) format note if the tcode is valid, then readi wi ll expect that the corr ect number of packets have been received and no further checking will be performed. if the number of packets received by read i is not correct, readi response is not deterministic. 24.10.8.3 invalid access opcode an error message is sent out when an invalid access opcode is received by read i. the error code within the error message indicates that an invalid access opcode was detected in the auxiliary input messages by the signal input formatter. refer to table 24-20 . the error message has the following format: figure 24-62. error message (invalid access opcode) format 24.10.9 faster read/write acce sses with default attributes read/write access throughput may be increased by taki ng advantage of the defaul t settings of the rwa register, and truncating the least significant zero bits of the download request message. for example, to read a word from the default memory map, with default attributes, a dow nload request message that selects tcode (8) error code (0b00011) length = 11 bits [5 bits] [6 bits] tcode (8) error code (0b00100) length = 11 bits [5 bits] [6 bits] tcode (8) error code (0b00101) length = 11 bits [5 bits] [6 bits] readi module mpc561/mpc563 reference manual, rev. 1.2 24-68 freescale semiconductor the rwa register, and transmits the sc, rwad, rw fiel ds only is sufficient. th is message will contain 41 bits instead of the 94 bits for writing the full contents of the rwa register. see table 24-11 and section 24.6.4, ?partial register updates ,? for rwar and partial register update details respectively. note the last data bit transmitted in th e download request message (tcode 18) will always be the msb of the regist er referenced by the opcode (sc field in the case of the rwa register). 24.10.10 throughput and latency throughput analysis has been performed for various r ead/write access cases such as single write, block write, single byte read, single word read, block byt e read, block word read accesses to memory-mapped locations. data is presented for the two cases when th e rwa register is written partially and completely. 24.10.10.1 assumptions fo r throughput analysis ? all accesses are single read accesses only. ? mcki running at 28 mhz. ? mcko running at 56 mhz. ? 56-mhz internal operation. ? five clock internal l-bus access (read) ? output signals always free (not in mi ddle of transmission) when requested. ? one idle clock between read messages. ? no delay from tool in responding ? tool keeps up with readi port. table 24-31. throughput comparison for fpm and rpm mdo/mdi configurations access type reduced port mode 2 mdo / 1 mdi pins full port mode 8 mdo / 2 mdi pins full rwar update partial rwar update full rwar update partial rwar update single write access to memory-mapped location ? word and byte access (in million messages per second) 0.28 0.35 0.53 0.65 single read access to memory-mapped location ? word access (in million messages per second) 0.25 0.51 0.52 1.05 single read access to memory-mapped location ? byte access (in million messages per second) 0.27 0.56 0.53 1.05 block write access to memory-mapped locations ? 64-kbyte block (word and byte) write access (in 64-kbyte block writes per second) 9 9 17 17 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-69 24.11 read/write timing diagrams figure 24-63. block write access block read access to memory-mapped locations ? 64-kbyte block (word) read access (in 64-kbyte block writes per second) 32 32 77 77 block read access to memory-mapped locations ? 64-kbyte block (byte) read access (in 64-kbyte block writes per second) 61 61 95 95 table 24-31. throughput comparison for fpm and rpm mdo/mdi configurations access type reduced port mode 2 mdo / 1 mdi pins full port mode 8 mdo / 2 mdi pins full rwar update partial rwar update full rwar update partial rwar update msei mseo mdi mdo download request message upload/download information message device ready for upload/ download device ready for upload/ download tcode 18 tcode 19 tcode 16 tcode 16 readi module mpc561/mpc563 reference manual, rev. 1.2 24-70 freescale semiconductor figure 24-64. block read access figure 24-65. device ready for upload/download request message msei mseo mdi mdo download request message tcode 18 upload/download information message tcode 19 upload/download information message tcode 19 mcko mseo mdo[7:0] 00010000 00000000 00000000 tcode = 16 (0x10) don?t care data (idle clock) readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-71 figure 24-66. upload request message figure 24-67. download request message mcki msei mdi[1:0] 01 00 01 11 11 00 00 00 tcode = 17 (0x11) access opcode = 15 (rwa register) (0xe) don?t care data (idle clock) don?t care data (idle clock) tcode = 18 (0x12) access opcode = 10 (dc register) (0xa) ec = 0b00 tm = 0b100 dpa = 0b0 dme = 0b0 dor = 0b0 data written to dc register: mcki msei mdi[1:0] 10 00 01 10 10 00 00 00 00 01 00 00 readi module mpc561/mpc563 reference manual, rev. 1.2 24-72 freescale semiconductor figure 24-68. upload/download information message figure 24-69. error message (invalid access opcode) 24.12 watchpoint support this section details the watchpoint support features of the readi module. the readi module provides watchpoint messaging via the auxiliary por t, as defined by the ieee-isto 5001-1999. readi is not compliant with all the breakpoint/watchpoint requireme nts defined in the ieee-isto 5001 standard. watchpoint trigger a nd breakpoint/watchpoint control registers are not implemented. watchpoint setting via readi can onl y be done using the bdm protocol. 24.12.1 watchpoint messaging the readi module provides watchpoint messag ing using ieee-isto 5001-1999 defined public messages. the watchpoint status signals from th e rcpu are snooped, and when watchpoints occur, a message is sent to the signal out put formatter to be messaged out (t he general message queue is bypassed to prevent watchpoint messages from being cancelled in the event of a queue overflow). the watchpoint tcode = 19 (0x13) dv =1 err = 0 data read = 0x3c16 (16 bit read access) don?t care data (idle clock) mcko mseo mdo[7:0] 01010011 00010110 00111100 00000000 tcode = 8 error code = 0b00101 (invalid access opcode) don?t care data (idle clock) mcko mseo mdo[7:0] 01001000 00000001 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-73 message has the second hi ghest priority. refer to section 24.7.3, ?message priority ,? for further details on message priorities. the watchpoint message contains the watchpoint c ode which indicates all the unique watchpoints have occurred since the last watchpoint message. if dupl icate watchpoints occur before the watchpoint message is sent out, a watchpoint overrun message is genera ted. the watchpoint source field will indicate which watchpoints occurred. the watchpoint message has the following format: figure 24-70. watchpoint message format 24.12.1.1 watchpoint source field the watchpoint source field is outlined in table 24-32 . 24.12.2 watchpoint overrun error message a watchpoint overrun error occurs when the same watc hpoint occurs multiple times before the first occurrence of that watchpoint has be en messaged out. the watchpoint me ssage (which has information of all the watchpoints that occurred prior to the dete ction of the same watchpoint occurring multiple times) will be sent before the error message can be sent. the overrun error causes further watc hpoint occurrences to be ignored, until the error message has been sent. the error code within the er ror message indicates that a watchpoi nt overrun error has occurred. refer to table 24-20 . the error message has the following format: figure 24-71. error message (watchpoint overrun) format table 24-32. watchpoint source watchpoint source description 0bxxxxx1 first l-bus watchpoint (lw0) 0bxxxx1x second l-bus watchpoint (lw1) 0bxxx1xx first i-bus watchpoint (iw0) 0bxx1xxx second i-bus watchpoint (iw1) 0bx1xxxx third i-bus watchpoint (iw2) 0b1xxxxx fourth i-bus watchpoint (iw3) length = 12 bits tcode (15) watchpoint source [6 bits] [6 bits] tcode (8) error code (0b00110) length = 11 bits [5 bits] [6 bits] readi module mpc561/mpc563 reference manual, rev. 1.2 24-74 freescale semiconductor 24.12.3 synchronization upon occurrence of a watchpoint, the next program a nd data trace message w ill be a synchronization message (provided program a nd data trace are enabled). 24.12.4 watchpoint timing diagrams figure 24-72. watchpoint message figure 24-73. error message (watchpoint overrun) 24.13 ownership trace this section details the ownership tra ce support features of the readi module. ownership trace provides a macrosc opic view, such as task flow re construction, when debugging software written in a high level (or object-orien ted) language. it offers the highest level of abstraction for tracking operating system software ex ecution. this is especially useful when the developer is not interested in debugging at lower levels. don?t care data (idle clock) tcode = 15 (0xe) watchpoint source = 0b110001 this indicates that first l-bus watchpoin t (lwo), third i-bus watchpoint (iw2), and fourth i-bus watchpoint (iw3) have occurred. mcko mseo mdo[7:0] 01001111 00001100 00000000 tcode = 8 error code = 0b00110 (watchpoint overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 10001000 00000001 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-75 24.13.1 ownership trace messaging ownership trace information is messaged via the aux iliary port using an owners hip trace message (otm). the ownership trace register (ot), which can be accessed via auxiliar y port, is updated by the operating system software to provide task/p rocess id information. when new info rmation is updated in the register by the embedded processor, it is me ssaged out via the auxiliary port, al lowing development tools to trace ownership flow. ownership trace information is mess aged out in the following format: figure 24-74. ownership trace message format 24.13.2 queue overflow ownership trace error message a program/data/ownership tr ace overrun error occurs wh en a trace message cannot be queued due to the queue being full, provided ownership trace is enabled. the overrun error causes the messag e queue to be flushed, and a erro r message to be queued. the error code within the error message indicates that a pr ogram/data/ownership trace ove rrun error has occurred. refer to table 24-20 . the error message has the following format: figure 24-75. error message format 24.13.2.1 otm flow ownership trace messages are generated when the operati ng system (privileged supervisor task) writes to the memory-mapped ownership trace register. the following flow desc ribes the otm process. 1. the ot register is a memory-mapped register, whose address is located in the uba. the ot register address can be read from th e uba register by the ieee-isto 5001 tool. 2. only privileged writes (byte/half word or wo rd) initiated by the rcpu to the ot register that terminate normally are valid . the data value (word) written into the register is formed into the ownership trace message that is queued to be transmitted. 3. ot register reads and non-privileg ed ot register writes, or writes initiated by any source other than the rcpu, do not cause ownership trace messag es to be transmitted by the readi module. length = 38 bits tcode (2) task/process id tag [32 bits] [6 bits] tcode (8) error code (0b0 0000, length = 11 bits [5 bits] [6 bits] 0b0 0001, 0b0 0010, 0b0 0111) readi module mpc561/mpc563 reference manual, rev. 1.2 24-76 freescale semiconductor 24.13.2.2 otm queueing readi implements a queue 32 messages deep for program trace, data trace, and ownership trace messages. messages that enter the queu e are transmitted via the output auxi liary port in the order in which they are queued. note if multiple trace messages need to be queued at the same time, ownership trace messages will have the lowest priority. 24.13.3 otm timing diagrams figure 24-76. ownership trace message figure 24-77. error message (program/data/ownership trace overrun) 24.14 rcpu development access this section details the rcpu development access support features of the readi module. the readi development port provides a full duplex se rial interface for acce ssing existing rcpu user register and development features including bdm (background debug mode). don?t care data (idle clock) tcode = 2 task/process id tag = 0x87654321 mcko mseo mdo[7:0] 01000010 11001000 01010000 11011001 00100001 00000000 tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-77 rcpu development access can be achi eved either via the readi signals or the bdm signals on the mcu. the access method is determined dur ing readi module configuration. figure 24-78 shows how readi and bdm signals are multiplexe d for rcpu development access. when the readi module is configured for rc pu development access, ieee-isto 5001 compliant vendor-defined messages are used for transm ission of data in and out of the mcu. note on the mpc561/mpc563 the bdm signa ls are shared with the readi signals. therefore bdm access is li mited to access via the nexus vendor-defined devel opment support messages. figure 24-78. rcpu development access multiplexing between readi and bdm signals 24.14.1 rcpu development access messaging the following rcpu development acc ess messages are used for hands haking between the device and the tool ? dsdi data message, dsdo data message, and bdm status message. 24.14.1.1 dsdi message the dsdi message is used by the tool to download information to the rcpu. readi usiu jtag rcpu tck / dsck / mcki tdo / dsdo / mdo0 tdi / dsdi / mdi0 multiplexer dsck dsdi dsdo rcpu development mux control debug development access bdm signals . . . . . . readi module mpc561/mpc563 reference manual, rev. 1.2 24-78 freescale semiconductor the dsdi data field has a 3-bit status header foll owed by 7 or 32 bits of data/instruction, depending on the rcpu development port mode. the dsdi message has the following format: figure 24-79. dsdi message format note when sending in a dsdi data message, the dsdi data should contain the control and status bits (start, mode, control), followed by the 7 or 32-bit cpu instruction/data or tr ap enable, msb first. see figure 24-85 for dsdi data message transmission sequence. 24.14.1.2 dsdo message the dsdo message is used by the device to upload information from the rcpu. the dsdo data field has a 3-bit status header follo wed by 7 or 32 bits of da ta/instruction, depending on the rcpu development port mode. the three status bits in the dsdo data indicates if the device is ready to receive the next message from the tool. the dsdo message has the following format: figure 24-80. dsdo message format note the dsdo data received will contain th e control and status bits and data from the cpu, msb first. see figure 24-85 for dsdo data message transmission sequence. 24.14.1.3 bdm status message bdm status message is generated by the device to le t the tool know about the status of debug mode. bdm status message (with bdm status field equal to 0b1) is sent when the rcpu is in debug mode and the device is ready to r eceive debug mode messages. max length = 41 bits tcode (56) dsdi data [10 or 35 bits] [6 bits] min length = 16 bits tcode (57) dsdo data [10 or 35 bits] [6 bits] max length = 41 bits min length = 16 bits readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-79 bdm status message (with bdm status field equal to 0b0) is sent out when the device exits bdm mode and rcpu is in normal operating mode. the bdm status message has the following format: figure 24-81. bdm status message format 24.14.1.4 error message (invalid message) an error message is sent out when an invalid mess age is received by readi. the error code within the error message indicates that an in valid tcode was detected in the auxiliary inpu t messages by the signal input formatter. refer to table 24-20 . the error message has the following format: figure 24-82. error message (invalid message) format 24.14.2 rcpu development access operation the rcpu development access can be achieved either via the readi signals or the bdm signals. to enable rcpu development access via the readi signa ls, the tool has to configure the dc register during the readi reset (rsti ). once the readi module takes the control of rcpu development access, the protocol for transmission of de velopment serial data in (dsdi) and out (dsdo) is performed through the ieee-isto 5001-1999 compliant vendor-defined messages. after enabling rcpu development access via the readi signals, the readi module can enable debug mode and enter debug mode. when debug mode is enabled and entered, readi sends a bdm status message (bdm status field equal to 0b1) to the development tool i ndicating that the rcpu has entered debug mode and is now expecting inst ructions from the readi signals. the development tool then uses the dsdi data messag e to send in the serial transmission data to readi. data is transmitted to the tool using the dsdo data message. this process continues until th e rcpu exits debug mode and readi sends the bdm status message (bdm status field equal to 0b0) indicating debug mode exit. note only after the dsdo data message is sent out should another dsdi data message be sent in. synchronous self-clocked mode is selected by readi for rcpu development access. in this mode, the internal transmission betwee n readi and the usiu is pe rformed at system frequency. length = 7 bits tcode (58) bdm status [1 bit] [6 bits] tcode (8) error code (0b00100) length = 11 bits [5 bits] [6 bits] readi module mpc561/mpc563 reference manual, rev. 1.2 24-80 freescale semiconductor when the rcpu is in debug mode, program trace is not allowed. if program tra ce is enabled, a program trace synchronization message is ge nerated when debug mode exits. when the rcpu is in debug mode, data trace and r/w access are allowed. the flow chart in figure 24-83 shows rcpu development access c onfiguration via readi. the modes of rcpu development access via re adi are described below. allowed modes are also summarized in table 24-8 of section 24.14.2.4, ?rcpu development access flow diagram .? 24.14.2.1 enabling rcpu developm ent access via readi signals reset sequencing is done by the t ool to initialize the readi signals and registers by asserting rsti (the device sends out the device id message after the rsti negation). system reset is held by the tool until the readi module is reset and initialized with desired rcpu development access setting. note the readi module will ignore any incoming dsdi data messages when the module is not configured for rcpu development access. 24.14.2.2 entering background deb ug mode (bdm) vi a readi signals there are three ways to enter debug mode (provided debug mode has been enabled): 1. enter debug mode (halted state) out-of-system reset through read i module configuration. this is displayed in figure 24-84 . 2. enter debug mode by downloading breakpoint inst ructions through rcpu development access when in non-debug (running) mode. 3. enter debug mode if an exception or interrupt occurs. when entering debug mode following an exception/ breakpoint, the rcpu signals vfls[0:1] are equal to 0b11. this causes readi to send a bd m status message to the tool i ndicating that the rcpu has entered debug mode and is now expecting inst ructions from the readi signals. debug mode enabling through readi and entering debug m ode out of system rese t is done by setting the following bits in the dc regist er (dme=0b1, dor=0b1) during system reset. debug mode entry causes rcpu to halt. 24.14.2.3 non-debug mode acces s of rcpu development access the rcpu development access can be also be used whil e the rcpu is not halted (in debug mode). this feature is used to send in breakpoints or sync hronization events to the rcpu. please refer to chapter 23, ?development support ? for further details. non-debug mode access of rcpu deve lopment can be achieved by confi guring the readi module to take control of rcpu development access during module configuration of the dc register (dme=0b0, dor=0bx). readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-81 24.14.2.4 rcpu developmen t access flow diagram figure 24-83 has flow diagram describing how the rcpu de velopment access can be achieved via readi signals. figure 24-83. rcpu development access flow diagram tool sends download request message and configures readi module (assign dpa, dme & dor, etc.) dsdi=1 (sync. self-clk mode) tool sends dsdi message device sends dsdo message no no yes yes (debug out-of-reset) (no debug out-of-reset) no device sends debug mode status ?bdm entry? (status bit = 1) bdm configuration out-of-reset generic rcpu development protocol tool asserts hreset tools negates hreset 16 clocks after rece iving device ready negation to enter debug mode negation to not enter debug mode dor=1 ? yes yes (debug mode enabled) (debug mode not enabled) no dme=1 ? (dpa, dme, dor, etc. bits locked) bdm entry? tool sends dsdi message device sends dsdo message bdm exit? debug mode not enalbed debug mode enabled (dme=0) (dme=1) tool asserts and negates rsti device sends did message (@ subsequent readi reset) (@ subsequent rcpu reset) *a* *b* *(exit loop via readi reset (*a*) or system reset (*b*)) device sends debug mode ?bdm exit? (status bit = 0) *(exit loop via readi reset (*a*) or via system reset (*b*)) dsdi=1 (synch.self-clk mode) dsdi=1 (sync. self-clk mode) dsck=1 until 16 clocks after sreset dsck=0 within 8 clocks of sreset message status message readi module mpc561/mpc563 reference manual, rev. 1.2 24-82 freescale semiconductor 24.14.3 throughput the tool can send a dsdi data me ssage into device upon the receipt of a dsdo data message as soon as the tool decodes the first two status bits of the dsdo data message just received and confirms valid data from the rcpu. an example throughput analysis is perf ormed with the following assumptions: ? readi configuration of rcpu development access and debu g mode is already entered through readi ? the module is configured for reduced port mode ? mcki running at 28 mhz ? mcko running at 56 mhz ? 56-mhz internal operation ? readi auxiliary input and output signals are free (not in middle of transmission) ? no delay from tool in responding ? tool keeps up with readi port ? tool reads the complete dsdo data messag e before shifting in dsdi data message ? 10 clocks estimated to format and encode/dec ode dsdi data and dsdo data messages within readi the dsdi data message is 41 bits (s ix bits of tcode and 35 bits of ds di data.). it takes 41 clocks (41 bits / 1 mdi signals) to shift in the dsdi data message . it is estimated that readi will take approximately 10 clocks to decode the dsdi data message. afte r the message has been decoded, readi will take 35 clocks to serially shift in the 35 b its of dsdi data to the rcpu devel opment port. hence, it takes a total of 86 clocks (41 + 10 + 35) to decode and shift in dsdi data fr om the tool to the rcpu development port. at 28 mhz, it translates to 3079 ns (35.8 x 81) to decode and shift in dsdi data to rcp u development port as dsdi bits are shifted into the rcpu development register, dsdo bits are shifted out from the same rcpu development register (dpdr) and these are captured by readi. it is estimated that readi will take approximately 10 clocks to encode the dsdo data. the dsdo message is 41 bits (6 bits of tcod e and 35 bits of dsdo data). it wi ll take 21 clocks (41 bits / 2 mdo signals) for readi to transmit this message. hence, it will take a total of 31 cl ocks (10 + 21) to encode the dsdo data message and shift out the dsdo data message to the tool. at 56 mhz, it will take 552 ns (17.8 x 31) to encode and shift out dsdo data to the tool. thus, it will take 3631 ns (3079 + 552) for one co mplete dsdi data and dsdo data messaging cycle. 24.14.4 development access timing diagrams figure 24-84 shows the timing diagram of rcpu de velopment access and entering debug mode out-of-system reset through readi. readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-83 figure 24-84. rcpu development access timing diagram ? debug mode entry out-of-reset figure 24-85 shows the transmission sequenc e of dsdi/dsdo data messages. figure 24-85. transmission sequence of dsdx data messages hreset sreset rsti msei mdi mseo mdo dc reg (bdm) config msg dsdi message bdm message entry dsdo message dsdi msg can be dsdo msg indicate status bits in the tool negates system clocks after ready msg sreset is negated by the mcu hreset at least 16 dev id message 1 3 dsdi msg (usiu drives) (tool drives) after some internal system clocks delay. (tool drives) bdm is set based on readi and bdm entry msg is device ready message tc = 18 tc = 56 dsdi message tc = 56 tc = 1 tc = 16 tc = 58 tc = 57 dsdo message tc = 57 bdm message exit tc = 58 device sends out dev id msg after negation of rsti dc reg. config msg (bdm) sent after devid msg received by tool 2 sent out when vfls[0:1]=11. module configuration 4 sent after. bdm msg 5 dsdo msg sent out 6 sent to device after it is ready. tcode and two 7 receiving device tcode (6 bits) header (3 bits) data (7 or 32 bits) 12 3 msb lsb msb lsb msb lsb readi module mpc561/mpc563 reference manual, rev. 1.2 24-84 freescale semiconductor dsdi message fields of the developmen t port access message are explained in table 24-33 . . dsdo message fields of the developmen t port access message are explained in table 24-34 . table 24-33. development port access: dsdi field header data function start mode control instruction / data (32 bits) bits 0:6 bits 7:31 1 0 0 cpu instruction transfer instruction to cpu 1 0 1 cpu data transfer data to cpu 1 1 0 trap enable does not exist transfer data to trap enable control register 1 1 1 0011111 does not exist negate breakpoint requests to the cpu. 1 1 1 0 does not exist nop table 24-34. development port access: dsdo field header data function ready status [0:1] bit 0 bit 1 bits 2:31 or 2:6 ? (depending on input mode) (0) 0 0 data valid data from cpu (0) 0 1 freeze status 1 1 the ?freeze? status is set to (1) when the cpu is in debug mode and to (0) otherwise. download procedure in progress 2 2 the ?download procedure in progress? status is assert ed (0) when debug port in the download procedure and is negated (1) otherwise. 1?s sequencing error (0) 1 0 1?s cpu interrupt (0) 1 1 1?s null readi module mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 24-85 figure 24-86. error message (invalid message) figure 24-87. dsdi data message (assert non-maskable breakpoint) figure 24-88. dsdi data message (cpu instruction ? rfi) tcode = 8 error code = 0b00100 (invalid message) don?t care data (idle clock) mcko mseo mdo[7:0] 00001000 00000001 00000000 mcki msei mdi[1:0] 00 10 11 11 11 10 11 11 00 don?t care data (idle clock) tcode = 56 (0x38) header = (start=1, mode=1, control=1) data = 0b1011111 (assert non maskable breakpoint) mcki msei mdi[1:0] 00 10 11 01 00 01 10 01 00 00 00 00 00 00 00 00 00 11 00 01 00 00 tcode = 56 (0x38) header = (start=1, mode=0, control=0) data = 0x4c000064 (rfi instruction) don?t care data (idle clock) readi module mpc561/mpc563 reference manual, rev. 1.2 24-86 freescale semiconductor figure 24-89. dsdo data message (cpu data out) 24.15 power management this section details the power manage ment features of the readi module. the readi module is a developm ent interface, and is not expe cted to function under normal (non-development) conditions. theref ore power management is require d to reduce and minimize power consumption during normal operation of the part. 24.15.1 functional description the following are the candida tes for power management: 24.15.2 low power modes when the mcu is in sleep, deep-sleep, or low power- down mode, all internal cl ocks on the mcu are shut down, including the mcko. the mseo signal will be held negated. low power mode entry for the mcu will be held of f until the readi module ha s transmitted all existing messages (in the queues and tr ansmit buffers). during th is time, input messages fr om the development tool are ignored. upon restoration of clocks in normal mode, program and data trac es will be synchronized, if enabled. table 24-35. power management mechanism overview feature power saving mechanism disabled mode if evti is negated at negation of rsti , the readi module will be disabled. no trace output will be provided, and output auxiliary port will be three-stated. sleep, deep-sleep and low power-down mode all outputs will be held static. readi reset (rsti ) output auxiliary signals will be three-stated. mcko mseo mdo[7:0] 11111110 00000001 10101010 01011110 00000001 00000000 tcode = 57 (0x39) header = (start=0, mode=0, control=0) data = ff00aaf5 (cpu data out) don?t care data (idle clock) 00111001 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-1 chapter 25 ieee 1149.1-compliant interface (jtag) the chip design includes user-accessibl e test logic that is compatible with the ieee 1149.1-1994 standard test access port and boundary scan architecture. the implementation supports circuit-board test strategies based on this standard. an overview of the pins requirement on jtag is shown in figure 25-1 . figure 25-1. pin requirement on jtag 25.1 ieee 1149.1 test access port the mpc561/mpc563 provides a dedicat ed user-accessible test access port (tap) that is compatible with the ieee 1149.1 standard test access port and boundary scan architecture in al l but two areas listed below. problems associated with testing high density circuit board s have led to development of this proposed standard under the sponsorship of the te st technology committee of ieee and the joint test action group (jtag). the mpc561/mp c563 implementation supports circui t-board test strategies based on this standard. ieee1149.1 compatibility exceptions: ? the mpc561/mpc563 enters jtag mode by going through a standa rd device reset sequence with the jcomp signal asserted high during poreset negation. once jtag has been entered, the mpc561/mpc563 remains in jtag mode until a nother reset sequence is applied to exit jtag mode, or the device is powered down. ? the jtag output port, tdo, is conf igured with a weak pul l-up until reset negate s or the driver is disabled. tap tdi tck tms jcomp / rsti tdo mpc561/mpc563 bsc bsc bsc bsc bsc ...... ........... ........... ........... ........... ........... bsc bsc ........... ....... trst ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-2 freescale semiconductor the tap consists of five dedicated signal pins, a 16-st ate tap controller, and two test data registers. a boundary scan register links all devi ce signal pins into a single shift re gister. the test logic implemented utilizes static logic design. the mpc561/mpc 563 implementation provides the capability to: 1. perform boundary scan operations to test circuit-board electrical continuity. 2. bypass the mpc561/mpc563 for a given circuit- board test by effectively reducing the boundary scan register to a single cell. 3. sample the mpc561/mpc563 system pins during operation and transp arently shift out the result in the boundary scan register. 4. disable the output drive to pi ns during circuit-board testing. note certain precautions must be observed to ensure that the ieee 1149-like test logic does not interfere with nontest ope ration. jcomp must be low prior to poreset assertion after lo w power mode exits, otherwise an unknown state will occur. 25.1.1 overview an overview of the mpc561/mpc563 scan chain implementa tion is shown in figure 25-2 . the mpc561/mpc563 implementation include s a tap controller, a 4-bit inst ruction register, and two test registers (a one-bit bypass register and a 427-bit (m pc563) or 423-bit (mpc561) boundary scan register). this implementation includes a dedicated tap consisting of the following signals: ? tck ? a test clock input to synchronize the te st logic. (with an inte rnal pull-down resistor) ? tms ? a test mode select input (with an internal pullup resistor) that is sa mpled on the rising edge of tck to sequence the tap controller?s state machine. ? tdi ? a test data input (with an internal pullup resistor) that is sampled on the rising edge of tck. ? tdo ? a three-state test data output that is activel y driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. (this pin also has a weak pull-up that is active when output drivers are disabled, ex cept during a hi-z instruction). ?trst ? an asynchronous reset with an internal pull-up resistor that provides initia lization of the tap controller and other logic required by the st andard. this input is multiplexed with the poreset signal. ? jcomp ? jtag compliancy ? this signal provi des jtag ieee1149.1 compatibility and selects between normal operation (low) and jtag test mode (high). note jtag mode does not provide acce ss to the internal mpc561/mpc563 circuitry. it allows acc ess only to the input or output pad (periphery) circuitry. ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-3 figure 25-2. test logic block diagram 25.1.2 entering jtag mode to enable jtag on reset fo r board test jcomp/rsti must be high on poreset rising edge as shown in figure 25-3 . note jtag puts all output pins in fast slew rate mode . enough current cannot be supplied to allow all the pins to be sw itched simultaneous ly, so this should be avoided. figure 25-3. jtag mode selection boundary scan register bypass m u x instruction apply & decode register 4-bit instruction register m u x tdo tdi tms tck jcomp / rsti 0 1 2 tap controller 3 trst poreset / trst poreset jcomp/rsti configuration jtag jtag on jtag off/readi config t ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-4 freescale semiconductor 25.1.2.1 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that cont rols the operation of the jtag logic. the state machine is shown in figure 25-4 . the value shown adjacent to ea ch arc represents the value of the tms signal sampled on the rising edge of the tck signal. figure 25-4. tap controller state machine 25.1.2.2 boundary scan register the mpc561/mpc563 scan chain implementation has a 427-bit (m pc563) or 423-bit (mpc561) boundary scan register. this register contains bits for most device si gnals, clock pins and associated control signals. the xtal, extal a nd xfc pins are associated with analog signals and are not included in the boundary scan register. the poreset , hreset , and sreset pins are also excluded from the boundary scan register. test logic reset run-test/idle select-dr_scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir_scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 00 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-5 the 520-bit boundary scan regi ster can be connected between tdi and tdo by selecting the extest or sample/preload instructions. this register is used to capturing signal pin data on the input pins, forcing fixed values on the output si gnal pins, and selecting the direction and drive characteristics (a logic value or high impedance) of the bidi rectional and three- state signal pins. the key to using the boundary scan register is knowi ng the boundary scan bit order and the pins that are associated with them. table 25-1 shows the bit order starting from the tdo output and going to the tdi input. table 25-1 displays boundary scan bit de finitions for the mpc561 and table 25-2 displays boundary scan bit definitions for the mpc563. table 25-1. mpc561 boundary scan bit definition bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type 0 bc_2 * controlr 0 1 bc_7 b_cnrx0 bidir 0 0 0 z io 5vfa 2 bc_2 * internal 1 3 bc_2 b_cntx0 output2 1 o 5vfa 4 bc_2 * controlr 0 5 bc_7 b_tpuch0 bidir 0 4 0 z io 5vsa 6 bc_2 * controlr 0 7 bc_7 b_tpuch1 bidir 0 6 0 z io 5vsa 8 bc_2 * controlr 0 9 bc_7 b_tpuch2 bidir 0 8 0 z io 5vsa 10 bc_2 * controlr 0 11 bc_7 b_tpuch3 bidir 0 10 0 z io 5vsa 12 bc_2 * controlr 0 13 bc_7 b_tpuch4 bidir 0 12 0 z io 5vsa 14 bc_2 * controlr 0 15 bc_7 b_tpuch5 bidir 0 14 0 z io 5vsa 16 bc_2 * controlr 0 17 bc_7 b_tpuch6 bidir 0 16 0 z io 5vsa 18 bc_2 * controlr 0 19 bc_7 b_tpuch7 bidir 0 18 0 z io 5vsa 20 bc_2 * controlr 0 21 bc_7 b_tpuch8 bidir 0 20 0 z io 5vsa 22 bc_2 * controlr 0 23 bc_7 b_tpuch9 bidir 0 22 0 z io 5vsa 24 bc_2 * controlr 0 25 bc_7 b_tpuch10 bidir 0 24 0 z io 5vsa ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-6 freescale semiconductor 26 bc_2 * controlr 0 27 bc_7 b_tpuch11 bidir 0 26 0 z io 5vsa 28 bc_2 * controlr 0 29 bc_7 b_tpuch12 bidir 0 28 0 z io 5vsa 30 bc_2 * controlr 0 31 bc_7 b_tpuch13 bidir 0 30 0 z io 5vsa 32 bc_2 * controlr 0 33 bc_7 b_tpuch14 bidir 0 32 0 z io 5vsa 34 bc_2 * controlr 0 35 bc_7 b_tpuch15 bidir 0 34 0 z io 5vsa 36 bc_2 * controlr 0 37 bc_7 b_t2clk_pcs4 bidir 0 36 0 z io 5vfa 38 bc_2 * controlr 0 39 bc_7 a_t2clk_pcs5 bidir 0 38 0 z io 5vfa 40 bc_2 * controlr 0 41 bc_7 a_tpuch0 bidir 0 40 0 z io 5vsa 42 bc_2 * controlr 0 43 bc_7 a_tpuch1 bidir 0 42 0 z io 5vsa 44 bc_2 * controlr 0 45 bc_7 a_tpuch2 bidir 0 44 0 z io 5vsa 46 bc_2 * controlr 0 47 bc_7 a_tpuch3 bidir 0 46 0 z io 5vsa 48 bc_2 * controlr 0 49 bc_7 a_tpuch4 bidir 0 48 0 z io 5vsa 50 bc_2 * controlr 0 51 bc_7 a_tpuch5 bidir 0 50 0 z io 5vsa 52 bc_2 * controlr 0 53 bc_7 a_tpuch6 bidir 0 52 0 z io 5vsa 54 bc_2 * controlr 0 55 bc_7 a_tpuch7 bidir 0 54 0 z io 5vsa 56 bc_2 * controlr 0 57 bc_7 a_tpuch8 bidir 0 56 0 z io 5vsa 58 bc_2 * controlr 0 59 bc_7 a_tpuch9 bidir 0 58 0 z io 5vsa 60 bc_2 * controlr 0 61 bc_7 a_tpuch10 bidir 0 60 0 z io 5vsa table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-7 62 bc_2 * controlr 0 63 bc_7 a_tpuch11 bidir 0 62 0 z io 5vsa 64 bc_2 * controlr 0 65 bc_7 a_tpuch12 bidir 0 64 0 z io 5vsa 66 bc_2 * controlr 0 67 bc_7 a_tpuch13 bidir 0 66 0 z io 5vsa 68 bc_2 * controlr 0 69 bc_7 a_tpuch14 bidir 0 68 0 z io 5vsa 70 bc_2 * controlr 0 71 bc_7 a_tpuch15 bidir 0 70 0 z io 5vsa 72 bc_2 * controlr 0 73 bc_7 a_an0_anw_pqb0 bidir 0 72 0 z io 5vsa 74 bc_2 * controlr 0 75 bc_7 a_an1_anx_pqb1 bidir 0 74 0 z io 5vsa 76 bc_2 * controlr 0 77 bc_7 a_an2_any_pqb2 bidir 0 76 0 z io 5vsa 78 bc_2 * controlr 0 79 bc_7 a_an3_anz_pqb3 bidir 0 78 0 z io 5vsa 80 bc_2 * controlr 0 81 bc_7 a_an48_pqb4 bidir 0 80 0 z io 5vsa 82 bc_2 * controlr 0 83 bc_7 a_an49_pqb5 bidir 0 82 0 z io 5vsa 84 bc_2 * controlr 0 85 bc_7 a_an50_pqb6 bidir 0 84 0 z io 5vsa 86 bc_2 * controlr 0 87 bc_7 a_an51_pqb7 bidir 0 86 0 z io 5vsa 88 bc_2 * controlr 0 89 bc_7 a_an52_ma0_pqa0 bidir 0 88 0 z io 5vsa 90 bc_2 * controlr 0 91 bc_7 a_an53_ma1_pqa1 bidir 0 90 0 z io 5vsa 92 bc_2 * controlr 0 93 bc_7 a_an54_ma2_pqa2 bidir 0 92 0 z io 5vsa 94 bc_2 * controlr 0 95 bc_7 a_an55_pqa3 bidir 0 94 0 z io 5vsa 96 bc_2 * controlr 0 97 bc_7 a_an56_pqa4 bidir 0 96 0 z io 5vsa table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-8 freescale semiconductor 98 bc_2 * controlr 0 99 bc_7 a_an57_pqa5 bidir 0 98 0 z io 5vsa 100 bc_2 * controlr 0 101 bc_7 a_an58_pqa6 bidir 0 100 0 z io 5vsa 102 bc_2 * controlr 0 103 bc_7 a_an59_pqa7 bidir 0 102 0 z io 5vsa 104 bc_2 * controlr 0 105 bc_7 b_an0_anw_pqb0 bidir 0 104 0 z io 5vsa 106 bc_2 * controlr 0 107 bc_7 b_an1_anx_pqb1 bidir 0 106 0 z io 5vsa 108 bc_2 * controlr 0 109 bc_7 b_an2_any_pqb2 bidir 0 108 0 z io 5vsa 110 bc_2 * controlr 0 111 bc_7 b_an3_anz_pqb3 bidir 0 110 0 z io 5vsa 112 bc_2 * controlr 0 113 bc_7 b_an48_pqb4 bidir 0 112 0 z io 5vsa 114 bc_2 * controlr 0 115 bc_7 b_an49_pqb5 bidir 0 114 0 z io 5vsa 116 bc_2 * controlr 0 117 bc_7 b_an50_pqb6 bidir 0 116 0 z io 5vsa 118 bc_2 * controlr 0 119 bc_7 b_an51_pqb7 bidir 0 118 0 z io 5vsa 120 bc_2 * controlr 0 121 bc_7 b_an52_ma0_pqa0 bidir 0 120 0 z io 5vsa 122 bc_2 * controlr 0 123 bc_7 b_an53_ma1_pqa1 bidir 0 122 0 z io 5vsa 124 bc_2 * controlr 0 125 bc_7 b_an54_ma2_pqa2 bidir 0 124 0 z io 5vsa 126 bc_2 * controlr 0 127 bc_7 b_an55_pqa3 bidir 0 126 0 z io 5vsa 128 bc_2 * controlr 0 129 bc_7 b_an56_pqa4 bidir 0 128 0 z io 5vsa 130 bc_2 * controlr 0 131 bc_7 b_an57_pqa5 bidir 0 130 0 z io 5vsa 132 bc_2 * controlr 0 133 bc_7 b_an58_pqa6 bidir 0 132 0 z io 5vsa table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-9 134 bc_2 * controlr 0 135 bc_7 b_an59_pqa7 bidir 0 134 0 z io 5vsa 136 bc_2 * controlr 0 137 bc_7 etrig2_pcs7 bidir 0 136 0 z io 5vfa 138 bc_2 * controlr 0 139 bc_7 etrig1_pcs6 bidir 0 138 0 z io 5vfa 140 bc_2 * controlr 0 141 bc_7 mda11 bidir 0 140 0 z io 5vsa 142 bc_2 * controlr 0 143 bc_7 mda12 bidir 0 142 0 z io 5vsa 144 bc_2 * controlr 0 145 bc_7 mda13 bidir 0 144 0 z io 5vsa 146 bc_2 * controlr 0 147 bc_7 mda14 bidir 0 146 0 z io 5vsa 148 bc_2 * controlr 0 149 bc_7 mda15 bidir 0 148 0 z io 5vsa 150 bc_2 * controlr 0 151 bc_7 mda27 bidir 0 150 0 z io 5vsa 152 bc_2 * controlr 0 153 bc_7 mda28 bidir 0 152 0 z io 5vsa 154 bc_2 * controlr 0 155 bc_7 mda29 bidir 0 154 0 z io 5vsa 156 bc_2 * controlr 0 157 bc_7 mda30 bidir 0 156 0 z io 5vsa 158 bc_2 * controlr 0 159 bc_7 mda31 bidir 0 158 0 z io 5vsa 160 bc_2 * controlr 0 161 bc_7 mpwm0_mdi1 bidir 0 160 0 z io 26v5vs 162 bc_2 * controlr 0 163 bc_7 mpwm1_mdo2 bidir 0 162 0 z io 26v5vs 164 bc_2 * controlr 0 165 bc_7 mpwm2_ppm_tx1 bidir 0 164 0 z io 26v5vs 166 bc_2 * controlr 0 167 bc_7 mpwm3_ppm_rx1 bidir 0 166 0 z io 26v5vs 168 bc_2 * controlr 0 169 bc_7 mpwm16 bidir 0 168 0 z io 5vsa table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-10 freescale semiconductor 170 bc_2 * controlr 0 171 bc_7 mpwm17_mdo3 bidir 0 170 0 z io 26v5vs 172 bc_2 * controlr 0 173 bc_7 mpwm18_mdo6 bidir 0 172 0 z io 26v5vs 174 bc_2 * controlr 0 175 bc_7 mpwm19_mdo7 bidir 0 174 0 z io 26v5vs 176 bc_2 * controlr 0 177 bc_7 mpio32b5_mdo5 bidir 0 176 0 z io 26v5vs 178 bc_2 * controlr 0 179 bc_7 mpio32b6_mpwm4_mdo6 bidir 0 178 0 z io 26v5vs 180 bc_2 * controlr 0 181 bc_7 mpio32b7_mpwm5 bidir 0 180 0 z io 5vsa 182 bc_2 * controlr 0 183 bc_7 mpio32b8_mpwm20 bidir 0 182 0 z io 5vsa 184 bc_2 * controlr 0 185 bc_7 mpio32b9_mpwm21 bidir 0 184 0 z io 5vsa 186 bc_2 * controlr 0 187 bc_7 mpio32b10_ppm_tsync bidir 0 186 0 z io 26v5vs 188 bc_2 * controlr 0 189 bc_7 mpio32b11_c_cnrx0 bidir 0 188 0 z io 5vfa 190 bc_2 * controlr 0 191 bc_7 mpio32b12_c_cntx0 bidir 0 190 0 z io 5vfa 192 bc_2 * controlr 0 193 bc_7 mpio32b13_ppm_tclk bidir 0 192 0 z io 26v5vs 194 bc_2 * controlr 0 195 bc_7 mpio32b14_ppm_rx0 bidir 0 194 0 z io 26v5vs 196 bc_2 * controlr 0 197 bc_7 mpio32b15_ppm_tx0 bidir 0 196 0 z io 26v5vs 198 bc_2 * controlr 0 199 bc_7 vf0_mpio32b0_mdo1 bidir 0 198 0 z io 26v5vs 200 bc_2 * controlr 0 201 bc_7 vf1_mpio32b1_mcko bidir 0 200 0 z io 26v5vs 202 bc_2 * controlr 0 203 bc_7 vf2_mpio32b2_msei_b bidir 0 202 0 z io 26v5vs 204 bc_2 * controlr 0 table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-11 205 bc_7 vfls0_mpio32b3_mseo_ b bidir 0 204 0 z io 26v5vs 206 bc_2 * controlr 0 207 bc_7 vfls1_mpio32b4 bidir 0 206 0 z io 26v5vs 208 bc_2 * internal 1 209 bc_2 a_cntx0 output2 1 i 5vfa 210 bc_2 * internal 0 211 bc_4 a_cnrx0 input x o 5vfa 212 bc_2 * controlr 0 213 bc_7 pcs0_ss_b_qgpio0 bidir 0 212 0 z io 5vfa 214 bc_2 * controlr 0 215 bc_7 pcs1_qgpio1 bidir 0 214 0 z io 5vfa 216 bc_2 * controlr 0 217 bc_7 pcs2_qgpio2 bidir 0 216 0 z io 5vfa 218 bc_2 * controlr 0 219 bc_7 pcs3_qgpio3 bidir 0 218 0 z io 5vfa 220 bc_2 * controlr 0 221 bc_7 miso_qgpio4 bidir 0 220 0 z io 5vh 222 bc_2 * controlr 0 223 bc_7 mosi_qgpio5 bidir 0 222 0 z io 5vh 224 bc_2 * controlr 0 225 bc_7 sck_qgpio6 bidir 0 224 0 z io 5vh 226 bc_2 * internal 0 227 bc_4 eck input x i 5vfa 228 bc_2 * internal 1 229 bc_2 txd1_qgpo1 output2 1 o 5vfa 230 bc_2 * internal 1 231 bc_2 txd2_qgpo2_c_cntx0 output2 1 o 5vfa 232 bc_4 rxd1_qgpi1 input x i 5vido 233 bc_4 rxd2_qgpi2_c_cnrx0 input x i 5vido 234 bc_2 * internal 1 235 bc_2 engclk_buclk output2 1 o buff 236 bc_2 * internal 1 237 bc_2 clkout output2 1 o 26vf 238 bc_4 extclk input x i extclk 239 bc_2 * controlr 0 table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-12 freescale semiconductor 240 bc_7 sreset_b bidir 0 239 0 z io 26vc 241 bc_2 * controlr 0 242 bc_7 hreset_b bidir 0 241 0 z io 26vc 243 bc_2 * controlr 0 244 bc_7 rstconf_b_texp bidir 0 243 0 z io 26v 245 bc_2 * controlr 0 246 bc_7 irq7_b_modck3 bidir 0 245 0 z io 26v 247 bc_2 * controlr 0 248 bc_7 irq6_b_modck2 bidir 0 247 0 z io 26v 249 bc_2 * controlr 0 250 bc_7 irq5_b_sgpioc5_modck 1 bidir 0 249 0 z io 26v 251 bc_2 * controlr 0 252 bc_7 data_sgpiod16 bidir 0 251 0 z io 26v5vs 253 bc_2 * controlr 0 254 bc_7 data_sgpiod17 bidir 0 253 0 z io 26v5vs 255 bc_2 * controlr 0 256 bc_7 data_sgpiod18 bidir 0 255 0 z io 26v5vs 257 bc_2 * controlr 0 258 bc_7 data_sgpiod14 bidir 0 257 0 z io 26v5vs 259 bc_2 * controlr 0 260 bc_7 data_sgpiod15 bidir 0 259 0 z io 26v5vs 261 bc_2 * controlr 0 262 bc_7 data_sgpiod19 bidir 0 261 0 z io 26v5vs 263 bc_2 * controlr 0 264 bc_7 data_sgpiod20 bidir 0 263 0 z io 26v5vs 265 bc_2 * controlr 0 266 bc_7 data_sgpiod12 bidir 0 265 0 z io 26v5vs 267 bc_2 * controlr 0 268 bc_7 data_sgpiod13 bidir 0 267 0 z io 26v5vs 269 bc_2 * controlr 0 270 bc_7 data_sgpiod21 bidir 0 269 0 z io 26v5vs 271 bc_2 * controlr 0 272 bc_7 data_sgpiod10 bidir 0 271 0 z io 26v5vs 273 bc_2 * controlr 0 274 bc_7 data_sgpiod11 bidir 0 273 0 z io 26v5vs table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-13 275 bc_2 * controlr 0 276 bc_7 data_sgpiod22 bidir 0 275 0 z io 26v5vs 277 bc_2 * controlr 0 278 bc_7 data_sgpiod23 bidir 0 277 0 z io 26v5vs 279 bc_2 * controlr 0 280 bc_7 data_sgpiod8 bidir 0 279 0 z io 26v5vs 281 bc_2 * controlr 0 282 bc_7 data_sgpiod9 bidir 0 281 0 z io 26v5vs 283 bc_2 * controlr 0 284 bc_7 data_sgpiod24 bidir 0 283 0 z io 26v5vs 285 bc_2 * controlr 0 286 bc_7 data_sgpiod25 bidir 0 285 0 z io 26v5vs 287 bc_2 * controlr 0 288 bc_7 data_sgpiod6 bidir 0 287 0 z io 26v5vs 289 bc_2 * controlr 0 290 bc_7 data_sgpiod7 bidir 0 289 0 z io 26v5vs 291 bc_2 * controlr 0 292 bc_7 data_sgpiod26 bidir 0 291 0 z io 26v5vs 293 bc_2 * controlr 0 294 bc_7 data_sgpiod27 bidir 0 293 0 z io 26v5vs 295 bc_2 * controlr 0 296 bc_7 data_sgpiod4 bidir 0 295 0 z io 26v5vs 297 bc_2 * controlr 0 298 bc_7 data_sgpiod5 bidir 0 297 0 z io 26v5vs 299 bc_2 * controlr 0 300 bc_7 data_sgpiod28 bidir 0 299 0 z io 26v5vs 301 bc_2 * controlr 0 302 bc_7 data_sgpiod29 bidir 0 301 0 z io 26v5vs 303 bc_2 * controlr 0 304 bc_7 data_sgpiod2 bidir 0 303 0 z io 26v5vs 305 bc_2 * controlr 0 306 bc_7 data_sgpiod3 bidir 0 305 0 z io 26v5vs 307 bc_2 * controlr 0 308 bc_7 data_sgpiod30 bidir 0 307 0 z io 26v5vs 309 bc_2 * controlr 0 310 bc_7 data_sgpiod0 bidir 0 309 0 z io 26v5vs table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-14 freescale semiconductor 311 bc_2 * controlr 0 312 bc_7 data_sgpiod1 bidir 0 311 0 z io 26v5vs 313 bc_2 * controlr 0 314 bc_7 data_sgpiod31 bidir 0 313 0 z io 26v5vs 315 bc_2 * controlr 0 316 bc_7 addr_sgpioa29 bidir 0 315 0 z io 26v5vs 317 bc_2 * controlr 0 318 bc_7 addr_sgpioa25 bidir 0 317 0 z io 26v5vs 319 bc_2 * controlr 0 320 bc_7 addr_sgpioa26 bidir 0 319 0 z io 26v5vs 321 bc_2 * controlr 0 322 bc_7 addr_sgpioa27 bidir 0 321 0 z io 26v5vs 323 bc_2 * controlr 0 324 bc_7 addr_sgpioa28 bidir 0 323 0 z io 26v5vs 325 bc_2 * controlr 0 326 bc_7 addr_sgpioa24 bidir 0 325 0 z io 26v5vs 327 bc_2 * controlr 0 328 bc_7 addr_sgpioa23 bidir 0 327 0 z io 26v5vs 329 bc_2 * controlr 0 330 bc_7 addr_sgpioa22 bidir 0 329 0 z io 26v5vs 331 bc_2 * controlr 0 332 bc_7 addr_sgpioa30 bidir 0 331 0 z io 26v5vs 333 bc_2 * controlr 0 334 bc_7 addr_sgpioa21 bidir 0 333 0 z io 26v5vs 335 bc_2 * controlr 0 336 bc_7 addr_sgpioa20 bidir 0 335 0 z io 26v5vs 337 bc_2 * controlr 0 338 bc_7 addr_sgpioa8 bidir 0 337 0 z io 26v5vs 339 bc_2 * controlr 0 340 bc_7 addr_sgpioa31 bidir 0 339 0 z io 26v5vs 341 bc_2 * controlr 0 342 bc_7 addr_sgpioa19 bidir 0 341 0 z io 26v5vs 343 bc_2 * controlr 0 344 bc_7 addr_sgpioa18 bidir 0 343 0 z io 26v5vs 345 bc_2 * controlr 0 346 bc_7 addr_sgpioa9 bidir 0 345 0 z io 26v5vs table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-15 347 bc_2 * controlr 0 348 bc_7 addr_sgpioa17 bidir 0 347 0 z io 26v5vs 349 bc_2 * controlr 0 350 bc_7 addr_sgpioa16 bidir 0 349 0 z io 26v5vs 351 bc_2 * controlr 0 352 bc_7 addr_sgpioa10 bidir 0 351 0 z io 26v5vs 353 bc_2 * controlr 0 354 bc_7 addr_sgpioa15 bidir 0 353 0 z io 26v5vs 355 bc_2 * controlr 0 356 bc_7 addr_sgpioa14 bidir 0 355 0 z io 26v5vs 357 bc_2 * controlr 0 358 bc_7 addr_sgpioa13 bidir 0 357 0 z io 26v5vs 359 bc_2 * controlr 0 360 bc_7 addr_sgpioa11 bidir 0 359 0 z io 26v5vs 361 bc_2 * controlr 0 362 bc_7 addr_sgpioa12 bidir 0 361 0 z io 26v5vs 363 bc_2 * controlr 0 364 bc_7 bi_b_sts_b bidir 0 363 0 z io 26v 365 bc_2 * controlr 0 366 bc_7 burst_b bidir 0 365 0 z io 26v 367 bc_2 * controlr 0 368 bc_7 bdip_b bidir 0 367 0 z io 26v 369 bc_2 * controlr 0 370 bc_7 ta_b bidir 0 369 0 z io 26v 371 bc_2 * controlr 0 372 bc_7 ts_b bidir 0 371 0 z io 26v 373 bc_2 * controlr 0 374 bc_7 tsiz1 bidir 0 373 0 z io 26v 375 bc_2 * controlr 0 376 bc_7 tsiz0 bidir 0 375 0 z io 26v 377 bc_2 * controlr 0 378 bc_7 tea_b bidir 0 377 0 z io 26v 379 bc_2 * internal 1 380 bc_2 oe_b output2 1 o 26v 381 bc_2 * controlr 0 382 bc_7 rd_wr_b bidir 0 381 0 z io 26v table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-16 freescale semiconductor 383 bc_2 * internal 1 384 bc_2 cs3_b output2 1 o 26v 385 bc_2 * internal 1 386 bc_2 cs2_b output2 1 o 26v 387 bc_2 * internal 1 388 bc_2 cs1_b output2 1 o 26v 389 bc_2 * internal 1 390 bc_2 cs0_b output2 1 o 26v 391 bc_2 * internal 1 392 bc_2 we_b_at3 output2 1 o 26v 393 bc_2 * internal 1 394 bc_2 we_b_at2 output2 1 o 26v 395 bc_2 * internal 1 396 bc_2 we_b_at1 output2 1 o 26v 397 bc_2 * internal 1 398 bc_2 we_b_at0 output2 1 o 26v 399 bc_2 * controlr 0 400 bc_7 br_b_vf1_iwp2 bidir 0 399 0 z io 26v 401 bc_2 * controlr 0 402 bc_7 bg_b_vf0_lwp1 bidir 0 401 0 z io 26v 403 bc_2 * controlr 0 404 bc_7 bb_b_vf2_iwp3 bidir 0 403 0 z io 26v 405 bc_2 * controlr 0 406 bc_7 sgpioc7_irqout_b_lwp 0 bidir 0 405 0 z io 26v5vs 407 bc_2 * controlr 0 408 bc_7 irq1_b_rsv_b_sgpioc1 bidir 0 407 0 z io 26v5vs 409 bc_2 * controlr 0 410 bc_7 irq0_b_sgpioc0_mdo4 bidir 0 409 0 z io 26v 411 bc_2 * controlr 0 412 bc_7 irq2_b_cr_b_sgpioc2_ mdo5_mts_b bidir 0 411 0 z io 26v5vs 413 bc_2 * controlr 0 414 bc_7 irq4_b_at2_sgpioc4 bidir 0 413 0 z io 26v5vs 415 bc_2 * controlr 0 416 bc_7 irq3_b_kr_b_retry_b_ sgpioc3 bidir 0 415 0 z io 26v5vs table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-17 417 bc_2 * internal 1 418 bc_2 iwp0_vfls0 output2 1 o 26v 419 bc_2 * internal 1 420 bc_2 iwp1_vfls1 output2 1 o 26v 421 bc_2 * controlr 0 422 bc_7 sgpioc6_frz_ptr_b bidir 0 421 0 z io 26v5vs table 25-2. mpc563 boundary scan bit definition bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type 0 bc_2 * controlr 0 1 bc_7 b_cnrx0 bidir 0 0 0 z io 5vfa 2 bc_2 * internal 1 3 bc_2 b_cntx0 output2 1 o 5vfa 4 bc_2 * controlr 0 5 bc_7 b_tpuch0 bidir 0 4 0 z io 5vsa 6 bc_2 * controlr 0 7 bc_7 b_tpuch1 bidir 0 6 0 z io 5vsa 8 bc_2 * controlr 0 9 bc_7 b_tpuch2 bidir 0 8 0 z io 5vsa 10 bc_2 * controlr 0 11 bc_7 b_tpuch3 bidir 0 10 0 z io 5vsa 12 bc_2 * controlr 0 13 bc_7 b_tpuch4 bidir 0 12 0 z io 5vsa 14 bc_2 * controlr 0 15 bc_7 b_tpuch5 bidir 0 14 0 z io 5vsa 16 bc_2 * controlr 0 17 bc_7 b_tpuch6 bidir 0 16 0 z io 5vsa 18 bc_2 * controlr 0 19 bc_7 b_tpuch7 bidir 0 18 0 z io 5vsa 20 bc_2 * controlr 0 21 bc_7 b_tpuch8 bidir 0 20 0 z io 5vsa 22 bc_2 * controlr 0 23 bc_7 b_tpuch9 bidir 0 22 0 z io 5vsa 24 bc_2 * controlr 0 table 25-1. mpc561 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe valu e contro l cell disable value disable result pin function pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-18 freescale semiconductor 25 bc_7 b_tpuch10 bidir 0 24 0 z io 5vsa 26 bc_2 * controlr 0 27 bc_7 b_tpuch11 bidir 0 26 0 z io 5vsa 28 bc_2 * controlr 0 29 bc_7 b_tpuch12 bidir 0 28 0 z io 5vsa 30 bc_2 * controlr 0 31 bc_7 b_tpuch13 bidir 0 30 0 z io 5vsa 32 bc_2 * controlr 0 33 bc_7 b_tpuch14 bidir 0 32 0 z io 5vsa 34 bc_2 * controlr 0 35 bc_7 b_tpuch15 bidir 0 34 0 z io 5vsa 36 bc_2 * controlr 0 37 bc_7 b_t2clk_pcs4 bidir 0 36 0 z io 5vfa 38 bc_2 * controlr 0 39 bc_7 a_t2clk_pcs5 bidir 0 38 0 z io 5vfa 40 bc_2 * controlr 0 41 bc_7 a_tpuch0 bidir 0 40 0 z io 5vsa 42 bc_2 * controlr 0 43 bc_7 a_tpuch1 bidir 0 42 0 z io 5vsa 44 bc_2 * controlr 0 45 bc_7 a_tpuch2 bidir 0 44 0 z io 5vsa 46 bc_2 * controlr 0 47 bc_7 a_tpuch3 bidir 0 46 0 z io 5vsa 48 bc_2 * controlr 0 49 bc_7 a_tpuch4 bidir 0 48 0 z io 5vsa 50 bc_2 * controlr 0 51 bc_7 a_tpuch5 bidir 0 50 0 z io 5vsa 52 bc_2 * controlr 0 53 bc_7 a_tpuch6 bidir 0 52 0 z io 5vsa 54 bc_2 * controlr 0 55 bc_7 a_tpuch7 bidir 0 54 0 z io 5vsa 56 bc_2 * controlr 0 57 bc_7 a_tpuch8 bidir 0 56 0 z io 5vsa 58 bc_2 * controlr 0 59 bc_7 a_tpuch9 bidir 0 58 0 z io 5vsa 60 bc_2 * controlr 0 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-19 61 bc_7 a_tpuch10 bidir 0 60 0 z io 5vsa 62 bc_2 * controlr 0 63 bc_7 a_tpuch11 bidir 0 62 0 z io 5vsa 64 bc_2 * controlr 0 65 bc_7 a_tpuch12 bidir 0 64 0 z io 5vsa 66 bc_2 * controlr 0 67 bc_7 a_tpuch13 bidir 0 66 0 z io 5vsa 68 bc_2 * controlr 0 69 bc_7 a_tpuch14 bidir 0 68 0 z io 5vsa 70 bc_2 * controlr 0 71 bc_7 a_tpuch15 bidir 0 70 0 z io 5vsa 72 bc_2 * controlr 0 73 bc_7 a_an0_anw_pqb0 bidir 0 72 0 z io 5vsa 74 bc_2 * controlr 0 75 bc_7 a_an1_anx_pqb1 bidir 0 74 0 z io 5vsa 76 bc_2 * controlr 0 77 bc_7 a_an2_any_pqb2 bidir 0 76 0 z io 5vsa 78 bc_2 * controlr 0 79 bc_7 a_an3_anz_pqb3 bidir 0 78 0 z io 5vsa 80 bc_2 * controlr 0 81 bc_7 a_an48_pqb4 bidir 0 80 0 z io 5vsa 82 bc_2 * controlr 0 83 bc_7 a_an49_pqb5 bidir 0 82 0 z io 5vsa 84 bc_2 * controlr 0 85 bc_7 a_an50_pqb6 bidir 0 84 0 z io 5vsa 86 bc_2 * controlr 0 87 bc_7 a_an51_pqb7 bidir 0 86 0 z io 5vsa 88 bc_2 * controlr 0 89 bc_7 a_an52_ma0_pqa0 bidir 0 88 0 z io 5vsa 90 bc_2 * controlr 0 91 bc_7 a_an53_ma1_pqa1 bidir 0 90 0 z io 5vsa 92 bc_2 * controlr 0 93 bc_7 a_an54_ma2_pqa2 bidir 0 92 0 z io 5vsa 94 bc_2 * controlr 0 95 bc_7 a_an55_pqa3 bidir 0 94 0 z io 5vsa 96 bc_2 * controlr 0 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-20 freescale semiconductor 97 bc_7 a_an56_pqa4 bidir 0 96 0 z io 5vsa 98 bc_2 * controlr 0 99 bc_7 a_an57_pqa5 bidir 0 98 0 z io 5vsa 100 bc_2 * controlr 0 101 bc_7 a_an58_pqa6 bidir 0 100 0 z io 5vsa 102 bc_2 * controlr 0 103 bc_7 a_an59_pqa7 bidir 0 102 0 z io 5vsa 104 bc_2 * controlr 0 105 bc_7 b_an0_anw_pqb0 bidir 0 104 0 z io 5vsa 106 bc_2 * controlr 0 107 bc_7 b_an1_anx_pqb1 bidir 0 106 0 z io 5vsa 108 bc_2 * controlr 0 109 bc_7 b_an2_any_pqb2 bidir 0 108 0 z io 5vsa 110 bc_2 * controlr 0 111 bc_7 b_an3_anz_pqb3 bidir 0 110 0 z io 5vsa 112 bc_2 * controlr 0 113 bc_7 b_an48_pqb4 bidir 0 112 0 z io 5vsa 114 bc_2 * controlr 0 115 bc_7 b_an49_pqb5 bidir 0 114 0 z io 5vsa 116 bc_2 * controlr 0 117 bc_7 b_an50_pqb6 bidir 0 116 0 z io 5vsa 118 bc_2 * controlr 0 119 bc_7 b_an51_pqb7 bidir 0 118 0 z io 5vsa 120 bc_2 * controlr 0 121 bc_7 b_an52_ma0_pqa0 bidir 0 120 0 z io 5vsa 122 bc_2 * controlr 0 123 bc_7 b_an53_ma1_pqa1 bidir 0 122 0 z io 5vsa 124 bc_2 * controlr 0 125 bc_7 b_an54_ma2_pqa2 bidir 0 124 0 z io 5vsa 126 bc_2 * controlr 0 127 bc_7 b_an55_pqa3 bidir 0 126 0 z io 5vsa 128 bc_2 * controlr 0 129 bc_7 b_an56_pqa4 bidir 0 128 0 z io 5vsa 130 bc_2 * controlr 0 131 bc_7 b_an57_pqa5 bidir 0 130 0 z io 5vsa 132 bc_2 * controlr 0 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-21 133 bc_7 b_an58_pqa6 bidir 0 132 0 z io 5vsa 134 bc_2 * controlr 0 135 bc_7 b_an59_pqa7 bidir 0 134 0 z io 5vsa 136 bc_2 * controlr 0 137 bc_7 etrig2_pcs7 bidir 0 136 0 z io 5vfa 138 bc_2 * controlr 0 139 bc_7 etrig1_pcs6 bidir 0 138 0 z io 5vfa 140 bc_2 * controlr 0 141 bc_7 mda11 bidir 0 140 0 z io 5vsa 142 bc_2 * controlr 0 143 bc_7 mda12 bidir 0 142 0 z io 5vsa 144 bc_2 * controlr 0 145 bc_7 mda13 bidir 0 144 0 z io 5vsa 146 bc_2 * controlr 0 147 bc_7 mda14 bidir 0 146 0 z io 5vsa 148 bc_2 * controlr 0 149 bc_7 mda15 bidir 0 148 0 z io 5vsa 150 bc_2 * controlr 0 151 bc_7 mda27 bidir 0 150 0 z io 5vsa 152 bc_2 * controlr 0 153 bc_7 mda28 bidir 0 152 0 z io 5vsa 154 bc_2 * controlr 0 155 bc_7 mda29 bidir 0 154 0 z io 5vsa 156 bc_2 * controlr 0 157 bc_7 mda30 bidir 0 156 0 z io 5vsa 158 bc_2 * controlr 0 159 bc_7 mda31 bidir 0 158 0 z io 5vsa 160 bc_2 * controlr 0 161 bc_7 mpwm0_mdi1 bidir 0 160 0 z io 26v5vs 162 bc_2 * controlr 0 163 bc_7 mpwm1_mdo2 bidir 0 162 0 z io 26v5vs 164 bc_2 * controlr 0 165 bc_7 mpwm2_ppm_tx1 bidir 0 164 0 z io 26v5vs 166 bc_2 * controlr 0 167 bc_7 mpwm3_ppm_rx1 bidir 0 166 0 z io 26v5vs 168 bc_2 * controlr 0 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-22 freescale semiconductor 169 bc_7 mpwm16 bidir 0 168 0 z io 5vsa 170 bc_2 * controlr 0 171 bc_7 mpwm17_mdo3 bidir 0 170 0 z io 26v5vs 172 bc_2 * controlr 0 173 bc_7 mpwm18_mdo6 bidir 0 172 0 z io 26v5vs 174 bc_2 * controlr 0 175 bc_7 mpwm19_mdo7 bidir 0 174 0 z io 26v5vs 176 bc_2 * controlr 0 177 bc_7 mpio32b5_mdo5 bidir 0 176 0 z io 26v5vs 178 bc_2 * controlr 0 179 bc_7 mpio32b6_mpwm4_mdo6 bidir 0 178 0 z io 26v5vs 180 bc_2 * controlr 0 181 bc_7 mpio32b7_mpwm5 bidir 0 180 0 z io 5vsa 182 bc_2 * controlr 0 183 bc_7 mpio32b8_mpwm20 bidir 0 182 0 z io 5vsa 184 bc_2 * controlr 0 185 bc_7 mpio32b9_mpwm21 bidir 0 184 0 z io 5vsa 186 bc_2 * controlr 0 187 bc_7 mpio32b10_ppm_tsync bidir 0 186 0 z io 26v5vs 188 bc_2 * controlr 0 189 bc_7 mpio32b11_c_cnrx0 bidir 0 188 0 z io 5vfa 190 bc_2 * controlr 0 191 bc_7 mpio32b12_c_cntx0 bidir 0 190 0 z io 5vfa 192 bc_2 * controlr 0 193 bc_7 mpio32b13_ppm_tclk bidir 0 192 0 z io 26v5vs 194 bc_2 * controlr 0 195 bc_7 mpio32b14_ppm_rx0 bidir 0 194 0 z io 26v5vs 196 bc_2 * controlr 0 197 bc_7 mpio32b15_ppm_tx0 bidir 0 196 0 z io 26v5vs 198 bc_2 * controlr 0 199 bc_7 vf0_mpio32b0_mdo1 bidir 0 198 0 z io 26v5vs 200 bc_2 * controlr 0 201 bc_7 vf1_mpio32b1_mcko bidir 0 200 0 z io 26v5vs 202 bc_2 * controlr 0 203 bc_7 vf2_mpio32b2_msei_b bidir 0 202 0 z io 26v5vs 204 bc_2 * controlr 0 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-23 205 bc_7 vfls0_mpio32b3_mseo_ b bidir 0 204 0 z io 26v5vs 206 bc_2 * controlr 0 207 bc_7 vfls1_mpio32b4 bidir 0 206 0 z io 26v5vs 208 bc_2 * internal 1 209 bc_2 a_cntx0 output2 1 o 5vfa 210 bc_2 * internal 0 211 bc_4 a_cnrx0 input x i 5vfa 212 bc_2 * controlr 0 213 bc_7 pcs0_ss_b_qgpio0 bidir 0 212 0 z io 5vfa 214 bc_2 * controlr 0 215 bc_7 pcs1_qgpio1 bidir 0 214 0 z io 5vh 216 bc_2 * controlr 0 217 bc_7 pcs2_qgpio2 bidir 0 216 0 z io 5vh 218 bc_2 * controlr 0 219 bc_7 pcs3_qgpio3 bidir 0 218 0 z io 5vh 220 bc_2 * controlr 0 221 bc_7 miso_qgpio4 bidir 0 220 0 z io 5vh 222 bc_2 * controlr 0 223 bc_7 mosi_qgpio5 bidir 0 222 0 z io 5vh 224 bc_2 * controlr 0 225 bc_7 sck_qgpio6 bidir 0 224 0 z io 5vh 226 bc_2 * internal 0 227 bc_4 eck input x i vfa 228 bc_2 * internal 1 229 bc_2 txd1_qgpo1 output2 1 o vfa 230 bc_2 * internal 1 231 bc_2 txd2_qgpo2_c_cntx0 output2 1 o vfa 232 bc_4 rxd1_qgpi1 input x i 5vido 233 bc_4 rxd2_qgpi2_c_cnrx0 input x i 5vido 234 bc_2 * internal 0 235 bc_4 b0epee input x 236 bc_2 * internal 0 237 bc_4 epee input x 238 bc_2 * internal 1 239 bc_2 engclk_buclk output2 1 table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-24 freescale semiconductor 240 bc_2 * internal 1 241 bc_2 clkout output2 1 o 26vf 242 bc_4 extclk input x i extclk 243 bc_2 * controlr 0 244 bc_7 sreset_b bidir 0 243 0 z io 26vc 245 bc_2 * controlr 0 246 bc_7 hreset_b bidir 0 245 0 z io 26vc 247 bc_2 * controlr 0 248 bc_7 rstconf_b_texp bidir 0 247 0 z io 26v 249 bc_2 * controlr 0 250 bc_7 irq7_b_modck3 bidir 0 249 0 z io 26v 251 bc_2 * controlr 0 252 bc_7 irq6_b_modck2 bidir 0 251 0 z io 26v 253 bc_2 * controlr 0 254 bc_7 irq5_b_sgpioc5_modck 1 bidir 0 253 0 z io 26v 255 bc_2 * controlr 0 256 bc_7 data_sgpiod16 bidir 0 255 0 z io 26v5vs 257 bc_2 * controlr 0 258 bc_7 data_sgpiod17 bidir 0 257 0 z io 26v5vs 259 bc_2 * controlr 0 260 bc_7 data_sgpiod18 bidir 0 259 0 z io 26v5vs 261 bc_2 * controlr 0 262 bc_7 data_sgpiod14 bidir 0 261 0 z io 26v5vs 263 bc_2 * controlr 0 264 bc_7 data_sgpiod15 bidir 0 263 0 z io 26v5vs 265 bc_2 * controlr 0 266 bc_7 data_sgpiod19 bidir 0 265 0 z io 26v5vs 267 bc_2 * controlr 0 268 bc_7 data_sgpiod20 bidir 0 267 0 z io 26v5vs 269 bc_2 * controlr 0 270 bc_7 data_sgpiod12 bidir 0 269 0 z io 26v5vs 271 bc_2 * controlr 0 272 bc_7 data_sgpiod13 bidir 0 271 0 z io 26v5vs 273 bc_2 * controlr 0 274 bc_7 data_sgpiod21 bidir 0 273 0 z io 26v5vs table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-25 275 bc_2 * controlr 0 276 bc_7 data_sgpiod10 bidir 0 275 0 z io 26v5vs 277 bc_2 * controlr 0 278 bc_7 data_sgpiod11 bidir 0 277 0 z io 26v5vs 279 bc_2 * controlr 0 280 bc_7 data_sgpiod22 bidir 0 279 0 z io 26v5vs 281 bc_2 * controlr 0 282 bc_7 data_sgpiod23 bidir 0 281 0 z io 26v5vs 283 bc_2 * controlr 0 284 bc_7 data_sgpiod8 bidir 0 283 0 z io 26v5vs 285 bc_2 * controlr 0 286 bc_7 data_sgpiod9 bidir 0 285 0 z io 26v5vs 287 bc_2 * controlr 0 288 bc_7 data_sgpiod24 bidir 0 287 0 z io 26v5vs 289 bc_2 * controlr 0 290 bc_7 data_sgpiod25 bidir 0 289 0 z io 26v5vs 291 bc_2 * controlr 0 292 bc_7 data_sgpiod6 bidir 0 291 0 z io 26v5vs 293 bc_2 * controlr 0 294 bc_7 data_sgpiod7 bidir 0 293 0 z io 26v5vs 295 bc_2 * controlr 0 296 bc_7 data_sgpiod26 bidir 0 295 0 z io 26v5vs 297 bc_2 * controlr 0 298 bc_7 data_sgpiod27 bidir 0 297 0 z io 26v5vs 299 bc_2 * controlr 0 300 bc_7 data_sgpiod4 bidir 0 299 0 z io 26v5vs 301 bc_2 * controlr 0 302 bc_7 data_sgpiod5 bidir 0 301 0 z io 26v5vs 303 bc_2 * controlr 0 304 bc_7 data_sgpiod28 bidir 0 303 0 z io 26v5vs 305 bc_2 * controlr 0 306 bc_7 data_sgpiod29 bidir 0 305 0 z io 26v5vs 307 bc_2 * controlr 0 308 bc_7 data_sgpiod2 bidir 0 307 0 z io 26v5vs 309 bc_2 * controlr 0 310 bc_7 data_sgpiod3 bidir 0 309 0 z io 26v5vs table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-26 freescale semiconductor 311 bc_2 * controlr 0 312 bc_7 data_sgpiod30 bidir 0 311 0 z io 26v5vs 313 bc_2 * controlr 0 314 bc_7 data_sgpiod0 bidir 0 313 0 z io 26v5vs 315 bc_2 * controlr 0 316 bc_7 data_sgpiod1 bidir 0 315 0 z io 26v5vs 317 bc_2 * controlr 0 318 bc_7 data_sgpiod31 bidir 0 317 0 z io 26v5vs 319 bc_2 * controlr 0 320 bc_7 addr_sgpioa29 bidir 0 319 0 z io 26v5vs 321 bc_2 * controlr 0 322 bc_7 addr_sgpioa25 bidir 0 321 0 z io 26v5vs 323 bc_2 * controlr 0 324 bc_7 addr_sgpioa26 bidir 0 323 0 z io 26v5vs 325 bc_2 * controlr 0 326 bc_7 addr_sgpioa27 bidir 0 325 0 z io 26v5vs 327 bc_2 * controlr 0 328 bc_7 addr_sgpioa28 bidir 0 327 0 z io 26v5vs 329 bc_2 * controlr 0 330 bc_7 addr_sgpioa24 bidir 0 329 0 z io 26v5vs 331 bc_2 * controlr 0 332 bc_7 addr_sgpioa23 bidir 0 331 0 z io 26v5vs 333 bc_2 * controlr 0 334 bc_7 addr_sgpioa22 bidir 0 333 0 z io 26v5vs 335 bc_2 * controlr 0 336 bc_7 addr_sgpioa30 bidir 0 335 0 z io 26v5vs 337 bc_2 * controlr 0 338 bc_7 addr_sgpioa21 bidir 0 337 0 z io 26v5vs 339 bc_2 * controlr 0 340 bc_7 addr_sgpioa20 bidir 0 339 0 z io 26v5vs 341 bc_2 * controlr 0 342 bc_7 addr_sgpioa8 bidir 0 341 0 z io 26v5vs 343 bc_2 * controlr 0 344 bc_7 addr_sgpioa31 bidir 0 343 0 z io 26v5vs 345 bc_2 * controlr 0 346 bc_7 addr_sgpioa19 bidir 0 345 0 z io 26v5vs table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-27 347 bc_2 * controlr 0 348 bc_7 addr_sgpioa18 bidir 0 347 0 z io 26v5vs 349 bc_2 * controlr 0 350 bc_7 addr_sgpioa9 bidir 0 349 0 z io 26v5vs 351 bc_2 * controlr 0 352 bc_7 addr_sgpioa17 bidir 0 351 0 z io 26v5vs 353 bc_2 * controlr 0 354 bc_7 addr_sgpioa16 bidir 0 353 0 z io 26v5vs 355 bc_2 * controlr 0 356 bc_7 addr_sgpioa10 bidir 0 355 0 z io 26v5vs 357 bc_2 * controlr 0 358 bc_7 addr_sgpioa15 bidir 0 357 0 z io 26v5vs 359 bc_2 * controlr 0 360 bc_7 addr_sgpioa14 bidir 0 359 0 z io 26v5vs 361 bc_2 * controlr 0 362 bc_7 addr_sgpioa13 bidir 0 361 0 z io 26v5vs 363 bc_2 * controlr 0 364 bc_7 addr_sgpioa11 bidir 0 363 0 z io 26v5vs 365 bc_2 * controlr 0 366 bc_7 addr_sgpioa12 bidir 0 365 0 z io 26v5vs 367 bc_2 * controlr 0 368 bc_7 bi_b_sts_b bidir 0 367 0 z io 26v 369 bc_2 * controlr 0 370 bc_7 burst_b bidir 0 369 0 z io 26v 371 bc_2 * controlr 0 372 bc_7 bdip_b bidir 0 371 0 z io 26v 373 bc_2 * controlr 0 374 bc_7 ta_b bidir 0 373 0 z io 26v 375 bc_2 * controlr 0 376 bc_7 ts_b bidir 0 375 0 z io 26v 377 bc_2 * controlr 0 378 bc_7 tsiz1 bidir 0 377 0 z io 26v 379 bc_2 * controlr 0 380 bc_7 tsiz0 bidir 0 379 0 z io 26v 381 bc_2 * controlr 0 382 bc_7 tea_b bidir 0 381 0 z io 26v table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-28 freescale semiconductor 383 bc_2 * internal 1 384 bc_2 oe_b output2 1 o 26v 385 bc_2 * controlr 0 386 bc_7 rd_wr_b bidir 0 385 0 z io 26v 387 bc_2 * internal 1 388 bc_2 cs3_b output2 1 o 26v 389 bc_2 * internal 1 390 bc_2 cs2_b output2 1 o 26v 391 bc_2 * internal 1 392 bc_2 cs1_b output2 1 o 26v 393 bc_2 * internal 1 394 bc_2 cs0_b output2 1 o 26v 395 bc_2 * internal 1 396 bc_2 we_b_at3 output2 1 o 26v 397 bc_2 * internal 1 398 bc_2 we_b_at2 output2 1 o 26v 399 bc_2 * internal 1 400 bc_2 we_b_at1 output2 1 o 26v 401 bc_2 * internal 1 402 bc_2 we_b_at0 output2 1 o 26v 403 bc_2 * controlr 0 404 bc_7 br_b_vf1_iwp2 bidir 0 403 0 z io 26v 405 bc_2 * controlr 0 406 bc_7 bg_b_vf0_lwp1 bidir 0 405 0 z io 26v 407 bc_2 * controlr 0 408 bc_7 bb_b_vf2_iwp3 bidir 0 407 0 z io 26v 409 bc_2 * controlr 0 410 bc_7 sgpioc7_irqout_b_lwp 0 bidir 0 409 0 z io 26v 411 bc_2 * controlr 0 412 bc_7 irq1_b_rsv_b_sgpi oc1 bidir 0 411 0 z io 26v5vs 413 bc_2 * controlr 0 414 bc_7 irq0_b_sgpioc0_mdo4 bidir 0 413 0 z io 26v5vs 415 bc_2 * controlr 0 416 bc_7 irq2_b_cr_b_sgpioc2_| mdo5_mts_b bidir 0 415 0 z io 26v table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-29 1.bi-state outputs (pin function = o) su ch as mdo_2, and mdo_3, are incorporated with general i/o pads hard-wired to keep output enable always on in system mode. the jtag control cell, i ndicated by the next lower bsdl bit in the chain, is configure d as an ?internal? only cell to be held at a ?1? value (always driving out) during jtag testing. 2. some input-only cells made with generic i/ o pads are configured with ?internal? control cells to keep them always in input m ode, such as epee, b0epee, and input pins that may be attached to analog references. other input-only cells are configured as bidirectional for jtag testing, to give the board-level atpg tools the flexability to use the pad as an input or output, depend ing on the network of other devices that the pin is connected too. if it is desired to restrict these pins to only act as receiver s during jtag mode, then these jtag bsdl entries can be converted as shown in the example below: 3. this description allows atpg tools to use a pin as a driver or receiver: 4. a modification to restrict atpg tools to use a functional input-only pin as an input receiver only:. 5. the poreset , hreset , and sreset pins are not part of the jtag boundary scan chain. these pins are used in the reset configuration to enter jtag. board-level connections to them will not be testable with the extest and clamp instructions. they do respond to the hi-z jtag instruction for parametric testing purposes.6. 6. the xtal, extal, and xfc pins are associated with analog signals and are excluded from the boundary scan chain. 7. the readi module reset pin, rsti_b, (bsdl pin 517) is in t he jtag boundary scan chain, but must be kept at a ?0? level durin g jtag testing, (except for hi-z testing), due to system interacti ons. it is classified as a ?linkage? pin, and its data and cont rol cells are configured to advise atpg tools to drive a ?0? value in during jtag testing. 8. pad type naming conventions: 26 v ? 2.6 v 5 v ? 5 v s ? slow f ? fast h ? high drive a ? analog input i ? input only d ? has direct connection to the pad (may be used for module test) 417 bc_2 * controlr 0 418 bc_7 irq4_b_at2_sgpioc4 bidir 0 417 0 z io 26v5vs 419 bc_2 * controlr 0 420 bc_7 irq3_b_kr_b_retry_b_ sgpioc3 bidir 0 419 0 z io 26v5vs 421 bc_2 * internal 1 422 bc_2 iwp0_vfls0 output2 1 o 26v 423 bc_2 * internal 1 424 bc_2 iwp1_vfls1 output2 1 o 26v 425 bc_2 * controlr 0 426 bc_7 sgpioc6_frz_ptr_b bidir 0 425 0 z io 26v5vs 188 bc_2 * controlr 0 189 bc_7 irq6_b_modck2 bidir 0 188 0 z i 26v 188 bc_2 * internal 0 189 bc_4 irq6_b_modck2 input x i 26v table 25-2. mpc563 boundary scan bit definition (continued) bsdl bit cell type pin/port name bsdl function safe value contro l cell disable value disabl e result pin functio n pad type ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-30 freescale semiconductor r ? resized cell instance 9. column descriptions: columns 1 through 8 are entries from the boundary-scan descr iption from the bsdl file. the columns and formats for each of these entries are defined in the ieee std. 1149.1b-1994 s upplement to the ieee std. 1149.1-1990, ieee standard test access port and boundary-scan architecture document . descriptions of these columns are described below: column 1: defines the bit?s ordinal position in the boundary scan register. the shif t register cell nearest tdo (i.e., first to be shifted in) is defined as bit 0; the last bit to be shifted in is 519. column 2: references one of the three standard jtag cell ty pes (bc_4, bc_2, and bc_7) that are used for this jtag cell in the mpc561/mpc563. see the ieee std. 1149.1-1990, ieee standard test access port and boundary-scan architecture document for further description of these standard cell types. column 3: lists the pin name (also called the portid) for all pi n-related cells. for jtag contro l cells or data cells that ha ve been designated as ?internal?, an asterisk, is shown in this column. column 4: lists the bsdl pin function. column 5: the ?safe bit? column specifie s the value that should be loaded into the capture (and update) flip-flop of a given cell when board-level test generation software might otherwise choose a value randomly. column 6: the ?control cell? column identifies the cell number of the control cell that is a ssociated with this data cell, an d can disable its output. column 7: the ?disable value? column gives the value that mu st be scanned into the control cell identified by the previous ?control cell? (column 6) to disable the port named by the relevant portid. column 8: the ?disable result? column identifies a given sign al value of the portid if that signal can be disabled. the value s shown specifies the condition of the driver of that signal when it is disabled. column 9: the ?pin function? column indicates the normal system pin direct ionality. (? input only pi n, o ? output only pin, i/o ? bidirectional i/o pin) column 10: the pad type column describes relevant characteri stics about each pad type. see the pad type keys in note 5 above. 25.1.3 instruction register the mpc561/mpc563 jtag implementation incl udes the public instructions (extest, sample/preload, and bypass), and also supports the clamp instruction. one additional public instruction (hi-z) provides the capability for disa bling all device output dr ivers. the mpc561/mpc563 includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. the four bits are used to decode the five unique instructions listed in. the parallel output of the instruction register is reset to all ones in th e test-logic-reset c ontroller state. note this preset state is equivalent to the bypass instruction. table 25-3. instruction decoding code b3 b2 b1 b0 1 1 b0 (lsb) is shifted first instruction 0 0 0 0 extest 0 0 0 1 sample/preload 0 x 1 x bypass 0100 hi-z 0 1 0 1 clamp and bypass ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-31 during the capture-ir controller state, the parallel inputs to the instruct ion shift register are loaded with the clamp command code. 25.1.3.1 extest the external test (extest) instruction selects th e 520-bit boundary scan regi ster. extest also asserts internal reset for the mpc561/mpc563 system logic to force a predicta ble beginning internal state while performing external boundary scan operations. by using the tap, the register is capable of: a) scanning user-defined values into the output buffers b) capturing values presented to input pins c) controlling the output drive of thre e-state output or bidirectional pins 25.1.3.2 sample/preload the sample/preload instruction in itializes the boundary scan register output cell s prior to selection of extest. this initialization en sures that known data will appear on the outputs when entering the extest instruction. the sample/pr eload instruction also provides a means to obtain a snapshot of system data and control signals. note since there is no internal synchroni zation between the scan chain clock (tck) and the system clock (clkout) , there must be provision of some form of external synchronization to achieve meaningful results. 25.1.3.3 bypass the bypass instruction sele cts the single-bit bypass register as shown in figure 25-5 . this creates a shift register path from tdi to the bypass register and, fi nally, to tdo, circumventing the 520-bit boundary scan register. this instruction is used to enhanc e test efficiency when a component other than the mpc561/mpc563 becomes the device under test. figure 25-5. bypass register when the bypass register is selected by the current instruction, the shift regi ster stage is set to a logic zero on the rising edge of tck in the capture -dr controller state. therefore, th e first bit to be shifted out after selecting the bypass re gister will always be a logic zero. 1 1 mux g1 c d to tdo from tdi 0 shift dr clock dr ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-32 freescale semiconductor 25.1.3.4 clamp the clamp instruction selects the singl e-bit bypass register as shown in figure 25-5 , and the state of all signals driven from system output pins is complete ly defined by the data previously shifted into the boundary scan register (for example, us ing the sample/preload instruction). 25.1.4 hi-z the hi-z instruction is provided as a manufacturer?s optional public instruction to prevent having to backdrive the output pins during circ uit-board testing. when hi-z is i nvoked, all output drivers, including the two-state drivers, ar e turned off (i.e., high impedance). the instruction selects the bypass register. 25.2 mpc561/mpc563 restrictions the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. the user must avoi d situations in which the mpc561/mp c563 output drivers are enabled into actively driven networks. the mpc561/mpc563 features a low-power stop mode. th e interaction of the scan chain interface with low-power stop mode is as follows: 1. the tap controller must be in th e test-logic-reset state to either enter or remain in the low-power stop mode. leaving the tap controller in the test -logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tck input is not blocked in low-power stop mode. to cons ume minimal power, the tck input should be externally connected to v dd or ground. 3. the tms pin includes an on-chip pull-up resistor. in low-power stop mode, this pin should remain either unconnected or connected to vdd to achie ve minimal power consumption. note that for proper reset of the scan chain test logic, the best approach is to pull jcomp low at power-on reset (poreset ). 4. jcomp must be low prior to poreset assertion after low power mode exits otherwise an unknown state will occur. 25.2.1 non-scan chain operation in non-scan chain operation, there are two constraints. first, the tck in put does not include an internal pull-up resistor and should not be le ft unconnected to preclude mid-level inputs. the second constraint is to ensure that the scan chain test logic is kept tr ansparent to the system logic by forcing tap into the test-logic-reset controller state, using either of two methods. connecting pin jc omp to logic 0 (or one of the reset pins), or tms must be sa mpled as a logic one for five consecutive tck risi ng edges. if then tms either remains unconnected or is connected to v dd , then the tap controller cannot leave the test-logic-reset state, rega rdless of the state of tck. ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor 25-33 25.2.2 bsdl description the bsdl file for the mpc561/mpc563 ca n be found on the freescale web site. ieee 1149.1-compliant interface (jtag) mpc561/mpc563 reference manual, rev. 1.2 25-34 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-1 appendix a mpc562/mpc564 compression features the mpc562/mpc564 contains a number of code compression features not found in the mpc561/mpc563 that function from the burst buffer controller module (bbc) module of the device. the bbc?s instruction code decompre ssor unit (icdu) is re sponsible for on-line (previously compressed) instruction code decompression in the decompre ssion on mode. the icdu contains a 2-kbyte ram (decram) that is used for decomp ressor vocabulary table storage wh en compression is enabled or as general-purpose memory on the u-bus when compression is disabled. note the code compression features of the mpc562/mpc564 are different than the code compression of the mpc556. a.1 icdu key features the following are instruction code decompression unit key features: ? instruction code on-line deco mpression is based on an ?i nstruction class? algorithm. ? there is no need for address translation between compressed and non-compressed address spaces ? icdu provides the ?next instruction address? to the rcpu. ? in most cases, instruction decompression takes one clock. ? code decompression is pipelined: ? no performance penalty during se quential program flow execution ? minimal performance penalty due to change of program flow execution ? two operation modes are availa ble: decompression on and deco mpression off. switches between compressed and non-compressed user a pplication software is possible. ? adaptive vocabularies scheme is supported; each user applic ation can have its own optimum vocabularies. a.2 class-based compression model main principles the operational model used by the mpc562/mpc 564 is explained in the sections below. a.2.1 compression model features ? implemented for mpc56x architecture ? up to 50% instructi on code size reduction ? no need for addre ss translation tables mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-2 freescale semiconductor ? no changes in the cpu architecture ? a compressor tool performs compression off-li ne in software using instruction class-based algorithms optimized for th e mpc56x instruction set ? decompression is done at run-time by special hardware ? optimized for cache-less systems: ? highly effective in system solutions for a low- cache hit ratio environmen t and for systems with fast embedded program memory ? deterministic program execution ? no performance penalty during se quential program flow execution ? minimal performance penalty due to change of program flow execution ? switches between compressed and non-compressed user application secti ons is possible. (a compressed subroutine ca n call a non-compressed one and be called from non-compressed portions of the user application) ? adaptive vocabularies, generate d for a particular application ? compressed address space is up to 1 gbyte ? branch displacement from its target: ? conditional branch displacement is up to 4 kbytes ? unconditional branch displacement is up to 4 mbytes note branch displacement is hardware l imited. the compiler can enlarge the branch scope by creating branch chains. a.2.2 model limitations no address arithmetic is allowed for instruc tion space because the address map changes during compression and no software tool can identify addre ss arithmetic structures in the code. address arithmetic for data tables is pe rmitted since data space is not co mpressed. only instruction space is compressed. a.2.3 instruction class-ba sed compression algorithm the code compression algorithm is based on creating optimal vocabularies of freque ntly appearing rcpu risc instructions or instruction ha lves and replacing these instructions with pointers to the vocabularies. the system contains several sets of vocabularies for different groups of instructions. these groups are referred to as classes. every instruction belongs to exactly one class. compression of the instruct ions in a class ma y be in one of the following modes. refer to figure a-1 . 1. compression of the whole instru ction into one vocabulary pointer 2. compression of each half of the in struction into a different vocabulary mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-3 3. compression of one of the instruction?s halves into a vocabulary pointer and bypass of the other half. a bypassed field is one for which non-compres sed data (16-bit halfword or 32-bit word) is placed in the compressed code. after compressi on is defined, the non-compressed data field is defined in the class. 4. bypass of the whole instructi on. no compression is permitted. figure a-1. instruction compression alternatives a 4-bit class identifier is added to the beginning of each compressed instru ction to supply class identification during decompressi on. compressed and bypass field leng ths may vary. (a fully bypassed instruction, including its 4-bit class identifier, is 36 bits.) the compressed instruction is guaranteed to start on an even bit. thus, four bits are needed to find the starting location of the instruction inside a memory word. the instruction address in decompression on mode consists of a 28-bit word addr ess (1 gbyte of address space) and a 4-bit instruction pointer (ip). see figure a-2 . uncompressed instruction compressed instruction 1. 2. 3. 4. legend uncompressed or bypassed code compressed code class identifier or 1. 2. 3. 4. mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-4 freescale semiconductor figure a-2. addressing instructions with compressed address a.2.4 compressed address genera tion with direct branches during the compression process, comp ressed instructions change their location in the memory and are not word aligned. displacement fi elds in the direct branch instructions have to be updated by the compression tool to make compressed instruct ion addressing possible. four lsb b its of the displacement immediate field (li or bd) in the compressed direct branch in structions are used for bi t addressing in the 32-bit memory word. the remaining bits of the fields are used in the branch target calcul ation of the base address (word address). the rcpu branch unit copies the bit point er into the ip field of issued compressed branch target address. the branch compre ssed target base address is calcul ated according the direct branch addressing mode. if a branch has absolute addressing mode, the branch target base address is calculated as a sign extension of the base address portion of the li (or bd) field. if a branch has relative addressing m ode, the branch target base address is calculated as a sum of the base address of the branch and sign extended base a ddress portion of the bran ch li (or bd) field. figure a-3 illustrates direct branch ta rget address generation in ?dec ompression on? mode. the base address for the unconditional branch has 20 bits this yields an unc onditional branch displacement limit of 4 mbytes. the word pointer for th e conditional branch has 10 bits. th is yields a conditional branch displacement limit of 4 kbytes. compressed instruction adddress memory layout base address 27 31 ip 2*ip bits ? compressed instruction x x+4 x+8 x+c mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-5 figure a-3. compressed target address generation by direct branches 0 6 26 30 31 30 31 30 3 1 30 3 1 28 3 1 0 26 6 16 16 0 0 0 unconditional immediate branch instruction before compression mapping unconditional immediate branch instruction after compression mapping (i-form) conditional immediate branch instruction before compression mapping conditional immediate branch instruction after compression mapping (b-form) branch target compressed address 4-biit pointer 4-bit pointer 4-bit pointer word pointer (li) word pointer - base address word pointer w o rd p o in te r (bd ) word pointer aa aa aa aa sign extension word point er sign extended base address generation for unconditional branches 27 08 or sign extension word pointer sign extended base address generation for conditional branches 27 018 + bit pointer from instruction or aa=0 aa=1 base address of the branch sign extended base address mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-6 freescale semiconductor when a change of flow occurs, the rcpu issues the new address in compre ssion format. the address extractor unit of the bbc extracts th e base address to instruction memory. when the compressed memory word is brought to the bbc from the memory, the icdu uses the ip field of th e rcpu-issued address to decompress the instruction. the bbc provides compre ssed addresses of the decompressed and next instructions to the rcpu together with the decompressed instruction. shortened word pointer fiel ds of direct branches in compressed mode imply some limitations on compilers that implement the powerpc isa architecture. they s hould generate binaries, with limited direct branch displacements to make the compression possible. if a conditional branch target, generated by a comp iler, must be farther than the compression mode limitation of 4 kbytes, the compiler may generate a sequence of a conditional branch with opposite condition to skip the follo wing unconditional branch to the original target. if the unconditional branch range is still not big enough, the co mpiler can use branch chains or indirect branches. a.2.5 compressed address ge neration?indirect branches the indirect branch destin ation address is copied w ithout any change from one of the following rcpu registers: ?lr ?ctr ?srr0 see the rcpu user?s manual for more details. these registers should contain (or be loaded by) the 32-bit compressed addre ss of existing compressed instructions to be used for correct branching. the lr register is automatically update d by the correct value of the ?next? instruction compressed address during subroutine calls by using the ? l ? - form of branch instructions (like bl or bcl ). the srr0 register is upda ted by the correct return compressed a ddress when exceptions are taken by the rcpu, thus the rfi instruction obtains the correct return address from an exception handler. a.2.6 compressed address generation?exceptions upon an exception, the rcpu core issues a re gular 0xfff00x00 or 0x00000x00 exception vector as specified in the powerpc isa architecture. the co mpressed exception routines (or branches to them) should start (reside) at the same location in me mory as noncompressed ones. the bbc icdu passes the vectors unchanged to the mcu intern al bus and provides corresponding compressed address to the rcpu together with the first excep tion handler instruction opcode. this scheme allows use of the bbc exception reloca tion feature regardless of the mcu operational mode. the reset routine vector is relocated differently in decompression on and in decompression off modes. this feature may be used by a software code comp ression tool to guarantee that a vocabulary table initialization routine is al ways executed before appl ication code is running. mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-7 a.2.7 class code compression algorithm rules ? compressed instruction length may vary between 6 and 36 bits and is even. ? a compressed instruction can begin at any even location in a memory word. ? an instruction source ma y be compressed as a single 32-bit se gment or as two independent 16-bit segments. ? possible partitions of an instruction for compression are: ? one 32-bit bypass segment ? one 32-bit compressed segment ? one 16-bit compressed segment and one 16-bit bypass segment ? two 16-bit compressed segments ? a bypass field is always the seco nd field of the two po ssible. length of a bypa ss field can be zero, 10, 15, 16 or 32 bits. ? the class prefix in a compressed instructi on is 4 bits long and covers up to 16 classes. ? the vocabulary table pointer of eac h field may be 2 to 9 bits long. ? vocabulary table pointers are reversed in the code . this means the pointer?s lsb will be the first bit. ? in a class with a single segment of full co mpression, data is fetched from both memories. ? every vocabulary table in the decram is 16 bytes (8 entries) aligned (3 lsbs zeroed). a.2.8 bypass field compression rules the bypass field can be either a full bypass, (i.e., the whole segmen t from the un-compressed instruction appears as is in the compressed in struction), or it can be represen ted in one of se veral compression encoding formats. these formats are ha rd-wired in the decompression module. a.2.8.1 branch right se gment compression #1 for the mpc562/mpc564, a 15-bit bypass is used to indicate that the aa bi t of a branch in struction should be inserted with a value of zero. the deco mpression process is performed as shown in figure a-4 . figure a-4. branch right segment compression #1 this bypass is coded by a value of ?13? (0xd) in the tp2len field of the dccr register. 15-bit compressed decompressed 0 13 14 16 29 30 right segment 31 0 lk bypass field mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-8 freescale semiconductor a.2.8.2 branch right se gment compression #2 also created for branch instructions on the mpc 562/mpc564, a bypass of 10 bits indicates that the aa bit should be inserted with a value of zero and that the 5-bit word offset should be extended to 10 bits. the decompression process is performed as shown in figure a-5 . figure a-5. branch right segment compression #2 this bypass is coded by a value of ?12? (0xc) in the tp2len field of the dccr register. a.2.8.3 right segment zero length compression bypass this mpc562/mpc564 bypass type indicat es that no bypass data exists in the compressed instruction. the bypassed segment is16 zero bits. this bypass is coded by a value of ?11? (0xb ) in the tp2len field of the dccr register. a.2.9 instruction class st ructures and programming the four possible compression layouts of an instruction and their attr ibutes are listed in this section. see section a.4, ?decompressor class c onfiguration registers (dccr0-15) ,? for the instruction class attributes and more programming details. a.2.9.1 global bypass this mpc562/mpc564 instruction is not compressed at all. figure a-6. global bypass instruction layout this class does not have a c onfiguration register. its pref ix is hard-wired to ?0000? and no other attributes are needed. 10-bit compressed bypass field decompressed 0 8 9 16 29 30 right segment 31 0 4 5 w o r d o f f s e t 1 ip lk 26 25 22 21 32-bit bypass data 0 0 0 0 32-bit segment ? to be bypassed uncompressed instruction compressed instruction msb mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-9 a.2.9.2 single segment full compression ? class_1 this mpc562/mpc564 instruction is compressed into a single segment. the vocabulary table pointer points to an offset in ta bles of all rams (decrams). figure a-7. class_1 instruction layout the definition of the class includes: ? tp1 length = 2-9 ? tp2 length = 0 ? tp1 base address, tp2 base address = the tw o tables? base addresses for ram #1 and ram #2, respectively. ?as, ds=0 data brought from ram#1 is the 16 msbs of the decompressed instruction and data brought from ram#2 is the 16 lsbs of th e decompressed instruction. a.2.9.3 twin segment full compression ? class_2 this mpc562/mpc564 instruction is divided into two segments. each segment is compressed and mapped into a different vocabulary. the vocabularies reside in different rams. proper programming can swap the vocabularies? locations. figure a-8. class_2 instruction layout the definition of the class includes: 32-bit segment ? to be compressed 2-to 9-bit tp1 4-bit class uncompressed instruction compressed instruction msb 16-bit segment #1 ? to be compressed 2- to 9-bit tp1 for segment #1 4-bit class uncompressed instruction compressed instruction 16-bit segment #2 ? to be compressed msb alternative #1 (class_2a) 2- to 9-bit tp2 for segment #2 2- to 9-bit tp1 for segment #2 4-bit class alternative #2 (class_2b) 2- to 9-bit tp2 for segment #1 mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-10 freescale semiconductor ? tp1 length=2-9 ? tp2 length=2-9 ?as=0 ? for alternative #1: ? tp1 base address = base address of segment #1 vocabulary in ram #1 ? tp2 base address = base address of segment #2 vocabulary in ram #2 ?ds=0 ? for alternative #2: ? tp1 base address = base address of segment #2 vocabulary in ram #1 ? tp2 base address = base address of segment #1 vocabulary in ram #2 ?ds=1 alternatives #1 and #2 are referred to as class_2a and class_2b respectively. a.2.9.4 left segment compression a nd right segment bypass ? class_3 for the mpc562/mpc564, the instruction is divided into two segments. the left segment is compressed and mapped into a vocabulary. the vocabulary location is programmable. the right segment is either fully bypassed by a 16-bit field or by a shorter field which is decompre ssed according to fixed rules. . figure a-9. class_3 instruction layout the definition of the class includes ? tp1 length=2-9 ? tp2 length=0xb, 0xc, 0xd, or 0xe indicati ng a 0, 10, 15 or 16 bit bypass, respectively. ? tp1 base address = base address of segment #1 vocabulary in ram #1, if it exists there. ? tp2 base address = base address of segment #1 vocabulary in ram #2, if it exists there. ?ds=0 ? as=0 or 1 directing access to the voca bulary in ram #1 or ram #2, respectively. when the vocabulary is located in ram #1, the class will be referred to as class_3a and when the vocabulary is located in ram #2, the clas s will be referred to as class_3b. 16-bit segment #1 ? to be compressed 2- to 9-bit tp1 for segment #1 4-bit class uncompressed instruction compressed instruction 16-bit segment #2 ? to be bypassed msb 0-, 10-, 15- or 16-bit bypass for segment #2 mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-11 a.2.9.5 left segment bypass and ri ght segment compression?class_4 this mpc562/mpc564 instruction is di vided into two segments. the left segment is either fully bypassed by a 16-bit field or by a shorter fiel d which is decompressed according to fixed rules. the right segment is compressed and mapped into a vocabulary. the vo cabulary location is programmable. the compressed fields must be swapped in the comp ressed instruction order to follow th e rule that bypass appears only in the second field of a compressed instruction. . figure a-10. class_4 instruction layout the definition of the class includes: ? tp1 length=2-9 ? tp2 length=0xb, 0xc, 0xd, or 0xe indicati ng a 0, 10, 15 or 16 bit bypass, respectively. ? tp1 base address = base address of segment #1 vocabulary in ram #1, if it exists there ? tp2 base address = base address of segment #1 vocabulary in ram #2, if it exists there ?ds=1 ? as=0 or 1 directing access to the voca bulary in ram #1 or ram #2, respectively. when the vocabulary is located in ram #1, the class is referred to as class_4band when the vocabulary is located in ram #2, the class is re ferred to as class_4a. refer to table a-4 . a.2.10 instruction layout programming summary table a-4 summarizes the programmi ng for all possible compre ssed instruction layouts. the un-compressed instruction of two half-words ar e referred as h1 & h2. the compressed instruction can be built out of: (1) x1 field ? representing a voca bulary pointer for encoding of either h1 or h1+h2; (2) x2 field ? representing a vocabul ary pointer for encoding of h2; and (3) bp ? representing a bypass field. vocabularies v1 and v2 refer to the 16 msb and 16 lsb of the uncompressed instruction, respectively. a.2.11 compression process the compression process is implemented by the following steps. see figure a-11 . ? user code compilation/linking ? vocabulary and class generation ? user application code compression by a software compression tool 16-bit segment #1 ? to be bypassed 2- to 9-bit tp1 for segment #2 4-bit class u ncompresse d i ns t ruc ti on compressed instruction 16-bit segment #2 ? to be compressed msb 0-, 10-, 15- or 16-bit bypass for segment #1 mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-12 freescale semiconductor the vocabulary and class configurati ons are generated by profiling the st atic code, based on the instruction class algorithm. the code compression can be crea ted by using either default or sp ecific application vocabularies, generated at the previous step. in case of default vocabularies, the generation step can be omitted, but compression efficiency is reduced. the compression tool replaces regular powerpc isa in structions with a compressed representation that contains fewer bits. the tool also updates offset fields in direct br anch instructions to include a compressed format offset (four bits of ip a nd word offset). thus, maximum branch offsets in decompression on mode are reduced. the rcpu uses the word offset for di rect branch target address computation. the rcpu provides the instruction poin ter portion of the branch offset field to the decompression unit as it is represented in the branch instruction. figure a-11. code compression process a.2.12 decompression ? the instruction code is stored in the memory in the compressed format ? the vocabularies are stored in a dedicated icdu ram (decram) ? the class configuration is stored in a dedicated icdu register (dccr) ? the decompression is done on-line by the dedicated decompressor unit ? decompression flow is as follows: (see figure a-12 ) ? rcpu provides to the bbc a 2-bit ali gned change of flow (cof) address compiler/ program executable compressor linker to o l vocabulary generator generator classes classes non-compressed program executable compressed vocabulary vocabulary generation tool mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-13 ? the icdu: ? converts the cof address to a word-aligne d physical address to access the memory ? fetches the compressed instru ction code from the memory, decompresses it and delivers non-compressed instructio n code, together with the bit-ali gned next instruct ion address, to the rcpu. figure a-12. code decompression process a.2.13 compression environment initialization in order to commence the execution of the compress ed code, the decram and the class information (in the dccr registers) must be prog rammed. the data to be programmed is supplied by the compressor tool and the vocabulary generator. ther e are two initialization scenarios: 1. wake up in decompression off mode ? if the chip wakes up with decompression disabled, the initialization routine can be executed at any time before entering d ecompression on mode. after the compression environment is initialized, the operational mode would be changed to decompression on. 2. wake up in decompression on mode ? if the chip wakes up in decompression on mode, it has to process compressed instructi ons without the vocabularies a nd class parameters. thus, all instructions executed until the end of the initia lization routine should be compressed in the global bypass format. decram loading is an essential part of this intial ization routine. after decram loading, efficient compressed code may be used. compressed memory instructions de vocabulary compressor mpc500 embedded cpu bit-aligned cof noncompressed instruction code address cof word aligned physical address compressed instruction compressed space ?next instruction? address code classes (dccr) registers icdu mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-14 freescale semiconductor a.2.14 compression/non-co mpression mode switch the mpc562/mpc564 allows the opti on to switch between compressed and non-compressed code on the fly. there are two ways to switch between the modes, as shown in section a.2.14.1, ?compression definition for exception handlers ,? and section a.2.14.2, ?running mixed code .? a.2.14.1 compression definiti on for exception handlers the mpc562/mpc564 can wake up upon reset with all the exception handlers defined to be compressed (or not), so when any exception occurs or complete s, the hardware switches to the appropriate mode without software intervention. a.2.14.2 running mixed code if the compression mode is enabled on the mpc562/mpc564, the softwa re can switch between compressed and non-compressed code by setting (or clearing) the co mpression mode bit in the rcpu msr register. this is done by setting/clearing bit 29 in the rcpu srr1 register (srr1 gets loaded into the msr register when the rfi instruction is executed. bit 29 is the dcmpen bit of the msr). the next step is to load srr0 with a targ et address in compressed/non-compress ed format and then executing an rfi instruction. following is a suggested routine to exec ute the switch in both directions (must be run in supervisor mode when rcpu msr[pr] bit is cleared): # r30 contains destination address in appropriate format .set turn_on_compression_bit_mask, 4 .set turn_off_compression_bit_mask, 0xfffb mfmsr r31 # to go to compressed code ori r31,r31,turn_on_compression_bit_mask # or alternative to go to uncompressed code: andi. r31,r31,turn_off_compression_bit_mask mtspr nri,r0 # disable external interrupts mtspr srr1,r31 mtspr srr0,r30 # destination address load rfi # branch and modify msr note when bbcmcr[en_comp] (bit 21) is set, modification of msr[dcmpen] (bit 29) by mtmsr instruc tion is strictly forbidden. it may cause the machine to hang until reset. a.3 operation modes a.3.1 instruction fetch the mpc562/mpc564 provides two instruction fetch modes: decompression off and decompression on. the operational modes are defined by rcpu msr[dcmpen] bit. if the bit is set, the mode is decompression on. otherwise, it is in decompression off. mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-15 a.3.1.1 decompression off mode refer to section 4.2.1.1, ?decompression off mode ? for an explanation of decompression off. a.3.1.2 decompression on mode in this mode, the mpc562/mpc564?s rcpu sends the two-bit aligned change of flow (cof) address to the bbc. the biu transfers the word portion of the address to the u-bus . the bbc continues to pre-fetch the data from the consequent memory addresses rega rdless of whether the rcpu requests them in order to supply data to the icdu. in the mpc562/mpc564, the data coming from the instru ction memory is not provided directly to the rcpu, but loaded into the icdu for decompression. decompressed instru ction code together with ?next instruction address? are provided to the rcpu wh enever it requires anot her instruction fetch. all addresses issued by the biu to the u-bus are transf erred in parallel to the impu. the impu compares the address of the access to its re gion programming. if any pr otection violation is detected by the impu, the current u-bus access is aborted by the biu and an instruction storage protection error exception is signaled to the rcpu. show cycle and program trace access attributes accompanying the co f rcpu access only are forwarded by the biu along with the u-bus access. additional inform ation about the ip of the compressed instruction address is provided on the u-bus data bus. refer below to section a.3.1.2.1, ?show cycles in decompression on mode ,? for more details. in this mode the mpc562/mpc564? s icdu decram is used as a deco mpressor vocabulary storage and may not be used as a general purpose ram. a.3.1.2.1 show cycles in decompression on mode in the mpc562/mpc564?s decompression on mode, the instruction address c onsists of an instruction base address and four bits of th e instruction bit pointer . in order to provide the capabil ity to show full instruction address, including instruction bit poi nter on the external bus , show cycle informati on is presented not only on the address bus, but also on some bits of the data bus: ? addr[0:29] ? show the va lue of the base address of compressed instruction (word pointer into the memory) ? data[0] ? shows in which mode the mpc562/mpc564 is operating ? 0 = decompression off mode ? 1 = decompression on mode ? data[1:4] ? represent an instruct ion bit pointer within the word. instruction show cycle bus transactions have the following characteristics (see figure 9-41 ): ? one clock cycle ? address phase only; in decompression on mode part of the compressed address is driven on data lines together with address lines. the external bus interface adds one cl ock delay between a read cycle and such show cycle. ?sts assertion only (no ta assertion) mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-16 freescale semiconductor note the bbcmcr[decomp_sc_en] bit dete rmines if the data portion (data[0:4]) of the instruct ion show cycle is driven or not, regardless of decompression mode (bbcmcr[en_comp] bit) a.3.2 vocabulary table storage operation the mpc562/mpc564 uses decram fo r decompressor vocabul ary tables (vt1 and vt2) storage in decompression on mode. the icdu utilizes decram as two separately accessed 1-kbyte ram arrays (16 bits wide) that are accessed via internal ic du buses. the vts should be loaded before the decompression process starts. in or der to allow decompression, the de cram must be disabled for the u-bus accesses after vts and decompressor class c onfiguration registers (d ccrs) are initialized. a.3.3 readi compression setting bbcmcr[decomp_sc _en] when decompression is enabled allows readi to track the compressed code (see chapter 24, ?readi module ?). bbcmcr[decomp_sc_en] should not be set if there is no intention to use comp ressed code, as it will degrade u-bus performan ce. the show cycle may be delayed by one clock by the usiu if the show cycle occurs after an external device read cycle. refer to section 24.6.5.2, ?compressed code mode guidelines .? the ictrl register must be programmed such that a s how cycle will be performe d for all changes in the program flow (isctl field = 0b01), or the ptm bit must be set and isctl must be set to a value other than 0b11. (see table a-2 .) a.3.3.1 i-bus support control register (ictrl) msb 0123 4 5 6 7 8 9 10 11 12131415 field cta ctb ctc ctd iwp0 iwp1 reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field iwp2 iwp3 siwp0 en siwp1 en siwp2 en siwp3 en diwp0 en diwp1 en diwp2 en diwp3 en ifm isct_ser 1 1 changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ictrl. reset 0000_0000_0000_0000 addr spr 158 figure a-13. i-bus support control register (ictrl) mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-17 table a-1. ictrl bit descriptions bits mnemonic description function non-compressed mode compressed mode 1 0:2 cta compare type of comparator a 0xx = not active (reset value) 100 = equal 101 = less than 110 = greater than 111 = not equal 1xx = not active 000 = equal (reset value) 001 = less than 010 = greater than 011 = not equal 3:5 ctb compare type of comparator b 6:8 ctc compare type of comparator c 9:11 ctd compare type of comparator d 12:13 iwp0 i-bus 1st watchpoint programming 0x = not active (reset value) 10 = match from comparator a 11 = match from comparators (a&b) 14:15 w1 i-bus 2nd watchpoint programming 0x = not active (reset value) 10 = match from comparator b 11 = match from comparators (a | b) 16:17 iwp2 i-bus 3rd watchpoint programming 0x = not active (reset value) 10 = match from comparator c 11 = match from comparators (c&d) 18:19 iwp3 i-bus 4th watchpoint programming 0x = not active (reset value) 10 = match from comparator d 11 = match from comparators (c | d) 0x = not active (reset value) 10 = match from comparator d 11 = match from comparators (c | d) 20 siwp0en software trap enable selection of the 1st i-bus watchpoint 0 = trap disabled (reset value) 1 = trap enabled 0 = trap disabled (reset value) 1 = trap enabled 21 siwp1en software trap enable selection of the 2nd i-bus watchpoint 22 siwp2en software trap enable selection of the 3rd i-bus watchpoint 23 siwp3en software trap enable selection of the 4th i-bus watchpoint 24 diwp0en development port trap enable selection of the 1st i-bus watchpoint (read only bit) 0 = trap disabled (reset value) 1 = trap enabled 0 = trap disabled (reset value) 1 = trap enabled 25 diwp1en development port trap enable selection of the 2nd i-bus watchpoint (read only bit) 26 diwp2en development port trap enable selection of the 3rd i-bus watchpoint (read only bit) 27 diwp3en development port trap enable selection of the 4th i-bus watchpoint (read only bit) mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-18 freescale semiconductor a.4 decompressor class configuration registers (dccr0-15) the dccr fields are programmed to achieve maximum flexibility in th e vocabulary tables placement into the two decram banks under constraint s, implied by hardware, which are: ? a bypass field must always be in the se cond field of the compressed instruction 28 ifm ignore first match, only for i-bus breakpoints 0 = do not ignore first match, used for ?go to x? (reset value) 1 = ignore first match (used for ?continue?) 0 = do not ignore first match, used for ?go to x? (reset value) 1 = ignore first match (used for ?continue?) 29:31 isct_ser rcpu serialize control and instruction fetch show cycle these bits control serialization and instruction fetch show cycles. see ta b l e a - 2 for the bit definitions. note: changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ictrl. these bits control serialization and instruction fetch show cycles. see ta bl e a - 2 for the bit definitions. note: changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ictrl. 1 mpc562/mpc564 only. table a-2. isct_ser bit descriptions serialize control (ser) instruction fetch (isctl) functions selected 0 00 rcpu is fully serialized and show cycles will be performed for all fetched instructions (reset value) 0 01 rcpu is fully serialized and show cycles will be performed for all changes in the program flow 0 10 rcpu is fully serialized and show cycles will be performed for all indirect changes in the program flow 0 11 rcpu is fully serialized and no show cycles will be performed for fetched instructions 1 00 illegal. this mode should not be selected. 1 01 rcpu is not serialized (normal mode) and show cycles will be performed for all changes in the program flow 1 10 rcpu is not serialized (normal mode) and show cycles will be performed for all indirect changes in the program flow 1 11 rcpu is not serialized (nor mal mode) and no show cycles will be performed for fetched instructions table a-1. ictrl bit descriptions (continued) bits mnemonic description function non-compressed mode compressed mode 1 mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-19 ? when fetching 32 bits of decompressed instructi on from the decram, each 16 bits will be read from different ram banks. the dccr registers should be programmed with data supplied by the code compression tool, in order to be correlated with the compressed code. , 1. the dccr0 register is hard coded for the ?bypass decompresso r class.? write accesses do not affect the dccr0 register. the dccr0 register will always return 0x0000 0000 when read. msb 0123456789101112131415 field tp1len tp2len tp1ba tp2ba reset unaffected addr dccr0 1 0x2f + a000 dccr1 0x2f + a004 dccr2 0x2f + a008 dccr3 0x2f + a00c dccr4 0x2f + a010 dccr5 0x2f + a014 dccr6 0x2f + a018 dccr7 0x2f + a01c dccr8 0x2f + a020 dccr9 0x2f + a024 dccr10 0x2f + a028 dccr11 0x2f + a02c dccr12 0x2f + a030 dccr13 0x2f + a034 dccr14 0x2f + a038 dccr15 0x2f + a03c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 field tp2ba as ds ? reset unaffected 0 unaffected 0000_0000 figure a-14. decompressor class configuration registers 1 (dccr x ) mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-20 freescale semiconductor table a-3. dccr0-dccr1 5 field descriptions bits name description 0:3 tp1len length and type of table pointer 1. this field? s value defines the length of the field that contains a pointer to the first vocabulary table allocated for the class. 0x0 empty field 0x1 reserved 0x2 tp1 length is 2 bits 0x3 tp1 length is 3 bits 0x4 tp1 length is 4 bits 0x5 tp1 length is 5 bits 0x6 tp1 length is 6 bits 0x7 tp1 length is 7 bits 0x8 tp1 length is 8 bits 0x9 tp1 length is 9 bits 0xa to 0xfreserved 4:7 tp2len length and type of table pointer 2. this field? s value defines the length of the field that contains either a pointer to the second vocabulary table allocated for the class or a bypass field. 0x0 empty field 0x1 reserved 0x2 tp2 length is 2 bits 0x3 tp2 length is 3 bits 0x4 tp2 length is 4 bits 0x5 tp2 length is 5 bits 0x6 tp2 length is 6 bits 0x7 tp2 length is 7 bits 0x8 tp2 length is 8 bits 0x9 tp2 length is 9 bits 0xa reserved 0xb tp2 field is a 0 bit compact bypass field 0xc tp2 field is a 10 bits compact bypass field 0xd tp2 field is a 15 bits compact bypass field 0xe tp2 field is a 16 bits bypass field 0xf reserved. 8:14 tp1ba base address for vocabulary table in ram bank 1. this field specifies the base page address of the class? vocabulary tabl e that resides in ram bank 1. 15:21 tp2ba base address for vocabulary table in ram bank 2. this field specifies the base page address of the class? vocabulary tabl e that resides in ram bank 2. 22 as address swap specification 0 address swap operation will not be performed for the class. 1 address swap operation will be performed for the class for further details concerning as operation refer to ta b l e a - 4 . 23 ds data swap specification 0 data swap operation will not be performed for the class. 1 data swap operation will be performed for the class. for further details concerning ds operation refer to ta bl e a - 4 . 24:31 ? reserved mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor a-21 table a-4. instruction layout encoding configuration configu ration code tp1 points to ram # tp2 points to ram # tp1ba points to tp2ba points to as ds compressed instruction layout ram # vocab. ram # vocab. single segment full compression class 1 1 and 2 ? 1 v1 2 v2 ? ? x1 1 1 x1, x2 - pointers to vocabularies twin segments full compression class 2a 121 v1 2 v2 ? 0x1 x2 twin segments full compression with swapped vocabularies (vocabulary in ram #2 for msb segment) class 2b v2 v1 1 x2 x1 left segment compression, right segment bypassed, vocabulary in ram #1 class 3a 1 bypass 1v1??0 0 x1 bp 2 2 bp - the bypassed data left segment compression, right segment bypassed, vocabulary in ram #2 class 3b 2 ? ? 2 v1 1 x1 bp 2 left segment bypassed, right segment compression, vocabulary in ram #1 class 4b 11v2??0 1 x2 bp 2 left segment bypassed, right segment compression, vocabulary in ram #2 class 4a 2 ? ? 2 v2 1 x2 bp 2 mpc562/mpc564 compression features mpc561/mpc563 reference manual, rev. 1.2 a-22 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-1 appendix b internal memory map this appendix includes the following memory maps: ? table b-1. spr (special purpose registers) ? table b-2. uc3f flash array ? table b-3. decram sram array ? table b-4. bbc (burst buffer controller module) ? table b-5. usiu (unified system interface unit) ? table b-6. cdr3 flash control registers eeprom (uc3f) ? table b-7. dptram control registers ? table b-8. dptram memory arrays ? table b-9. time processor unit 3 a and b (tpu3 a and b) ? table b-10. qadc64e a and b (que ued analog-to-dig ital converter) ? table b-11. qsmcm (queued se rial multi-channel module) ? table b-12. peripheral pin multiplexing (ppm) module ? table b-13. mios14 (modular input/output subsystem) ? table b-14. toucan a, b and c (can 2.0b controller) ? table b-15. uimb (u-bus to imb bus interface) ? table b-16. calram control registers ? table b-17. calram array ? table b-18. readi module registers internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-2 freescale semiconductor memory map tables use the notation shown below: in each table, the codes in the reset column indicate which reset affects register values. notations used in the access column notations used in the reset column s = supervisor access only ? (em dash) = untouched u = user access s = sreset t = test access h = hreset m = module reset por = power-on reset u = unchanged x = unknown r = rsti table b-1. spr (special purpose registers) address access symbol register size reset cr u cr condition state register see section 3.7.4 for bit descriptions. 32 ? fpscr u fpscr floating-point status and control register see ta b l e 3 - 5 for bit descriptions. 32 ? msr s msr machine state register see ta b l e 3 - 1 1 for bit descriptions. 32 ? spr 1 u xer integer exception register see ta b l e 3 - 1 0 for bit descriptions. 32 ? spr 8 u lr link register see section 3.7.6 for bit descriptions. 32 ? spr 9 u ctr count register see section 3.7.7 for bit descriptions. 32 ? spr 18 s dsisr dae/source instruction service register see section 3.9.2 for bit descriptions. 32 ? spr 19 s dar data address register see section 3.9.3 for bit descriptions. 32 ? spr 22 s dec decrementer register see section 3.9.5 for more information. 32 por spr 26 s srr0 machine status save/restore register 0 see section 3.9.6 for bit descriptions. 32 ? spr 27 s srr1 machine status save/restore register1 see section 3.9.7 for bit descriptions. 32 ? spr 80 s eie external interrupt enable see section 3.9.10.1 for bit descriptions. 32 ? internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-3 spr 81 s eid external interrupt disable see section 3.9.10.1 for bit descriptions. 32 ? spr 82 s nri non-recoverable interrupt register see section 3.9.10.1 for bit descriptions. 32 ? spr 144 ? spr 147 ? cmpa ? cmpd comparator a-d value register see table 23-17 for bit descriptions. 32 h spr 148 d, s ecr exception cause register see table 23-18 for bit descriptions. 32 ? spr 149 d, s der debug enable register see table 23-19 for bit descriptions. 32 ? spr 150 d, s counta breakpoint counter a value and control register see table 23-20 for bit descriptions. 32 ? spr 151 d, s countb breakpoint counter b value and control register see table 23-21 for bit descriptions. 32 ? spr 152 ? spr 153 ? cmpe ? cmpf comparator e-f value register see table 23-22 for bit descriptions. 32 ? spr 154 ? spr 155 ? cmpg ? cmph comparator g-h value register see table 23-23 for bit descriptions. 32 ? spr 156 d, s lctrl1 l-bus support control register 1 see table 23-24 for bit descriptions. 32 s spr 157 d, s lctrl2 l-bus support control register 2 see table 23-25 for bit descriptions. 32 s spr 158 d, s ictrl i-bus support control register see table 23-26 for bit descriptions. 32 s spr 159 d, s bar breakpoint address register see table 23-28 for bit descriptions. 32 ? spr 268, 269 u tbl/tbu time base (read only) register see section 6.2.2.4.2 for bit descriptions. 32 ? spr 272 ? spr 275 ssprg0 ? sprg3 general special-purpose registers 0-3 see ta b l e 3 - 1 3 for bit descriptions. 32 ? spr 284, 285 s tbl/tbu time base (write only) register see section 6.2.2.4.2 for bit descriptions. 32 ? spr 287 s pvr processor version register see ta b l e 3 - 1 4 for bit descriptions. 32 ? spr 1022 s fpecr floating-point exception cause register see ta b l e 3 - 1 6 for bit descriptions. 32 s spr 528 s mi_gra mi global region attribute register see ta b l e 4 - 8 for bit descriptions. 32 ? table b-1. spr (special purpose registers) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-4 freescale semiconductor spr 529 s eibadr external interrupt relocation table base address register see ta b l e 4 - 9 for bit descriptions. 32 ? spr 536 s l2u_gra l2u global region attribute register see table 11-10 for bit descriptions. 32 ? spr 560 s bbcmcr bbc module configuration register see ta b l e 4 - 4 for bit descriptions. 32 h spr 568 s l2u_mcr l2u module configuration register see table 11-7 for bit descriptions. 32 ? spr 630 s dpdr development port data register see section 23.4.6 for bit descriptions. 32 ? spr 638 s immr internal me mory mapping register see ta b l e 6 - 1 2 for bit descriptions. 32 h spr 784 ? 787 s mi_rbax mi region x base address register see ta b l e 4 - 5 for bit descriptions. 32 ? spr 792 ? 795 s l2u_rbax l2u region x base address register see table 11-8 for bit descriptions. 32 ? spr 816 ? 819 s mi_rax mi region x attribute register see ta b l e 4 - 6 for bit descriptions. 32 ? spr 824 ? 827 s l2u_rax l2u region x attribute register see table 11-9 for bit descriptions. 32 ? table b-2. uc3f flash array address access symbol register size reset 0x00 0000 ? 0x07 ffff u,s uc3f uc3f flash array 32 ? table b-3. decram sram array address access symbol register size reset 0x2f 8000 ? 0x2f 87ff u,s decram decram sram 32 ? table b-4. bbc (burst buffer controller module) address access symbol register size reset 0x2f a000 s (read only) 1 dccr0 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a004 s dccr1 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? table b-1. spr (special purpose registers) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-5 0x2f a008 s dccr2 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a00c s dccr3 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a010 s dccr4 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a014 s dccr5 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a018 s dccr6 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a01c s dccr7 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a020 s dccr8 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a024 s dccr9 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a028 s dccr10 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a02c s dccr11 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a030 s dccr12 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a034 s dccr13 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a038 s dccr14 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 0x2f a03c s dccr15 decompressor class configuration register see ta bl e a - 3 for bit descriptions. 32 ? 1 always reads 0x0000 0000. table b-5. usiu (unified system interface unit) address access symbol register size reset 0x2f c000 u 1 siumcr siu module configuration register see ta b l e 6 - 7 for bit descriptions. 32 h 0x2f c004 u 2 sypcr system protection control register see ta b l e 6 - 1 5 for bit descriptions. 32 h 0x2f c008 ? ? reserved ? ? 0x2f c00e u, write only swsr software service register see ta b l e 6 - 1 6 for bit descriptions. 16 s table b-4. bbc (burst buffer controller module) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-6 freescale semiconductor 0x2f c010 u sipend interrupt pending register see section 6.2.2.2.1 for bit descriptions. 32 s 0x2f c014 u simask interrupt mask register simask is a 32-bit read/write register. each bit in the register corresponds to an interrupt request bit in the sipend register. 32 s 0x2f c018 u siel interrupt edge level mask. see section 6.2.2.2.7 for bit descriptions. 32 h 0x2f c01c u, read only sivec interrupt vector. see section 6.2.2.2.8 for bit descriptions. 32 ? 0x2f c020 u tesr transfer error status register see ta b l e 6 - 1 7 for bit descriptions. 32 s 0x2f c024 u sgpiodt1 usiu general-purpose i/o data register 1 see ta b l e 6 - 2 3 for bit descriptions. 32 h 0x2f c028 u sgpiodt2 usiu general-purpose i/o data register 2 see ta b l e 6 - 2 4 for bit descriptions. 32 h 0x2f c02c u sgpiocr usiu general-purpose i/o control register see ta b l e 6 - 2 5 for bit descriptions. 32 h 0x2f c030 u emcr external master mode control register see ta b l e 6 - 1 3 for bit descriptions. 32 h 0x2f c038 u pdmcr2 pads module configuration register 2 see ta b l e 2 - 6 for bit descriptions. 32 h 0x2f c03c u pdmcr pads module configuration register see ta b l e 2 - 5 for bit descriptions. 32 h 0x2f c040 ? 0x2f c044 u sipend2 ? sipend3 interrupt pending registers 2 and 3 see section 6.2.2.2.1 for bit descriptions. 32 s 0x2f c048 ? 0x2f c04c u simask2 ? simask3 interrupt mask register and interrupt mask registers 2 and 3 see section 6.2.2.2.9 for bit descriptions. 32 s 0x2f c050 ? 0x2f c054 u sisr2 ? sisr3 sisr2 and sisr3 registers see section 6.2.2.2.9 for bit descriptions. 32 s 0x2f c0fc ? 0x2f c0ff ??reserved ?? memory controller registers 0x2f c100 u br0 base register 0. see table 10-8 for bit descriptions. 32 h 0x2f c104 u or0 option register 0. see table 10-10 for bit descriptions. 32 h 0x2f c108 u br1 base register 1. see table 10-8 for bit descriptions. 32 h table b-5. usiu (unified system interface unit) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-7 0x2f c10c u or1 option register 1. see table 10-10 for bit descriptions. 32 h 0x2f c110 u br2 base register 2. see table 10-8 for bit descriptions. 32 h 0x2f c114 u or2 option register 2. see table 10-10 for bit descriptions. 32 h 0x2f c118 u br3 base register 3. see table 10-8 for bit descriptions. 32 h 0x2f c11c u or3 option register 3. see table 10-10 for bit descriptions. 32 h 0x2f c120 ? 0x2f c13c ??reserved ?? 0x2f c140 u dmbr dual-mapping base register. see table 10-11 for bit descriptions. 32 h 0x2f c144 u dmor dual-mapping option register. see table 10-12 for bit descriptions. 32 h 0x2f c148 ? 0x2f c174 ??reserved ?? 0x2f c178 u mstat memory status. see table 10-7 for bit descriptions. 16 h system integration timers 0x2f c200 u 3 tbscr time base status and control. see ta b l e 6 - 1 8 for bit descriptions. 16 h 0x2f c204 u 3 tbref0 time base reference 0. see section 6.2.2.4.3 for bit descriptions. 32 u 0x2f c208 u 3 tbref1 time base reference 1. see section 6.2.2.4.3 for bit descriptions. 32 u 0x2f c20c ? 0x2f c21c ??reserved ?? 0x2f c220 u 4 rtcsc real-time clock status and control. see ta b l e 6 - 1 9 for bit descriptions. 16 h 0x2f c224 u 4 rtc real-time clock. see section 6.2.2.4.6 for bit descriptions. 32 u 0x2f c228 t 4 rtsec real-time alarm seconds. reserved 32 ? 0x2f c22c u 4 rtcal real-time alarm. see section 6.2.2.4.7 for bit descriptions. 32 u 0x2f c230 ? 0x2f c23c ??reserved ?? 0x2f c240 u 3 piscr pit status and control. see ta b l e 6 - 2 0 for bit descriptions. 16 h table b-5. usiu (unified system interface unit) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-8 freescale semiconductor 0x2f c244 u 3 pitc pit count. see ta b l e 6 - 2 1 for bit descriptions. 32 (half reserved) u 0x2f c248 u, read only pitr pit register. see ta b l e 6 - 2 2 for bit descriptions. 32 (half reserved) u 0x2f c24c ? 0x2f c27c ??reserved ?? clocks and reset 0x2f c280 u 2 sccr system clock control register. see ta b l e 8 - 9 for bit descriptions. 32 h 0x2f c284 u 3,5,6 plprcr pll low power and reset control register. see ta b l e 8 - 1 1 for bit descriptions. 32 h 0x2f c288 u 3 rsr reset status register. see ta b l e 7 - 3 for bit descriptions. 16 por 0x2f c28c u colir change of lock interrupt register. see ta b l e 8 - 1 2 for bit descriptions. 16 u 0x2f c290 u vsrmcr iramstby control register. see ta b l e 8 - 1 3 for bit descriptions. 16 u 0x2f c294 ? 0x2f c2fc ??reserved ?? system integration timer keys 0x2f c300 u tbscrk time base status and control key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c304 u tbref0k time base reference 0 key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c308 u tbref1k time base reference 1 key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c30c u tbk time base and decrementer key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c310 ? 0x2f c31c ??reserved ?? 0x2f c320 u rtcsck real-time clock status and control key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c324 u rtck real-time clock key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c328 u rtseck real-time alarm seconds key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c32c u rtcalk real-time alarm key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c330 ? 0x2f c33c ??reserved ?? table b-5. usiu (unified system interface unit) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-9 0x2f c340 u piscrik pit status and control key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c344 u pitck pit count key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c348 ? 0x2f c37c ??reserved ?? clocks and reset keys 0x2f c380 u sccrk system clock control key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c384 u plprcrk pll low-power and reset control register key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c388 u rsrk reset status register key. see ta b l e 8 - 8 for bit descriptions. 32 por 0x2f c38c ? 0x2f c3f8 ??reserved ?? test register 0x2f c3fc s siutst siu test register 32 s 1 entire register is locked if bit 15 (dlk) is set. 2 write once after power on reset (por). 3 must use the key register to unlock if it has been locked by a key register, see section 8.8.3.2, ?keep-alive power registers lock mechanism .? 4 locked after power on reset (por). a write of 0x55ccaa33 must perfor med to the key register to unlock. see section 8.8.3.2, ?keep-alive power registers lock mechanism .? 5 can have bits 0:11 (mf bits) write-protected by setting bit 4 (mfpdl ) in the sccr register to 1. bit 21 (csrc) and bits 22:23 (lpm) can be locked by setting bit 5 (lpml) of the sccr register to 1. 6 bit 24 (csr) is write-once after soft reset. table b-6. cdr3 flash contro l registers eeprom (uc3f) 1 1 available on the mpc563/mpc564 only, address access symbol register size reset c3f 0x2f c800 s uc3fmcr c3f eeprom configur ation register. see table 21-3 for bit descriptions. 32 por, h 0x2f c804 s uc3fmcre c3f eeprom extended configuration register. see table 21-4 for bit descriptions. 32 por, h 0x2f c808 s uc3fctl c3 f eeprom high voltage control register. see table 21-5 for bit descriptions. 32 por, h table b-5. usiu (unified system interface unit) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-10 freescale semiconductor table b-7. dptram control registers address access symbol register size reset dptram control 0x30 0000 u, s 1 1 access to the dptram array through the imb3 bus is disa bled once bit 5 (emu) of either tpumcr_a or tpumcr_b is set. dptmcr dptram module configuration register. see table 20-2 for bit descriptions. 16 s 0x30 0002 s dpttcr test configuration register. 16 s 0x30 0004 s rambar ram array base address register. see table 20-3 for bit descriptions. 16 s 0x30 0006 s misrh multiple input signature register high. 16 s 0x30 0008 s misrl multiple input signature register low. 16 s 0x30 000a s miscnt misc counter register. 16 s table b-8. dptram memory arrays address access symbol register size reset 0x30 2000 ? 0x30 37ff u, s 1 1 access to the dptram array through the imb3 bus is disa bled once bit 5 (emu) of either tpumcr_a or tpumcr_b is set. dptram dptram memory array 16 ? table b-9. time processor unit 3 a and b (tpu3 a and b) address access symbol register size reset tpu3_a (note: bit descriptions apply to tpu3_b as well) 0x30 4000 s 1 tpumcr_a tpu3_a module configuration register. see table 19-7 for bit descriptions. 16 only s, m 0x30 4002 t tcr_a tpu3_a test configuration register. 16 s, m 0x30 4004 t dscr_a tpu3_a development support control register. see table 19-8 for bit descriptions. 16 2 s, m 0x30 4006 t dssr_a tpu3_a development support status register. see table 19-9 for bit descriptions. 16 2 s, m 0x30 4008 s ticr_a tpu3_a interrupt configuration register. see table 19-10 for bit descriptions. 16 2 s, m 0x30 400a s cier_a tpu3_a channel interrupt enable register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-11 0x30 400e s cfsr1_a tpu3_a channel function selection register 1. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-12 freescale semiconductor 0x30 4150 ? 0x30 415f s/u 3 ? tpu3_a channel 5 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 4160 ? 0x30 416f s/u 3 ? tpu3_a channel 6 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 4170 ? 0x30 417f s/u 3 ? tpu3_a channel 7 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 4180 ? 0x30 418f s/u 3 ? tpu3_a channel 8 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 4190 ? 0x30 419f s/u 3 ? tpu3_a channel 9 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41a0 ? 0x30 41af s/u 3 ? tpu3_a channel 10 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41b0 ? 0x30 41bf s/u 3 ? tpu3_a channel 11 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41c0 ? 0x30 41cf s/u 3 ? tpu3_a channel 11 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41d0 ? 0x30 41df s/u 3 ? tpu3_a channel 11 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41e0 ? 0x30 41ef s/u 3 ? tpu3_a channel 14 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? 0x30 41f0 ? 0x30 41ff s/u 3 ? tpu3_a channel 15 parameter registers. see section 19.4.15 for more information. 16, 32 2 ? tpu3_b 0x30 4400 1 s 1 tpumcr_b tpu3_b module configuration register 16 only s, m 0x30 4402 t tcr_b tpu3_b test configuration register 16 s, m 0x30 4404 t dscr_b tpu3_b development support control register 16 2 s, m 0x30 4406 t dssr_b tpu3_b development support status register 16 2 s, m 0x30 4408 s ticr_b tpu3_b interrupt configuration register 16 2 s, m 0x30 440a s cier_b tpu3_b channel interrupt enable register 16 2 s, m 0x30 440c s cfsr0_b tpu3_b channel function selection register 0 16 2 s, m 0x30 440e s cfsr1_b tpu3_b channel function selection register 1 16 2 s, m 0x30 4410 s cfsr2_b tpu3_b channel function selection register 2 16 2 s, m 0x30 4412 s cfsr3_b tpu3_b channel function selection register 3 16 2 s, m 0x30 4414 s/u 3 hsqr0_b tpu3_b host sequence register 0 16 2 s, m 0x30 4416 s/u 3 hsqr1_b tpu3_b host sequence register 1 16 2 s, m 0x30 4418 s/u 3 hsrr0_b tpu3_b host service request register 0 16 2 s, m 0x30 441a s/u 3 hsrr1_b tpu3_b host service request register 1 16 2 s, m table b-9. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-13 0x30 441c s cpr0_b tpu3_b channel priority register 0 16 2 s, m 0x30 441e s cpr1_b tpu3_b channel priority register 1 16 2 s, m 0x30 4420 s cisr_b tpu3_b channel interrupt status register 16 s, m 0x30 4422 t lr_b tpu3_b link register 16 2 s, m 0x30 4424 t sglr_b tpu3_b service grant latch register 16 2 s, m 0x30 4426 t dcnr_b tpu3_b decoded channel number register 16 2 s, m 0x30 4428 s 4 tpumcr2_b tpu3_b module configuration register 2 16 2 s, m 0x30 442a s tpumcr3_b tpu3_b module configuration register 3 16, 32 2 s, m 0x30 442c t isdr_b tpu3_b internal scan data register 16, 32 2 ? 0x30 442e t iscr_b tpu3_b internal scan control register 16, 32 2 ? 0x30 4500 ? 0x30 450f s/u 3 ? tpu3_b channel 0 parameter registers 16, 32 2 ? 0x30 4510 ? 0x30 451f s/u 3 ? tpu3_b channel 1 parameter registers 16, 32 2 ? 0x30 4520 ? 0x30 452f s/u 3 ? tpu3_b channel 2 parameter registers 16, 32 2 ? 0x30 4530 ? 0x30 453f s/u 3 ? tpu3_b channel 3 parameter registers 16, 32 2 ? 0x30 4540 ? 0x30 454f s/u 3 ? tpu3_b channel 4 parameter registers 16, 32 2 ? 0x30 4550 ? 0x30 455f s/u 3 ? tpu3_b channel 5 parameter registers 16, 32 2 ? 0x30 4560 ? 0x30 456f s/u 3 ? tpu3_b channel 6 parameter registers 16, 32 2 ? 0x30 4570 ? 0x30 457f s/u 3 ? tpu3_b channel 7 parameter registers 16, 32 2 ? 0x30 4580 ? 0x30 458f s/u 3 ? tpu3_b channel 8 parameter registers 16, 32 2 ? 0x30 4590 ? 0x30 459f s/u 3 ? tpu3_b channel 9 parameter registers 16, 32 2 ? 0x30 45a0 ? 0x30 45af s/u 3 ? tpu3_b channel 10 parameter registers 16, 32 2 ? 0x30 45b0 ? 0x30 45bf s/u 3 ? tpu3_b channel 11 parameter registers 16, 32 2 ? 0x30 45c0 ? 0x30 45cf s/u 3 ? tpu3_b channel 11 parameter registers 16, 32 2 ? 0x30 45d0 ? 0x30 45df s/u 3 ? tpu3_b channel 11 parameter registers 16, 32 2 ? table b-9. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-14 freescale semiconductor 0x30 45e0 ? 0x30 45ef s/u 3 ? tpu3_b channel 14 parameter registers 16, 32 2 ? 0x30 45f0 ? 0x30 45ff s/u 3 ? tpu3_b channel 15 parameter registers 16 2 ? 1 bit 10 (tpu3) and bit 11 (t2csl) are write-once. bits 1:2 (tcr1p) and bits 3:4 (tcr2p) are write-once if pwod is not set in the tpumcr3 register. this register cannot be accessed with a 32-bit read. it can only be accessed with an 8- or 16-bit read. 2 some tpu registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed. 3 s/u = supervisor accessible only if supv = 1 or unrestricted if supv = 0. unrestricted regi sters allow both user and supervisor access. the supv bit is in the tpumcr register. 4 tpu code development (debug) register 5 bits 9:10 (etbank), 14 (t2cf), and 15 (dtpu) are write-once. table b-10. qadc64e a and b (queued analog-to-digital converter) address access symbol register size reset qadc_a (note: bit descriptions apply to qadc_b as well) 0x30 4800 s qadc64mcr_a qadc64 module configuration register. see table 13-5 and ta b l e 1 4 - 5 for bit descriptions. 16 s 0x30 4802 s qadc64tst qadc64 test register. 16 s 0x30 4804 s qadc64int_a interrupt register. see section 13.2.2 and section 14.3.2 for bit descriptions. 16 s 0x30 4806 s/u portqa_a/ portqb_a port a and port b data. see ta bl e 1 - 9 and ta bl e 1 4 - 8 for bit descriptions. 16 u 0x30 4808 s/u ddrqa_a/ ddrqb_a port a data and port b direction register. see section 13.3.4 and section 14.3.4 for more information. 16 s 0x30 480a s/u qacr0_a qadc64 control register 0. see table 13-9 and ta b l e 1 4 - 9 for bit descriptions. 16 s 0x30 480c s/u 1 qacr1_a qadc64 control register 1. see table 13-10 and table 14-11 for bit descriptions. 16 s 0x30 480e s/u 1 qacr2_a qadc64 control register 2. see table 13-12 and table 14-13 for bit descriptions. 16 s 0x30 4810 s/u qasr0_a qadc64 status register 0. see table 13-14 and table 14-15 for bit descriptions. 16 s table b-9. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-15 0x30 4812 s/u qasr1_a qadc64 status register 1. see table 13-17 and table 14-18 for bit descriptions. 16 s 0x30 4814 ? 0x30 49fe ??reserved ?? 0x30 4a00 ? 0x30 4a7e s/u ccw_a conversion command word table. see table 13-18 and table 14-19 for bit descriptions. 16 u 0x30 4a80 ? 0x30 4afe s/u rjurr_a result word table right-justified, unsigned result register. see section 13.3.10 and section 14.3.10 for bit descriptions. 16 x 0x30 4b00 ? 0x30 4b7e s/u ljsrr_a result word table left-justified, signed result register. see section 13.3.10 and section 14.3.10 for bit descriptions. 16 x 0x30 4b80 ? 0x30 4bfe s/u ljurr_a result word table left-justified, unsigned result register. see section 13.3.10 and section 14.3.10 for bit descriptions. 16 x qadc_b 0x30 4c00 s qadc64mcr_b qadc64 module configuration register 16 s 0x30 4c02 t qadc64test_ b qadc64 test register 16 ? 0x30 4c04 s qadc64int_b interrupt register 16 s 0x30 4c06 s/u portqa_b/ portqb_b port a and port b data 16 u 0x30 4c08 s/u ddrqa_b/ ddrqb_b port a data and port b direction register 16 s 0x30 4c0a s/u qacr0_b qadc64 control register 0 16 s 0x30 4c0c s/u 1 qacr1_b qadc64 control register 1 16 s 0x30 4c0e s/u 1 qacr2_b qadc64 control register 2 16 s 0x30 4c10 s/u qasr0_b qadc64 status register 0 16 s 0x30 4c12 s/u qasr1_b qadc64 status register 1 16 s 0x30 4c14 ? 0x30 4dfe ??reserved ?? 0x30 4e00 ? 0x30 4e7e s/u ccw_b conversion command word table 16 u 0x30 4e80 ? 0x30 4efe s/u rjurr_b result word table. right-justified, unsigned result register. 16 x table b-10. qadc64e a and b (queued analog-to-digital converter) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-16 freescale semiconductor 0x30 4f00 ? 0x30 4f7e s/u ljsrr_b result word table. left-justified, signed result register. 16 x 0x30 4f80 ? 0x30 4ffe s/u ljurr_b result word table. left-justified, unsigned result register. 16 x 1 bit 3 (ssex) is readable in test mode only. table b-11. qsmcm (queued se rial multi-channel module) address access symbol register size reset qsmcm 0x30 5000 s qsmcmmcr qsmcm module configuration register. see table 15-4 for bit descriptions. 16 s 0x30 5002 t qtest qsmcm test register 16 s 0x30 5004 s qdsci_il dual sci interrupt level. see table 15-5 for bit descriptions. 16 s 0x30 5006 s qspi_il queued spi interrupt level. see table 15-6 for bit descriptions. 16 s 0x30 5008 s/u scc1r0 sci1 control register 1. see table 15-24 for bit descriptions. 16 s 0x30 500a s/u scc1r1 sci1 control register 1. see table 15-25 for bit descriptions. 16 s 0x30 500c s/u sc1sr sci1 status register. see table 15-26 for bit descriptions. 16 s 0x30 500e s/u sc1dr sci1 data register. see table 15-27 for bit descriptions. 16 s 0x30 5010 ? 0x30 5012 ??reserved ?? 0x30 5014 s/u portqs qsmcm port qs data register. see section 15.5.2 for bit descriptions. 16 s 0x30 5016 s/u pqspar/ ddrqst qsmcm port qs pin assignment register/ qsmcm port qs data direction register. see section 15.5.2 for bit descriptions. 16 s 0x30 5018 s/u spcr0 qspi control register 0. see table 15-13 for bit descriptions. 16 s 0x30 501a s/u spcr1 qspi control register 1. see table 15-15 for bit descriptions. 16 s 0x30 501c s/u spcr2 qspi control register 2. see table 15-16 for bit descriptions. 16 s 0x30 501e s/u spcr3 qspi control register 3. see table 15-17 for bit descriptions. 8s table b-10. qadc64e a and b (queued analog-to-digital converter) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-17 0x30 501f s/u spsr qspi status register 3. see table 15-18 for bit descriptions. 8s 0x30 5020 s/u scc2r0 sci2 control register 0. see table 15-24 for bit descriptions. 16 s 0x30 5022 s/u scc2r1 sci2 control register 1. see table 15-25 for bit descriptions. 16 s 0x30 5024 s/u sc2sr sci2 status register. see table 15-26 for bit descriptions. 16 s 0x30 5026 s/u sc2dr sci2 data register. see table 15-27 for bit descriptions. 16 s 0x30 5028 s/u 1 qsci1cr qsci1 control register. see table 15-32 for bit descriptions. 16 s 0x30 502a s/u 2 qsci1sr qsci1 status register. see table 15-33 for bit descriptions. 16 s 0x30 502c ? 0x30 504a s/u sctq transmit queue locations 16 s 0x30 504c ? 0x30 506a s/u scrq receive queue locations 16 s 0x30 506c ? 0x30 513f ??reserved ?? 0x30 5140 ? 0x30 517f s/u recram receive data ram 16 s 0x30 5180 ? 0x30 51bf s/u tran.ram transmit data ram 16 s 0x30 51c0 ? 0x30 51df s/u comd.ram command ram 16 s 1 bits 0?3 writeable only in test mode, otherwise read only. 2 bits 3?11 writeable only in test mode, otherwise read only. table b-12. peripheral pin multiplexing (ppm) module address access symbol register size reset 0x30 5c00 s/u ppmmcr ppm module configuration register see ta bl e 1 8 - 2 for bit descriptions. 16 s 0x30 5c04 s/u ppmpcr ppm contol register see ta bl e 1 8 - 3 for bit descriptions. 16 s 0x30 5c06 s/u tx_config_1 transmit configuration register 1 see ta bl e 1 8 - 6 for channel settings. 16 s 0x30 5c08 s/u tx_config_2 transmit configuration register 2 see ta bl e 1 8 - 6 for channel settings. 16 s table b-11. qsmcm (queued serial multi-channel module) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-18 freescale semiconductor 0x30 5c0e s/u rx_config_1 receive configuration register 1 see ta bl e 1 8 - 6 for channel settings. 16 s 0x30 5c10 s/u rx_config_2 receive configuration register 2 see ta bl e 1 8 - 6 for channel settings. 16 s 0x30 5c16 s/u rx_data receive data register see section 18.4.5 for bit descriptions. 16 s 0x30 5c1a s/u rx_shifter receive shift register see section 18.4.6 for bit descriptions. 16 s 0x30 5c1e s/u tx_data transmit data register see section 18.4.7 for bit descriptions. 16 s 0x30 5c22 s/u gpdo general-purpose data out see section 18.4.8 for bit descriptions. 16 s 0x30 5c24 s/u gpdi general-purpose data in see section 18.4.9 for bit descriptions. 16 s 0x30 5c26 s/u short_reg short register see ta bl e 1 8 - 7 for bit descriptions. 16 s 0x30 5c28 s/u short_ch_reg short channels register see table 18-10 for bit descriptions. 16 s 0x30 5c2a s/u scale_tclk_reg scale transmit clock register see table 18-13 for bit descriptions. 16 s table b-13. mios14 (modular input/output subsystem) address access symbol register size reset mpwmsm0 (mios pulse width modulation submodule 0) 0x30 6000 s/u mpwmperr mpwmsm0 period register. see table 17-26 for bit descriptions. 16 s 1 0x30 6002 s/u mpwmpulr mpwmsm0 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 6004 s/u mpwmcntr mpwmsm0 counter register. see table 17-28 for bit descriptions. 16 s 0x30 6006 s/u mpwmscr mpwmsm0 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm1 (mios pulse width modulation submodule 1) 0x30 6008 s/u mpwmperr mpwmsm1 period register. see table 17-26 for bit descriptions. 16 s 0x30 600a s/u mpwmpulr mpwmsm1 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 600c s/u mpwmcntr mpwmsm1 counter register. see table 17-28 for bit descriptions. 16 s table b-12. peripheral pin multiplexing (ppm) module (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-19 0x30 600e s/u mpwmscr mpwmsm1 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm2 (mios pulse width modulation submodule 2) 0x30 6010 s/u mpwmperr mpwmsm2 period register. see table 17-26 for bit descriptions. 16 s 0x30 6012 s/u mpwmpulr mpwmsm2 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 6014 s/u mpwmcntr mpwmsm2 counter register. see table 17-28 for bit descriptions. 16 s 0x30 6016 s/u mpwmscr mpwmsm2 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm3 (mios pulse width modulation submodule 3) 0x30 6018 s/u mpwmperr mpwmsm3 period register. see table 17-26 for bit descriptions. 16 s 0x30 601a s/u mpwmpulr mpwmsm3 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 601c s/u mpwmcntr mpwmsm3 counter register. see table 17-28 for bit descriptions. 16 s 0x30 601e s/u mpwmscr mpwmsm3 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm4 (mios pulse width modulation submodule 4) 0x30 6020 s/u mpwmperr mpwmsm4 period register. see table 17-26 for bit descriptions. 16 s 0x30 6022 s/u mpwmpulr mpwmsm4 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 6024 s/u mpwmcntr mpwmsm4 counter register. see table 17-28 for bit descriptions. 16 s 0x30 6026 s/u mpwmscr mpwmsm4 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm5 (mios pulse width modulation submodule 5) 0x30 6028 s/u mpwmperr mpwmsm5 period register. see table 17-26 for bit descriptions. 16 s 0x30 602a s/u mpwmpulr mpwmsm5 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 602c s/u mpwmcntr mpwmsm5 counter register. see table 17-28 for bit descriptions. 16 s 0x30 602e s/u mpwmscr mpwmsm5 status/control register. see table 17-29 for bit descriptions. 16 s table b-13. mios14 (modular input/output subsystem) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-20 freescale semiconductor mmcsm6 (mios modulus counter submodule 6) 0x30 6030 s/u mmcsmcnt mmcsm6 up-counter register. see table 17-10 for bit descriptions. 16 x 0x30 6032 s/u mmcsmml mmcsm6 modulus latch register. see table 17-11 for bit descriptions. 16 s 0x30 6034 s/u mmcsmscrd mmcsm6 status/control register. see table 17-12 for bit descriptions. 16 s 0x30 6036 s/u mmcsmscr mmcsm6 status/control register. see table 17-12 for bit descriptions. 16 s mmcsm7 (mios modulus counter submodule 7) 0x30 6038 s/u mmcsmcnt mmcsm7 up-counter register. see table 17-10 for bit descriptions. 16 x 0x30 603a s/u mmcsmml mmcsm7 modulus latch register. see table 17-11 for bit descriptions. 16 s 0x30 603e s/u mmcsmscr mmcsm7 status/control register. see table 17-12 for bit descriptions. 16 s mmcsm8 (mios modulus counter submodule 8) 0x30 6040 s/u mmcsmcnt mmcsm8 up-counter register. see table 17-10 for bit descriptions. 16 x 0x30 6042 s/u mmcsmml mmcsm8 modulus latch register. see table 17-11 for bit descriptions. 16 s 0x30 6046 s/u mmcsmscr mmcsm8 status/control register. see table 17-12 for bit descriptions. 16 s mdasm11 (mios double action submodule 11) 0x30 6058 s/u mdasmar mdasm11 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 605a s/u mdasmbr mdasm11 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 605a s/u mdasmscr mdasm11 status/control register. see table 17-21 for bit descriptions. 16 s mdasm12 (mios double action submodule 12) 0x30 6060 s/u mdasmar mdasm12 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 6062 s/u mdasmbr mdasm12 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 6064 s/u mdasmscrd mdasm12 dataa register. see table 17-19 for bit descriptions. 16 s table b-13. mios14 (modular input/output subsystem) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-21 0x30 6066 s/u mdasmscr mdasm status/control register. see table 17-21 for bit descriptions. 16 s mdasm13 (mios double action submodule 13) 0x30 6068 s/u mdasmar mdasm13 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 606a s/u mdasmbr mdasm13 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 606e s/u mdasmscr mdasm13 status/control register. see table 17-21 for bit descriptions. 16 s mdasm14 (mios double action submodule 14) 0x30 6070 s/u mdasmar mdasm14 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 6072 s/u mdasmbr mdasm14 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 6076 s/u mdasmscr mdasm14 status/control register. see table 17-21 for bit descriptions. 16 s mdasm (mios double action submodule 15) 0x30 6078 s/u mdasmar mdasm15 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 607a s/u mdasmbr mdasm15 dataa register. see table 17-19 for bit descriptions. 16 s 0x30 607e s/u mdasmscr mdasm15 status/control register. see table 17-21 for bit descriptions. 16 s mpwmsm16 (mios pulse width modulation submodule 16) 0x30 6080 s/u mpwmperr mpwmsm16 period register. see table 17-26 for bit descriptions. 16 s 0x30 6082 s/u mpwmpulr mpwmsm16 pulse width register. see table 17-27 for bit descriptions. 16 s 0x30 6084 s/u mpwmcntr mpw msm16 counter register. see table 17-28 for bit descriptions. 16 s 0x30 6086 s/u mpwmscr mpwmsm 16 status/control register. see table 17-29 for bit descriptions. 16 s mpwmsm17 (mios pulse width modulation submodule 17) 0x30 6088 s/u mpwmperr mpwmsm17 period register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-22 freescale semiconductor 0x30 608c s/u mpwmcntr mpw msm17 counter register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-23 0x30 60a6 s/u mpwmscr mpwmsm20 status/control register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-24 freescale semiconductor 0x30 60c2 s/u mmcsmml mmcsm24 modulus latch register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-25 0x30 6f2 s/u mdasmbr mdasm30 dataa register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-26 freescale semiconductor 0x30 6c04 s/u mios14er0 mios14 interrupt enable register. see internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-27 0x30 708a s/u timer_a toucan_a free-running timer register. see table 16-19 for bit descriptions. 16 s 0x30 708c ? 0x30 708e ??reserved ?? 0x30 7090 s/u rxgmskhi_a toucan_a receive global mask high. see table 16-20 for bit descriptions. 32 s 0x30 7092 s/u rxgmsklo_a toucan_a receive global mask low. see table 16-20 for bit descriptions. 32 s 0x30 7094 s/u rx14mskhi_a toucan_a receive buffer 14 mask high. see table 16-21 for bit descriptions. 32 s 0x30 7096 s/u rx14msklo_a toucan_a receive buffer 14 mask low. see table 16-21 for bit descriptions. 32 s 0x30 7098 s/u rx15mskhi_a toucan_a receive buffer 15 mask high. see table 16-22 for bit descriptions. 32 s 0x30 709a s/u rx15msklo_a toucan_a receive buffer 15 mask low. see table 16-22 for bit descriptions. 32 s 0x30 709c ? 0x30 709e ??reserved ?? 0x30 70a0 s/u estat_a toucan_a error and status register. see table 16-23 for bit descriptions. 16 s 0x30 70a2 s/u imask_a toucan_a interrupt masks. see table 16-26 for bit descriptions. 16 s 0x30 70a4 s/u iflag_a toucan_a interrupt flags. see table 16-27 for bit descriptions. 16 s 0x30 70a6 s/u rxectr_a/ txectr_a toucan_a receive error counter/ toucan_a transmit error counter. see table 16-28 for bit descriptions. 16 s 0x30 7100 ? 0x30 710f s/u mbuff0_a 1 toucan_a message buffer 0 2 ?u 0x30 7110 ? 0x30 711f s/u mbuff1_a 1 toucan_a message buffer 1 2 ?u 0x30 7120 ? 0x30 712f s/u mbuff2_a 1 toucan_a message buffer 2 2 ?u 0x30 7130 ? 0x30 713f s/u mbuff3_a 1 toucan_a message buffer 3 2 ?u 0x30 7140 ? 0x30 714f s/u mbuff4_a 1 toucan_a message buffer 4 2 ?u 0x30 7150 ? 0x30 715f s/u mbuff5_a 1 toucan_a message buffer 5 2 ?u 0x30 7160 ? 0x30 716f s/u mbuff6_a 1 toucan_a message buffer 6 2 ?u table b-14. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-28 freescale semiconductor 0x307170 ? 0x30717f s/u mbuff7_a 1 toucan_a message buffer 7 2 ?u 0x30 7180 ? 0x30 718f s/u mbuff8_a 1 toucan_a message buffer 8 2 ?u 0x30 7190 ? 0x30 719f s/u mbuff9_a 1 toucan_a message buffer 9 2 ?u 0x30 71a0 ? 0x30 71af s/u mbuff10_a 1 toucan_a message buffer 10 2 ?u 0x30 71b0 ? 0x30 71bf s/u mbuff11_a 1 toucan_a message buffer 11 2 ?u 0x30 71c0 ? 0x30 71cf s/u mbuff12_a 1 toucan_a message buffer 12 2 ?u 0x30 71d0 ? 0x30 71df s/u mbuff13_a 1 toucan_a message buffer 13 2 ?u 0x30 71e0 ? 0x30 71ef s/u mbuff14_a 1 toucan_a message buffer 14 2 ?u 0x30 71f0 ? 0x30 71ff s/u mbuff15_a 1 toucan_a message buffer 15 2 ?u toucan_b 0x30 7480 s canmcr_b toucan_b module configuration register 16 s 0x30 7482 t cantcr_b toucan_b test register 16 s 0x30 7484 s canicr_b toucan_b interrupt configuration register 16 s 0x30 7486 s/u canctrl0_b/ canctrl1_b toucan_b control register 0/ toucan_b control register 1 16 s 0x30 7488 s/u presdiv_b/ ctrl2_b toucan_b control and prescaler divider register/toucan_b control register 2 16 s 0x30 748a s/u timer_b toucan_b free-running timer register s 0x30 748c ? 0x30 748e ??reserved ?? 0x30 7490 s/u rxgmskhi_b toucan_b receive global mask high 32 s 0x30 7492 s/u rxgmsklo_b toucan_b receive global mask low 32 s 0x30 7494 s/u rx14mskhi_b toucan_b receive buffer 14 mask high 32 s 0x30 7496 s/u rx14msklo_b toucan_b receive buffer 14 mask low 3 s 0x30 7498 s/u rx15mskhi_b toucan_b receive buffer 15 mask high 32 s 0x30 749a s/u rx15msklo_b toucan_b receive buffer 15 mask low 32 s 0x30 749c ? 0x30 749e ??reserved ?? 0x30 74a0 s/u estat_b toucan_b error and status register 16 s table b-14. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-29 0x30 74a2 s/u imask_b toucan_b interrupt masks 16 s 0x30 74a4 s/u iflag_b toucan_b interrupt flags 16 s 0x30 74a6 s/u rxectr_b/ txectr_b toucan_b receive error counter/ toucan_b transmit error counter 16 s 0x30 7500 ? 0x30 750f s/u mbuff0_b 1 toucan_b message buffer 0. ? u 0x30 7510 ? 0x30 751f s/u mbuff1_b 1 toucan_b message buffer 1. ? u 0x30 7520 ? 0x30 752f s/u mbuff2_b 1 toucan_b message buffer 2. ? u 0x30 7530 ? 0x30 753f s/u mbuff3_b 1 toucan_b message buffer 3. ? u 0x30 7540 ? 0x30 754f s/u mbuff4_b 1 toucan_b message buffer 4. ? u 0x30 7550 ? 0x30 755f s/u mbuff5_b 1 toucan_b message buffer 5. ? u 0x30 7560 ? 0x30 756f s/u mbuff6_b 1 toucan_b message buffer 6. ? u 0x30 7570 ? 0x30 757f s/u mbuff7_b 1 toucan_b message buffer 7. ? u 0x30 7580 ? 0x30 758f s/u mbuff8_b 1 toucan_b message buffer 8. ? u 0x30 7590 ? 0x30 759f s/u mbuff9_b 1 toucan_b message buffer 9. ? u 0x30 75a0 ? 0x30 75af s/u mbuff10_b 1 toucan_b message buffer 10. ? u 0x30 75b0 ? 0x30 75bf s/u mbuff11_b 1 toucan_b message buffer 11. ? u 0x30 75c0 ? 0x30 75cf s/u mbuff12_b 1 toucan_b message buffer 12. ? u 0x30 75d0 ? 0x30 75df s/u mbuff13_b 1 toucan_b message buffer 13. ? u 0x30 75e0 ? 0x30 75ef s/u mbuff14_b 1 toucan_b message buffer 14. ? u 0x30 75f0 ? 0x30 75ff s/u mbuff15_b 1 toucan_b message buffer 15. ? u toucan_c 0x30 7880 s canmcr_c toucan_c mo dule configuration register 16 s 0x30 7882 t cantcr_c toucan_c test register 16 s table b-14. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-30 freescale semiconductor 0x30 7884 s canicr_c toucan_c inte rrupt configuration register 16 s 0x30 7886 s/u canctrl0_c/ canctrl1_c toucan_c control register 0/ toucan_c control register 1 16 s 0x30 7888 s/u presdiv_c/ ctrl2_c toucan_c control and prescaler divider register/ toucan_c control register 2 16 s 0x30 788a s/u timer_c toucan_c free-running timer register s 0x30 788c ? 0x30 788e ??reserved ?? 0x30 7890 s/u rxgmskhi_c toucan_c receive global mask high 32 s 0x30 7892 s/u rxgmsklo_c toucan_c receive global mask low 32 s 0x30 7894 s/u rx14mskhi_c toucan_c receive buffer 14 mask high 32 s 0x30 7896 s/u rx14msklo_c toucan_c receive buffer 14 mask low 32 s 0x30 7898 s/u rx15mskhi_c toucan_c receive buffer 15 mask high 32 s 0x30 789a s/u rx15msklo_c toucan_c receive buffer 15 mask low 32 s 0x30 789c ? 0x30 789e ??reserved ?? 0x30 78a0 s/u estat_c toucan_c error and status register 16 s 0x30 78a2 s/u imask_c toucan _c interrupt masks 16 s 0x30 78a4 s/u iflag_c toucan_c interrupt flags 16 s 0x30 78a6 s/u rxectr_c/ txectr_c toucan_c receive error counter/ toucan_c transmit error counter 16 s 0x30 7900 ? 0x30 790f s/u mbuff0_c 1 toucan_c message buffer 0. ? u 0x30 7910 ? 0x30 791f s/u mbuff1_c 1 toucan_b message buffer 1. ? u 0x30 7920 ? 0x30 792f s/u mbuff2_c 1 toucan_c message buffer 2. ? u 0x30 7930 ? 0x30 793f s/u mbuff3_c 1 toucan_c message buffer 3. ? u 0x30 7940 ? 0x30 794f s/u mbuff4_c 1 toucan_c message buffer 4. ? u 0x30 7950 ? 0x30 795f s/u mbuff5_c 1 toucan_c message buffer 5. ? u 0x30 7960 ? 0x30 796f s/u mbuff6_c 1 toucan_c message buffer 6. ? u 0x30 7970 ? 0x30 797f s/u mbuff7_c 1 toucan_c message buffer 7. ? u table b-14. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-31 0x30 7980 ? 0x30 798f s/u mbuff8_c 1 toucan_c message buffer 8. ? u 0x30 7990 ? 0x30 799f s/u mbuff9_c 1 toucan_c message buffer 9. ? u 0x30 79a0 ? 0x30 79af s/u mbuff10_c 1 toucan_c message buffer 10. ? u 0x30 79b0 ? 0x30 79bf s/u mbuff11_c 1 toucan_c message buffer 11. ? u 0x30 79c0 ? 0x30 79cf s/u mbuff12_c 1 toucan_c message buffer 12. ? u 0x30 79d0 ? 0x30 79df s/u mbuff13_c 1 toucan_c message buffer 13. ? u 0x30 79e0 ? 0x30 79ef s/u mbuff14_c 1 toucan_c message buffer 14. ? u 0x30 79f0 ? 0x30 79ff s/u mbuff15_c 1 toucan_c message buffer 15. ? u 1 the last word of each of the mbuff arrays (address 0x. ...e) is reserved and may cause a rcpu exception if read. 2 see ta b l e 1 6 - 3 and ta bl e 1 6 - 4 for message buffer definitions. table b-15. uimb (u-bus to imb bus interface) address access symbol register size reset 0x30 7f80 s 1 1 s = supervisor mode only, t = test mode only umcr uimb module configuration register. see table 12-6 for bit descriptions. 32 h 0x30 7f84 ? 0x30 7f8c ? ? reserved 32 h 0x30 7f90 s/t utstcreg uimb test control register. reserved 32 h 0x30 7f94 ? 0x30 7f9c ? ? reserved 32 h 0x30 7fa0 s uipend pending interrupt request register. see section 12.5.3 and table 12-7 for bit descriptions. 32 h table b-16. calram control registers address access symbol register size reset calram 0x38 0000 s crammcr calrammodule configuration register. see ta bl e 2 2 - 3 for bit descriptions. 32 s table b-14. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-32 freescale semiconductor 0x38 0004 s cramtst calram test register. 32 s 0x38 0008 s cram_rba0 calram region base address register 1 32 s 0x38 000c s cram_rba1 calram region base address register 1 32 s 0x38 0010 s cram_rba2 calram region base address register 1 32 s 0x38 0014 s cram_rba3 calram region base address register 1 32 s 0x38 0018 s cram_rba4 calram region base address register 1 32 s 0x38 001c s cram_rba5 calram region base address register 1 32 s 0x38 0020 s cram_rba6 calram region base address register 1 32 s 0x38 0024 s cram_rba7 calram region base address register 1 32 s 0x38 0028 s cram_olvcr calram overlay configuration register.see ta bl e 2 2 - 7 for bit descriptions. 32 s 0x38 002c s 2 readi_otr readi ownership trace register. see section 24.6.1.1, ?user-mapped register (otr) ,? for more information. 32 h 1 see section 22.5.2, ?calram region base address registers (cram_rbax) ,? for more information. 2 this register is write only. table b-17. calram array address access symbol register size reset calram 0x3f 8000 ? 0x3f ffff u,s cram calram array 32 kbytes ? table b-18. readi module registers address access symbol register size reset 0x08 read only readi_did device id register see table 24-6 for bit descriptions. 32 r 0x0a read only readi_dc development control register see table 24-7 for bit descriptions. 8r 0x0b read/write readi_mc mode control register 1 see table 24-9 for bit descriptions. 8r 0x0d read only readi_uba user base address register see table 24-10 for bit descriptions. 32 r 0x0f read/write readi_rwa read/write access register see table 24-11 for bit descriptions. 80 r 0x10 read/write readi_udi upload/download information register see table 24-12 for bit descriptions. 34 r table b-16. calram control registers (continued) address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor b-33 0x14 read/write readi_dta1 data trace attributes register 1 see table 24-15 for bit descriptions. 48 r 0x15 read/write readi_dta2 data trace attributes register 2 see table 24-15 for bit descriptions. 48 r 1 not available on all revisions. refer to the device errata for the version of silicon in use. table b-18. readi module registers address access symbol register size reset internal memory map mpc561/mpc563 reference manual, rev. 1.2 b-34 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor c-1 appendix c clock and board guidelines the mpc561/mpc563 built-in pll, oscillator, and othe r analog and sensitive circ uits require that the board design follow special layout gui delines to ensure proper operation of the chip clocks. this appendix describes how the clock supplies and external co mponents should be connect ed in a system. these guidelines must be fulfilled to reduce switching noise which is generated on internal and external buses during operation. any noise injected into the sensit ive clock and pll logic reduces clock performance. the usiu maintains a pll loss-of-lock warning indi cation that can be used to determine the clock stability in the mpc561/mpc563. clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 c-2 freescale semiconductor c.1 mpc56x device power distribution vdd (external 2.6 v) vss (external gnd) nvddl (external 2.6 v) vss (internal gnd) vddsyn xfc vsssyn extal xtal kapwr iramstby 6 keyed vdd 2.6 v kap 2.6 v cx(pf) 4 cy(pf) <100 ? 100 nf cxfc 100 nf 3 100 nf 100 nf <10 ? 1 f 1 nf 1 nf 1f 100 nf r1 2 (main supply) 1 vddf 5 (external 2.6 v) 1. the main power supply may optionally supply operating current to reduce the keep-alive current requirements. see the circuit in section 8.11.1, ?system cloc k control register (sccr) .? 2. resistor r 1 is currently not required. space should be left on the board to add it in the future if necessary. 3. all 100 nf capacitors should be placed close to the pin. 4. c l is a function of specific crystal c l = c x + c y . see section c.2, ?crystal oscillator external components .? 5. this flash power supply is available on mpc563/564. vddf should be connected to vdd as close as possible to the chip, preferably directly to an inner power plane of the board. 6. see c.3.3 for more information. 7. "all compenent values shown are nominal. compenent tole rance should be considered when designing the system." 100 nf q1 board mpc56x device v supply clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor c-3 figure c-1. mpc561/mpc563 power distribution diagram ? 2.6 v figure c-2. power distribution diagram ? 5 v and analog vddh (digital 5 v) vdda vssa vrh vrl anx (analog input) keyed vdd 5 v 100 nf 1uf 1nf ~10k ? <10 ? <10 ? to from sensors 100 nf ~10 nf r2 3 sensors 100 nf analog ground plane altref 100 nf vflash 1. 10 ohms is recommended because i ref (max) is 250 a per qadc64. 10 ohm x 2 modules x 250 a = 5 mv (approximately one count, or one lsb) 2. the qadc64 circuit design allows for vdda being less than vrh with a value of up to 10 ohms in this rc filter. 3. this size of resistor r 2 depends on the sensor load current. it should be sized to match the voltage at vrh. board mpc56x device 1, 2 clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 c-4 freescale semiconductor c.2 crystal oscillator external components figure c-3. crystal oscillator circuit the load capacitances specified in table c-1 include all stray capacitance. tolerance of the capacitors is 10%. the oscillator capacitors c x and c y were calculated as follows: c a = c b = 2c l c a = c x + c pad + c socket c b = c y + c pad + c socket where: c l is load capacitance c pad is pad capacitance ? xtal pad capacitance is c pad = ~7 pf table c-1. external components value for different crystals (q1) component ndk cp32c 20 mhz kinseki cx-11f 20 mhz murata ccstc 4 mhz units c l 1 1 c l according to crystal specification, c l = c x + c y . 614 ?pf r 1 3 1meg 3 1meg 3 1meg 3 ohm c x 616 ? 2 2 the murata ceramic resonator includes the load capacitors. (8pf should be selected) 3. resistor r 1 is currently not required. space should be le ft on the board to add it in the future if necessary. pf c y 616 ?pf extal xtal cx cy r 1 1 vsssyn 1. resistor r 1 is currently not required. space should be left on the board to add it in the future if necessary. q 1 board mpc56x device clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor c-5 ? extal pad capacitance is c pad = ~7 pf c socket is socket and board trace capacitance ? socket capacitance c <=1pf ? board trace capacitance c <=1pf. th is should be low since the crysta l must be located very close to the chip. c.2.1 kapwr filtering the kapwr signal is the mpc561/mp c563 keep-alive power. kapwr is used for th e crystal oscillator circuit, and should be isolated from the noisy supplies. it is recommende d that an rc filter be used on kapwr, or bypass capacitors that are loca ted as close as possible to the part. figure c-4. rc filter example figure c-5. bypass capacitors example (alternative) c.2.2 pll external components vddsyn and vsssyn are the pll dedi cated power supplies. these supplies must be used only for the pll and isolated from all other noisy signals in the boa rd. vddsyn could be isolat ed with rc filter (see figure c-6 ), or lc filter. the maximum noise allowed on vddsyn, and vsssyn is 50 mv with typical cut-off frequency of 500 hz. kapwr vsssyn kap 2.6 v 100 nf <10 ? board mpc56x device note: a filter cut off frequency of 500hz is recommended, however this will result in a capacitor size of 33uf using a 10 ohm resistor. this may be too expensive or large for the system. in this case the filter shown with cut- off frequency of 160khz will suffice. kapwr vsssyn kap 2.6 v 100 nf 1 f board mpc56x device clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 c-6 freescale semiconductor figure c-6. rc filter example figure c-7. lc filter example (alternative) c.2.3 pll off-chip capacitor c xfc c xfc is the pll feedback capacitor. it must be located as close as po ssible to the xfc and vddsyn pads. the maximum noise allowed on xfc is 50 mv peak-to- peak with a typical cut- off frequency of 500 hz. the xfc capacitor creates a low pass filter in the pll loop. the filter output feeds the pll vco. the capacitor is charged and discharg ed by short current pulses, generated by the phase detector. so the capacitor leakage and absorption dire ctly affect the ac component in the vco input voltage that creates pll output clock jitter. therefor e, the dielectric quality of c xfc should be high. smaller c xfc makes the pll faster to gain lock but less stable. higher c xfc makes the pll more stable but slower to gain lock. because each board layout and application is unique, c xfc must be evaluated in a system. the minimum required value (includi ng capacitor tolerance) for c xfc is determined by the following two cases: 0 < (mf+1) < 4 c xfc = (1130 * (mf+1) ? 80) pf (mf+1) >= 4 c xfc = (2100 * (mf+1)) pf vddsyn vsssyn keyed 100 nf 10 ? vdd 2.6 v board mpc56x device note: a filter cut off frequency of 500hz is recommended, however this will result in a capacitor size of 33uf using a 10 ohm resistor. this may be too expensive or large for the system. in this case the filter shown with cut- off frequency of 160khz will suffice. vddsyn vsssyn keyed 100 nf 8.2 mh vdd 2.6 v board mpc56x device note: a filter cut off frequency of 500hz is recommended, however this will result in a capacitor size of 15uf using a 8.2mh inductor. this may be too expensive or large for the system. in this case the filter shown with cut- off frequency of 5.5khz will suffice. clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor c-7 mf is the multiplication factor in the plprcr register (refer to section 8.11.2, ?pll, low-power, and reset-control register (plprcr) ? for more information). figure c-8. pll off-chip capacitor example c.3 pll and clock oscillator external components layout requirements c.3.1 traces and placement traces connecting capacitors, crystal, resistor should be as short as possible. therefore, the components (crystal, resistor and capacitors) should be placed as close to the oscillator pins of the mpc561/mpc563 as possible. the voltage to the vddsyn pin should be well re gulated and the pin should be provided with an extremely low impedance path from th e vddsyn filter to the vddsyn pad. the vsssyn pin should be provided wi th an extremely low impedance path in the board. all the filters for the supplies should be located as close as possible to the chip package. it is recommended to design individual vsssyn plane to improve vsssyn quietness. c.3.2 grounding/guarding the traces from the oscilla tor pins and pll pins of the mpc561/mpc563 should be guarded from all other traces to reduce crosstalk. it can be provided by keepi ng other traces away from th e oscillator circuit and placing a ground plane around the components and traces. c.3.3 iramstby regulator circuit iramstby is the data retenti on power supply for all on-board ram arrays (calram, dptram, decram). it has a shunt regulator circuit to divert excess current to ground in order to regulate voltage on the iramstby power supply pin. iramstby should be connected to a positive power supply, via a resistor, and bypassed by a capacitor to ground as shown in figure c-9 . xfc cxfc vddsyn board mpc56x device clock and board guidelines mpc561/mpc563 reference manual, rev. 1.2 c-8 freescale semiconductor figure c-9. iramstby regulator circuit the iramstby regulator has a minimum operating curr ent required for the circuit to regulate. this minimum current, along with the range of regulation voltages, determines the regulator?s limits of operation. also, the regulator has a maximum current that it can si nk without the regulat ed voltage rising out of range. 1. operating conditions: -40 c to 150 c, all process variations. 2. supply current includes sram array standby currents. the boundary equations which describe the limits of the operating parameters for the iramstby regulator are as follows: table c-2. iramstby regulator operating specifications parameter minimum typical maximum supply current 50 an/a1.75 ma regulated voltage 1.35 v 1.70 v 1.95 v iramstby v supply v supply c supply board mpc56x device r supply (v supplymin ? 1.95 v) r supply > 50 a (v supplymax ? 1.35 v) r supply < 1.75 ma mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-1 appendix d tpu3 rom functions the following pages provide brief descriptions of th e pre-programmed functions in the tpu3. for detailed descriptions, refer to the programming note for the indivi dual function. the freescale tpu literature pack provides a list of avai lable programming notes. d.1 overview the tpu3 contains 4 kbytes of microcode rom. it can have up to 8 kbytes of memory and a maximum of four entry tables (see figure d-1 ). this appendix defines the st andard rom functions for the mpc561/mpc563. figure d-1. tpu3 memory map the tpu3 can address up to 8 kbytes of memory at any one time. it has 4 kbytes of internal rom, located in banks 0 and 1, and 8 kbytes of dual-ported sram (dptram), locate d in banks 0, 1, 2, and 3. as only one type of memory can be used at a time, the tpu3 must either use the internal rom or the sram. functions from both memory type s cannot be used in conjunction. a new feature of the tpu3 microcode rom is the two 16 -function entry tables in th e 4 kbytes of internal rom. the etbank field in the tpum cr2 register, written once after re set, determines which one of bank 1 bank 0 0 1ff entry code ad d - entry code code 3 ff bank 2 ad d - entry code bank 3 ad d - entry (unimplemented) tpu3rom bank 1 bank 0 0 entry code ad d - entry code code b a nk 2 ad d - entry dptram 1 7 ff 5 ff 3 ff 1ff . 1 the dptram is located at 0x30 2000. add-entry code bank 3 ad d - entry 7 ff tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-2 freescale semiconductor these entry tables the rcpu selects. though the tpu3 can access either entry table, only one table can be used at a time and functions from the tables cannot be mixed. the de fault entry table, located in bank 0, is identical to the standard microcode rom in the tpu2, making any rcpu code written for the tpu2 interchangable with the tpu3. the functions in th e default entry table in bank 0 are listed in table d-1 . the functions in the bank 1 entry ta ble are identical to t hose in bank 0, except in three cases. function 1, spwm in the bank 0 table, has been replaced by rwtpin , a function that allows a read and write to the tpu3 timebases and corresponding pi n. function 5, ppwa in the bank 0 ta ble, is an identification (id) function in the bank 1 table that provides the mi crocode rom revision number. function 7, mcpwm, has been replaced by multi in later sili con revisions. the functions in the bank 1 entry table are listed in table d-1 . the rcpu selects which entry tabl e to use by setting the etbank fiel d in the tpumcr2 register. this register is written once after reset. although one entry table is specified at star t-up, in some cases it is possible to use functions from both tables without resett ing the microcontroller. a customer may, for example, wish to use the id functi on from bank 1 to verify the tpu3 microcode version but then use the mcpwm function from bank 0. as a customer will typically only run the id function during system table d-1. bank 0 and bank 1 functions function number bank 0 functions (def ault) bank 1 functions 0xf pta (programmable time accumulato r) pta (programmable time accumulator) 0xe qom (queued output match) qom (queued output match) 0xd tsm (table stepper motor) tsm (table stepper motor) 0xc fqm (frequency measuremen t) fqm (frequency measurement) 0xb uart (universal asynchronous receiver/transmitter) uart (universal asynchronous receiver/transmitter) 0xa nitc (new input c apture/input transition counter) nitc (new input capt ure/input transition counter) 9 comm (multiphase motor commutation) comm (multiphase motor commutation) 8 halld (hall effect decode) halld (hall effect decode) 7 mcpwm (multi-channel pulse width modulation) multi (multi tpu) 1 1 the multi functions are only on revision d and later of the mpc561 and not available on revision b and earlier of the mpc563. 6 fqd (fast quadrature decode) fqd (fast quadrature decode) 5 ppwa (period/pulse width accumulator) id (identification) 4 oc (output compare) oc (output compare) 3 pwm (pulse width modulation) pwm (pulse width modulation) 2 dio (discrete input/output) d io (discrete input/output) 1 spwm (synchronized pulse width modulation) rwtpin (read/write timers and pin) 0 siop (serial input/output port) s iop (serial input/output port) tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-3 configuration, and not again after that , the bank 1 entry table can be cha nged to the bank 0 entry table using the soft reset feature of the tpu3. this pr ocedure is described in the following steps: 1. set etbank field in tpumcr2 to 0b01 to select the entry table in bank 1 2. run the id function 3. stop the tpu3 by setting the stop bit in the tpumcr to one 4. reset the tpu3 by setting the so ftrst bit in the tpumcr2 register 5. wait at least nine clocks 6. clear the softrst bit in the tpumcr2 register the tpu3 stays in reset until the rcpu clears the softrst bit. after the softrst bit has been cleared, the tpu3 will be reset and the entry table in bank 0 will be selected by default. to select the bank 0 entry table, write 0b00 to the etbank field in tpumcr2. always initialize a ny write-once regist er to ensure that an incorrect value is not accidentally written. the sections below document the bank 0 and bank 1 functions listed in table d-1 of the tpu3 rom module. d.2 programmable time accumulator (pta) pta starts on a rising or falling e dge and accumulates, over a programma ble number of periods or pulses, a 32-bit sum of the total high time, low time, or input signal period. after the specified number of periods or pulses, the pta generates an interrupt request. one to 255 period measurements can be accumulate d before the tpu3 interrupts the rcpu, providing instantaneous or average freque ncy measurement capability. see freescale tpu progamming note programmable time accumulator tpu function (pta), (tpupn06/d) . figure d-2 shows all of the host interface areas for the pta function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-4 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? pta function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 0 1 host sequence 00 ? high time accumulate 0x30yy14 ? 0x30yy16 01 ? low time accumulate 10 ? period accumulate, rising 11 ? period accumulate, falling 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? not used 11 ? initialize 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 channel_control param 0 0x30xxw2 max_count period_count param 1 0x30xxw4 last_time param 2 0x30xxw6 accum param 3 0x30xxw8 hw param 4 0x30xxwa lw param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-2. pta parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-5 d.3 queued output matc h tpu3 function (qom) qom can generate single- or multip le-output match events from a tabl e of offsets in parameter ram. loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously. qom can be used with other tpu3 channels in a vari ety of ways: the function ca n be triggered by a link from the channel, the reference time for the sequence of matches can be obtained from it, or the channel can be used as a discrete output pin. qom can gene rate pulse-width modulated waveforms, including waveforms with high times of 0 or 100% . see freescale tpu3 progamming note queued output match tpu function (qom), (tpupn01/d). figure d-3 shows all of the host interface areas for the qom function. the bit encodings shown in table d-2 describe the corresponding fields in parameter ram. see ta b l e 1 9 - 2 4 for the pram address offset map. table d-2. qom bit encoding a timebase selection 0 use tcr1 as timebase 1 use tcr2 as timebase edge selection 0 falling edge at match 1 rising edge at match b:c reference for first match 00 immediate tcr value 01 last event time 10 value pointed to by ref_addr 11 last event time control bits figure d-2. pta parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-6 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? qom function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta bl e d - 1 0 1 host sequence 00 ? single-shot mode 0x30yy14 ? 0x30yy16 01 ? loop mode 10 ? continuous mode 11 ? continuous mode 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, no pin change 10 ? initialize, pin low 11 ? initialize, pin high 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 ref_addr b last_off_addr a param 0 0x30xxw2 loop_cnt (last_match_tm) off_ptr c param 1 0x30xxw4 offset_1 : param 2 0x30xxw6 offset_2 : param 3 0x30xxw8 offset_3 : param 4 0x30xxwa offset_4 : param 5 0x30xxwc offset_5 1 : param 6 0x30xxwe offset_6 1 : param 7 0x30xx(w+1)0 offset_7 1 : param 8 0x30xx(w+1)2 offset_8 1 : param 9 : : : 0x30xx(w+1)e offset_14 1 : param 15 1. not available on all channels. = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-3. qom parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-7 d.4 table stepper motor (tsm) the tsm function provides accelerat ion and deceleration control of a stepper motor with up to 58 programmable step rates. tsm uses a table in parameter ram, rather than an algorithm, to define the stepper motor acceleration profile, allowing full defininition of the pr ofile. in addition, a slew rate parameter allows fine cont rol of the motor?s terminal running speed independent of the acceleration table. the rcpu writes a desired position, and the tpu3 ac celerates, slews, and decel erates the motor to the required position. full- and half-step support is pr ovided for two-phase motors. see freescale tpu3 progamming note table stepper motor tpu f unction (tsm), (tpupn04/d). figure d-4 and figure d-5 show all of the host in terface areas for the tsm f unction when operating in master or slave mode. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-8 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? tsm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 0 1 host sequence x0 ? local mode acceleration table 0x30yy14 ? 0x30yy16 x1 ? split mode acceleration table 0x ? rotate pin_sequence once between steps 1x ? rotate pin_sequence twice between steps 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, pin low 10 ? initialize, pin high 11 ? move request (master only) 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 desired_position param 0 0x30xxw2 current_position param 1 0x30xxw4 table_size channel _counter table_index param 2 0x30xxw6 slew_period s param 3 0x30xxw8 start_period a param 4 0x30xxwa pin_sequence param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see ta b l e 1 9 - 2 4 for the pram address offset map. figure d-4. tsm parameters ? master mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-9 control bits name options addresses 0123 channel function select xxxx ? tsm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta bl e d - 1 0 1 host sequence x0 ? rotate pin_sequence once 0x30yy14 ? 0x30yy16 between steps x1 ? split mode acceleration table 1x ? rotate pin_sequence once between steps 1x ? rotate pin_sequence twice between steps 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, pin low 10 ? initialize, pin high 11 ? move request (master only) 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xx(w+1)0 accel_ratio_2 accel_ratio_1 param 0 0x30xx(w+1)2 accel_ratio_4 accel_ratio_3 param 1 0x30xx(w+1)4 accel_ratio_6 accel_ratio_5 param 2 0x30xx(w+1)6 accel_ratio_8 accel_ratio_7 param 3 0x30xx(w+1)8 accel_ratio_10 accel_ratio_9 param 4 0x30xx(w+1)a accel_ratio_12 accel_ratio_11 param 5 0x30xx(w+1)c 1 accel_ratio_14 1 accel_ratio_13 1 param 6 : : : : 0x30xx(w+3)a 1 accel_ratio_36 1 accel_ratio_35 1 param 29 1. optional additional parameters not available in all cases. refer to freescale programming note tpupn04/d for details. = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-5. tsm parameters ? slave mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-10 freescale semiconductor d.5 frequency measurement (fqm) fqm counts the number of tpu-cha nnel input pulses during a user-def ined window period. the function has single-shot and conti nuous modes. in continuous mode, no pulses are lost between sample windows, and the user can select whether to detect pulses on the rising or falling edge. this function is intended for high-speed measurement. (measurement of slow pulses with noise rejec tion can be made with pta.) see freescale tpu progamming note frequent measurement tpu function (fqm), (tpupn03/d) . figure d-6 shows all of the host interf ace areas for the fqm function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-11 control bits name options addresses 0123 channel function select xxxx ? fqm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 01 c host sequence 00 ? begin with falling edge, 0x30yy14 ? 0x30yy16 single-shot mode 01 ? begin with falling edge, continuous mode 10 ? begin with rising edge, single-shot mode 11 ? begin with rising edge, continuous mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ?not used 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 param 0 0x30xxw2 param 1 0x30xxw4 channel_control param 2 0x30xxw6 window_size param 3 0x30xxw8 pulse_count param 4 0x30xxwa in_window_accumulator param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = primary channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-6. fqm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-12 freescale semiconductor d.6 universal asynchronous receiver/transmitter (uart) the uart uses one or two tpu3 channels to provi de asynchronous communications. data word length is programmable from 1 to 14 bits. the function s upports detection or generation of even, odd, and no parity. baud rate is freely program mable and can be higher than 100 kbaud. eight bidirectional uart channels running in excess of 9600 baud can be implemented on the tpu3. see freescale tpu3 progamming note asynchronous serial interface tp u function (uart), (tpupn07/d). figure d-7 and figure d-8 show all of the host interface areas for the uart function in transmitting and receiving modes. see table 19-24 for the pram address offset map. control bits figure d-6. fqm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-13 control bits name options addresses 0123 channel function select xxxx ? uart function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 0 1 host sequence 00 ? no parity 0x30yy14 ? 0x30yy16 01 ? no parity 10 ? even parity 11 ? odd parity 01 host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? transmit 11 ? receive 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 pa r i t y _ t e m p param 0 0x30xxw2 match_rate param 1 0x30xxw4 tdre transmit_data_reg param 2 0x30xxw6 data_size param 3 0x30xxw8 actual_bit_count param 4 0x30xxwa shift_register param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see ta b l e 1 9 - 2 4 for the pram address offset map. figure d-7. uart transmitter parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-14 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? uart function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 0 1 host sequence 00 ? no parity 0x30yy14 ? 0x30yy16 01 ? no parity 10 ? even parity 11 ? odd parity 01 host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? transmit 11 ? receive 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 pa r i t y _ t e m p param 0 0x30xxw2 match_rate param 1 0x30xxw4 pe re transmit_data_reg param 2 0x30xxw6 data_size param 3 0x30xxw8 actual_bit_count param 4 0x30xxwa shift_register param 5 0x30xxwc param 6 0x30xxwa param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-8. uart receiver parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-15 d.7 new input capture/tr ansition counter (nitc) nitc allows, for a specified number of transitions, a tpu3 channel to: capture the value of a tcr (test configuration register) or any specified location in pa rameter ram and then generate an interrupt request to notify the bus master (t imes of the two most recent transitions remain in parameter ram), capture input continually or detect a specific number of transiti ons and end channel activity until reinitialization, or generate a link to other channels after the transi tions have taken place. see freescale tpu progamming note new input capture/input transition coun ter tpu function (nitc), (tpupn08/d). figure d-9 shows all of the host interface areas for the nitc function. control bits figure d-8. uart receiver parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-16 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? nitc function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 0 1 host sequence 00 ? single-shot mode, no links 0x30yy14 ? 0x30yy16 01 ? continuous mode, no links 10 ? single-shot mode, links 11 ? continuous mode, links 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize tcr mode 10 ? initialize parameter mode 11 ? not used 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 channel_control param 0 0x30xxw2 start_link_ channel link_chan nel_count param_addr 0 param 1 0x30xxw4 max_count param 2 0x30xxw6 trans_count param 3 0x30xxw8 final_trans_time param 4 0x30xxwa last_trans_time param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-9. nitc parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-17 d.8 multiphase motor commutation (comm) the comm function generates phase commutation signals for a variet y of brushless motors, including three-phase brushless direct current motors. it deri ves the commutation state di rectly from the position decoded in fqd, eliminating the need for hall effect sensors. the state sequence is implemented as a user-configur able state machine, providing a flexible approach with other general applications. a rcpu offset parameter is provided to allow the rcpu to advance or retard all swtiching angles on the fl y. this feature is useful for tor que maintenance at high speeds. see freescale tpu progamming note multiphase motor commutat ion tpu function (comm), (tpupn09/d). figure d-10 and figure d-10 show all of the host interfa ce areas for the comm function. see table 19-24 for the pram address offset map. control bits figure d-9. nitc parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-18 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? comm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see ta b l e d - 1 01 c host sequence 00 ? sensorless match update mode 0x30yy14 ? 0x30yy16 01 ? sensorless match update mode 10 ? sensorless link update mode 11 ? sensorled mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize or force state 11 ? initialize or force immediate state test 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel inerrput enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 start_link_ channel counter_addr param 0 0x30xxw2 no_of_states state_no param 1 0x30xxw4 offset param 2 0x30xxw6 update_period param 3 0x30xxw8 upper param 4 0x30xxwa lower param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the figure d-10. comm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-19 pram address offset map. figure d-10. comm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-20 freescale semiconductor d.9 hall effect decode (halld) the halld function decodes the sens or signals from a brushless moto r (the function s upports two- or three-sensor decoding) and a direct ion input from the rcpu into a st ate number. the decoded state number is written into a comm channel, which outputs the required commutation driv e signals. in addition to brushless motor applications, the f unction can have more general appli cations, such as decoding ?option? switches. see freescale tpu progamming note hall effect decode tpu function (halld), (tpupn10/d). figure d-11 shows all of the host interfa ce areas for the halld function. parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xx(w + 1)0 length state 0 pin_config param 8 0x30xx(w + 1)2 length state 1 pin_config param 9 0x30xx(w + 1)4 length state 2 pin_config param 10 0x30xx(w + 1)6 length state 3 pin_config param 11 0x30xx(w + 1)8 length state 4 pin_config param 12 0x30xx(w + 1)a length state 5 pin_config param 13 0x30xx(w + 1)c length state 6 1 pin_config param 14 0x30xx(w + 1)e length state 7 1 pin_config param 15 0x30xx(w + 2)0 length state 8 1 pin_config param 16 0x30xx(w + 2)2 length state 9 1 pin_config param 17 : : : : : : 0x30xx(w + 3)a length state 21 1 pin_config param 29 1. not available on all channels. = written by rcpu = written by rcpu and tpu w = master channel number = written by tpu = unused parameters for address offsets, xx=41 for tpu_a, 45 for tpu_bsee table 19-24 for pram address offset map. figure d-10. comm parameters (continued) tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-21 control bits name options addresses 0123 c channel function select xxxx ? halld function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta bl e d - 1 0 1 c host sequence 00 ? channel a 0x30yy14 ? 0x30yy16 01 ? channel b 10 ? channel b 11 ? channel c (3-channel mode only) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize, 2-channel mode 11 ? initialize, 3-channel mode 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status x ? not used 0x30yy20 parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 param 0 0x30xxw2 param 1 0x30xxw4 param 2 0x30xxw6 direction 1 param 3 0x30xxw8 state_no_addr 2 param 4 0x30xxwa pinstate param 5 0x30xxwc param 6 0x30xxwe param 7 1. channel a only. 2. one channel only (channel b in 2-channel mode, channel c in 3-channel mode. = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-11. halld parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-22 freescale semiconductor d.10 multichannel pulse-width modulation (mcpwm) mcpwm generates pulse-width modula ted outputs with full 0 to 100% duty cycle range independent of other tpu3 activity. this capability requires two tpu3 channels plus an external gate for one pwm. (a simple one-channel pwm capability is supported by the qom function.) multiple pwms generated by mcpwm have two types of high time alignment: e dge aligned and center aligned. edge-aligned mode uses n + 1 tpu3 channels for n pwms, a nd center-aligned mode uses 2n + 1 channels. center-aligned mode allows a user to define ?dead time? so that two pwms can be used to drive an h-bridge without destru ctive current spikes. this feature is imp ortant for motor control applications. see freescale tpu progamming note multichannel pwm tpu functi on (mcpwm), (tpupn05/d). figure d-12 through table d-17 shows the host interface areas for the mcpwm function in each mode. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-23 control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 01 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize, as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 period param 0 0x30xxw2 irq_rate period_count param 1 0x30xxw4 last_rise_time param 2 0x30xxw6 last_fall_time param 3 0x30xxw8 rise_time_ptr param 4 0x30xxwa fall_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-12. mcpwm parameters ? master mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-24 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0a assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x03xxw0 period param 0 0x30xxw2 high_time param 1 0x30xxw4 param 2 0x30xxw6 high_time_ptr param 3 0x30xxw8 rise_time_ptr param 4 0x30xxwa fall_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-13. mcpwm parameters ? slave edge-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-25 see table 19-24 for the pram address offset map. control bits figure d-13. mcpwm parameters ? slave edge-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-26 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0a assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 period param 0 0x30xxw2 nxt_b_rise_time param 1 0x30xxw4 nxt_b_fall_time param 2 0x30xxw6 dead_time high_time_ptr param 3 0x30xxw8 rise_time_ptr param 4 0x30xxwa fall_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-14. mcpwm parameters ? slave ch a non-inverted center-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-27 control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 high_time param 0 0x30xxw2 current_high_time param 1 0x30xxw4 temp_storage param 2 0x30xxw6 param 3 0x30xxw8 b_fall_time_ptr param 4 0x30xxwa b_rise_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-15. mcpwm parameters ? slave ch b non-inverted center-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-28 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number 0x30yy0a assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 period param 0 0x30xxw2 nxt_b_rise_time param 1 0x30xxw4 nxt_b_fall_time param 2 0x30xxw6 dead_time high_time_ptr param 3 0x30xxw8 rise_time_ptr param 4 0x30xxwa fall_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-16. mcpwm parameters ? slave ch a inverted center-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-29 control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11 ? initialize as master 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 high_time param 0 0x30xxw2 current_high_time param 1 0x30xxw4 temp_storage param 2 0x30xxw6 param 3 0x30xxw8 b_fall_time_ptr param 4 0x30xxwa b_rise_time_ptr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-17. mcpwm parameters ? slave ch b inverted center-aligned mode tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-30 freescale semiconductor d.11 multi tpu (multi) the multi function consists of four sub-functions: frinc: a free running incremen ting 32-bit counter. the counter frequency is determined by a variable parameter ?tic ks? and either tcr1 or tcr2 can be used as a timebase. this function runs continuously without servi ce from the rcpu and can only be stopped by setting its priority to zero. frdec: a free running 32-bit decrementing c ounter, similar to fr inc but with the additional feature that it can be program med to generate an interrupt when the counter reaches zero. pwm_in: this function analyses a pwm-input signal by measur ing a selectable number of periods. it adds both periods as well as high-time for the selected number of periods. speed: this function measures pe riods from a defined edge to the next defined edge. the measurement is not specified for a numbe r of periods, but is continuous. if the result is read regularly, the function me asures the time for the number of periods detected between the two reads. in other words, the function averages the periods between two consecutive reads. this function uses tcr1 for the timebase. this function is available only on re vision d and later of the mpc561 a nd is not available on revision b and earlier of the mpc563. figure d-18 through figure d-21 show all of the host interf ace areas for the multi function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-31 control bits name options addresses 0123 c channel function select xxxx ? multi function number. 0x30yy0a assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence x0 ? initialize with timebase as tcr1 0x30yy0c ? 0x30yy12 x1 ? initialize with timebase as tcr2 01 c host service request 00 ? not used 0x30yy14 ? 0x30yy16 01 ? pwm_in or speed mode 10 ? free running decrementer mode 11 ? free running incrementer mode 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable x ? not used 0x30yy1c ? 0x30yy1e 0 c channel interrupt status x ? not used 0x30yy20 parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 ticks param 0 0x30xxw2 counter_high param 1 0x30xxw4 counter_low param 2 0x30xxw6 param 3 0x30xxw8 param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-18. multi parameters ? frinc tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-32 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? multi function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? timebase tcr1, interrupt off 0x30yy14 ? 0x30yy16 01 ? timebase tcr2, interrupt off 10 ? timebase tcr1, interrupt on 11 ? timebase tcr2, interrupt on 01 c host service request 00 ? n/a 0x30yy18 ? 0x30yy1a 01 ? pwm_in or speed mode 10 ? free running decrementer mode 11 ? free running incrementer mode 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 ticks param 0 0x30xxw2 counter_high param 1 0x30xxw4 counter_low param 2 0x30xxw6 param 3 0x30xxw8 param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-19. multi parameters ? fredec tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-33 control bits name options addresses 0123 c channel function select xxxx ? multi function number 0x30yy0a assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? pwm_in with tcr1 0x30yy0c ? 0x30yy12 01 ? pwm_in with tcr2 10 ? speed fallin g edge triggered 11 ? speed rising edge triggered 01 c host service request 00 ? n/a 0x30yy14 ? 0x30yy16 01 ? pwm_in or speed mode 10 ? free running decrementer mode 11 ? free running incrementer mode 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 measure time param 0 0x30xxw2 last event param 1 0x30xxw4 undefined high_temp param 2 0x30xxw6 low_temp param 3 0x30xxw8 periods high_byte param 4 0x30xxwa low_word param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-20. multi parameters ? speed tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-34 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? multi function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? pwm_in with tcr1 0x30yy14 ? 0x30yy16 01 ? pwm_in with tcr2 10 ? speed fallin g edge triggered 11 ? speed rising edge triggered 01 c host service request 00 ? n/a 0x30yy18 ? 0x30yy1a 01 ? pwm_in or speed mode 10 ? free running decrementer mode 11 ? free running incrementer mode 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 number of periods per count param 0 0x30xxw2 last_rising param 1 0x30xxw4 high_temp param 2 0x30xxw6 per_temp param 3 0x30xxw8 high param 4 0x30xxwa periods param 5 0x30xxwc irq_time param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-21. multi parameters ? pwm_in tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-35 d.12 fast quadrature decode tpu3 function (fqd) fqd is a position-feedback functi on for motor control. it provides the rcpu with a 16-bit free-running position counter by decoding the two si gnals from a slotted encoder. f qd incorporates a ?speed switch? that disables one of the channels at high speed, allo wing faster signals to be decoded. furthermore, every counter update provides a time stamp that is useful for interpolating position a nd determining velocity at low speed or in instances that implement low-reso lution encoders. the itc function handles the third index channel provided by some encode rs. see freescale tpu progamming note fast quadrature decode tpu function (fqd), (tpupn02/d). figure d-22 and figure d-23 show the host interface areas fo r the fqd function for primary and secondary channels. see table 19-24 for the pram address offset map. control bits figure d-21. multi parameters ? pwm_in tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-36 freescale semiconductor control bits name options addresses 0123 c channel function select xxxx ? fqd function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? primary channel (normal mode) 0x30yy14 ? 0x30yy16 01 ? secondary channel (normal mode) 10 ? primary channel (fast mode) 11 ? secondary channel (fast mode) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? read tcr1 11 ? initialize 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable x ? not used 0x30yy0a 0 c channel interrupt status x ? not used 0x30yy20 parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 edge_time param 0 0x30xxw2 position_count param 1 0x30xxw4 tcr1_value param 2 0x30xxw6 chan_pinstate param 3 0x30xxw8 corr_pinstate_addr param 4 0x30xxwa edge_time_lsb_addr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-22. fqd parameters ? primary channel tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-37 control bits name options addresses 0123 c channel function select xxxx ? fqd function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? primary channel (normal mode) 0x30yy14 ? 0x30yy16 01 ? secondary channel (normal mode) 10 ? primary channel (fast mode) 11 ? secondary channel (fast mode) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? read tcr1 11 ? initialize 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable x ? not used 0x30yy0a 0 c channel interrupt status x ? not used 0x30yy20 parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 param 0 0x30xxw2 param 1 0x30xxw4 tcr1_value param 2 0x30xxw6 chan_pinstate param 3 0x30xxw8 corr_pinstate_addr param 4 0x30xxwa edge_time_lsb_addr param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-23. fqd parameters ? secondary channel tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-38 freescale semiconductor d.13 period/pulse-width accumulator (ppwa) the period/pulse-width accumulator (ppwa) algorithm accumulates a 16-bi t or 24-bit sum of either the period or the pulse width of an input signal over a programmable numbe r of periods or pulses (from one to 255). after an accumulation period, the algorithm can generate a link to a sequent ial block of up to eight channels. the user specifies a starting channel of the block and number of ch annels within the block. generation of links depend s on the mode of operation. any channel can be used to measure an accumulated num ber of periods of an i nput signal. a maximum of 24 bits can be used for the accumu lation parameter. from one to 255 period measurements can be made and summed with the previous measurement(s) before the tpu3 interrupts the rcpu, allowing instantaneous or average frequenc y measurement, and the latest complete accumulation (over the programmed number of periods). the pulse width (high-time portion) of an input signal can be measured (up to 24 bits) and added to a previous measurement over a pr ogrammable number of periods ( one to 255). this provides an instantaneous or average pulse-width measurement cap ability, allowing the latest complete accumulation (over the specified number of periods) to always be available in a parameter. by using the output compare function in conjunction with ppwa, an output signal can be generated that is proportional to a specified input signal. the ratio of the input a nd output frequency is programmable. one or more output signals with di fferent frequencies, yet proportional and synchronized to a single input signal, can be generated on separate channels. see free scale tpu progamming note period/pulse-width accumulator tpu function (ppwa), (tpupn11/d). figure d-24 shows the host interface areas and parameter ram for the ppwa function. see table 19-24 for the pram address offset map. control bits name options addresses figure d-23. fqd parameters ? secondary channel tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-39 control bits name options addresses 0123 c channel function select xxxx ? ppwa function number 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? accumulate 24-bit periods, no links 0x30yy14 ? 0x30yy16 01 ? accumulate 16-bit periods, links 10 ? accumulate 24-bit pulse widths, no links 11 ? accumulate 16-bit pulse widths, links 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ? not used 01 c channel priority 00 ? channel disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 start_link_ channel link_channel_ count 1 channel_control param 0 0x30xxw2 max_count 2 period_count param 1 0x30xxw4 last_accum param 2 0x30xxw6 accum param 3 0x30xxw8 accum_rate ppwa_ub param 4 0x30xxwa ppwa_lw param 5 0x30xxwc param 6 0x30xxwe param 7 1. the tpu does not check the value of link_channel_count. if this parameter is not >0 and < 8, results are unpredictable. 2. max_count may be written at any time by the host rcpu, but if the value written is < period_count, a period or pulse-width accumulation is terminated. if this happens, the number of periods over whic h the accumulation is performed will not correspond to max_count. = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx =41 for tpu_a, 45 for tpu_b yy = 40 for tpu_a, figure d-24. ppwa parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-40 freescale semiconductor d.14 id tpu3 function (id) this is a simple function that returns the version of the tpu3 ro m on the current device. figure d-25 shows all of the host interf ace areas for the id function. 44 for tpu_b see table 19-24 . control bits figure d-24. ppwa parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-41 control bits name options addresses 0123 channel function select xxxx ? id function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 host service request 00 ? no action 0x30yy18 ? 0x30yy1a 01 ? read tpu rom version 10 ? not used 11 ? not used 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 tpu3_id rom_revision param 0 0x30xxw2 param 1 0x30xxw4 param 2 0x30xxw6 param 3 0x30xxw8 param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 figure d-25. id parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-42 freescale semiconductor d.15 output compare (oc) the output compare (oc) function gene rates a rising edge, falling edge, or a toggle of the previous edge: immediately upon rcpu initiat ion (generating a pulse with a length equal to a programma ble delay time), after a programmable delay time, or continuously. upon receiving a link from a channel, oc references, without rcpu interaction, a specifiab le period and calculates an offs et that is equal to the period x the ratio, where the ratio is a supplied parameter. this algorithm generates, with each high/low time , a 50% duty-cycle continuous square equal to the calculated offset. due to offset ca lculation, there is an in itial link time before c ontinuous pulse generation begins. see freescale tpu progamming note output compare tpu func tion (oc), (tpupn12/d). figure d-26 shows the host interface areas and parameter ram for the oc function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-43 control bits name options addresses 0123 c channel function select xxxx ? oc function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 0x ? matches and pulses scheduled 0x30yy14 ? 0x30yy16 x1 ? only read tcr1, tcr2 01 c host service request 00 ? no host service request 0x30yy18 ? 0x30yy1a 01 ? host-initiated pulse 10 ? not used 11 ? initialize, continuous pulses 01 c channel priority 00 ? channel disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 channel_control param 0 0x30xxw2 offset param 1 0x30xxw4 ratio ref_addr1 0 param 2 0x30xxw6 ref_addr2 0 ref_addr3 0 param 3 0x30xxw8 ref_time param 4 0x30xxwa actual_match_time param 5 0x30xxwc tcr1 param 6 0x30xxwe tcr2 param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-26. oc parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-44 freescale semiconductor d.16 pulse-width modulation (pwm) the tpu3 can generate a pulse-width modulation (p wm) waveform with any duty cycle from 0 to 100% (within the resolution and latency capability of the tpu3). to define the pwm, the rcpu provides one parameter that indicates the period and another that indicates the high time. update s to one or both of these parameters can effect waveform change immediately , or coherently at the next low-to-high pin transition. see freescale tpu progamming note pulse-width modulation tpu function (pwm), (tpupn17/d) . figure d-27 shows the host interface areas and parameter ram for the pwm function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-45 control bits name options addresses 0123 c channel function select xxxx ? pwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? immediate update of pwm 10 ? initialize 11 ? not used 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 channel_control param 0 0x30xxw2 oldris param 1 0x30xxw4 pwmhi (1, 3) param 2 0x30xxw6 pwmper (2, 3) param 3 0x30xxw8 pwmris param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-27. pwm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-46 freescale semiconductor d.17 discrete input/output (dio) the dio function (bank 0 and bank 1) allows a tp u3 channel to be used as a digital i/o pin. when a pin is used as a discrete input, a parameter indicates the current input level and the previous 15 levels of a pin. bit 15, the most signi ficant bit of the parameter, indicat es the most recent state. bit 14 indicates the next most recent stat e, and so on. the programmer can update the parameter when a transition occurs, when the rcpu makes a request, or when a rate specified in another parameter is matched. when a pin is used as a discrete output, it is set high or low only upon request by the rcpu. see freescale tpu progamming note discrete input/output tpu f unction (dio), (tpupn18/d). figure d-28 shows the host interface ar eas for the dio function. see table 19-24 for the pram address offset map. control bits figure d-27. pwm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-47 control bits name options addresses 0123 c channel function select xxxx ? dio function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? update on transition 0x30yy14 ? 0x30yy16 01 ? update at match rate 10 ? update on hsr 11 11 ? not used 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? drive pin high 10 ? drive pin low 11 ? initialize 01 0x30yy1c ? 0x30yy1e c channel priority 00 ? disabled 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 channel_control param 0 0x30xxw2 pin_level param 1 0x30xxw4 match_rate param 2 0x30xxw6 param 3 0x30xxw8 param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-28. dio parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-48 freescale semiconductor d.18 synchronized pulse-width modulation (spwm) the spwm function (bank 0) generates a pulse-wid th modulated waveform (pwm). the rcpu can change the period or high time of the waveform at any time. three different operating modes allow the function to maintain complex timing relationshi ps between channels without rcpu intervention. the spwm output waveform duty cycle excludes 0% and 100%. if it is not necessary for a pwm to maintain a time relationship to another pwm, the pwm function should be used instead. see freescale tpu progamming note synchronized pulse-width modulati on tpu function (spwm), (tpupn19/d). figure d-29 shows all of the host interface areas for the spwm function. see table 19-24 for the pram address offset map. control bits figure d-28. dio parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-49 control bits name options addresses 0123 c channel function select xxxx ? spwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? mode 0 0x30yy14 ? 0x30yy16 01 ? mode 1 10 ? mode 2 11 ? not used 01 c host service request 00 ? no host service request 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ? immediate update (mode 1) 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x03xxw0 lastrise channel_control param 0 0x30xxw2 nextrise param 1 0x30xxw4 high_time param 2 0x30xxw6 period param 3 0x30xxw8 ref_addr1 param 4 0x30xxwa delay param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-29. spwm parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-50 freescale semiconductor parameter ram (mode 1) address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 lastrise channel_control param 0 0x30xxw2 nextrise param 1 0x30xxw4 high_time param 2 0x30xxw6 delay param 3 0x30xxw8 ref_addr1 ref_addr2 param 4 0x30xxwa ref_value param 5 0x30xxwc param 6 0x30xxwe param 7 parameter ram (mode 2) address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 lastrise channel_control param 0 0x30xxw2 nextrise param 1 0x30xxw4 high_time param 2 0x30xxw6 period param 3 0x30xxw8 start_link_ channel link_channel_ count ref_addr1 param 4 0x30xxwa delay param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-29. spwm parameters (continued) tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-51 d.19 read/write timers and pin tpu3 function (rwtpin) the rwtpin bank 1 tpu3 function enables the rcpu to read, via locations in pram, both the tcr1 and tcr2 timer counters, and than selectively load tcr1 or tcr2 wi th a rcpu-supplied value contained in pram. the function also allows control of the pin state and di rection of the rwtpin channel. a pin-state parameter is ma intained in pram and is updated upon ever y service request. it can contain a value of the current pin state whether the pin is programmed as an input or output. the function also receives links. upon receipt, it will read the tw o tcrs into pram, updating the pin-state parameter and generating a mask able interrupt request to the rcpu. the rcpu can control the channel pin, the tcrs, or bot h. to control the channel pin only, the ?read tcr? option is used and the values return ed ignored. because this function controls the tcrs without affecting the channel pin, it can run on a tpu3 channel whos e pin is controlled by a function running on another channel (for example, a slave stepper-motor channel). see freescal e tpu progamming note using the tpu function library and tpu emulation mode, (tpupn00/d). figure d-30 shows all of the host interface areas for the pta function. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-52 freescale semiconductor control bits name options addresses 0123 channel function select xxxx ? rwtpin function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 host service request 00 ? no action 0x30yy18 ? 0x30yy1a 01 ? read tcrs and read/write pin 10 ? write tcr1, read tcrs and read/write pin 11 ? write tcr2, read tcrs and read/write pin 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 param 0 0x30xxw2 param 1 0x30xxw4 channel_control param 2 0x30xxw6 channel_pin_state param 3 0x30xxw8 tcr1_value param 4 0x30xxwa tcr2_value param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b see table 19-24 for the pram address offset map. figure d-30. rwtpin parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-53 d.20 serial input/output port (siop) the serial input/output port (siop) tpu3 function uses two or three tp u3 channels to form a uni- or bidirectional synchronous serial port th at can be used to communicate with a wide variety of devices. it can be used to add serial capabilities to a device wit hout a serial port, or to ex tend the capabilities of one with a hardware-synchronous port. the siop tpu3 f unction has been designed to closely resemble the siop hardware port found on some freescale mcus. siop operates in master mode (the tpu3 always ge nerates the clock) and ha s the following programmable features: 1. choice of one-channel clock-only, two-channel cl ock + transmit, two-channe l clock + receive, or three-channel clock + transmit + receive operating modes 2. freely programmable ba ud-rate period over a 15-bi t range of tcr1 counts 3. selection of msb or lsb first shift direction 4. variable transfer size from 1 to 16 bits 5. programmable clock polarity when a transfer of data is complete, the siop function notifies the host rcpu by issuing an interrupt request. the arrangement of the multiple siop channels is fixed: the data-out ch annel is the channel above the clock channel and the data-in channel is the ch annel below the clock cha nnel. in clock-only or uni-directional mode, the unused tpu3 channels are free to run other tpu3 functions. two possible siop configurations are shown in figure d-31 figure d-31. two possible siop configurations d.20.1 parameters figure d-32 shows the host interface areas and parameter ram for the siop function. the following sections describe these parameters. da t a o ut-chan x+1 clo c k o u t -chan x d ata in-chan x-1 765432 10 765432 10 d ata out-chan x+1 clo c k o u t -chan x 7 6 5 4 3 2 1 089 8-bit bidirectional transfer, msb first with data valid on clock rising edge 10-bit output only transfer, lsb first with data valid on clock falling edge tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-54 freescale semiconductor note only the clock channel requires any programming. the data -in and data-out channels are entirely under tpu3 microcode control. tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-55 control bits name options addresses 0123 c channel function select xxxx ? siop function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see ta b l e d - 1 0 1 c host sequence 00 ? clock channel active only, 0x30yy14 ? 0x30yy16 no data transfer 01 ? d out channels active, no data receive 10 ? clock and d in channels active, no data transmit 11 ? full bidirectional transmit and receive 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? no action 10 ? no action 11 ? initialize clock channel and start transfer 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted parameter ram address offsets bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30xxw0 s channel_control param 0 0x30xxw2 half-period param 1 0x30xxw4 bit_count param 2 0x30xxw6 xfer_size param 3 0x30xxw8 data param 4 0x30xxwa param 5 0x30xxwc param 6 0x30xxwe param 7 = written by rcpu = written by rcpu and tpu w = channel number = written by tpu = unused parameters for address offsets: xx=41 for tpu_a, 45 for tpu_b yy=40 for tpu_a, 44 for tpu_b figure d-32. siop parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-56 freescale semiconductor d.20.1.1 chan_control this 9-bit, rcpu-written parameter is used to set up the clock polarity fo r the siop data transfer. the valid values for chan_control for this function are given in table d-3 . chan_control must be written by the host before issuin g the host service request (hsr ) to initialize the function. d.20.1.2 bit_d bit_d is a rcpu-written bit th at determines the direction of shift of the siop data. if bit_d is zero, then siop_data is right shifted (lsb fi rst). if bit_d is one then siop_d ata is left shifted (msb first). d.20.1.3 half_period this rcpu-written parameter defi nes the baud rate of the siop function. the value contained in half_period is the number of tcr1 counts for a half-siop cloc k period (for example, for a 50 baud rate, with a tcr1 period of 240 ns, the value [(1/50) /2]/240 ns = 42) should be written to half_period. the range for half_period is 1 to 0x8000, although the minimum value in practice will be limited by other system conditions. see the notes in section d.20.1.6, ?siop_data ? for information on the use and performance of the siop function. d.20.1.4 bit_count the tpu3 uses this parameter to count down the numbe r of bits remaining during a transfer in progress. during the siop initialization state, bit_count is loaded with the value contained in xfer_size and then decremented as the data is transferred. when it reaches zero, the transfer is complete and the tpu3 issues an interrupt request to the rcpu. d.20.1.5 xfer_size this rcpu-written parameter dete rmines the number of bits that make up a data transfer. during initialization, xfer_size is copied into bit_coun t. xfer_size is shown as a 5-bit parameter to match the maximum size of 16 bits in siop_data, although the tpu3 uses the whole word location. for normal use, xfer_size should be in the 1- to 16-bit range. see table 19-24 for the pram address offset map. table d-3. siop function valid chan_control options chan_control 1 8 7 6 5 4 3 2 1 0 1 other values of chan_control may result in indeterminate operation. resulting action 0 1 0 0 0 1 1 0 1 data valid on clock falling edge. 0 1 0 0 0 1 1 1 0 data valid on clock rising edge. control bits figure d-32. siop parameters tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-57 d.20.1.6 siop_data this parameter is the data register for all siop transfers. data is shifted out of one end of siop_data and shifted in at the othe r end, the shift direction being determined by the value of bi t_d. in output-only mode, zero will be shifted into siop_data and in input-only mode, th e data shifted out is ignored. in clock-only mode, siop_data is still shifted. note the tpu3 does not ?justify? the data position in siop_dat a (for example, if an 8-bit bidirectional transfer is made, shifting lsb first, then the bottom byte of siop_data will be shifted out and the input data will be shifted into the upper byte of siop_data). note siop_data is not buffered. the rcpu should only access it between completion of one transfer and the start of the next. d.20.2 host rcpu initializa tion of the siop function the rcpu initializes the siop function by: 1. disabling the channel by cleari ng the two channel-priority bits 2. selecting the siop function on the channel by wr iting the assigned siop function number to the function-select bits 3. writing chan_control in the clock channel parameter ram 4. writing half_period, bit_d, and xfer_si ze in the clock-channel parameter ram to determine the speed, shift dir ection, and size of the transfer 5. writing siop_data if the data output is to be used 6. selecting the required operating m ode via the two ho st-sequence bits 7. issuing a host service request type 0b11 8. enabling service by assigning h, m, or l priority to the clock channel via the two channel-priority bits the tpu3 then starts the data transfer, and issues an interrupt request when the transfer is complete. once the function has been initialized, the rcpu only needs to write siop_data with the new data and issue a hsr 0b11 to initiate a new transfer. in input-only or clock- only modes, just the hsr 0b11 is required. d.20.3 siop function performance like all tpu3 functions, the perfor mance limit of the siop function depends, becaus e of the operational nature of the scheduler, on the servic e time (latency) associated with other active tpu3 channels. where two channels are used for a uni-dir ectional system and no other tpu3 channels are active, the maximum baud rate is approximately 230 at a bus speed of 16.77 mhz. a three-ch annel bidirectional system under the same conditions has a maximum baud rate of approximately 200. when more tpu3 channels are tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-58 freescale semiconductor active, these performance figures wi ll be degraded; however, the scheduler assures that the worst-case latency in any tpu3 application can be closely approximated. tpu3 reference manual guidelines and information given in the siop-state timing table shoul d be used to perform an analysis on any proposed tpu3 application that appears to a pproach the tpu?s performance limits. d.20.3.1 xfer_size greater than 16 xfer_size is normally progra mmed to be in the 1- to 16-bit range to match the size of siop_data, and has thus been shown as a 5-bit valu e in the host interface diagram. howe ver, the tpu3 actually uses all 16 bits of the xfer_size parameter wh en loading bit_count. in some unusual circumstances this can be used to an advantage. if an input de vice is producing a data st ream of greater than 16 bits then manipulation of xfer_size will allow selective capturing of the data. in clock-only mode, the extended xfer_size can be used to generate up to 0xffff clocks. d.20.3.2 data positioning as stated above, the tpu3 does not ?justify? the data position in siop_data. therefore, in the case of a byte transfer, the data output will be sourced from one byte and the data input will shif t into the other byte. this is true for all data sizes exce pt 16 bits, in which case the full siop_data register is used for both data output and input. d.20.3.3 data timing in the example given in figure d-33 , the data output transitions ar e shown as being completely synchronous with the relevant clock edge and it is as sumed that the data input is latched exactly on the opposite clock edge. this is th e simplest way to show the examples, but is not strictly true. since the tpu3 is a multi-tasking system, and the data channels ar e manipulated directly by microcode software while servicing the clock edge, there is a fi nite delay between the re levant clock edge and th e data-out being valid or the data-in being latched. this de lay is equivalent to the latency in servicing the clock channel due to other tpu3 activity and is shown as ?td? in the timing diagram. td is the delay between the clock edge and the next output data be ing valid and also the delay between th e opposite clock edge and the input data being read. for the vast majority of applications, the delay td will not present a problem and can be ignored. only for a system which he avily loads the tpu3 should the wo rst case latency be calculated for table d-4. siop state timing 1 1 execution times do not include the time slot transition time (tst = 10 or 14 rcpu clocks). state number and name max. rcpu clock cycles number of ram accesses by tpu3 s1 siop_init hsq = x0 x1 28 38 7 7 s2 data_out hsq = x0 x1 14 24 4 4 s3 data_in hsq = 0x 1x 14 28 4 6 tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor d-59 the siop clock channel + actual siop service time ( = td) and ensure that the baud rate is chosen such that half_period - td is not less that the minimum setup time of th e receiving device. a transmitting device must also hold data valid for a minimum time of td after the clock. figure d-33. siop function data transition example dat a out cha n x+1 clo c k cha n x data in cha n x-1 td td tpu3 rom functions mpc561/mpc563 reference manual, rev. 1.2 d-60 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor e-1 appendix e memory access timing table e-1 lists all possible memory access timings for in ternal and external memory combinations. the clock values show the number of cloc ks from the moment an address is valid on a specific bus, until data is back on that same bus. the following assumptio ns were used when co mpiling the information: ? the arbitration time was ignore d. the values assume that th e bus (or buses) involved in a transaction was in the idle state when the transaction needs that bus. ? the uimb works in a mode of 1: 1. this is relevant for imb access values. in the case of 2:1 mode, the clock latency for a cycle on the imb should be doubled (eac h imb access take s two clocks). ? the basic delay of an external bus to a u- bus is four clocks (external master case). ? all imb accesses are assumed to be 16-bit accesses only. if 32-bit accesses ar e used, then each such imb access is split into two separate 16-bit cy cles with normal imb performance for each. table e-1. memory access times using different buses internal buses external ram/flash show cycle flash ram decra m imb siu internal memory mapped external non-mappe d internal memory write read rcpu load/store 3/4 1 1 ?/? indicates on/off page flash access. 1654+n 2 2 n is the number of read cycle clocks from ex ternal address valid till exte rnal data valid. in the ca se of zero wait states, n = 2. 4+n 2 2 rcpu instruction fetches 2-1-1-1-1.. 3 3 3 assuming bbc is parked on the u-bus 2 ? 1 4 4 siumcr[burst_en] = 1 2+n 2+n ?1 5 5 until address is valid on external pins peripheral mode (only external master is active) 4/5 6 6 7 6 slave mode (both external and internal cpus are active) 5/6 7 6 8 7 memory access timing mpc561/mpc563 reference manual, rev. 1.2 e-2 freescale semiconductor table e-2. instruction timing examples for different buses note: l = l-bus, u = u-bus, e = e-bus, c = cmf (flash), imb = intermodule bus, dc = decram access number of clocks total 12345678910111213 load/store -> ebus l u e 6 1 eul load/store -> imb 16 bits l u imb 6 imb u l instruction fetch-> cmf new page 3 consecutive accesses c,u 2 u 2 c,u 1 u c,u 1 u instruction fetch-> decram (decompression off) u icd u icd u u instruction fetch-> cmf new page load/store -> imb c,u 2 u l u imb 6 imb u l instruction fetch-> cmf new page load/store -> imb c u 6 u l u imb 6 imb u l external bus-> cmf new page e u 5 ue external bus-> imb e u imb 7 imb u e load/store-> decram l u u l memory access timing mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor e-3 note: shaded areas = address phase ; non-shaded areas = data phase instruction fetch-> cmf 2 consecutive accesses and external bus-> cmf c,u 2 u c? 3 ??????? u11 u e retr y e 4 u8 ue 1 n is the number of read cycle clocks from external address valid until external data va lid. in the case of zero wait states, n = 2. 2 core instruction fetch data bus is usually the u-bus 3 8 clocks are dedicated for external accesses, and internal accesses are denied. 4 assuming the external master immediately retries table e-2. instruction timing examples for different buses (continued) note: l = l-bus, u = u-bus, e = e-bus, c = cmf (flash), imb = intermodule bus, dc = decram access number of clocks total 12345678910111213 memory access timing mpc561/mpc563 reference manual, rev. 1.2 e-4 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-1 appendix f electrical characteristics this appendix contains detailed information on power considerations, dc/ac elec trical characteristics, and ac timing characteri stics of the mpc561/mpc 563. the mpc561/mpc563 is designed to operate at 40 mhz, or optionally at 56 or 66 mhz. refer to appendix g, ?66-mhz electr ical characteristics ,? for more information. ) table f-1. absolute maximum ratings (vss = 0v) rating symbol min. value max. value unit 1 2.6-v supply voltage 1 v ddl -0.3 3.0 2 v 2 flash supply voltage 3,4 v flash -0.3 5.6 v 3 flash core voltage 1, 4 v ddf -0.3 3.0 v 4 oscillator, keep-alive reg. supply voltage 1 kapwr -0.3 3.0 v 5 sram supply voltage 1,5 iramstby -0.3 3.0 v 6 clock synthesizer supply voltage 1 v ddsyn -0.3 3.0 v 7n.a. ? ? ? ? 8 qadc supply voltage 6 v dda -0.3 5.6 v 9 5-v supply voltage v ddh -0.3 5.6 v 10 dc input voltages 7,8 v in v ss -0.3 5.6 9 v 11 reference v rh , with reference to v rl v rh -0.3 5.6 v 12 reference altref, with reference to v rl v arh -0.3 5.6 v 13 v ss differential voltage v ss ? v ssa -0.1 0.1 v 15 v ref differential voltage v rh ? v rl -5.6 5.6 v 16 v rl to v ssa differential voltage v rl ? v ssa -0.3 0.3 v 17 maximum input current per pin 10, 11, 12 i ma -25 13 25 13 ma 18 qadc maximum input current per pin i max -25 13 25 13 ma 19 operating temperature range ? ambient (packaged), m temperature range. t a -40 (t l ) +125 (t h ) c 19a operating temperature range ? ambient (packaged), c temperature range. t a -40 (t l ) +85 (t h ) c 20 operating temperature range ? solder ball (packaged any perimeter solder ball) 14 t sb -40 (t l ) +135 (t h ) c 21 junction temperature range t j -40 +150 c 22 storage temperature range t stg -55 +150 c 23 maximum solder temperature 15 t sdr ? 235 c 24 moisture sensitivity level 16 msl ? 3 ? electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-2 freescale semiconductor functional operating conditions are given in section f.5, ?dc electri cal characteristics .? absolute maximum ratings are stress ratings only, and functiona l operation at the maximum is not guaranteed. stress beyond those listed may affect device reliabilit y or cause permanent damage to the device. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). note negative current flows out of the pin and positive cu rrent flows into the pin. f.1 package the mpc561/mpc563 is available in packaged form. the package is a 388-ball pbga having a 1.0 mm ball pitch, frees cale case outline 1164-01 (see figure f-64 and figure f-65 ). f.2 emi characteristics f.2.1 reference documents the document referenced for the emc testing of mpc561/mpc563 is sae j1752/3 issued 1995-03 1 for internal digital supply of v ddl = 2.6-v typical. 2 2.6 volt supply pins can withstand up to 3.6 volts for acumulative time of 24 hours over the lifetime of the device. 3 during operation the value of v flash must be 5.0 v 5% 4 these power supplies are available on mpc563 and mpc564 only. 5 maximum average current into the iramstby pin must be < 1.75ma. 6 v dda =5.0 v 5%. 7 all 2.6-v input-only pi ns are 5-v tolerant. 8 note that long term reliability may be compromised if 2. 6-v output drivers drive a node which has been previously pulled to >3.1 v by an external component. hreset and sreset are fully 5-v compatible. 9 6.35 v on 5-v only pins (all qadc, all tpu, all qsmc m and the following mios pins: mda[11:15], mda[27:31], mpwm16, mpio32b[7:9]/mpwm[20:21], mpio32b11/c_cnrx0, mpio32b12/c_cntx0 ). in ternal structures hold the input voltage below this maximum voltage on a ll of these pins, except the qsmcm rxd1/qpi1 and rxd2/qpi2/c_cnrx0 pins, if the maximum injection current specification is met (1 ma for all pins; exception: 3 ma on qadc pins) and vddh is within operating vo ltage specifications (see specification 43 in ta bl e f - 4 ). exception: the rxd1/qgpi1 and rxd2/gpi2 pins do not have clamp di odes to vddh. voltage must be limited to less than 6.5 volts on these 2 pins to prevent damage. 10 maximum continuous current on i/o pins provided the over all power dissipation is below the power dissipation of the package. proper operation is not guaranteed at this condition. 11 condition applies to one pin at a time. 12 transitions within the limit do not affe ct device reliability or cause permanent damage. exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels. 13 maximum transient current per iso7637. 14 maximum operating temperature on any solder ball in outer f our rows of solder balls on the package. these rows are referred to as ?perimeter balls? to distinguish th em from the balls in the center of the package. 15 solder profile per cdf-aec-q100, current revision. 16 moisture sensitivity per jedec te st method j-std-020-a (april 1999). electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-3 f.2.2 definitions and acronyms emc ? electromagnetic compatibility emi ? electromagnetic interference tem cell ? transverse el ectromagnetic mode cell f.2.3 emi testing specifications 1. scan range: 150 khz ? 1000 mhz 2. operating frequency: 56 mhz 3. operating voltages: 2.6 v, 5.0 v 4. max spikes: tbd dbuv 5. i/o port wavefo rms: per j1752/3 6. temperature: 25 c f.3 thermal characteristics table f-2. thermal characteristics characteristic symbol value unit bga package thermal resistance, junction to ambient ? natural convection r ja 47.3 1,2,3 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 2 per semi g38-87 and jesd51-2 with the board horizontal. 3 these values are the mean + 3 standard deviations of characterized data. c/w bga package thermal resistance, junction to ambient ? four layer (2s2p) board, natural convection r jma 29.4 3,4 , 5 4 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 5 per jesd51-6 with the board horizontal. c/w bga package thermal resistance, junction to board r jb 21.2 3,6 6 thermal resistance between the die and the printed circui t board (four layer (2s2p) board, natural convection). c/w bga package thermal resistance, junction to case (top) r jt 7.0 3,7 7 indicates the thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012. 1) with the cold plate temperature used for the case temperature. c/w bga package thermal resistance, junction to package top, natural convection jt 1.6 8 8 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per eia/jesd51-2. c/w electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-4 freescale semiconductor an estimation of the chip junction temperature, t j , in c can be obtained from the equation: t j = t a + (r ja x p d ) where: t a = ambient temperature (c) r ja = package junction to ambient resistance (c/w) p d = power dissipation in package the junction to ambient thermal resi stance is an industry standard va lue which provides a quick and easy estimation of thermal performance. unfortunately, the answer is only an estimate; test cases have demonstrated that errors of a factor of two are possible. as a result, mo re detailed therma l characterization is supplied. historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ja = case to ambient thermal resistance (c/w) r jc is device related and canno t be influenced. th e user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the air flow can be changed around the device, add a heat sink, change the mounting ar rangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most usef ul for ceramic packages with heat sinks where about 90% of the heat flow is through the case to the heat sink to ambient. for most packages, a better model is required. the simplest thermal model of a pa ckage which has demonstrated reas onable accuracy (about 20 percent) is a two resistor model consisting of a junction to board and a junction to case thermal resistance. the junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. the junction to board therma l resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it ha s been observed that the thermal performance of most plasti c packages and especially pbga p ackages is strongly dependent on the board. temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb x p d ) where: t b = board temperature (c) r jb = package junction to board resistance (c/w) p d = power dissipation in package ( ? ) electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-5 if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction te mperature can be made. for this me thod to work, the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias at taching the thermal balls to the ground plane. when the board temperature is not known, a thermal si mulation of the application is needed. the simple two-resistor model can be us ed with the thermal simulation of the a pplication (2), or a more accurate and complex model of the pack age can be used in the thermal simula tion. consultation on the creation of the complex model is available. to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t t = thermocouple temperature on top of package (c) jt = thermal characterization parameter p d = power dissipation in package the thermal characterization para meter is measured per jesd51-2 specification published by jedec using a 40 gauge type-t thermocouple epoxied to th e top center of the package case. the thermocouple should be positioned so that the thermocouple junction rest s on the package. a sm all amount of epoxy is placed over the thermocouple junction and over about one mm of wire extendi ng from the junction. the thermocouple wire is placed flat against the package case to avoid me asurement errors caused by cooling effects of the thermocouple wire. f.3.1 thermal references the website for semiconductor equipm ent and materials international is www.semi.org and their global headquarters address is: 3081 zanker ro ad, san jose ca, 95134; 1-408-943-6900. mil-spec and eia/jesd (jedec) sp ecifications are available from global engineering documents on the web at www.global.ihs.co m or 800-854-7179 or 303-397-7956. jedec specifications are availabl e on the web at www.jedec.org. 1. c.e. triplett and b. joiner, ? an experimental characterization of a 272 pbga within an automotive engine controller module ,? proceedings of semith erm, san diego, 1998, pp. 47-54. 2. b. joiner and v. adams, ? measurement and simulation of junc tion to board thermal resistance and its application in thermal modeling ,? proceedings of semitherm, san diego, 1999, pp. 212-220. electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-6 freescale semiconductor f.4 esd protection table f-3. esd protection characteristics symbol value units esd for human body model (hbm) 1 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for automotive grade integrated circuits. 2000 v hbm circuit description r1 1500 ? c 100 pf esd for machine model (mm) 200 v mm circuit description r1 0 ? c 200 pf number of pulses per pin 2 positive pulses (mm) negative pulses (mm) positive pulses (hbm) negative pulses (hbm) 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric an d functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. ? ? ? ? 3 3 1 1 ? interval of pulses ? 1 s electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-7 f.5 dc electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) table f-4. dc electrical characteristics characteristic symbol min max unit 1 2.6-v only input high voltage 1 except data[0:31] and extclk v ih 2.6 2.0 v ddh + 0.3 v 1a 2.6-v input high voltage extclk v ih c1.6v ddh + 0.3 v 2 data[0:31] precharge voltage 2 data[0:31] precharge voltage (predischarge circuit enabled) 3 vdatapc vdatapc5 3.1 5.25 v 3 5-v input only high voltage 4 v ih 5 0.7 * v ddh v ddh + 0.3 v 4 5-v input high voltage (qadc pqa, pqb) v ih a5 0.7 * v ddh (v dda | v ddh ) + 0.3 5 v 5 muxed 2.6-v/ 5-v pins (gpio muxed with addr and data) 2.6-v input high voltage addr., data 5-v input high voltage (gpio) v ih 2.6m v ih 5m 2.0 0.7 * v ddh v ddh + 0.3 v ddh + 0.3 v v 6 2.6-v input low voltage except extclk v il 2.6 v ss ? 0.3 0.8 v 7 2.6-v input low voltage extclk v il 2.6c v ss ? 0.3 0.4 v 8 5-v input low voltage v il 5v ss ? 0.3 0.48 * v ddh v 9 5-v input low voltage (qadc pqa, pqb) v il a5 v ssa ? 0.3 0.48 * v ddh v 10 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v input low voltage (addr., data) 5-v input low voltage (gpio) v il 2.6m v il 5m v ss ? 0.3 v ss ? 0.3 0.8 0.48 * v ddh v 11 qadc analog input voltage 6 note: assumes v dda v ddh vindc v ssh ? 0.3 v ddh + 0.3 v 12 2.6-v weak pull-up/down current pull-up @ 0 to v il 2.6, pull-down @ v ih 2.6 to v dd i act2.6v 20 130 a 13 5-v weak pull-up/down current 6 pull-up @ 0 to v il 5, pull-down @ v ih 5 to v ddh i act5v 20 130 a 14 2.6-v input leakage current 6 pull-up/down inactive ? measured @rails i inact2.6v ?2.5 a 15 5v input leakage current 6,7 pull-up/down inactive ? measured @rails i inact5v ?2.5 a 16 qadc64 input current, channel off 8 pqa, pqb i off -200 -200 200 200 na electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-8 freescale semiconductor 17 2.6-v output high voltage v dd = v ddl 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) v oh 2.6 v oh 2.6a 2.3 2.1 ?v 18 5-v output high voltage v dd = v ddh (ioh= -2ma) all 5-v only outputs except tpu. v oh 5v ddh ? 0.7 ? v 19 5-v output high voltage v dd = v ddh (ioh= -5ma) for tpu pins only v oh tp5 v ddh ? 0.65 ? v 20 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) 5-v output high voltage (ioh = -2ma) v oh 2.6m v oh 2.6ma v oh 5m 2.3 2.1 v ddh ? 0.7 ?v 21 2.6-v output low voltage v dd = v ddl (iol = 3.2ma) v ol 2.6 ? 0.5 v 22 5-v output low voltage v dd = v ddh (iol = 2ma) all 5-v only outputs except tpu v ol 5 ? 0.45 v 23 5-v output low voltage v dd = v ddh -tpu pins only iol = 2ma iol = 10ma v ol tp5 ? 0.45 1.0 v 24 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output low voltage (iol = 3.2ma) 5-v output low voltage (iol = 2ma) v ol 2.6m v ol 5m 0.5 0.45 v 25 output low current (@ v ol 2.6= 0.4 v) iol2.6 2.0 ? ma 27 clkout load capacitance ? sccr com & cqds com[0:1]= 0b01, cqds = 0b1 com[0:1]= 0b01 cqds = 0b0 com[0:1]= 0b00 cqds = 0bx c clk ? 25 50 90 pf pf pf 29 capacitance for input, output, and bidirectional pins: vin = 0 v, f = 1 mhz (except qadc) c in ?7pf 30 load capacitance for bus pins only 9 com[0:1] of sccr = 0b11 com[0:1] of sccr = 0b10 cl ? 25 50 pf 31 total input capacitance pqa not sampling pqb not sampling c in ? ? 15 15 pf 32 hysteresis (only irq, tpu, mios, gpio, qadc (digital inputs) and hreset, sreset, poreset) 10 vh 0.5 ? v 33 operating current (2.6-v supplies) @ 40 mhz 11,12 v dd /q vddl /n vddl i ddl ? 120 kapwr (crystal frequency: 20 mhz) i ddkap ?5 kapwr (crystal frequency: 4 mhz) i ddkap ?2 iramstby i ddsram 50 x 10 -3 1.75 13 v ddsyn i ddsyn ?2ma v ddf (read, program, or erase) 14 i ddf ?35 v ddfstop 16 i ddfstop ?10 v ddfdisabled 16 i ddfdisb ? 100 a table f-4. dc electrical characteristics (continued) characteristic symbol min max unit electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-9 34 operating current (5-v supplies)@ 40 mhz 12 v ddh v dda 15 v flashf5 (program or erase) v flashf5read v flashf5 (stopped) i ddh5 i dda i ddf5 i ddf5r si ddf5 ? 20 5 10 16 3 1 ma v flashf5 (disabled) si ddf5d ? 100 a 35 operating current (2.6-v supplies)@ 56 mhz 12 v dd /q vddl /n vddl i ddl ? 210 kapwr (crystal frequency: 20 mhz) i ddkap ?5 kapwr (crystal frequency: 4 mhz) i ddkap ?2 iramstby i ddsram 50 x 10 -3 1.75 13 v ddsyn (crystal frequency: 20 mhz) i ddsyn ?2ma v ddf (read, program, or erase) 16 i ddf ?35 v ddfstop i ddfstop ?10 v ddfdisabled i ddfdisb ? 100 a 36 operating current (5-v supplies)@ 56 mhz 12, 15 v ddh v dda 15 v flashf5 (program or erase) v flashf5read v flashf5 (stopped) v flashf5 (disabled) i ddh5 i dda i ddf5 i ddf5r si ddf5 si ddf5d ? 20 5.0 10 16 4 1 100 ma ma ma ma ma a 37 qadc64 low power stop mode (v dda )i dda ?10 a 38 low power current (qv ddl + nv ddi + v dd ) @56 mhz doze, active pll and active clocks sleep, active pll with clocks off deep sleep, pll and clocks off i dddz i ddslp i dddpslp ? 110 15 8 ma ma ma 39 nv ddl , qv ddl ,v dd , v ddf 16 operating voltage nv ddl , qv ddl , v dd , v ddf 2.5 2.7 v 40 v flash flash operating/programming voltage 16 v flash 4.75 5.25 v 41 oscillator, keep-alive registers operating voltage 17,18 kapwr v dd - 0.2 v v dd + 0.2 v 19 v 42 n.a. ? ? ? ? 43 v ddh operating voltage v ddh 4.75 5.25 v 44 qadc operating voltage v dda 4.75 5.25 v 45 clock synthesizer operating voltage difference 18 v ddsyn v dd ? 0.2 v v dd + 0.2 v 19 v 46 n.a. ? ? ? ? 47 v ss differential voltage v ss ? v ssa -100 100 mv 48 qadc64 reference voltage low 20 v rl v ssa v ssa + 0.1 v 49 qadc64 reference voltage high 20 v rh 3.0 v dda v 50 qadc64 v ref differential voltage v rh ? v rl 3.0 5.25 v 51 qadc64 reference supply current, dc qadc64 reference supply current, transient i ref i reft ? ? 500 4.0 a ma 52 qadc64 alt reference voltage 21 v arh 1.0 .75 * v dda v table f-4. dc electrical characteristics (continued) characteristic symbol min max unit electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-10 freescale semiconductor 53 standby supply current kapwr only (4 mhz crystal) kapwr only (20 mhz crystal) measured @ 2.7 v isb kapwr4 isb kapwr20 ? 2.0 5 m m 53a iramstby regulator current data retention 17 specified v dd applied (v dd , v ddh = v ss ) i stby 50 x 10 -3 1.75 ma 53b iramstby regulator voltage for data retention 17, 22 (power-down mode) specified v dd applied (v dd , v ddh = v ss ) 21 v stby 1.35 1.95 v 54 dc injection current per pin gpio, tpu, mios, qsmcm, epee and 5 v pins 6, 23, 24 i ic5 -1.0 1.0 ma 55 dc injection current per pin 2.6 v 6, 24, 25, 26 i ic26 -1.0 1.0 ma 56 qadc64 disruptive input current 24,27 i na - 3 3 ma 57 power dissipation ? 56 mhz 40 mhz pd 1.12 0.8 w w 1 this characteristic is for 2.6-v output and 5-v input friendly pins. 2 vdatapc is the maximum voltage the data pins can have been precharged to by an external device when the mpc561/mpc563 data pins turn on as outpu ts. the 3.1-v maximum for vdatapc is to allow the data pins to be driven from an external memory running at a higher voltage. note that if the data pins are precharged to higher than v ddl , then the 50-pf maximum load characteristic must be observed. 3 the predischarge circuit is enabled by setting the predis_en bit to a ?1? in the pdmcr2 register. vdatapc is the maximum voltage the data pins can have been precharged to by an external device when the mpc561/mpc563 data pins turn on as outputs. the 5.25-v maximum for vdatapc is to allow the data pins to be driven from an external memory running at a higher voltage. note that if the data pins are precharged to higher than v ddl , then the maximum load characteristic must match the data bus drive setting an d the data bus can withstand up to 3.6 volts for a cumulative time of 24 hours over the lifetime of the device. 4 this characteristic is for 5-v output and 5-v input pins. 5 0.3v > v dda or v ddh , whichever is greater. 6 within this range, no significant injection will be seen. see qadc64 disruptive input current (i na ). 7 during reset all 2.6v and 2.6v/5v pads will leak up to 10 a to qvddl if the pad has a voltage > qvddl. 8 maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 8 to 12 c, in the ambient temperature range of 50 to 125 c. 9 all bus pins support two drive strengths capabilities , 25 pf and 50 pf. current drive is less at the 25-pf capacitive load. both modes achieve 40-mhz (or, optionally, 56-mhz) timing. 10 only irq, tpu, mios, gpio, qadc (when digital inputs) and r eset pins have hysteresis, thus there is no hysteresis specification on all other pins 11 values to be characterized. current consumption values will be updated as information becomes available. initial values are only estimates based on predicted capacitive di fferences between cdr1 and cdr3 as well as actual cdr1 measurements. 12 all power consumption specifications assume 50-pf loads and running a typi cal application. the power consumption of some modules could go up if they are exercised hea vier, but the power consumption of other modules would decrease. 13 this value depends on the r value set by the user. refer to appendix c, ?clock and board guidelines .? 14 these power supplies are available on the mpc563 and mpc564 only. 15 current measured at maximum system clock frequency with qadc active. 16 transient currents can reach 50ma. 17 kapwr and iramstby can be powered-up prior to any other supply or at the same time as the other 2.6 v supplies. iramstby must lead or coincide with vdd; however it can lag kapwr. table f-4. dc electrical characteristics (continued) characteristic symbol min max unit electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-11 f.6 oscillator and pll electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) 18 this parameter is periodically sampled rather than 100% tested 19 up to 0.5 v during power up/down. 20 to obtain full-range results, v ssa v rl v indc v rh v dda 21 when using the qadc in legacy mode it is recommended to connect this pin to 2.6v or 3.3v, however it can be connected to 0v or 5v without damage to the device. 22 a resistor must be placed in series with the iramstby power supply. refer to appendix c, ?clock and board guidelines .? 23 all injection current is transferred to the v ddh . an external load is required to dissipate this current to maintain the power supply within the specified voltage range. 24 absolute maximum voltage ratings for each pin (see ta b l e f - 1 ) must also be met during this condition. 25 total injection current for all i/o pins on the chip must not exceed 20 ma (sustained current). exceeding this limit can cause disruption of normal operation. 26 current refers to two qadc64 modules operating simultaneously. 27 below disruptive current conditions, the channel being st ressed has conversion values of 0x3ff for analog inputs greater than v rh and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions. table f-5. oscillator and pll characteristic symbol min typica l max unit 1 oscillator startup time (for ty pical crystal capacitive load) 4-mhz crystal 20-mhz crystal oscstart4 oscstart20 10 10 ms ms 2 pll lock time t lock 1000 1 1 assumes stable power and oscillator. input clocks 3 pll operating range 2 2 f vcoout is 2x the system frequency. f vcoout 30 112 mhz 4 crystal operating range, modck=0b010,0b110 modck[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111 f crystal 3 15 5 25 mhz mhz 5pll jitter pll jitter (averaged over 10 s) f jit f jit10 -1% -0.3% +1% +0.3% ? 6 limp mode clock out frequency ? 3 3 3 estimated value, real values to be characterized and updated. 11 17 3 mhz 7 oscillator bias current (xtal) 4 mhz 20 mhz i bias ? | 1.5 | | 0.8 | | 4.0 | ma ma 8 oscillator drive (xtal) i osc 7?ma 9 oscillator bias resistor r osc 0.5 1 3 m ? electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-12 freescale semiconductor f.7 flash electrical characteristics the characteristics found in this section apply only to the mpc563. note: (v ddf = 2.6 v 0.1 v, v flash = 5.0 v 0.25 v, t a = t l to t h , t b = t l to t h ) note: (v ddf = 2.6 v 0.1 v, v flash = 5.0 v 0.25 v, t a = t l to t h , t b = t l to t h ) table f-6. array program and erase characteristics symbol meaning value units minimum typical 1 1 typical program and erase times assume nominal supply values and 25 c. maximum t erase block erase time 2 2 erase time specification does not include pre-programming operation 312s t erasem module erase time 2 13 60 s t prog word programming time 3,4 3 word size is 32 bits. 4 the maximum hardware programming time of the entire flash (not including the shadow row) is 20 s x (512 kbytes / 4 bytes per word), or 131,072 words, (no software overhead). 15 20 s table f-7. censor cell program and erase characteristics symbol meaning value units minimum typical 1 1 typical set and clear times assume nominal supply values and 25 c. maximum t clear censor bit clear time 2 2 clear time specification does not include pre-set operation. 13 60 s t set censor bit set time 115 250 s table f-8. flash module life symbol meaning value array p/e cycles 1 1 a program/erase cycle is defined as switching the bits from 1 to 0 to 1. maximum number of program/erase cycles per block to guarantee data retention. 1,000 censor set/clear cycles 2 2 a censor set/clear cycle is defined as switching the bits from 1 to 0 to 1. minimum number of program/eras e cycles per bit before failure. 100 array and censor data retention minimum data retention at an average of 85 c junction temperature. minimum data retention at an average of 125 c junction temperature. min 15 years 3 min 10 years 3 3 maximum total time @ 150 c junction temperature 1 year. electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-13 f.8 power-up/down sequencing the supply symbols used in this section are described in table f-9 . . there are two power-up/down options. choosing which one is required for an application will depend upon circuitry connected to 2.6-v compliant pins and dual 2.6-v/5-v compliant pins. power-up/down option a is required if 2.6-v compli ant pins and dual 2.6-v/5- v compliant pins are connected to the 5-v supply with a pull-up resistor or dr iven by 5-v logic during power-up/down. in applications for which this scenario is not true the power-up/do wn option b may be implemented. opti on b is less stri ngent and easier to ensure over a vari ety of applications. refer to table 2-1 for a list of 2.6 v and dua l 2.6v/5 v compliant pins. the power consumption during power-up/down seque ncing will stay below the operating power consumption specifications when following these guidelines. note: the v ddh ramp voltage should be kept below 50v/ms and the v ddl ramp rate less that 25v/ms. f.8.1 power-up/down option a the option a power-up sequence (excluding v ddka ) is 1. v ddh v ddl + 3.1 v (v ddh cannot lead v ddl by more than 3.1 v) 2. v ddh v ddl - 0.5 v (v ddh cannot lag v ddl by more than 0.5 v) the first step in the sequence is required is due to ga te-to-drain stress limits for transistors in the pads of 2.6-v compliant pins and dual 2.6-v/5-v compliant pi ns. damage can occur if gate-to-drain voltage potential is greater than 3.1 v. th is is only a concern at power-up/down. the second step in the sequence table f-9. power supply pin groups symbol types of power pins v ddh (high voltage supply group) supply to the 5-v pads for output driver (v ddh ) supply to the analog (qadc64e) circuitry (v dda ) high voltage supply to the flash module (v flash ) 1 1 these power supplies are only available on the mpc563 and mpc564. v ddl (low voltage supply pins) supply to low voltage pad drivers (qvddl, nvddl) supply to all low voltage internal logic (v dd ) supply to low voltage flash circuitry (v ddf ) 1 supply to system pll v ddka (low voltage keep-alive supply pins 2 2 any supply in the v ddka group can be powered with the v ddl if the function which it supplies is not required during ?keep-alive.? supply to iramstby supply to oscillator and other circuitry for keep- alive functions (kapwr). electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-14 freescale semiconductor is required is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins. the diodes are forward biased when v ddl is greater than v ddh and will start to conduct current. figure f-1 illustrates the power-up sequence if no keep-alive supply is required. figure f-2 illustrates the power-up sequence if a keep-alive s upply is required. the keep-alive supply should be powered-up at the same instant or before both the high volta ge and low voltage supplies are powered-up. figure f-1. option a power-up sequence without keep-alive supply figure f-2. option a power-up sequence with keep-alive supply the option a power-down sequence (excluding v ddka ) is 1. v ddh v ddl + 3.1 v (v ddh cannot lag v ddl by more than 3.1 v) 2. v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v) figure f-3 illustrates the power-down sequence if no keep-alive supply is required. v ddh v ddl v ddh cannot lead v ddl by more than 3.1 v 3.1-v lead v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag v ddh v ddl 3.1-v lead 0.5-v lag v ddka v ddh cannot lead v ddl by more than 3.1 v v ddh cannot lag v ddl by more than 0.5 v electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-15 figure f-3. option a power-down sequence without keep-alive supply figure f-4 illustrates the power-down sequence if a keep-alive supply is required. figure f-4. option a power-down sequence with keep-alive supply f.8.2 power-up/down option b a less stringent power-up sequence may be implem ented if 2.6-v compliant pins and dual 2.6-v/5-v compliant pins are not connected to the 5-v supply with a pull-up resistor or driv en by 5-v logic during power-up/down. v ddh v ddl 3.1-v max ramp down rates may differ with load, so care should be taken maintain v ddh with respect to v ddl . v ddh cannot lag v ddl by more than 3.1 v. v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v.) 0.5-v max v ddh v ddl v ddh cannot lag v ddl by more than 3.1 v. 3.1-v max 0.5-v max v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v.) v ddka ramp down rates may differ with load. electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-16 freescale semiconductor the option b power-up sequence (excluding v ddka ) is: 1. v ddh > v ddl - 0.5 v (v ddh cannot lag v ddl by more than 0.5 v) thus the v ddh supply group can be fully powered -up prior to power-up of the v ddl supply group, with no adverse affects to the device. the requirement that v ddh cannot lag v ddl by more than 0.5 v is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins . the diodes are forward biased when v ddl is greater than v ddh and will start to conduct current. figure f-5 illustrates the power-up sequence if no keep-alive supply is required. figure f-6 illustrates the power-up sequence if a keep-alive s upply is required. the keep-alive supply should be powered-up at the same time or before both the high voltage and low voltage supplies are powered-up. figure f-5. option b power-up sequence without keep-alive supply figure f-6. option b power-up sequence with keep-alive supply the option b power-down sequence (excluding v ddka ) is: 1. the v ddl supply group can be fully powered- down prior to power-down of the v ddh supply group, with no adverse af fects to the device. v ddh v ddl v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag v ddh v ddl v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag v ddka electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-17 for power-down, the low voltage suppl y should come down before the hi gh voltage supply, although with varying loads, the high voltage may actually get ahead. figure f-7 illustrates the power-dow n sequence if no keep-alive supply is required. figure f-8 illustrates the power-down sequence if a keep-alive supply is required. figure f-7. option b power-down sequence without keep-alive supply figure f-8. option b power-down sequence with keep-alive supply f.9 issues regarding power sequence f.9.1 application of poreset or hreset when v ddh is rising and v ddl is at 0.0 v, as v ddh reaches 1.6 v, all 5 v drivers are tristated. before v ddh reaches 1.6v, all 5 v outputs are unknown. if v ddl is rising and v ddh is at least 3.1v greater than v ddl , then the 5 v drivers can come out of tristate when v ddl reaches 1.1v, and the 2.6 v drivers can start driving when v ddl reaches 0.5 v. for these reasons, the poreset or hreset signal must be asserted during power-up before v ddl is above 0.5 v. v ddh v ddl ramp down rates may differ with load. 0.5-v lag v ddh cannot lead v ddl by more than 0.5v v ddh 5.25v v ddh v ddl ramp down rates may differ with load. 0.5-v lag v ddh cannot lead v ddl by more than 0.5v v ddkap electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-18 freescale semiconductor if the poreset or hreset signal is not asserted before this condi tion, there is a possi bility of disturbing the programmed state of the flash. in addition, the state of the pads are indeterminant until poreset or hreset propagates through the device to initialize all circuitry. f.9.2 keep-alive ram poreset or hreset must be asserted during power-down prior to any suppl y dropping out of specified operating conditions. an additional constraint is placed on poreset assertion since it is an asynchronous input. to assure that the assertion of poreset does not potentially cause stores to keep-alive ram to be corrupted (store single or store multiple) or non-c oherent (store multiple), either of the following solutions is recommended: ? assert hreset at least 0.5 s prior to when poreset is asserted. ? assert irq 0 (non-maskable interrupt) at least 0.5 s prior to when poreset is asserted. the service routine for irq 0 should not perform any wr ites to keep-alive ram. the amount of delay that should be added to poreset assertion is dependent upon the frequency of operation and the maximum number of store multiples ex ecuted that are required to be coherent. if store multiples of more than 28 registers are needed and if the frequency of operation is lower that 56 mhz, the delay added to poreset assertion will need to be greater than 0.5 s. in addition, if kapwr features are being used, poreset should not be driven low while the v ddh and v ddl supplies are off. f.10 ac timing figure f-9 displays generic examples of mpc561/mpc 563 timing. specific timing diagrams are shown in figure f-10 through figure f-36 . electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-19 figure f-9. generic timing examples clkout 5-v outputs 5-v inputs 5-v inputs v ol v oh v ih v il v il v ih v ih v il v il v ih a b cd cd a. maximum output delay specification b. minimum output hold time c. minimum input setup time specification d. minimum input hold time specification 5-v outputs a b addr/data/ctrl v dd /2 a b a b addr/data/ctrl outputs v dd /2 addr/data/ctrl c d cd v ol v oh v ol v oh v ol v oh v dd /2 v dd /2 v dd /2 addr/data/ctrl inputs v dd v dd /2 v dd /2 v dd /2 v dd /2 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-20 freescale semiconductor table f-10. bus operation timing note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max 1 clkout period (tc) 25 17.86 ns 1a engclk frequency 5 v ? eeclk = 01 2. 6 v ? eeclk = 00 10 20 10 28 mhz 2 clock pulse width low 12.5 ?2% 12.5 + 2% 8.93 ?2% 8.93 + 2% ns 3 clock pulse width high 12.5 ? 2% 12.5 + 2% 8.93 ? 2% 8.93 + 2% ns 4 clkout rise time abus/dbus rise time 3.5 3.0 3.5 3.0 ns 5 clkout fall time abus/dbus fall time 3.5 3.0 3.5 3.0 ns 6 circuit parameter 7 5 ns 7 clkout to signal invalid (hold time) addr[8:31] rd/wr burst d[0:31] 3.5 3.5 ns 7a clkout to signal invalid: (hold time) tsiz[0:1] rsv at[0:3] bdip ptr retry 3.5 3.5 ns 7b clkout to signal invalid (hold time) 2 br bg frz vfls[0:1] vf[0:2] iwp(0:2] lwp[0:1] sts 3 3.5 3.5 ns 7c slave mode clkout to signal invalid d[0:31] 3.5 3.5 ns electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-21 8 clkout to signal valid addr[8:31] rd/wr burst d[0:31] 4 6.25 14 4.5 11 ns 8a clkout to signal valid tsiz[0:1] rsv at[0:3] bdip ptr retry 6.25 13 4.5 9.5 ns 8b clkout to signal valid 2 br bg vfls[0:1] vf[0:2] iwp[0:2] frz lwp[0:1] sts valid. 6.25 14 4.5 10.5 ns 8c slave mode clkout to signal valid d[0:31] 14 11 ns 8d clkout to data pre-discharge time 16 16 ns 8e clkout to data pre-discharge start 33ns 9 clkout to high z addr[8:31] rd/wr burst d[0:31] tsiz[0:1] rsv at[0:3] ptr retry 6.25 13 4.5 9.5 ns 10 clkout to ts , bb assertion 7.25 14 5.5 10.5 ns 10a clkout to ta , bi assertion (when driven by the memory controller) 8.5 8.5 ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-22 freescale semiconductor 10b clkout to retry assertion (when driven by the memory controller) 10 10 ns 11 clkout to ts , bb negation 7.25 14 5.5 10.5 ns 11a clkout to ta , bi negation (when driven by the memory controller) 211211ns 11b clkout to retry negation (when driven by the memory controller) 211211ns 12 clkout to ts , bb high z 6.25 20 4.5 16 ns 12a clkout to ta , bi high z (when driven by the memory controller) 15 15 ns 13 clkout to tea assertion 8.5 8.5 ns 14 clkout to tea high z 15 15 ns 15 input valid to clkout (setup time) ta tea bi 3 12 8.5 ns 15a input valid to clkout (setup time) kr cr retry 10 7.25 ns 15b input valid to clkout (setup time) bb bg br 2 86.5ns 16 clkout to signal invalid (hold time) ta tea bi bb bg br 2, 3 22ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-23 16a clkout to signal invalid (hold time) retry kr cr 22ns 17 signal valid to clkout rising edge (setup time) d[0:31] 4 66ns 17b signal valid to clkout rising edge (short setup time, sst = 1) d[0:31] 4 33 18 clkout rising edge to signal invalid (hold time) d[0:31] 4 22ns 19 clkout rising edge to cs asserted -gpcm- acs = 00 7.25 15 6.5 11.5 ns 19a clkout falling edge to cs asserted -gpcm- acs = 10, trlx = 0 or 1 86ns 19b clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0 or 1 6.25 14 5.5 10.5 ns 19c clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 6.25 17 6.69 12.69 ns 20 clkout rising edge to cs negated -gpcm- read access or write access when csnt = 0 or write access when csnt = 1 and acs = 00 1817ns 21 addr[8:31] to cs asserted -gpcm- acs = 10, trlx = 0 0.75 1 ns 21a addr[8:31] to cs asserted -gpcm- acs = 11, trlx = 0 86ns 22 clkout rising edge to oe ,we [0:3]/be [0:3] asserted 1816ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-24 freescale semiconductor 23 clkout rising edge to oe n egated 1816ns 24 addr[8:31] to cs asserted -gpcm- acs = 10, trlx = 1 23 16.42 ns 24a addr[8:31] to cs asserted -gpcm- acs = 11, trlx = 1 28 20 ns 25 clkout rising edge to we [0:3]/be [0:3] negated -gpcm-write access csnt = ?0? 7.5 6 ns 25a clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1, ebdf = 0?. 6.25 14 5.5 10.5 ns 25b clkout falling edge to cs negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 6.25 14 5.5 10.5 ns 25c clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx = ?0?, csnt = ?1, ebdf = 1?. 6.25 17 5.5 12.69 ns 25d clkout falling edge to cs negated -gpcm-write access trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 6.25 17 6.25 17 ns 26 we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, csnt = ?0? 32.25ns 26a we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 0 85.71ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-25 26b cs negated to d[0:31], high z -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 32.25ns 26c cs negated to d[0:31], high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 85.71ns 26d we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 0 28 20 ns 26e cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 28 20 ns 26f we [0:3]/be [0:3] negated to d[0:31] highz -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 1 53.75ns 26g cs negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 53.75ns 26h we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 1 24 17.25 ns 26i cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 24 17.25 ns 27 cs , we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access 5 0.75 1 ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-26 freescale semiconductor 27a we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?, acs = 10,acs = =?11?, ebdf = 0 85.71ns 27b we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 0 28 20 ns 27c we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 43ns 27d we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 24 17.25 ns 28 addr[8:31], tsiz[0:1], rd/wr , burst , valid to clkout rising edge. (slave mode setup time) 96ns 28a slave mode d[0:31] valid to clkout rising edge 55ns table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-27 note the d[0:31] input timings 17 and 18 refe r to the rising edge of the clkout in which the ta input signal is asserted. figure f-10. clkout pin timing 29 ts valid to clkout rising edge (setup time) 75ns 30 clkout rising edge to ts valid (hold time). 55ns 1 56-mhz operation is available as an option. some par ts (without the 56-mhz option) will operate at a maximum frequency of 40 mhz. 2 the timing for br output is relevant when the mpc561/mpc563 is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc561/mpc563 is selected to work with internal bus arbiter. 3 the setup times required for ta , tea , and bi are relevant only when they are supplied by the external device (and not the memory controller). 4 the maximum value of spec 8 for data[0:31] pins mu st be extended by 1.1 ns if the pins have been precharged to greater than v ddl . this is the case if an external sl ave device on the bus is running at the max. value of vdatapc. this is currently specified at 3.1 v. the 1.1 ns addition to spec 8 reflects the expected timing degradation for 3.1 v. 5 the timing 27 refers to cs when acs = ?00? and to we [0:3]/be [0:3] when csnt = ?0?. table f-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 40 mhz 56 mhz 1 unit min max min max 1 3 2 4 5 clkout electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-28 freescale semiconductor figure f-11. synchronous output signals timing 8 8a 7b 9 9 7a 7 8b clkout output signals output signals output signals electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-29 figure f-12. predischarge timing 8e clkout data 8d 0v < 3.1v 5.25v 2.6v sp8e: clkout to predischarge drivers enabled sp8d: clkout to data below 3.1v ts electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-30 freescale semiconductor figure f-13. synchronous active pull-up and open drain outputs signals timing 10 12 11 10a 12a 11a 13 14 clkout ts , bb ta , bi tea electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-31 figure f-14. synchronous input signals timing 15 16 15a 16a 15b 16 clkout ta , bi tea , kr , retry , cr bb , bg , br electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-32 freescale semiconductor figure f-15. input data timing in normal case 15a 16 17 18 data[0:31] ta clkout electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-33 figure f-16. external bus read timi ng (gpcm controlled ? acs = ?00?) 8 10 19 22 11 20 23 17 18 25 clkout ts addr[8:31] csx oe we [0:3]/be [0:3] data[0:31] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-34 freescale semiconductor figure f-17. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?10?) 8 10 19a 22 11 20 23 17 18 21 clkout ts addr[8:31] csx oe data[0:31] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-35 figure f-18. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?11?) 19c 19b 8 10 22 11 20 23 17 18 21a clkout ts addr[8:31] csx oe data[0:31] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-36 freescale semiconductor figure f-19. external bus read timing (gpcm controlled ? trlx = ?1?, acs = ?10?, acs = ?11?) figure f-20. address show cycle bus timing 8 19a 11 20 23 17 18 24 24a 19b 19c 10 clkout ts addr[8:31] csx oe data[0:31] 11 10 8 9 clkout ts addr[8:31] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-37 figure f-21. address and data show cycle bus timing 8 10 11 9 8 27 data[0:31] clkout ts addr[8:31] csx we [0:3]/be [0:3] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-38 freescale semiconductor figure f-22. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?0?) 8 10 19 22 11 20 25 9 23 8 26 26b 27 data[0:31] oe we [0:3]/be [0:3] csx addr[8:31] ts clkout electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-39 figure f-23. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c d[0:31] oe we [0:3]/be [0:3] csx addr[8:31] clkout ts electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-40 freescale semiconductor figure f-24. external bus write timing (gpcm controlled ? trlx = ?1?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c clkout ts addr[8:31] csx we [0:3]/be [0:3] oe data[0:31] electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-41 figure f-25. external master read from internal registers timing 29 28 30 10a 12a 11a 13 14 9 8 10b 11b clkout ts addr[8:31], tsiz[0:1], rd/wr , burst , ta , bi tea data[0:31] retry bdip electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-42 freescale semiconductor figure f-26. external master write to internal registers timing 29 28 30 10a 12a 11a 13 14 28a 18 10b 11b clkout ts addr[8:31], tsiz[0:1], rd/wr , burst ta , bi tea , data[0:31] retry electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-43 figure f-27. interrupt detection timing for external edge sensitive lines f.10.1 debug port timing table f-11. interrupt timing note: (t a = t l to t h ) characteristic 40 mhz 56 mhz unit min max min max 33 irq x pulse width low tc tc ns 34 irq x pulse width high; between level irq tc tc ns 35 irq x edge to edge time 4 * tc 4 * tc ns table f-12. debug port timing note: (t a = t l to t h ) characteristic 40 mhz 56 mhz unit min max min max 36 dsck cycle time 50 ? 37.4 ? ns 37 dsck clock pulse width 25 ? 18.7 ? ns 38 dsck rise and fall times 0 7 0 7 ns 39 dsdi input data setup time 15 ? 15 ? ns 40 dsdi data hold time 5 ? 5 ? ns 41 dsck low to dsdo data valid 0 18 0 18 ns 42 dsck low to dsdo invalid 0 ? 0 ? ns 33 34 irq x 35 edge irq level irq electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-44 freescale semiconductor figure f-28. debug port clock input timing figure f-29. debug port timings 36 36 37 37 38 38 dsck 40 42 41 39 dsck dsdi dsdo electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-45 f.11 readi electrical characteristics the ac electrical characteristics (56 mhz) ar e described in the foll owing tables and figures figure f-30. auxiliary port data input timing diagram table f-13. readi ac electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h 50 pf load unless noted otherwise) number characteristic min max unit 1 mcko cycle time (tco) 17.9 ? ns 2 mcko duty cycle 40 60 % 3 output rise and fall times 0 3 ns 4 mcko low to mdo data valid -1.79 3.58 ns 5 mcki cycle time (tci) 35.6 ? ns 6 mcki duty cycle 40 60 % 7 input rise and fall times 0 3 ns 8 mdi, evti , msei setup time 7.12 ? ns 9 mdi hold time 3.56 ? ns 10 rsti pulse width 71.6 ? ns 11 mcko low to mseo valid -1.79 3.58 ns 12 evti pulse width 71.6 ? ns 13 evti to rsti setup (at reset only) (4.0) x tc ? ns 14 evti to rsti hold (at reset only) (4.0) x tc ? ns mcki mdi, evti ,msei input data valid 89 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-46 freescale semiconductor figure f-31. auxiliary port data output timing diagram mdo and mseo data is held valid until the next mcko low transition. when rsti is asserted, evti is used to enable or disable the au xiliary port. because mcko probably is not active at this point, the timing mu st be based on the system clock. since the system clock is not realized on the connector, its value must be known by the tool. figure f-32. enable auxiliary from rsti figure f-33. disable auxiliary from rsti mcko output data valid mdo, mseo 4 11 rsti evti 13 14 rsti evti 13 14 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-47 f.12 reset timing table f-14. reset timing note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) characteristic expression 40 mhz 56 mhz unit minmaxminmax 43 clkout to hreset high impedance 20 20 ns 44 clkout to sreset high impedance 20 20 ns 45 rstconf pulse width 17 * tc 425 302 ns 46 configuration data to hreset rising edge setup time 15 * tc + tcc 382 272 ns 47 configuration data to rstconf rising edge set up time 15 * tc + tcc 382 272 ns 48 configuration data hold time after rstconf negation 00ns 49 configuration data hold time after hreset negation 00ns 49a rstconf hold time after hreset negation 1 1 weak pull-ups and pull-downs used for reset timing will comply with the 130 a mode select current outlined in electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-48 freescale semiconductor figure f-34. reset timing ? configuration from data bus 46 48 49 45 47 49a hreset rstconf data[0:31] (in) electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-49 figure f-35. reset timing ? data bus weak drive during configuration 50 51 52 43 55a clkout hreset rstconf data[0:31] (out) (weak) electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-50 freescale semiconductor figure f-36. reset timing ? debug port configuration f.13 ieee 1149.1 electrical characteristics table f-15. jtag timing note: (t a = t l to t h ) characteristic 10 mhz 1 unit min max 56 tck cycle time 1 (jtag clock) 100 ? ns 57 tck clock pulse width measured at v dd /2 50 ? ns 58 tck rise and fall times 0 10 ns 59 tms, tdi data setup time 5 ns 60 tms, tdi data hold time 25 ns 61 tck low to tdo data valid 20 ns 62 tck low to tdo data invalid 0 ns 63 tck low to tdo high impedance 20 ns 66 tck falling edge to output valid 50 ns 67 tck falling edge to output valid out of high impedance 50 ns 68 tck falling edge to output high impedance 50 ns 69 boundary scan input valid to tck rising edge 50 ns 70 tck rising edge to boundary scan input invalid 50 ns 53 44 54 54 53 55 dsck, dsdi sreset clkout electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-51 figure f-37. jtag test clock input timing 1 jtag timing (tck) is only tested at 10 mhz. tck is the operating clock of the mpc561/mpc563 in jtag mode. 56 57 57 58 tck electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-52 freescale semiconductor figure f-38. jtag test access port timing diagram 60 62 59 61 63 tck tms, tdi tdo electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-53 figure f-39. boundary scan (jtag) timing diagram 66 67 68 69 70 output signals tck output signals output signals electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-54 freescale semiconductor f.14 qadc64e electrical characteristics table f-16. qadc64e conversion characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) num parameter symbol min max units 97 qadc clock (qclk) frequency 1 1 conversion characteristics vary with f qclk rate. reduced conversion accuracy occurs at max f qclk rate. f qclk 0.5 3.0 mhz 98 conversion cycles 2 legacy mode: qadcmcr[flip] = 0 enhanced mode: qadcmcr[flip] = 1 2 the number of conversion cycles is de pendent on the ist bit in the ccw register. cc cc 12 14 28 20 qclk cycles qclk cycles 99 conversion time f qclk = 2.0 mhz 1 legacy mode: qadcmcr[flip] = 0 min = ccw[ist] =0b00, ccw[byp] = 0 max = ccw[ist] =0b11, ccw[byp] = 1 enhanced mode: qadcmcr[flip] = 1 min = ccw[ist] =0b0 max = ccw[ist] =0b1 t conv 6.0 7.0 14 10 s s s s 100 stop mode recovery time t sr ?10 s 101 resolution 3 3 at v rh ? v rl = 5.12 v, one count = 5 mv. ?5?mv 102 absolute (total unadjusted) error 4, 5, 6, 7 f qclk = 2.0mhz 3 , 2 clock input sample time 4 accuracy tested and guaranteed at v rh ? v rl = 5.0 v 0.25 v 5 this parameter is periodically sampled rather than 100% tested. 6 absolute error includes 1/2 count (~2.5 mv) of inherent quantization error and circuit (differential, integral, and offset) error. specification assumes that adequate low-pass filt ering is present on analog input pins ? capacitive filter with 0.01 f to 0.1 f capacitor between analog input and analog ground, typical source isolation impedance of 10 k ? . 7 input signals with large slew rates or high frequency noise components cannot be converted accurately. these signals may affect the conversion accuracy of other channels. ae -2 2 counts 102a absolute (total unadjusted) error 8, 9, 10, 11 f qclk = 2.0mhz 3 , 2 clock input sample time ae alt -7.8 3.5 mv 104 dc disruptive input injection current 12, 13, 14, 15, 16 i inj 17 i inj 18 -3 19 -1 3 1 m ma 105 current coupling ratio 20 pqa pqb k? ? 8x10 -5 8x10 -5 106 incremental error d ue to injection current all channels have same 10k ? < rs <100k ? channel under test has rs=10k ? , i inj =+ 3ma e inj + 1.0 + 1.0 counts counts 107 source impedance at input 21 r s ?100 k ? 107a incremental capacitance during sampling 22 c samp ?5 pf electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-55 8 accuracy tested and guaranteed at v arh ? v rl = 1.0v to 0.75 x v dda v. see specification 52 in electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-56 freescale semiconductor f.15 qsmcm electrical characteristics table f-17. qspi timing note: (t a = t l to t h , 50 pf load on all qspi pins unless otherwise noted) num function symbol min max unit 108 operating frequency 1 master slave f op ? ? f sys /4 f sys /4 hz hz 109 cycle time master slave t qcyc 4*tc 4*tc 510 * tc 2 ? ns ns 110 enable lead time master slave t lead 2*tc 2*tc 128 * tc ? ns ns 111 enable lag time master slave t lag ? 2*tc sck/2 ? ns ns 112 clock (sck) high or low time master slave 3 t sw 2*tc? 60 2*tc? n 255 * tc ? ns ns 113 sequential transfer delay master slave (does not require deselect) t td 17*tc 13*tc 8192 * tc - ns ns 114 data setup time (inputs) master slave t su 30 20 - - ns ns 115 data hold time (inputs) master slave t hi 0 20 - - ns ns 116 slave access time t a ?tcns 117 slave miso disable time t dis ?2 * tcns 118 data valid (after sck edge) master slave t v ? ? 50 50 ns ns 119 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 120 sck, mosi, miso rise time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 200 pf, slrc1 bit of pdmcr = ?1? (fast) up to 200 pf, slrc1 bit of pdmcr = "0" (slow) t ri t ro t ro t ro ? ? ? 1 200 21 300 s ns ns ns electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-57 120a pcs[0:1] rise time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 50 pf, slrc1 bit of pdmcr = ?1? (fast) t ri t ro t ro ? ? ? 1 50 25 s ns ns 121 sck, mosi, miso fall time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 200 pf, slrc1 bit of pdmcr = ?1? (fast) up to 200 pf, slrc1 bit of pdmcr = ?0? (slow) t ri t fo t fo t fo ? ? ? ? 1 200 21 300 s ns ns ns 121a pcs[0:1] fall time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 50 pf, slrc1 bit of pdmcr = ?1? (fast) t ri t fo t fo ? ? ? 1 50 25 s ns ns 1 all ac timing is tested to the 5-v levels outlined in electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-58 freescale semiconductor figure f-40. qspi timing ? master, cpha = 0 figure f-41. qspi timing ? master, cpha = 1 data lsb in msb in msb out msb in msb out data lsb out port data pcs[0:3] output pd miso input mosi output sck cpol=0 output sck cpol=1 111 110 113 121 120 112 109 114 115 111 120 121 119 118 121 120 output msb msb msb out data lsb out port data port data data lsb in msb in 111 110 113 120 121 109 112 109 115 112 120 121 114 119 118 121 120 pcs[0:3] output miso input mosi output sck cpol=0 output sck cpol=1 output electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-59 figure f-42. qspi timing ? slave, cpha = 0 figure f-43. qspi timing ? slave, cpha = 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 data slave lsb out pd msb out msb in data lsb in pd 114 115 121 118 119 117 111 113 109 111 120 121 116 118 110 112 121 120 ss input sck cpol=0 input sck cpol=1 input miso output mosi input electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-60 freescale semiconductor f.16 gpio electrical characteristics table f-19. gpio timing note: (t a = t l to t h ) num rating symbol min max unit 122 sgpioa[8:31], sgpiod[0: 31], sgpioc[1:4, 6:7], mpio32b[0:10, 13:15], a_ pqa[0:7], a_pqb[0:7], b_pqa[0:7], b_pqb[ 0:7] rise time. input t ri - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 200 ns output (pdmcr[slrc0] = 1), 50 pf load t ro - 25 ns 122a qgpio[4:6] rise time. input t ri 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 200 ns output (pdmcr[slrc0] = 1), 200 pf load t ro - 21 ns 122b qgpio[0:3], mpio32b[ 11;12] rise time. input t ri - 1 ms output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 50 ns output (pdmcr[slrc0] = 1), 50 pf load t ro - 21 ns 122c sgpioc[0, 5] rise time. 2 input t ri - 1 s output (sccr[com] = 0b11), 25 pf load t ro - 10 ns output (sccr[com] = 0b00), 50 pf load t ro - 10 ns 123 sgpioa[8:31], sgpiod[0: 31], sgpioc[1:4, 6:7], mpio32b[0:10, 13:15], a_ pqa[0:7], a_pqb[0:7], b_pqa[0:7], b_pqb[ 0:7] fall time. input t fi - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 200 ns output (pdmcr[slrc0] = 1), 50 pf load t fo - 25 ns 123a qgpio[4:6] fall time. input t fi - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 200 ns output (pdmcr[slrc0] = 1), 200 pf load t fo - 21 ns 123b qgpio[0:3], mpio32b[11;12] fall time. input t fi - 1 ms output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 50 ns output (pdmcr[slrc0] = 1), 50 pf load t fo - 21 ns electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-61 f.17 tpu3 electrical characteristics figure f-44. tpu3 timing 123c sgpioc[0, 5] fall time. 2 input t fi - 1 s output (sccr[com] = 0b11), 25 pf load t fo - 10 ns output (sccr[com] = 0b00), 50 pf load t fo - 10 ns 1 for this 5-v output, a drive load of 200 pf is possible but with a rise/fall time of 300 ns. 2 these are 2.6 v gpio pins. table f-20. tpu3 timing note: (t a = t l to t h ) num rating symbol min max unit 124 slew rate of tpu output channel valid 1,2 (slrc0 of pdmcr = 0, 50 pf to 200 pf load ) (slrc0 of pdmcr = 1, 50 pf load ) 1 ac timing is shown with respect to 10% v dd & 90% v dd levels. 2 timing not valid for external t2clk input. t chtov 92 3 650 25 ns ns 125 clkout high to tpu output channel hold t chtoh 015ns 126 tpu input channel pulse width 3 3 t cyc is defined as the clkout period. t tipw 4?t cyc table f-19. gpio timing (continued) note: (t a = t l to t h ) tpu i/o tim clkout tpu output tpu input 125 126 124 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-62 freescale semiconductor f.18 toucan electrical characteristics f.19 ppm timing characteristics table f-21. toucan timing 1 note: (t a = t l to t h ) 1 ac timing is shown is tested to the 3-v levels outlined in electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-63 following are ppm timing diagrams. figure f-45. ppm_tclk timing figure f-46. ppm data transfer timing (spi mode) 139 rise time input output ? 2.6v ppm pads (pdmcr2[ppmv] = 0) 5v ppm pads (pdmcr2[ppmv] = 1) t hi t ro ? ? ? 1 7 15 s ns ns 140 fall time input output ? 2.6v ppm pads (pdmcr2[ppmv] = 0) 5v ppm pads (pdmcr2[ppmv] = 1) t fi t fo ? ? ? 1 7 15 s ns ns 1 all ac timing is tested to the 2.6-v levels outlined in electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-64 freescale semiconductor f.20 mios timing characteristics all mios output pins are slew rate controlled. slew rate control circui try adds 90 ns as minimum to the output timing and 650 ns as a maximum. this slew rate is from 10% v dd to 90% v dd , an additional 100 ns should be added for total 0 to v dd slew rate. figure f-47. mcpsm enable to vs_pclk pulse timing diagram f.20.1 mpwmsm timing characteristics table f-23. mcpsm timing characteristics note: after reset mcpsmscr_psl[3:0] is set to 0b0000. note: vs_pclk is the mios prescaler clock which is di stributed to all the count er (e.g., mpwmsm and mmcsm) submodules. characteristic symbol delay unit mcpsm enable to vs_pclk pulse 1 1 the mcpsm clock prescaler value (mcpsmscr_psl[3 :0]) should be written to the mcpsmscr (mcpsm status/control register) before rewriting the mcpsmscr to set the enable bit (mcpsmscr_pren). if this is not done the prescaler will start with the old value in the mc psmscr_psl[3:0] before reloading the new value into the counter. t cpsmc (mcpsmscr_psl[3:0]) -1 system clock cycles table f-24. mpwmsm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max pwmsm output resolution t pwmr ? 1 2.0 2 pwm output pulse 3 t pwmo 2.0 ? bit (pren) miob vs_pclk t cpsmc prescaler enable note 1: f sys is the internal system clock for the imb3 bus. note 2: the numbers associated with the f sys ticks refer to the imb3 internal state. note 3: vs_pclk is the mios prescaler clock which is di stributed around the mios to counter modules such as the mmcsm and mpwmsm. f sys electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-65 figure f-48. mpwmsm minimum out put pulse example timing diagram note f sys is the internal system clock for the imb3 bus. mpwmi input pin to mpwmscr_pin status set t pin 12 cpsm enable to output set 4 t pwmp (mpwmperr - mpwmpulr + 1) * (256 - mpwmscr_cp) * mcpsmscr_psl + 1 mpwmsm enable to output set (min) 5 t pwme (mpwmperr - mpwmpulr) * (256 - mpwmscr_cp) * mcpsmscr_psl + 3 + (255 - mpwmscr_cp) * mcpsmscr_psl 6 mpwmsm enable to output set (max) 5 t pwme t pwme (min) + mcpsmscr_psl - 1 6 interrupt flag to output pin reset (period start) 7 t flgp (256 - mpwmscr_cp) * mcpsmscr_psl - 1 6 1 minimum output resolution depends on mpwmsm and mcpsm prescaler settings. 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mpwmscr_cp[7:0] =0xff. 3 excluding the case where the output is always ?0?. 4 with mpwmsm enabled before enabling the mcpsm. please also see note 1 on the mcpsm timing information. 5 the exact timing from mpwmsm enable to the pin being se t depends on the timing of the register write and the mcpsm vs_pclk. 6 when mcpsmscr_psl = 0x0000, this gives a prescale va lue of 16 and it is 16 which should be used in these calculations. when mcpsmscr_psl = 0x0001, the cpsm is inactive. 7 the interrupt is set before the output pin is reset (signifying the start of a new period). table f-24. mpwmsm timing characteristics (continued) note: all delays are in syst em clock periods. characteristic symbol min max f sys mpwmo output pin min t pwmo electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-66 freescale semiconductor figure f-49. mcpsm enable to mpwmo output pin rising edge timing diagram figure f-50. mpwmsm enable to mpwmo ou tput pin rising edge timing diagram figure f-51. mpwmsm interrupt flag to mpwm o output pin falling edge timing diagram f sys bit (pren) miob vs_pclk t pwmp prescaler enable 341 mpwmo output pin bit t pwme mpwmscr enable 341 mpwmo output pin f sys t flgp mpsmo pin output a mpwmsm interrupt flag f sys electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-67 f.20.2 mmcsm timing characteristics figure f-52. mmcsm minimum input pin (e ither load or clock) timing diagram note f sys is the internal system clock for the imb3 bus. table f-25. mmcsm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max mmcsm input pin period t pper 4? mmcsm pin low time t plo 2? mmcsm pin high time t phi 2? clock pin to counter bus increment. t pccb 12 load pin to new counter bus value t plcb 12 clock pin to pinc delay t pinc 12 load pin to pinl delay t pinl 12 counter bus resolution t cbr ? 1 1 minimum output resolution depends on mmcsm and mcpsm prescaler settings. 2 2 2 maximum resolution is obtained by setting cpsm psl[3:0] =0x2 and mmcsmscr_cp[7:0] =0xff. counter bus overflow reload to interrupt flag t cbflg 1 mcpsm enable to counter bus increment. t mcmp (256 - mmcsmscr_cp) * mcpsmscr_psl + 2 mmcsm enable to counter bus increment (min) 3 3 the exact timing from mmcsm enable to the pin being se t depends on the timing of the mmcsmscr register write and the mcpsm vs_pclk. the mmcsm enable is taken to mean the mmcsmscr_cls[1:0] being written to 2?b11. t mcme 4 + mcpsmscr_psl* (255 - mmcsmscr_cp) 3 mmcsm enable to counter bus increment (max) 3 t mcme 4 + mcpsmscr_psl * (255 - mmcsmscr_cp) + (mcpsmscr_psl - 1) 3 f sys mmcsm pin t phi min t plo min t pper min electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-68 freescale semiconductor figure f-53. mmcsm clock pin to counter bus increment timing diagram figure f-54. mmcsm load pin to counter bus reload timing diagram figure f-55. mmcsm counter bus reload to interrupt flag setting timing diagram f sys mmcsm clock pin t pccb counter bus[15:0] a a+1 f sys mmcsm load pin t plcb counter bus[15:0] a b f sys mmcsm interrupt flag t cbflg counter bus[15:0] ffff 5afe fffe a mmcsmml[15:0] 5afe a electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-69 figure f-56. mmcsm prescaler clock select to counter bus increment timing diagram f.20.3 mdasm timing characteristics table f-26. mdasm timing characteristics note: all delays are in syst em clock periods. characteristics symbol min max input modes: (ipw m, ipm, ic, dis) mdasm input pin period t pper 4? mdasm pin low time t plo 2? mdasm pin high time t phi 2? input capture resolution t capr ?2 input pin to counter bus capture delay t pcap 13 1 1 if the counter bus capt ure occurs when the counter bus is changing then the capture is delayed one cycle. in situations where the counter bus is stab le when the input c apture occurs the t pcap has a maximum delay of two cycles (the one-cycle uncertainty is due to the synchronizer). input pin to interrupt flag delay t pflg 23 input pin to pin delay t pin 12 counter bus resolution t cbr ?2 2 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mdasmscr_cp[7:0] =0xff. output modes: (oc, opwm) output pulse width 3 3 maximum output resolution and pulse width depends on counter (e.g., mmcsm) and mcpsm prescaler settings. t pulw 2? compare resolution 3 t comr ?2 2 counter bus to pin change t cbp 3 counter bus to interrupt flag set. t cbflg 3 f sys mmcsmscr_cls[1:0] t mcme counter bus[15:0] a a+1 34 2 11 00 11 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-70 freescale semiconductor figure f-57. mdasm minimum input pin timing diagram note f sys is the internal system clock for the imb3 bus. figure f-58. mdasm input pin to c ounter bus capture timing diagram figure f-59. mdasm input pin to md asm interrupt flag timing diagram f sys mdai input pin t phi min t plo min t pper min f sys mdai input pin t pcap counter bus[15:0] a mdasmar[15:0] xxxx a f sys mdai input pin t pflg mdasm interrupt flag electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-71 figure f-60. mdasm minimum out put pulse width timing diagram figure f-61. counter bus to mdasm output pin change timing diagram figure f-62. counter bus to mdasm interrupt flag setting timing diagram f.21 mpiosm timing characteristics table f-27. mpiosm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max input mode mpiosm input pin period t pper ? 1 ? f sys mdao output pin t pulw min f sys mdao output pin t cbp counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe f sys mdasm interrupt flag t cbflg counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-72 freescale semiconductor figure f-63. mpiosm input pin to mpio sm_dr (data register) timing diagram note f sys is the internal system clock for the imb3 bus. mpiosm pin low time t plo ? 1 ? mpiosm pin high time t phi ? 1 ? input pin to mpiosm_dr delay t pdr 01 output mode output pulse width 2 t pulw ? 2 ? 1 the minimum input pin period, pin low and pin hi gh times depend on the rate at which the mpiosm_dr register is polled. 2 the minimum output pulse width depends on how quick ly the cpu updates the value inside the miopsm_dr register. table f-27. mpiosm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max f sys mpiosm input pins t pdr mpiosm_dr ffa5 005a ffa5 005a electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-73 f.22 pin summary table f-28. mpc561/mpc563 signal names and pin names signal name pin name ball assignment usiu addr/sgpioa[8:31] addr_sgpioa8 af9 addr_sgpioa9 af8 addr_sgpioa10 ac6 addr_sgpioa11 y4 addr_sgpioa12 y3 addr_sgpioa13 ad7 addr_sgpioa14 ae7 addr_sgpioa15 af7 addr_sgpioa16 ad8 addr_sgpioa17 ae8 addr_sgpioa18 ac7 addr_sgpioa19 ad9 addr_sgpioa20 ac8 addr_sgpioa21 ad10 addr_sgpioa22 af10 addr_sgpioa23 ac9 addr_sgpioa24 ad11 addr_sgpioa25 ad12 addr_sgpioa26 ac11 addr_sgpioa27 af11 addr_sgpioa28 ae11 addr_sgpioa29 ae12 addr_sgpioa30 ae10 addr_sgpioa31 ae9 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-74 freescale semiconductor data/sgpiod[0:31] data_sgpiod0 ad13 data_sgpiod1 ac12 data_sgpiod2 af14 data_sgpiod3 af13 data_sgpiod4 af15 data_sgpiod5 ac13 data_sgpiod6 af16 data_sgpiod7 ac14 data_sgpiod8 af17 data_sgpiod9 ac16 data_sgpiod10 af18 data_sgpiod11 ac17 data_sgpiod12 ac18 data_sgpiod13 ad18 data_sgpiod14 ac20 data_sgpiod15 ad19 data_sgpiod16 ad20 data_sgpiod17 ae20 data_sgpiod18 af20 data_sgpiod19 ae19 data_sgpiod20 af19 data_sgpiod21 ae18 data_sgpiod22 ad17 data_sgpiod23 ae17 data_sgpiod24 ad16 data_sgpiod25 ae16 data_sgpiod26 ad15 data_sgpiod27 ae15 data_sgpiod28 ad14 data_sgpiod29 ae14 data_sgpiod30 ae13 data_sgpiod31 af12 irq 0/sgpioc0/mdo4 irq0_b_sgpioc0_mdo4 p3 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-75 irq 1/rsv /sgpioc1 irq1_b_rsv_b_sgpioc1 p4 irq 2/cr /sgpioc2/mts 1 irq2_b_cr_b_sgpioc2_mts_b p2 irq 3/kr /retry /sgpioc irq3_b_kr_b_retry_b_sgpioc3 n1 irq 4/at2/sgpioc4 irq4_b_at2_sgpioc4 p1 irq 5/sgpioc5/modck1 irq5_b_sgpioc5_modck1 ad21 irq [6:7]/modck[2:3] irq6_b_modck2 ae21 irq7_b_modck3 y24 pull_sel (input only) pull_sel r26 tsiz[0:1] tsiz0 v4 tsiz1 w1 rd/wr rd_wr _b v1 burst burst y1 bdip bdip_b w4 ts ts_b w2 ta t a _ b w 3 tea tea_b v3 rstconf /texp rstconf_b_texp y25 oe oe_b v2 bi /sts bi_b_sts_b y2 cs [0:3] cs0_b u1 cs1_b u2 cs2_b u3 cs3_b u4 we[ 0:3]/be [0:3]/at[0:3] we0_b_we0_b_a0 t1 we0_b_be1_b_at1 t2 we0_b_be2_b_at2 t3 we0_b_be3_b_at3 t4 poreset /trst poreset_b_trst_b w25 hreset hreset_b w23 sreset sreset_b w24 sgpioc6/frz/ptr sgpioc6_frz_ptr_b n4 sgpioc7/irqout /lwp0 sgpioc7_irqout_b_lwp0 r1 bg /vf0/lwp1 bg_b_vf0_lwp1 r3 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-76 freescale semiconductor br /vf1/iwp2 br_b_vf1_iwp2 r4 bb /vf2/iwp3 bb_b_vf2_iwp3 r2 iwp[0:1]/vfls[0:1] iwp0_vfls0 n2 iwp1_vfls1 n3 tms/evti tms_evti_b m2 tdi/dsdi/mdi0 tdi_dsdi_mdi0 m1 tck/dsck/mcki tck_dsck_mcki l2 tdo/dsdo/mdo0 tdo_dsdo_mdo0 m4 jcomp/rsti jcomp_rsti_b l1 xtal xtal ad26 extal extal ac26 xfc xfc aa26 clkout clkout u23 extclk extclk v24 engclk/buclk engclk_buclk v26 qsmcm pcs0/ss /qgpio0 pcs0_ss_b_qgpio0 n25 pcs[1:3]/qgpio[1:3] pcs1_qgpio1 n24 pcs2_qgpio2 n23 pcs3_qgpio3 p26 miso /qgpio4 miso_b_qgpio4 p25 mosi /qgpio5 mosi_b_qgpio5 p24 sck/qgpio6 sck_qgpio6 p23 txd1/qgpo1 txd1_qgpo1 r25 txd2/qgpo2/c_cntx0 txd2_qgpo2_c_cntx0 r24 rxd1/qgpi1 rxd1_qgpi1 r23 rxd2/qgpi2/c_cnrx0 rxd2_qgpi2_c_cnrx0 t26 mios14 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-77 mda[11:15] mda11 c20 mda12 d20 mda13 a21 mda14 b21 mda15 c21 mda[27:31] mda27 d21 mda28 a22 mda29 b22 mda30 f24 mda31 f25 mpwm[0:1]/mdi[1:2] mpwm0_mdi1 f26 mpwm1_mdo2 g23 mpwm2/ppm_tx1 mpwm2_ppm_tx1 g26 mpwm3/ppm_rx1 mpwm3_ppm_rx1 g25 mpwm16 mpwm16 g24 mpwm17/mdo3 mpwm17_mdo3 h23 mpwm[18:19]/mdo[6:7] mpwm18_mdo6 h24 mpwm19_mdo7 h25 vf0/mpio32b0/mdo1 vf0_mpio32b0_mdo1 l23 vf1/mpio32b1/mcko vf1_mpio32b1_mcko l24 vf2/mpio32b2/msei vf2_mpio32b2_msei_b m24 vfls0/mpio32b3/mseo vfls0_mpio32b3_mseo_b m25 vfls1/mpio32b4 vfls1_mpio32b4 m26 mpio32b5/mdo5 mpio32b5_mdo5 h26 mpio32b6/mpwm4/mdo6 mpio32b6_mpwm4_mdo6 j23 mpio32b7/mpwm5 mpio32b7_mpwm5 j24 mpio32b[8:9]/mpwm[20:21] mpio32b8_mpwm20 j25 mpio32b9_mpwm21 j26 mpio32b10/ppm_tsync mpio32b10_ppm_tsync k25 mpio32b11/c_cnrx0 mpio32b11_c_cnrx0 k24 mpio32b12/c_cntx0 mpio32b12_c_cntx0 k23 mpio32b13/ppm_tclk mpio32b13_ppm_tclk k26 mpio32b14/ppm_rx0 mpio32b14_ppm_rx0 l26 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-78 freescale semiconductor mpio32b15/ppm_tx0 mpio32b15_ppm_tx0 l25 tpu_a/tpu_b a_tpuch[0:15] a_tpuch0 f3 a_tpuch1 c5 a_tpuch2 b5 a_tpuch3 a5 a_tpuch4 c6 a_tpuch5 d6 a_tpuch6 b6 a_tpuch7 a6 a_tpuch8 c7 a_tpuch9 d7 a_tpuch10 b7 a_tpuch11 a7 a_tpuch12 c8 a_tpuch13 d8 a_tpuch14 b8 a_tpuch15 a8 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-79 b_tpuch[0:15] b_tpuch0 k1 b_tpuch1 k2 b_tpuch2 k3 b_tpuch3 k4 b_tpuch4 j1 b_tpuch5 j2 b_tpuch6 j3 b_tpuch7 j4 b_tpuch8 h1 b_tpuch9 h2 b_tpuch10 h3 b_tpuch11 h4 b_tpuch12 g1 b_tpuch13 g2 b_tpuch14 g3 b_tpuch15 g4 a_t2clk/pcs5 a_ t2clk_pcs5 f2 b_t2clk/pcs4 b_ t2clk_pcs4 f1 qadc64e_a/qadc64e_b etrig[1:2]/pcs[6:7] etrig1_pcs6 b20 etrig2_pcs7 a20 a_an0/anw/pqb0 a_an0_anw_pqb0 c11 a_an1/anx/pqb1 a_an1_anx_pqb1 d11 a_an2/any/pqb2 a_an2_any_pqb2 b11 a_an3/anz/pqb3 a_an3_anz_pqb3 a11 a_an[48:51]/pqb[4:7] a_an48_pqb4 c12 a_an49_pqb5 d12 a_an50_pqb6 b12 a_an51_pqb7 a12 a_an[52:54]/ma[0:2]/pqa [0:2] a_an52_ma0_pqa0 c13 a_an53_ma1_pqa1 d13 a_an54_ma2_pqa2 b13 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-80 freescale semiconductor a_an[55:59]/pqa[3:7] a_an55_pqa3 a13 a_an56_pqa4 a14 a_an57_pqa5 d14 a_an58_pqa6 b14 a_an59_pqa7 c14 b_an0/anw/pqb0 b_an0_anw_pqb0 a15 b_an1/anx/pqb1 b_an1_anx_pqb1 b15 b_an2/any/pqb2 b_an2_any_pqb2 c15 b_an3/anz/pqb3 b_an3_anz_pqb3 d15 b_an[48:51]/pqb[4:7] b_an48_pqb4 a16 b_an49_pqb5 b16 b_an50_pqb6 c16 b_an51_pqb7 d16 b_an[52:54]/ma[0:2]/pqa [0:2] b_an52_ma0_pqa0 a17 b_an53_ma1_pqa1 b17 b_an54_ma2_pqa2 c17 b_an[55:59]/pqa[3:7] b_an55_pqa3 d17 b_an56_pqa4 a18 b_an57_pqa5 b18 b_an58_pqa6 c18 b_an59_pqa7 d18 toucan_a/toucan_b/toucan_c a_cntx0 a_cntx0 m23 b_cntx0 b_cntx0 l4 a_cnrx0 a_cnrx0 n26 b_cnrx0 b_cnrx0 l3 uc3f b0epee 2 boepee t24 epee 2 epee t23 vflash 2 vflash u26 vddf 2 vddf u25 vssf 2 vssf u24 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-81 global power supplies nvddl nvddl ac10 ac15 ac19 ac4 ad3 ae2 af1 c9 d9 y23 vdd vdd a1 a25 ac22 ad23 ae24 af25 b2 b24 c23 c3 d22 d4 v23 vddh vddh af21 af5 c19 c22 d19 e1 f23 t25 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-82 freescale semiconductor vss vss a19, a2, a23, a24, a26, a3, a4, aa1, aa2, aa23, aa24, aa25, aa3 , ab1, ab2, ab24, ab25, ab4, ac1, ac21, ac23, ac25, ac3, ac5, ad2, ad22, ad24, ad4, ad5, ae1, ae22, ae23, ae25, ae3, ae4, ae5, af2, af22, af23, af24, af26 , af3, af4, af6, b1, b19, b23, b25, b3, b4 , c1, c2, c24, c26, c4, d1, d2, d23, d25, d26, d3, d5, e2, e24, e25, e26, e3, e4, l11, l12, l13, l14, l15, l16, m11, m1 2, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, v25 kapwr kapwr w26 iramstby iramstby m3 qvddl qvddl aa4 ab23 ab3 ac2 ac24 ad1 ad25 ad6 ae26 ae6 b26 c25 d24 e23 f4 usiu power supplies vddsyn vddsyn y26 vsssyn vsssyn ab26 qadc64e power supplies vrh vrh c10 vrl vrl a10 table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-83 f.22.1 package diagrams the package for the mpc561/mpc563 is the 388 pbga (27 x 27 mm, 1.0 mm ball pitch). this package has 352 balls in the perimeter rows and 36 ground balls in the center isla nd for a total of 388 balls. the case outline drawing is 1164-01, as shown in figure f-64 . altref altref b10 vdda vdda d10 vssa vssa a9 b9 1 this pin also included the mdo5 function on the k27s mask set off the mpc561. 2 mpc563 only, no connection on mpc561. table f-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-84 freescale semiconductor 1 note: top down view figure f-64. mpc561/mpc563 package footprint (1 of 2) electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-85 figure f-65. mpc561/mpc563 package footprint (2 of 2) electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-86 freescale semiconductor f.22.1.1 mpc561/mpc563 ball map the ball diagram of the mpc561/mpc563 is shown in figure f-66 . figure f-66. mpc561/mpc563 ball map 1 2 3 4 5 6 7 8 9 10 11121314 15 16 17 18 19 20 21 22 23 24 25 26 a vdd vss vss vss a_tpuch3 a_tpuch7 a_tpuch 11 a_tpuch15 vssa vrl a_an3_a nz_pqb3 a_an51_p qb7 a_an55_ pqa3 a_an56_p qa4 b_an0_an w_pqb0 b_an48_ pqb4 b_an52_m a0_pqa0 b_an56_p qa4 vss etrig2_ pcs7 mda13 mda28 vss vss vdd vss a b vss vdd vss vss a_tpuch2 a_tpuch6 a_tpuch 10 a_tpuch14 vssa altref a_an2_a ny_pqb2 a_an50_p qb6 a_an54_ ma2_pq a2 a_an58_p qa6 b_an1_an x_pqb1 b_an49_ pqb5 b_an53_m a1_pqa1 b_an57_p qa5 vss etrig1_ pcs6 mda14 mda29 vss vdd vss qvddl b c vss vss vdd vss a_tpuch1 a_tpuch4 a_tpuch 8 a_tpuch12 nvddl vrh a_an0_a nw_pqb 0 a_an48_p qb4 a_an52_ ma0_pq a0 a_an59_p qa7 b_an2_an y_pqb2 b_an50_ pqb6 b_an54_m a2_pqa2 b_an58_p qa6 vddh mda11 mda15 vddh vdd vss qvddl vss c d vss vss vss vdd vss a_tpuch5 a_tpuch 9 a_tpuch13 nvddl vdda a_an1_a nx_pqb1 a_an49_p qb5 a_an53_ ma1_pq a1 a_an57_p qa5 b_an3_an z_pqb3 b_an51_ pqb7 b_an55_p qa3 b_an59_p qa7 vddh mda12 mda27 vdd vss qvddl vss vss d e vddh vss vss vss qvddl vss vss vss e f b_t2clk_p cs4 a_t2clk_ pcs5 a_tpuch 0 qvddl vddh mda30 mda31 mpwm0_md i1 f g b_tpuch12 b_tpuch1 3 b_tpuch 14 b_tpuch1 5 mpwm1_md o2 mpwm16 mpwm3_pp m_rx1 mpwm2_pp m_tx1 g h b_tpuch8 b_tpuch9 b_tpuch 10 b_tpuch1 1 mpwm17_m do3 mpwm18_md o6 mpwm19_m do7 mpio32b5_ mdo5 h j b_tpuch4 b_tpuch5 b_tpuch 6 b_tpuch7 mpio32b6_ mpwm4_md o6 mpio32b7_mp wm5 mpio32b8_ mpwm20 mpio32b9_ mpwm21 j k b_tpuch0 b_tpuch1 b_tpuch 2 b_tpuch3 mpio32b12_ c_cntx0 mpio32b11_c _cnrx0 mpio32b10_ ppm_tsync mpio32b13_ ppm_tclk k l jcomp_rs ti_b tck_dsck _mcki b_cnrx0 b_cntx0 vss vss vss vss vss vss vf0_mpio32 b0_mdo1 vf1_mpio32b 1_mcko mpio32b15_ ppm_tx0 mpio32b14_ ppm_rx0 l m tdi_dsdi_ mdi0 tms_evti _b iramstby tdo_dsd o_mdo0 vss vss vss vss vss vss a_cntx0 vf2_mpio32b 2_msei_b vfls0_mpio 32b3_mseo _b vfls1_mpio 32b4 m n irq3_b_kr _b_retry _b_sgpio c3 iwp0_vfl s0 iwp1_vfl s1 sgpioc6_ frz_ptr_ b vss vss vss vss vss vss pcs2_qgpi o2 pcs1_qgpio1 pcs0_ss_b_ qgpio0 a_cnrx0 n p irq4_b_at 2_sgpioc4 irq2_b_c r_b_sgpi oc2_mdo 5_mts irq0_b_s gpioc0_ mdo4 irq1_b_r sv_b_sg pioc1 vss vss vss vss vss vss sck_qgpio 6 mosi_qgpio5 miso_qgpi o4 pcs3_qgpi o3 p r sgpioc7_i rqout_b_ lwp0 bb_b_vf2 _iwp3 bg_b_vf 0_lwp1 br_b_vf1 _iwp2 vss vss vss vss vss vss rxd1_qgpi 1 txd2_qgpo2 _c_cntx0 txd1_qgpo 1 pull-sel r t we_b_at0 we_b_at1 we_b_at 2 we_b_at 3 vss vss vss vss vss vss epee boepee vddh rxd2_qgpi 2_c_cnrx0 t u cs0_b cs1_b cs2_b cs3_b clkout vssf vddf vflash u v rd_wr_b oe_b tea_b tsiz0 vdd extclk vss engclk_bu clk v w tsiz1 ts_b ta_b bdip_b hreset_b sreset_b poreset_b _trst_b kapwr w y burst_b bi_b_sts_ b addr_sg pioa12 addr_sg pioa11 nvddl irq7_b_modc k3 rstconf_b _texp vddsyn y aa vss vss vss qvddl vss vss vss xfc aa ab vss vss qvddl vss qvddl vss vss vsssyn ab ac vss qvddl vss nvddl vss addr_sgp ioa10 addr_sg pioa18 addr_sgpi oa20 addr_sg pioa23 nvddl addr_s gpioa26 data_sg piod1 data_sg piod5 data_sg piod7 nvddl data_sg piod9 data_sgp iod11 data_sg piod12 nvddl data_s gpiod14 vss vdd vss qvddl vss extal ac ad qvddl vss nvddl vss vss qvddl addr_sg pioa13 addr_sgpi oa16 addr_sg pioa19 addr_sgp ioa21 addr_s gpioa24 addr_sg pioa25 data_sg piod0 data_sg piod28 data_sgp iod26 data_sg piod24 data_sgp iod22 data_sg piod13 data_sgpi od15 data_s gpiod16 irq5_b_s gpioc5_m odck1 vss vdd vss qvddl xtal ad ae vss nvddl vss vss vss qvddl addr_sg pioa14 addr_sgpi oa17 addr_sg pioa31 addr_sgp ioa30 addr_s gpioa28 addr_sg pioa29 data_sg piod30 data_sg piod29 data_sgp iod27 data_sg piod25 data_sgp iod23 data_sg piod21 data_sgpi od19 data_s gpiod17 irq6_b_m odck2 vss vss vdd vss qvddl ae af nvddl vss vss vss vddh vss addr_sg pioa15 addr_sgpi oa9 addr_sg pioa8 addr_sgp ioa22 addr_s gpioa27 data_sg piod31 data_sg piod3 data_sg piod2 data_sgp iod4 data_sg piod6 data_sgp iod8 data_sg piod10 data_sgpi od20 data_s gpiod18 vddh vss vss vss vdd vss af 1 2 3 4 5 6 7 8 9 10 11121314 15 16 17 18 19 20 21 22 23 24 25 26 ball map (as viewed from top, through the package and silicon) note: the flash balls are only available on the mp c563 and mpc564. these are no connects on the mpc561 and mpc562. flash supplies and inputs are lo cated on the following balls: t23, t24, u24, u25. u26. electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-87 figure f-67. mpc561/mpc563 ball map (black and white, page 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a vdd vss vss vss a_tpuch3 a_tpuch7 a_tpuch 11 a_tpuch15 vssa vrl a_an3_a nz_pqb3 a_an51_p qb7 a_an55_ pqa3 a_an56_p qa4 b vss vdd vss vss a_tpuch2 a_tpuch6 a_tpuch 10 a_tpuch14 vssa altref a_an2_a ny_pqb2 a_an50_p qb6 a_an54_ ma2_pq a2 a_an58_p qa6 c vss vss vdd vss a_tpuch1 a_tpuch4 a_tpuch 8 a_tpuch12 nvddl vrh a_an0_a nw_pqb 0 a_an48_p qb4 a_an52_ ma0_pq a0 a_an59_p qa7 d vss vss vss vdd vss a_tpuch5 a_tpuch 9 a_tpuch13 nvddl vdda a_an1_a nx_pqb1 a_an49_p qb5 a_an53_ ma1_pq a1 a_an57_p qa5 e vddh vss vss vss f b_t2clk_p cs4 a_t2clk_ pcs5 a_tpuch 0 qvddl g b_tpuch12 b_tpuch1 3 b_tpuch 14 b_tpuch1 5 h b_tpuch8 b_tpuch9 b_tpuch 10 b_tpuch1 1 j b_tpuch4 b_tpuch5 b_tpuch 6 b_tpuch7 k b_tpuch0 b_tpuch1 b_tpuch 2 b_tpuch3 l jcomp_rs ti_b tck_dsck _mcki b_cnrx0 b_cntx0 m tdi_dsdi_ mdi0 tms_evti _b iramstby tdo_dsd o_mdo0 n irq3_b_kr _b_retry iwp0_vfl iwp1_vfl sgpioc6_ frz_ptr_ vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-88 freescale semiconductor figure f-68. mpc561/mpc563 ball map (black and white, page 2) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss p irq4_b_at 2_sgpioc4 irq2_b_c r_b_sgpi oc2_mdo 5_mts irq0_b_s gpioc0_ mdo4 irq1_b_r sv_b_sg pioc1 r sgpioc7_i rqout_b_ lwp0 bb_b_vf2 _iwp3 bg_b_vf 0_lwp1 br_b_vf1 _iwp2 t we_b_at0 we_b_at1 we_b_at 2 we_b_at 3 u cs0_b cs1_b cs2_b cs3_b v rd_wr_b oe_b tea_b tsiz0 w tsiz1 ts_b ta_b bdip_b y burst_b bi_b_sts_ b addr_sg pioa12 addr_sg pioa11 aa vss vss vss qvddl ab vss vss qvddl vss ac vss qvddl vss nvddl vss addr_sgp ioa10 addr_sg pioa18 addr_sgpi oa20 addr_sg pioa23 nvddl addr_s gpioa26 data_sg piod1 data_sg piod5 ad qvddl vss nvddl vss vss qvddl addr_sg pioa13 addr_sgpi oa16 addr_sg pioa19 addr_sgp ioa21 addr_s gpioa24 addr_sg pioa25 data_sg piod0 ae vss nvddl vss vss vss qvddl addr_sg pioa14 addr_sgpi oa17 addr_sg pioa31 addr_sgp ioa30 addr_s gpioa28 addr_sg pioa29 data_sg piod30 af nvddl vss vss vss vddh vss addr_sg pioa15 addr_sgpi oa9 addr_sg pioa8 addr_sgp ioa22 addr_s gpioa27 data_sg piod31 data_sg piod3 12345678910111213 electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor f-89 figure f-69. mpc561/mpc563 ball map (black and white, page 3) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 14 15 16 17 18 19 20 21 22 23 24 25 26 a_an56_p qa4 b_an0_an w_pqb0 b_an48_ pqb4 b_an52_m a0_pqa0 b_an56_p qa4 vss etrig2_ pcs7 mda13 mda28 vss vss vdd vss a a_an58_p qa6 b_an1_an x_pqb1 b_an49_ pqb5 b_an53_m a1_pqa1 b_an57_p qa5 vss etrig1_ pcs6 mda14 mda29 vss vdd vss qvddl b a_an59_p qa7 b_an2_an y_pqb2 b_an50_ pqb6 b_an54_m a2_pqa2 b_an58_p qa6 vddh mda11 mda15 vddh vdd vss qvddl vss c a_an57_p qa5 b_an3_an z_pqb3 b_an51_ pqb7 b_an55_p qa3 b_an59_p qa7 vddh mda12 mda27 vdd vss qvddl vss vss d qvddl vss vss vss e vddh mda30 mda31 mpwm0_md i1 f mpwm1_md o2 mpwm16 mpwm3_pp m_rx1 mpwm2_pp m_tx1 g mpwm17_m do3 mpwm18_md o6 mpwm19_m do7 mpio32b5_ mdo5 h mpio32b6_ mpwm4_md o6 mpio32b7_mp wm5 mpio32b8_ mpwm20 mpio32b9_ mpwm21 j mpio32b12_ c_cntx0 mpio32b11_c _cnrx0 mpio32b10_ ppm_tsync mpio32b13_ ppm_tclk k vf0_mpio32 b0_mdo1 vf1_mpio32b 1_mcko mpio32b15_ ppm_tx0 mpio32b14_ ppm_rx0 l a_cntx0 vf2_mpio32b 2_msei_b vfls0_mpio 32b3_mseo _b vfls1_mpio 32b4 m pcs2_qgpi o2 pcs1_qgpio1 pcs0_ss_b_ qgpio0 a_cnrx0 n electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 f-90 freescale semiconductor figure f-70. mpc561/mpc563 ball map (black and white, page 4) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss sck_qgpio 6 mosi_qgpio5 miso_qgpi o4 pcs3_qgpi o3 p rxd1_qgpi 1 txd2_qgpo2 _c_cntx0 txd1_qgpo 1 pull_sel r epee 1 boepee 1 vddh rxd2_qgpi 2_c_cnrx0 t clkout vssf 1 vddf 1 vflash 1 u vdd extclk vss engclk_bu clk v hreset_b sreset_b poreset_b _trst_b kapwr w nvddl irq7_b_modc k3 rstconf_b _texp vddsyn y vss vss vss xfc aa qvddl vss vss vsssyn ab data_sg piod7 nvddl data_sg piod9 data_sgp iod11 data_sg piod12 nvddl data_s gpiod14 vss vdd vss qvddl vss extal ac data_sg piod28 data_sgp iod26 data_sg piod24 data_sgp iod22 data_sg piod13 data_sgpi od15 data_s gpiod16 irq5_b_s gpioc5_m odck1 vss vdd vss qvddl xtal ad data_sg piod29 data_sgp iod27 data_sg piod25 data_sgp iod23 data_sg piod21 data_sgpi od19 data_s gpiod17 irq6_b_m odck2 vss vss vdd vss qvddl ae data_sg piod2 data_sgp iod4 data_sg piod6 data_sgp iod8 data_sg piod10 data_sgpi od20 data_s gpiod18 vddh vss vss vss vdd vss af 14 15 16 17 18 19 20 21 22 23 24 25 26 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-1 appendix g 66-mhz electrical characteristics this appendix contains detailed information on power considerations, dc/ac elec trical characteristics, and ac timing characteristics of the mpc561/mpc563 at the optional operating frequency of 66 mhz. for information on the 40- and 56-m hz operating frequency, refer to appendix f, ?electrical characteristics .? g.1 66-mhz feature limitations the following feature limitations apply when operating the mpc561/ mpc563 at a system frequency of 66 mhz: ? internal flash programming must be performed with a system frequency of 56 mhz or less. ? data bus pre-discharge cannot be used to prevent damage due to voltages higher than 3.1 v on the data bus. ? in a dual controller application with the mpc563 as master and mpc561 as slave, revision d of mpc561 silicon must be used. ) table g-1. absolute maxi mum ratings (vss = 0v) rating symbol min. value max. value unit 1 2.6-v supply voltage 1 v ddl -0.3 3.0 2 v 2 flash supply voltage 3 , 4 v flash -0.3 5.6 v 3 flash core voltage 1, 4 v ddf -0.3 3.0 v 4 oscillator, keep-alive reg. supply voltage 1 kapwr -0.3 3.0 v 5 sram supply voltage 1,5 iramstby -0.3 3.0 v 6 clock synthesizer supply voltage 1 v ddsyn -0.3 3.0 v 7n.a. ? ? ? ? 8 qadc supply voltage 6 v dda -0.3 5.6 v 9 5-v supply voltage v ddh -0.3 5.6 v 10 dc input voltages 7,8 v in v ss -0.3 5.6 9 v 11 reference v rh , with reference to v rl v rh -0.3 5.6 v 12 reference altref, with reference to v rl v arh -0.3 5.6 v 13 v ss differential voltage v ss ? v ssa -0.1 0.1 v 15 v ref differential voltage v rh ? v rl -5.6 5.6 v 16 v rl to v ssa differential voltage v rl ? v ssa -0.3 0.3 v 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-2 freescale semiconductor functional operating conditions are given in section g.6, ?dc electrical characteristics .? absolute maximum ratings are stress ratings only, and functiona l operation at the maximum is not guaranteed. stress beyond those listed may affect device reliabilit y or cause permanent damage to the device. 17 maximum input current per pin 10, 11, 12 i ma -25 13 25 13 ma 18 qadc maximum input current per pin i max -25 13 25 13 ma 19 operating temperature range ? ambient (packaged), m temperature range. t a -40 (t l ) +125 (t h ) c 19a operating temperature range ? ambient (packaged), c temperature range. t a -40 (t l ) +85 (t h ) c 20 operating temperature range ? solder ball (packaged any perimeter solder ball) 14 t sb -40 (t l ) +135 (t h ) c 21 junction temperature range t j -40 +150 c 22 storage temperature range t stg -55 +150 c 23 maximum solder temperature 15 t sdr ? 235 c 24 moisture sensitivity level 16 msl ? 3 ? 1 for internal digital supply of v ddl = 2.6-v typical. 2 2.6 volt supply pins can withstand up to 3.6 volts for acumulative time of 24 hours over the lifetime of the device. 3 during operation the value of v flash must be 5.0 v 5% 4 these power supplies are available on mpc563 and mpc564 only. 5 maximum average current into the iramstby pin must be < 1.75ma. 6 v dda =5.0 v 5%. 7 all 2.6-v input-only pi ns are 5-v tolerant. 8 note that long term reliability may be compromised if 2. 6-v output drivers drive a node which has been previously pulled to >3.1 v by an external component. hreset and sreset are fully 5-v compatible. 9 6.35 v on 5-v only pins (all qadc, all tpu, all qsmc m and the following mios pins: mda[11:15], mda[27:31], mpwm16, mpio32b[7:9]/mpwm[20:21], mpio32b11/c_cnrx0, mpio32b12/c_cntx0 ). in ternal structures hold the input voltage below this maximum voltage on a ll of these pins, except the qsmcm rxd1/qpi1 and rxd2/qpi2/c_cnrx0 pins, if the maximum injection current spec ification is met (1 ma for all pins; exception: 3 ma on qadc pins) and vddh is within operating volt age specifications (see specification 43 in ta bl e g - 4 ). exception: the rxd1/qgpi1 and rxd2/gpi2 pins do not have clamp di odes to vddh. voltage must be limited to less than 6.5 volts on these 2 pins to prevent damage. 10 maximum continuous current on i/o pins provided the over all power dissipation is below the power dissipation of the package. proper operation is not guaranteed at this condition. 11 condition applies to one pin at a time. 12 transitions within the limit do not affe ct device reliability or cause permanent damage. exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels. 13 maximum transient current per iso7637. 14 maximum operating temperature on any solder ball in outer f our rows of solder balls on the package. these rows are referred to as ?perimeter balls? to distinguish th em from the balls in the center of the package. 15 solder profile per cdf-aec-q100, current revision. 16 moisture sensitivity per jedec te st method j-std-020-a (april 1999). table g-1. absolute maximum ra tings (vss = 0v) (continued) rating symbol min. value max. value unit 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-3 this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). note negative current flows out of the pin and positive cu rrent flows into the pin. g.2 package the mpc561/mpc563 is available in packaged form. the package is a 388-ball pbga having a 1.0 mm ball pitch, frees cale case outline 1164-01 (see figure g-63 and figure g-64 ). g.3 emi characteristics g.3.1 reference documents the document referenced for the emc testing of mpc561/mpc563 is sae j1752/3 issued 1995-03 g.3.2 definitions and acronyms emc ? electromagnetic compatibility emi ? electromagnetic interference tem cell ? transverse el ectromagnetic mode cell g.3.3 emi testing specifications 1. scan range: 150 khz ? 1000 mhz 2. operating frequency: 66 mhz 3. operating voltages: 2.6 v, 5.0 v 4. max spikes: tbd dbuv 5. i/o port wavefo rms: per j1752/3 6. temperature: 25 c g.4 thermal characteristics table g-2. thermal characteristics characteristic symbol value unit bga package thermal resistance, junction to ambient ? natural convection r ja 47.3 1,2,3 c/w bga package thermal resistance, junction to ambient ? four layer (2s2p) board, natural convection r jma 29.4 3,4 , 5 c/w 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-4 freescale semiconductor an estimation of the chip junction temperature, t j , in c can be obtained from the equation: t j = t a + (r ja x p d ) where: t a = ambient temperature (c) r ja = package junction to ambient resistance (c/w) p d = power dissipation in package the junction to ambient thermal resi stance is an industry standard va lue which provides a quick and easy estimation of thermal performance. unfortunately, the answer is only an estimate; test cases have demonstrated that errors of a factor of two are possible. as a result, mo re detailed therma l characterization is supplied. historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ja = case to ambient thermal resistance (c/w) bga package thermal resistance, junction to board r jb 21.2 3,6 c/w bga package thermal resistance, junction to case (top) r jt 7.0 3,7 c/w bga package thermal resistance, junction to package top, natural convection jt 1.6 8 c/w 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 2 per semi g38-87 and jesd51-2 with the board horizontal. 3 these values are the mean + 3 standard deviations of characterized data. 4 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 5 per jesd51-6 with the board horizontal. 6 thermal resistance between the die and the printed circui t board (four layer (2s2p) board, natural convection). 7 indicates the thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012. 1) with the cold plate temperature used for the case temperature. 8 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per eia/jesd51-2. table g-2. thermal characteristics (continued) characteristic symbol value unit 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-5 r jc is device related and canno t be influenced. th e user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the air flow can be changed around the device, add a heat sink, change the mounting ar rangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most usef ul for ceramic packages with heat sinks where about 90% of the heat flow is through the case to the heat sink to ambient. for most packages, a better model is required. the simplest thermal model of a pa ckage which has demonstrated reas onable accuracy (about 20 percent) is a two resistor model consisting of a junction to board and a junction to case thermal resistance. the junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. the junction to board therma l resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it ha s been observed that the thermal performance of most plasti c packages and especially pbga p ackages is strongly dependent on the board. temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb x p d ) where: t b = board temperature (c) r jb = package junction to board resistance (c/w) p d = power dissipation in package ( ? ) if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction te mperature can be made. for this me thod to work, the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias at taching the thermal balls to the ground plane. when the board temperature is not known, a thermal si mulation of the application is needed. the simple two-resistor model can be us ed with the thermal simulation of the a pplication (2), or a more accurate and complex model of the pack age can be used in the thermal simula tion. consultation on the creation of the complex model is available. to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t t = thermocouple temperature on top of package (c) jt = thermal characterization parameter p d = power dissipation in package the thermal characterization para meter is measured per jesd51-2 specification published by jedec using a 40 gauge type-t thermocouple epoxied to th e top center of the package case. the thermocouple 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-6 freescale semiconductor should be positioned so that the thermocouple junction rest s on the package. a sm all amount of epoxy is placed over the thermocouple junction and over about one mm of wire extendi ng from the junction. the thermocouple wire is placed flat against the package case to avoid me asurement errors caused by cooling effects of the thermocouple wire. g.4.1 thermal references the website for semiconductor equipm ent and materials international is www.semi.org and their global headquarters address is: 3081 zanker ro ad, san jose ca, 95134; 1-408-943-6900. mil-spec and eia/jesd (jedec) sp ecifications are available from global engineering documents on the web at www.global.ihs.co m or 800-854-7179 or 303-397-7956. jedec specifications are availabl e on the web at www.jedec.org. 1. c.e. triplett and b. joiner, ? an experimental characterization of a 272 pbga within an automotive engine controller module ,? proceedings of semith erm, san diego, 1998, pp. 47-54. 2. b. joiner and v. adams, ? measurement and simulation of junc tion to board thermal resistance and its application in thermal modeling ,? proceedings of semitherm, san diego, 1999, pp. 212-220. g.5 esd protection table g-3. esd protection characteristics symbol value units esd for human body model (hbm) 1 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for automotive grade integrated circuits. 2000 v hbm circuit description r1 1500 ? c 100 pf esd for machine model (mm) 200 v mm circuit description r1 0 ? c 200 pf number of pulses per pin 2 positive pulses (mm) negative pulses (mm) positive pulses (hbm) negative pulses (hbm) 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric an d functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. ? ? ? ? 3 3 1 1 ? interval of pulses ? 1 s 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-7 g.6 dc electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) table g-4. dc electrical characteristics characteristic symbol min max unit 1 2.6-v only input high voltage 1 except data[0:31] and extclk v ih 2.6 2.0 v ddh + 0.3 v 1a 2.6-v input high voltage extclk v ih c1.6v ddh + 0.3 v 2n.a. ? ? ? ? 3 5-v input only high voltage 2 v ih 5 0.7 * v ddh v ddh + 0.3 v 4 5-v input high voltage (qadc pqa, pqb) v ih a5 0.7 * v ddh (v dda | v ddh ) + 0.3 3 v 5 muxed 2.6-v/ 5-v pins (gpio muxed with addr and data) 2.6-v input high voltage addr., data 5-v input high voltage (gpio) v ih 2.6m v ih 5m 2.0 0.7 * v ddh v ddh + 0.3 v ddh + 0.3 v v 6 2.6-v input low voltage except extclk v il 2.6 v ss ? 0.3 0.8 v 7 2.6-v input low voltage extclk v il 2.6c v ss ? 0.3 0.4 v 8 5-v input low voltage v il 5v ss ? 0.3 0.48 * v ddh v 9 5-v input low voltage (qadc pqa, pqb) v il a5 v ssa ? 0.3 0.48 * v ddh v 10 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v input low voltage (addr., data) 5-v input low voltage (gpio) v il 2.6m v il 5m v ss ? 0.3 v ss ? 0.3 0.8 0.48 * v ddh v 11 qadc analog input voltage 4 note: assumes v dda v ddh vindc v ssh ? 0.3 v ddh + 0.3 v 12 2.6-v weak pull-up/down current pull-up @ 0 to v il 2.6, pull-down @ v ih 2.6 to v dd i act2.6v 20 130 a 13 5-v weak pull-up/down current 4 pull-up @ 0 to v il 5, pull-down @ v ih 5 to v ddh i act5v 20 130 a 14 2.6-v input leakage current 4 pull-up/down inactive ? measured @rails i inact2.6v ?2.5 a 15 5v input leakage current 4,5 pull-up/down inactive ? measured @rails i inact5v ?2.5 a 16 qadc64 input current, channel off 6 pqa, pqb i off -200 -200 200 200 na 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-8 freescale semiconductor 17 2.6-v output high voltage v dd = v ddl 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) v oh 2.6 v oh 2.6a 2.3 2.1 ?v 18 5-v output high voltage v dd = v ddh (ioh= -2ma) all 5-v only outputs except tpu. v oh 5v ddh ? 0.7 ? v 19 5-v output high voltage v dd = v ddh (ioh= -5ma) for tpu pins only v oh tp5 v ddh ? 0.65 ? v 20 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) 5-v output high voltage (ioh = -2ma) v oh 2.6m v oh 2.6ma v oh 5m 2.3 2.1 v ddh ? 0.7 ?v 21 2.6-v output low voltage v dd = v ddl (iol = 3.2ma) v ol 2.6 ? 0.5 v 22 5-v output low voltage v dd = v ddh (iol = 2ma) all 5-v only outputs except tpu v ol 5 ? 0.45 v 23 5-v output low voltage v dd = v ddh -tpu pins only iol = 2ma iol = 10ma v ol tp5 ? 0.45 1.0 v 24 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output low voltage (iol = 3.2ma) 5-v output low voltage (iol = 2ma) v ol 2.6m v ol 5m 0.5 0.45 v 25 output low current (@ v ol 2.6= 0.4 v) iol2.6 2.0 ? ma 27 clkout load capacitance ? sccr com & cqds com[0:1]= 0b01, cqds = 0b1 com[0:1]= 0b01 cqds = 0b0 com[0:1]= 0b00 cqds = 0bx c clk ? 25 50 90 pf pf pf 29 capacitance for input, output, and bidirectional pins: vin = 0 v, f = 1 mhz (except qadc) c in ?7pf 30 load capacitance for bus pins only 7 com[0:1] of sccr = 0b11 com[0:1] of sccr = 0b10 cl ? 25 50 pf 31 total input capacitance pqa not sampling pqb not sampling c in ? ? 15 15 pf 32 hysteresis (only irq, tpu, mios, gpio, qadc (digital inputs) and hreset, sreset, poreset) 8 vh 0.5 ? v 33 n.a. (see appendix f, ?electrical characteristics ?) ? ? ? ? 34 n.a. (see appendix f, ?electrical characteristics ?) ? ? ? ? 35 n.a. (see appendix f, ?electrical characteristics ?) ? ? ? ? 35a operating current (2.6-v supplies)@ 66 mhz 10 v dd /q vddl /n vddl i ddl ? 250 kapwr (crystal frequency: 20 mhz) i ddkap ?5 kapwr (crystal frequency: 4 mhz) i ddkap ?2 iramstby i ddsram 50 x 10 -3 1.75 11 v ddsyn (crystal frequency: 20 mhz) i ddsyn ?2ma v ddf (read, program, or erase) 9 i ddf ?35 v ddfstop i ddfstop ?10 v ddfdisabled i ddfdisb ? 100 a table g-4. dc electrical characteristics (continued) characteristic symbol min max unit 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-9 36 n.a. (see appendix f, ?electrical characteristics ?) ? ? ? ? 36a operating current (5-v supplies)@ 66 mhz 10, 11 v ddh i ddh5 ? 20 ma v dda 11 i dda ? 5ma v flashf5 (program or erase) i ddf5 ? 10 9 ma v flashf5read i ddf5r ? 5 ma v flashf5 (stopped) si ddf5 ? 1 ma v flashf5 (disabled) si ddf5d ? 100 a 37 qadc64 low power stop mode (v dda )i dda ?10 a 38 low power current (qv ddl + nv ddi + v dd ) @ 66 mhz doze, active pll and active clocks sleep, active pll with clocks off deep sleep, pll and clocks off i dddz i ddslp i dddpslp ? 130 18 9.5 ma ma ma 39 nv ddl , qv ddl ,v dd , v ddf 9 operating voltage nv ddl , qv ddl , v dd , v ddf 2.5 2.7 v 40 v flash flash operating/programming voltage 9 v flash 4.75 5.25 v 41 oscillator, keep-alive registers operating voltage 10,11 kapwr v dd - 0.2 v v dd + 0.2 v 12 v 42 n.a. ? ? ? ? 43 v ddh operating voltage v ddh 4.75 5.25 v 44 qadc operating voltage v dda 4.75 5.25 v 45 clock synthesizer operating voltage difference 11 v ddsyn v dd ? 0.2 v v dd + 0.2 v 12 v 46 n.a. ? ? ? ? 47 v ss differential voltage v ss ? v ssa -100 100 mv 48 qadc64 reference voltage low 13 v rl v ssa v ssa + 0.1 v 49 qadc64 reference voltage high 13 v rh 3.0 v dda v 50 qadc64 v ref differential voltage v rh ? v rl 3.0 5.25 v 51 qadc64 reference supply current, dc qadc64 reference supply current, transient i ref i reft ? ? 500 4.0 a ma 52 qadc64 alt reference voltage 14 v arh 1.0 .75 * v dda v 53 standby supply current kapwr only (4 mhz crystal) kapwr only (20 mhz crystal) measured @ 2.7 v isb kapwr4 isb kapwr20 ? 2.0 5 m m 53a iramstby regulator current data retention 10 specified v dd applied (v dd , v ddh = v ss ) i stby 50 x 10 -3 1.75 ma 53b iramstby regulator voltage for data retention 10, 15 (power-down mode) specified v dd applied (v dd , v ddh = v ss ) 14 v stby 1.35 1.95 v 54 dc injection current per pin gpio, tpu, mios, qsmcm, epee and 5 v pins 4, 16, 17 i ic5 -1.0 1.0 ma 55 dc injection current per pin 2.6 v 4, 17, 18, 19 i ic26 -1.0 1.0 ma 56 qadc64 disruptive input current 17, 20 i na - 3 3 ma 57 power dissipation ? 66 mhz pd 1.32 w 1 this characteristic is for 2.6-v output and 5-v input friendly pins. table g-4. dc electrical characteristics (continued) characteristic symbol min max unit 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-10 freescale semiconductor g.7 oscillator and pll electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) 2 this characteristic is for 5-v output and 5-v input pins. 3 0.3v > v dda or v ddh , whichever is greater. 4 within this range, no significant injection will be seen. see qadc64 disruptive input current (i na ). 5 during reset all 2.6v and 2.6v/5v pads will leak up to 10 a to qvddl if the pad has a voltage > qvddl. 6 maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 8 to 12 c, in the ambient temperature range of 50 to 125 c. 7 all bus pins support two drive strengths capabilities , 25 pf and 50 pf. current drive is less at the 25-pf capacitive load. both modes achieve 66-mhz timing. 8 only irq, tpu, mios, gpio, qadc (when digital inputs) and r eset pins have hysteresis, thus there is no hysteresis specification on all other pins 9 transient currents can reach 50ma. 10 kapwr and iramstby can be powered-up prior to any other supply or at the same time as the other 2.6 v supplies. iramstby must lead or coincide with vdd; however it can lag kapwr. 11 this parameter is periodically sampled rather than 100% tested 12 up to 0.5 v during power up/down. 13 to obtain full-range results, v ssa v rl v indc v rh v dda 14 when using the qadc in legacy mode it is recommended to connect this pin to 2.6v or 3.3v, however it can be connected to 0v or 5v without damage to the device. 15 a resistor must be placed in series with the iramstby power supply. refer to appendix c, ?clock and board guidelines .? 16 all injection current is transferred to the v ddh . an external load is required to dissipate this current to maintain the power supply within the specified voltage range. 17 absolute maximum voltage ratings for each pin (see ta b l e g - 1 ) must also be met during this condition. 18 total injection current for all i/o pins on the chip must not exceed 20 ma (sustained current). exceeding this limit can cause disruption of normal operation. 19 current refers to two qadc64 modules operating simultaneously. 20 below disruptive current conditions, the channel being st ressed has conversion values of 0x3ff for analog inputs greater than v rh and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions. table g-5. oscillator and pll characteristic symbol min typica l max unit 1 oscillator startup time (for typical crystal capacitive load) 4-mhz crystal 20-mhz crystal oscstart4 oscstart20 10 10 ms ms 2 pll lock time t lock 1000 1 input clocks 3 pll operating range 2 f vcoout 30 132 mhz 4 crystal operating range, modck=0b010,0b110 modck[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111 f crystal 3 15 5 25 mhz mhz 5 pll jitter pll jitter (averaged over 10 s) f jit f jit10 -1% -0.3% +1% +0.3% ? 6 limp mode clock out frequency ? 3 3 11 17 3 mhz 7 oscillator bias current (xtal) 4 mhz 20 mhz i bias ? | 1.5 | | 0.8 | | 4.0 | ma ma 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-11 g.8 flash electrical characteristics the characteristics found in this section apply only to the mpc563. note flash programming should be restricted to 56 mhz. flash read operations are unaffected by this condition. note: (v ddf = 2.6 v 0.1 v, v flash = 5.0 v 0.25 v, t a = t l to t h , t b = t l to t h ) note: (v ddf = 2.6 v 0.1 v, v flash = 5.0 v 0.25 v, t a = t l to t h , t b = t l to t h ) 8 oscillator drive (xtal) i osc 7?ma 9 oscillator bias resistor r osc 0.5 1 3 m ? 1 assumes stable power and oscillator. 2 f vcoout is 2x the system frequency. 3 estimated value, real values to be characterized and updated. table g-6. array program and erase characteristics symbol meaning value units minimum typical 1 1 typical program and erase times assume nominal supply values and 25 c. maximum t erase block erase time 2 2 erase time specification does not include pre-programming operation 312s t erasem module erase time 2 13 60 s t prog word programming time 3,4 3 word size is 32 bits. 4 the maximum hardware programming time of the entire flash (not including the shadow row) is 20 s x (512 kbytes / 4 bytes per word), or 131,072 words, (no software overhead). 15 20 s table g-7. censor cell program and erase characteristics symbol meaning value units minimum typical 1 1 typical set and clear times assume nominal supply values and 25 c. maximum t clear censor bit clear time 2 2 clear time specification does not include pre-set operation. 13 60 s t set censor bit set time 115 250 s table g-5. oscillator and pll (continued) characteristic symbol min typica l max unit 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-12 freescale semiconductor g.9 power-up/down sequencing the supply symbols used in this section are described in table g-9 . . table g-8. flash module life symbol meaning value array p/e cycles 1 1 a program/erase cycle is defined as switching the bits from 1 to 0 to 1. maximum number of program/erase cycles per block to guarantee data retention. 1,000 censor set/clear cycles 2 2 a censor set/clear cycle is defined as switching the bits from 1 to 0 to 1. minimum number of program/eras e cycles per bit before failure. 100 array and censor data retention minimum data retention at an average of 85 c junction temperature. minimum data retention at an average of 125 c junction temperature. min 15 years 3 min 10 years 3 3 maximum total time @ 150 c junction temperature 1 year. table g-9. power supply pin groups symbol types of power pins v ddh (high voltage supply group) supply to the 5-v pads for output driver (v ddh ) supply to the analog (qadc64e) circuitry (v dda ) high voltage supply to the flash module (v flash ) 1 1 these power supplies are only available on the mpc563 and mpc564. v ddl (low voltage supply pins) supply to low voltage pad drivers (qvddl, nvddl) supply to all low voltage internal logic (v dd ) supply to low voltage flash circuitry (v ddf ) 1 supply to system pll v ddka (low voltage keep-alive supply pins 2 2 any supply in the v ddka group can be powered with the v ddl if the function which it supplies is not required during ?keep-alive.? supply to iramstby supply to oscillator and other circui try for keep-alive functions (kapwr). 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-13 there are two power-up/down options. choosing which one is required for an application will depend upon circuitry connected to 2.6-v compliant pins and dual 2.6-v/5-v compliant pins. power-up/down option a is required if 2.6-v compli ant pins and dual 2.6-v/5- v compliant pins are connected to the 5-v supply with a pull-up resistor or dr iven by 5-v logic during power-up/down. in applications for which this scenario is not true the power-up/do wn option b may be implemented. opti on b is less stri ngent and easier to ensure over a vari ety of applications. refer to table 2-1 for a list of 2.6 v and dua l 2.6v/5 v compliant pins. the power consumption during power-up/down seque ncing will stay below the operating power consumption specifications when following these guidelines. note: the v ddh ramp voltage should be kept below 50v/ms and the v ddl ramp rate less that 25v/ms. g.9.1 power-up/down option a the option a power-up sequence (excluding v ddka ) is 1. v ddh v ddl + 3.1 v (v ddh cannot lead v ddl by more than 3.1 v) 2. v ddh v ddl - 0.5 v (v ddh cannot lag v ddl by more than 0.5 v) the first step in the sequence is required is due to ga te-to-drain stress limits for transistors in the pads of 2.6-v compliant pins and dual 2.6-v/5-v compliant pi ns. damage can occur if gate-to-drain voltage potential is greater than 3.1 v. th is is only a concern at power-up/down. the second step in the sequence is required is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins. the diodes are forward biased when v ddl is greater than v ddh and will start to conduct current. figure g-1 illustrates the power-up sequence if no keep-alive supply is required. figure g-2 illustrates the power-up sequence if a keep-alive s upply is required. the keep-alive supply should be powered-up at the same instant or before both the high volta ge and low voltage supplies are powered-up. figure g-1. option a power-up sequence without keep-alive supply v ddh v ddl v ddh cannot lead v ddl by more than 3.1 v 3.1-v lead v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-14 freescale semiconductor figure g-2. option a power-up sequence with keep-alive supply the option a power-down sequence (excluding v ddka ) is 1. v ddh v ddl + 3.1 v (v ddh cannot lag v ddl by more than 3.1 v) 2. v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v) figure g-3 illustrates the power-down sequence if no keep-alive supply is required. figure g-3. option a power-down sequence without keep-alive supply v ddh v ddl 3.1-v lead 0.5-v lag v ddka v ddh cannot lead v ddl by more than 3.1 v v ddh cannot lag v ddl by more than 0.5 v v ddh v ddl 3.1-v max ramp down rates may differ with load, so care should be taken maintain v ddh with respect to v ddl . v ddh cannot lag v ddl by more than 3.1 v. v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v.) 0.5-v max 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-15 figure g-4 illustrates the power-down sequence if a keep-alive supply is required. figure g-4. option a power-down sequence with keep-alive supply g.9.2 power-up/down option b a less stringent power-up sequence may be implem ented if 2.6-v compliant pins and dual 2.6-v/5-v compliant pins are not connected to the 5-v supply with a pull-up resistor or driv en by 5-v logic during power-up/down. the option b power-up sequence (excluding v ddka ) is: 1. v ddh > v ddl - 0.5 v (v ddh cannot lag v ddl by more than 0.5 v) thus the v ddh supply group can be fully powered -up prior to power-up of the v ddl supply group, with no adverse affects to the device. the requirement that v ddh cannot lag v ddl by more than 0.5 v is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins . the diodes are forward biased when v ddl is greater than v ddh and will start to conduct current. figure g-5 illustrates the power-up sequence if no keep-alive supply is required. figure g-6 illustrates the power-up sequence if a keep-alive s upply is required. the keep-alive supply should be powered-up at the same time or before both the high voltage and low voltage supplies are powered-up. v ddh v ddl v ddh cannot lag v ddl by more than 3.1 v. 3.1-v max 0.5-v max v ddh v ddl - 0.5 v (v ddh cannot lead v ddl by more than 0.5 v.) v ddka ramp down rates may differ with load. 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-16 freescale semiconductor figure g-5. option b power-up sequence without keep-alive supply figure g-6. option b power-up sequence with keep-alive supply the option b power-down sequence (excluding v ddka ) is: 1. the v ddl supply group can be fully powered- down prior to power-down of the v ddh supply group, with no adverse af fects to the device. for power-down, the low voltage suppl y should come down before the hi gh voltage supply, although with varying loads, the high voltage may actually get ahead. figure g-7 illustrates the power- down sequence if no keep-alive supply is required. figure g-8 illustrates the power-down sequence if a keep-alive supply is required. v ddh v ddl v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag v ddh v ddl v ddh cannot lag v ddl by more than 0.5 v 0.5-v lag v ddka 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-17 figure g-7. option b power-down sequence without keep-alive supply figure g-8. option b power-down sequence with keep-alive supply g.10 issues regarding power sequence g.10.1 application of poreset or hreset when v ddh is rising and v ddl is at 0.0 v, as v ddh reaches 1.6 v, all 5 v drivers are tristated. before v ddh reaches 1.6v, all 5 v outputs are unknown. if v ddl is rising and v ddh is at least 3.1v greater than v ddl , then the 5 v drivers can come out of tristate when v ddl reaches 1.1v, and the 2.6 v drivers can start driving when v ddl reaches 0.5 v. for these reasons, the poreset or hreset signal must be asserted during power-up before v ddl is above 0.5 v. if the poreset or hreset signal is not asserted before this condi tion, there is a possi bility of disturbing the programmed state of the flash. in addition, the state of the pads are indeterminant until poreset or hreset propagates through the device to initialize all circuitry. v ddh v ddl ramp down rates may differ with load. 0.5-v lag v ddh cannot lead v ddl by more than 0.5v v ddh 5.25v v ddh v ddl ramp down rates may differ with load. 0.5-v lag v ddh cannot lead v ddl by more than 0.5v v ddkap 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-18 freescale semiconductor g.10.2 keep-alive ram poreset or hreset must be asserted during power-down prior to any suppl y dropping out of specified operating conditions. an additional constraint is placed on poreset assertion since it is an asynchronous input. to assure that the assertion of poreset does not potentially cause stores to keep-alive ram to be corrupted (store single or store multiple) or non-c oherent (store multiple), either of the following solutions is recommended: ? assert hreset at least 0.5 s prior to when poreset is asserted. ? assert irq 0 (non-maskable interrupt) at least 0.5 s prior to when poreset is asserted. the service routine for irq 0 should not perform any wr ites to keep-alive ram. the amount of delay that should be added to poreset assertion is dependent upon the frequency of operation and the maximum number of store multiples ex ecuted that are required to be coherent. if store multiples of more than 28 registers are needed and if the frequency of operation is lower that 66 mhz, the delay added to poreset assertion will need to be greater than 0.5 s. in addition, if kapwr features are being used, poreset should not be driven low while the v ddh and v ddl supplies are off. g.11 ac timing figure g-9 displays generic examples of mpc561/mpc 563 timing. specific timing diagrams are shown in figure g-10 through figure g-35 . 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-19 figure g-9. generic timing examples clkout 5-v outputs 5-v inputs 5-v inputs v ol v oh v ih v il v il v ih v ih v il v il v ih a b cd cd a. maximum output delay specification b. minimum output hold time c. minimum input setup time specification d. minimum input hold time specification 5-v outputs a b addr/data/ctrl v dd /2 a b a b addr/data/ctrl outputs v dd /2 addr/data/ctrl c d cd v ol v oh v ol v oh v ol v oh v dd /2 v dd /2 v dd /2 addr/data/ctrl inputs v dd v dd /2 v dd /2 v dd /2 v dd /2 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-20 freescale semiconductor table g-10. bus operation timing note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 1 clkout period (tc) 15.15 ? ns 1a engclk frequency 5 v ? eeclk = 01 2. 6 v ? eeclk = 00 ? 10 33 mh z 2 clock pulse width low 7.575 ?2% 7.575 + 2% ns 3 clock pulse width high 7.575 ? 2% 7.575 + 2% ns 4 clkout rise time abus/dbus rise time ?3.5 3.0 ns 5 clkout fall time abus/dbus fall time ?3.5 3.0 ns 6 n.a. ? ? ? 7 clkout to signal invalid (hold time) addr[8:31] rd/wr burst d[0:31] 1.8 ? ns 7a clkout to signal invalid: (hold time) tsiz[0:1] rsv at[0:3] bdip ptr retry 2.0 ? ns 7b clkout to signal invalid (hold time) 1 br bg frz vfls[0:1] vf[0:2] iwp(0:2] lwp[0:1] sts 2 2.15 ? ns 7c slave mode clkout to signal invalid d[0:31] 1.8 ? ns 8 clkout to signal valid addr[8:31] rd/wr burst d[0:31] 3 5.95 9.8 ns 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-21 8a clkout to signal valid tsiz[0:1] rsv at[0:3] bdip ptr retry 4.65 8.3 ns 8b clkout to signal valid 1 br bg vfls[0:1] vf[0:2] iwp[0:2] frz lwp[0:1] sts valid. 4.55 8.75 ns 8c slave mode clkout to signal valid d[0:31] ?8.3ns 8d clkout to data pre-discharge time 4 ??ns 8e clkout to data pre-discharge start 4 ??ns 9 clkout to high z addr[8:31] rd/wr burst d[0:31] tsiz[0:1] rsv at[0:3] ptr retry 5.95 9.8 ns 10 clkout to ts , bb assertion 3.33 7.9 ns 10a clkout to ta , bi assertion (when driven by the memory controller) ?7.85ns 10b clkout to retry assertion (when driven by the memory controller) ?6.4ns 11 clkout to ts , bb negation 2.78 5.95 ns 11a clkout to ta , bi negation (when driven by the memory controller) 0.28 2.8 ns 11b clkout to retry negation (when driven by the memory controller) 011ns 12 clkout to ts , bb high z 3.85 13.6 ns table g-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-22 freescale semiconductor 12a clkout to ta , bi high z (when driven by the memory controller) ? 12.75 ns 13 clkout to tea assertion ? 5.85 ns 14 clkout to tea high z ? 12.75 ns 15 input valid to clkout (setup time) ta tea bi 2 6.35 ? ns 15a input valid to clkout (setup time) kr cr retry 6.6 ? ns 15b input valid to clkout (setup time) bb bg br 1 5.46 ? ns 16 clkout to signal invalid (hold time) ta tea bi bb bg br 1, 2 1?ns 16a clkout to signal invalid (hold time) retry kr cr 1?ns 17 signal valid to clkout rising edge (setup time) d[0:31] 3 4?ns 17b signal valid to clkout rising edge (short setup time, sst = 1) d[0:31] 3 3?ns 18 clkout rising edge to signal invalid (hold time) d[0:31] 3 0.5 ? ns 19 clkout rising edge to cs asserted -gpcm- acs = 00 6.1 9.75 ns 19a clkout falling edge to cs asserted -gpcm- acs = 10, trlx = 0 or 1 ?4.25ns table g-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-23 19b clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0 or 1 49ns 19c clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 6.69 12.69 ns 20 clkout rising edge to cs negated -gpcm- read access or write access when csnt = 0 or write access when csnt = 1 and acs = 00 1.55 4.85 ns 21 addr[8:31] to cs asserted -gpcm- acs = 10, trlx = 0 1.2 ? ns 21a addr[8:31] to cs asserted -gpcm- acs = 11, trlx = 0 5.1 ? ns 22 clkout rising edge to oe ,we [0:3]/be [0:3] asserted 1 5.45 ns 23 clkout rising edge to oe negated 1.45 5.06 ns 24 addr[8:31] to cs asserted -gpcm- acs = 10, trlx = 1 13.95 ? ns 24a addr[8:31] to cs asserted -gpcm- acs = 11, trlx = 1 17 ? ns 25 clkout rising edge to we [0:3]/be [0:3] negated -gpcm-write access csnt = ?0? ?4.75ns 25a clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1, ebdf = 0?. 4.5 9.5 ns 25b clkout falling edge to cs negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 4.5 9.5 ns 25c clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx=?0?, csnt=?1, ebdf=1?. 5.5 12.69 ns 25d clkout falling edge to cs negated -gpcm-write access trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 6.25 17 ns 26 we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, csnt = ?0? 1.95 ? ns 26a we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 0 4.85 ? ns 26b cs negated to d[0:31], high z -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 1.95 ? ns table g-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-24 freescale semiconductor 26c cs negated to d[0:31], high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 4.85 ? ns 26d we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 0 17 ? ns 26e cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 17 ? ns 26f we [0:3]/be [0:3] negated to d[0:31] highz -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 1 3.2 ? ns 26g cs negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 3.2 ? ns 26h we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 1 14.65 ? ns 26i cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 14.65 ? ns 27 cs , we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access 5 1.2 ? ns 27a we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?, acs = 10,acs = =?11?, ebdf = 0 4.85 ? ns 27b we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 0 17 ? ns 27c we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 2.55 ? ns table g-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-25 note the d[0:31] input timings 17 and 18 refe r to the rising edge of the clkout in which the ta input signal is asserted. figure g-10. clkout pin timing 27d we [0:3]/be [0:3] negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to addr[8:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 14.65 ? ns 28 addr[8:31], tsiz[0:1], rd/wr , burst , valid to clkout rising edge. (slave mode setup time) 3.5 ? ns 28a slave mode d[0:31] valid to clkout rising edge 3.7 ? ns 29 ts valid to clkout rising edge (setup time) 2 ? ns 30 clkout rising edge to ts valid (hold time). 3.6 ? ns 1 the timing for br output is relevant when the devicempc561/m pc563 is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc561/mpc563 is selected to work with internal bus arbiter. 2 the setup times required for ta , tea , and bi are relevant only when they are supplied by the external device (and not the memory controller). 3 the maximum value of spec 8 for data[0:31] pins must be extended by 1.1 ns if the pins have been precharged to greater than v ddl . this is the case if an external slave device on the bus is running at the max. value of vdatapc. this is currently specified at 3.1 v. the 1. 1 ns addition to spec 8 reflects the expected timing degradation for 3.1 v. 4 the device may be used without limitat ion in conjuction with 2.6 v external memories. pre-discharge function is not available for 66-mhz operation. 5 the timing 27 refers to cs when acs = ?00? and to we [0:3]/be [0:3] when csnt = ?0?. table g-10. bus operation timing (continued) note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h , 50 pf load unless noted otherwise) characteristic 66 mhz uni t min max 1 3 2 4 5 clkout 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-26 freescale semiconductor figure g-11. synchronous output signals timing 8 8a 7b 9 9 7a 7 8b clkout output signals output signals output signals 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-27 figure g-12. synchronous active pull-up and open drain outputs signals timing 10 12 11 10a 12a 11a 13 14 clkout ts , bb ta , bi tea 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-28 freescale semiconductor figure g-13. synchronous input signals timing 15 16 15a 16a 15b 16 clkout ta , bi tea , kr , retry , cr bb , bg , br 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-29 figure g-14. input data timing in normal case 15a 16 17 18 data[0:31] ta clkout 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-30 freescale semiconductor figure g-15. external bus read timing (gpcm controlled ? acs = ?00?) 8 10 19 22 11 20 23 17 18 25 clkout ts addr[8:31] csx oe we [0:3]/be [0:3] data[0:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-31 figure g-16. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?10?) 8 10 19a 22 11 20 23 17 18 21 clkout ts addr[8:31] csx oe data[0:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-32 freescale semiconductor figure g-17. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?11?) 19c 19b 8 10 22 11 20 23 17 18 21a clkout ts addr[8:31] csx oe data[0:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-33 figure g-18. external bus read timing (gpcm controlled ? trlx = ?1?, acs = ?10?, acs = ?11?) 8 19a 11 20 23 17 18 24 24a 19b 19c 10 clkout ts addr[8:31] csx oe data[0:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-34 freescale semiconductor figure g-19. address show cycle bus timing 11 10 8 9 clkout ts addr[8:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-35 figure g-20. address and data show cycle bus timing 8 10 11 9 8 27 data[0:31] clkout ts addr[8:31] csx we [0:3]/be [0:3] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-36 freescale semiconductor figure g-21. external bus write timing (g pcm controlled ? trlx = ?0?, csnt = ?0?) 8 10 19 22 11 20 25 9 23 8 26 26b 27 data[0:31] oe we [0:3]/be [0:3] csx addr[8:31] ts clkout 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-37 figure g-22. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c d[0:31] oe we [0:3]/be [0:3] csx addr[8:31] clkout ts 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-38 freescale semiconductor figure g-23. external bus write timing (gpcm controlled ? trlx = ?1?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c clkout ts addr[8:31] csx we [0:3]/be [0:3] oe data[0:31] 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-39 figure g-24. external master read from internal registers timing 29 28 30 10a 12a 11a 13 14 9 8 10b 11b clkout ts addr[8:31], tsiz[0:1], rd/wr , burst , ta , bi tea data[0:31] retry bdip 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-40 freescale semiconductor figure g-25. external master write to internal registers timing table g-11. interrupt timing note: (t a = t l to t h ) characteristic 66 mhz unit min max 33 irq x pulse width low tc ? ns 34 irq x pulse width high; between level irq tc ? ns 35 irq x edge to edge time 4 * tc ? ns 29 28 30 10a 12a 11a 13 14 28a 18 10b 11b clkout ts addr[8:31], tsiz[0:1], rd/wr , burst ta , bi tea , data[0:31] retry 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-41 figure g-26. interrupt detection timing for external edge sensitive lines g.11.1 debug port timing table g-12. debug port timing note: (t a = t l to t h ) characteristic 66 mhz unit min max 36 dsck cycle time 30.30 ? ns 37 dsck clock pulse width 15.15 ? ns 38 dsck rise and fall times 0 7 ns 39 dsdi input data setup time 15 ? ns 40 dsdi data hold time 5 ? ns 41 dsck low to dsdo data valid 0 18 ns 42 dsck low to dsdo invalid 0 ? ns 33 34 irq x 35 edge irq level irq 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-42 freescale semiconductor figure g-27. debug port clock input timing figure g-28. debug port timings 36 36 37 37 38 38 dsck 40 42 41 39 dsck dsdi dsdo 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-43 g.12 readi electrical characteristics the ac electrical characteristics (56 mhz) ar e described in the foll owing tables and figures figure g-29. auxiliary port data input timing diagram figure g-30. auxiliary port data output timing diagram mdo and mseo data is held valid until the next mcko low transition. when rsti is asserted, evti is used to enable or disable the au xiliary port. because mcko probably is not active at this point, the timing mu st be based on the system clock. since the system clock is not realized on the connector, its value must be known by the tool. table g-13. readi ac electrical characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h 50 pf load unless noted otherwise) number characteristic min max unit 1 mcko cycle time (tco) 17.9 ? ns 2 mcko duty cycle 40 60 % 3 output rise and fall times 0 3 ns 4 mcko low to mdo data valid -1.79 3.58 ns 5 mcki cycle time (tci) 35.6 ? ns 6 mcki duty cycle 40 60 % 7 input rise and fall times 0 3 ns 8 mdi, evti , msei setup time 7.12 ? ns 9 mdi hold time 3.56 ? ns 10 rsti pulse width 71.6 ? ns 11 mcko low to mseo valid -1.79 3.58 ns 12 evti pulse width 71.6 ? ns 13 evti to rsti setup (at reset only) (4.0) x tc ? ns 14 evti to rsti hold (at reset only) (4.0) x tc ? ns mcki mdi, evti ,msei input data valid 89 mcko output data valid mdo, mseo 4 11 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-44 freescale semiconductor figure g-31. enable auxiliary from rsti figure g-32. disable auxiliary from rsti g.13 reset timing table g-14. reset timing note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) characteristic 66 mhz unit min max 43 clkout to hreset high impedance ? 20 ns 44 clkout to sreset high impedance ? 20 ns 45 rstconf pulse width 257 ? ns 46 configuration data to hreset rising edge setup time 231 ? ns 47 configuration data to rstconf rising edge set up time 231 ? ns 48 configuration data hold time after rstconf negation 0 ? ns 49 configuration data hold time after hreset negation 0 ? ns 49a rstconf hold time after hreset negation 1 24 ? 50 hreset and rstconf asserted to data out drive 25 ? ns 51 rstconf negated to data out high impedance 25 ? ns 52 clkout of last rising ed ge before chip tristates hreset to data out high impedance 25 ? ns 53 dsdi, dsck set up 46 ? ns 54 dsdi, dsck hold time 0 ? ns 55 sreset negated to clkout rising edge for dsdi and dsck sample 121 ? ns 55a hreset , sreset , poreset pulse width 2 100 ? ns rsti evti 13 14 rsti evti 13 14 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-45 figure g-33. reset timing ? configuration from data bus 1 weak pull-ups and pull-downs used for reset timing will comply with the 130 a mode select current outlined in 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-46 freescale semiconductor figure g-34. reset timing ? data bus weak drive during configuration 50 51 52 43 55a clkout hreset rstconf data[0:31] (out) (weak) 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-47 figure g-35. reset timing ? debug port configuration g.14 ieee 1149.1 electrical characteristics table g-15. jtag timing note: (t a = t l to t h ) characteristic 10 mhz 1 unit min max 56 tck cycle time 1 (jtag clock) 100 ? ns 57 tck clock pulse width measured at v dd /2 50 ? ns 58 tck rise and fall times 0 10 ns 59 tms, tdi data setup time 5 ns 60 tms, tdi data hold time 25 ns 61 tck low to tdo data valid 20 ns 62 tck low to tdo data invalid 0 ns 63 tck low to tdo high impedance 20 ns 66 tck falling edge to output valid 50 ns 67 tck falling edge to output valid out of high impedance 50 ns 68 tck falling edge to output high impedance 50 ns 69 boundary scan input valid to tck rising edge 50 ns 70 tck rising edge to boundary scan input invalid 50 ns 53 44 54 54 53 55 dsck, dsdi sreset clkout 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-48 freescale semiconductor figure g-36. jtag test clock input timing figure g-37. jtag test access port timing diagram 1 jtag timing (tck) is only tested at 10 mhz. tck is the operating clock of the mpc561/mpc563 in jtag mode. 56 57 57 58 tck 60 62 59 61 63 tck tms, tdi tdo 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-49 figure g-38. boundary scan (jtag) timing diagram 66 67 68 69 70 output signals tck output signals output signals 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-50 freescale semiconductor g.15 qadc64e electrical characteristics table g-16. qadc64e conversion characteristics note: (v dd = 2.6 v 0.1 v, v ddh = 5.0 v 0.25 v, t a = t l to t h ) num parameter symbol min max units 97 qadc clock (qclk) frequency 1 1 conversion characteristics vary with f qclk rate. reduced conversion accuracy occurs at max f qclk rate. f qclk 0.5 3.0 mhz 98 conversion cycles 2 legacy mode: qadcmcr[flip] = 0 enhanced mode: qadcmcr[flip] = 1 2 the number of conversion cycles is de pendent on the ist bit in the ccw register. cc cc 12 14 28 20 qclk cycles qclk cycles 99 conversion time f qclk = 2.0 mhz 1 legacy mode: qadcmcr[flip] = 0 min = ccw[ist] =0b00, ccw[byp] = 0 max = ccw[ist] =0b11, ccw[byp] = 1 enhanced mode: qadcmcr[flip] = 1 min = ccw[ist] =0b0 max = ccw[ist] =0b1 t conv 6.0 7.0 14 10 s s s s 100 stop mode recovery time t sr ?10 s 101 resolution 3 3 at v rh ? v rl = 5.12 v, one count = 5 mv. ?5?mv 102 absolute (total unadjusted) error 4, 5, 6, 7 f qclk = 2.0mhz 3 , 2 clock input sample time 4 accuracy tested and guaranteed at v rh ? v rl = 5.0 v 0.25 v 5 this parameter is periodically sampled rather than 100% tested. 6 absolute error includes 1/2 count (~2.5 mv) of inherent quantization error and circuit (differential, integral, and offset) error. specification assumes that adequate low-pass filt ering is present on analog input pins ? capacitive filter with 0.01 f to 0.1 f capacitor between analog input and analog ground, typical source isolation impedance of 10 k ? . 7 input signals with large slew rates or high frequency noise components cannot be converted accurately. these signals may affect the conversion accuracy of other channels. ae -2 2 counts 102a absolute (total unadjusted) error 8, 9, 10, 11 f qclk = 2.0mhz 3 , 2 clock input sample time ae alt -7.8 3.5 mv 104 dc disruptive input injection current 12, 13, 14, 15, 16 i inj 17 i inj 18 -3 19 -1 3 1 m ma 105 current coupling ratio 20 pqa pqb k? ? 8x10 -5 8x10 -5 106 incremental error d ue to injection current all channels have same 10k ? < rs <100k ? channel under test has rs=10k ? , i inj =+ 3ma e inj + 1.0 + 1.0 counts counts 107 source impedance at input 21 r s ?100 k ? 107a incremental capacitance during sampling 22 c samp ?5 pf 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-51 8 accuracy tested and guaranteed at v arh ? v rl = 1.0v to 0.75 x v dda v. see specification 52 in 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-52 freescale semiconductor g.16 qsmcm electrical characteristics table g-17. qspi timing note: (t a = t l to t h , 50 pf load on all qspi pins unless otherwise noted) num function symbol min max unit 108 operating frequency 1 master slave f op ? ? f sys /4 f sys /4 hz hz 109 cycle time master slave t qcyc 4*tc 4*tc 510 * tc 2 ? ns ns 110 enable lead time master slave t lead 2*tc 2*tc 128 * tc ? ns ns 111 enable lag time master slave t lag ? 2*tc sck/2 ? ns ns 112 clock (sck) high or low time master slave 3 t sw 2*tc? 60 2*tc? n 255 * tc ? ns ns 113 sequential transfer delay master slave (does not require deselect) t td 17*tc 13*tc 8192 * tc - ns ns 114 data setup time (inputs) master slave t su 30 20 - - ns ns 115 data hold time (inputs) master slave t hi 0 20 - - ns ns 116 slave access time t a ?tcns 117 slave miso disable time t dis ?2 * tcns 118 data valid (after sck edge) master slave t v ? ? 50 50 ns ns 119 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 120 sck, mosi, miso rise time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 200 pf, slrc1 bit of pdmcr = ?1? (fast) up to 200 pf, slrc1 bit of pdmcr = "0" (slow) t ri t ro t ro t ro ? ? ? 1 200 21 300 s ns ns ns 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-53 120a pcs[0:1] rise time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 50 pf, slrc1 bit of pdmcr = ?1? (fast) t ri t ro t ro ? ? ? 1 50 25 s ns ns 121 sck, mosi, miso fall time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 200 pf, slrc1 bit of pdmcr = ?1? (fast) up to 200 pf, slrc1 bit of pdmcr = ?0? (slow) t ri t fo t fo t fo ? ? ? ? 1 200 21 300 s ns ns ns 121a pcs[0:1] fall time input ? output ? up to 50 pf, slrc1 bit of pdmcr = ?0? (slow) up to 50 pf, slrc1 bit of pdmcr = ?1? (fast) t ri t fo t fo ? ? ? 1 50 25 s ns ns 1 all ac timing is tested to the 5-v levels outlined in 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-54 freescale semiconductor figure g-39. qspi timing ? master, cpha = 0 figure g-40. qspi timing ? master, cpha = 1 data lsb in msb in msb out msb in msb out data lsb out port data pcs[0:3] output pd miso input mosi output sck cpol=0 output sck cpol=1 111 110 113 121 120 112 109 114 115 111 120 121 119 118 121 120 output msb msb msb out data lsb out port data port data data lsb in msb in 111 110 113 120 121 109 112 109 115 112 120 121 114 119 118 121 120 pcs[0:3] output miso input mosi output sck cpol=0 output sck cpol=1 output 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-55 figure g-41. qspi timing ? slave, cpha = 0 figure g-42. qspi timing ? slave, cpha = 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 data slave lsb out pd msb out msb in data lsb in pd 114 115 121 118 119 117 111 113 109 111 120 121 116 118 110 112 121 120 ss input sck cpol=0 input sck cpol=1 input miso output mosi input 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-56 freescale semiconductor g.17 gpio electrical characteristics table g-19. gpio timing note: (t a = t l to t h ) num rating symbol min max unit 122 sgpioa[8:31], sgpiod[0: 31], sgpioc[1:4, 6:7], mpio32b[0:10, 13:15], a_ pqa[0:7], a_pqb[0:7], b_pqa[0:7], b_pqb[ 0:7] rise time. input t ri - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 200 ns output (pdmcr[slrc0] = 1), 50 pf load t ro - 25 ns 122a qgpio[4:6] rise time. input t ri 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 200 ns output (pdmcr[slrc0] = 1), 200 pf load t ro - 21 ns 122b qgpio[0:3], mpio32b[ 11;12] rise time. input t ri - 1 ms output (pdmcr[slrc0] = 0), 50 pf load 1 t ro - 50 ns output (pdmcr[slrc0] = 1), 50 pf load t ro - 21 ns 122c sgpioc[0, 5] rise time. 2 input t ri - 1 s output (sccr[com] = 0b11), 25 pf load t ro - 10 ns output (sccr[com] = 0b00), 50 pf load t ro - 10 ns 123 sgpioa[8:31], sgpiod[0: 31], sgpioc[1:4, 6:7], mpio32b[0:10, 13:15], a_ pqa[0:7], a_pqb[0:7], b_pqa[0:7], b_pqb[ 0:7] fall time. input t fi - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 200 ns output (pdmcr[slrc0] = 1), 50 pf load t fo - 25 ns 123a qgpio[4:6] fall time. input t fi - 1 s output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 200 ns output (pdmcr[slrc0] = 1), 200 pf load t fo - 21 ns 123b qgpio[0:3], mpio32b[11;12] fall time. input t fi - 1 ms output (pdmcr[slrc0] = 0), 50 pf load 1 t fo - 50 ns output (pdmcr[slrc0] = 1), 50 pf load t fo - 21 ns 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-57 g.18 tpu3 electrical characteristics figure g-43. tpu3 timing 123c sgpioc[0, 5] fall time. 1 input t fi - 1 s output (sccr[com] = 0b11), 25 pf load t fo - 10 ns output (sccr[com] = 0b00), 50 pf load t fo - 10 ns 1 for this 5-v output, a drive load of 200 pf is possible but with a rise/fall time of 300 ns. 2 these are 2.6 v gpio pins. table g-20. tpu3 timing note: (t a = t l to t h ) num rating symbol min max unit 124 slew rate of tpu output channel valid 1,2 (slrc0 of pdmcr = 0, 50 pf to 200 pf load ) (slrc0 of pdmcr = 1, 50 pf load ) 1 ac timing is shown with respect to 10% v dd & 90% v dd levels. 2 timing not valid for external t2clk input. t chtov 92 3 650 25 ns ns 125 clkout high to tpu output channel hold t chtoh 015ns 126 tpu input channel pulse width 3 3 t cyc is defined as the clkout period. t tipw 4?t cyc table g-19. gpio timing (continued) note: (t a = t l to t h ) tpu i/o tim clkout tpu output tpu input 125 126 124 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-58 freescale semiconductor g.19 toucan electrical characteristics g.20 ppm timing characteristics table g-21. toucan timing 1 note: (t a = t l to t h ) 1 ac timing is shown is tested to the 3-v levels outlined in 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-59 following are ppm timing diagrams. figure g-44. ppm_tclk timing figure g-45. ppm data transfer timing (spi mode) g.21 mios timing characteristics all mios output pins are slew rate controlled. slew rate control circui try adds 90 ns as minimum to the output timing and 650 ns as a maximum. this slew rate is from 10% v dd to 90% v dd , an additional 100 ns should be added for total 0 to v dd slew rate. 139 rise time input output ? 2.6v ppm pads (pdmcr2[ppmv] = 0) 5v ppm pads (pdmcr2[ppmv] = 1) t hi t ro ? ? ? 1 7 15 s ns ns 140 fall time input output ? 2.6v ppm pads (pdmcr2[ppmv] = 0) 5v ppm pads (pdmcr2[ppmv] = 1) t fi t fo ? ? ? 1 7 15 s ns ns 1 all ac timing is tested to the 2.6-v levels outlined in 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-60 freescale semiconductor figure g-46. mcpsm enable to vs_pclk pulse timing diagram g.21.1 mpwmsm timing characteristics table g-23. mcpsm timing characteristics note: after reset mcpsmscr_psl[3:0] is set to 0b0000. note: vs_pclk is the mios prescaler clock which is di stributed to all the count er (e.g., mpwmsm and mmcsm) submodules. characteristic symbol delay unit mcpsm enable to vs_pclk pulse 1 1 the mcpsm clock prescaler value (mcpsmscr_psl[3 :0]) should be written to the mcpsmscr (mcpsm status/control register) before rewriting the mcpsmscr to set the enable bit (mcpsmscr_pren). if this is not done the prescaler will start with the old value in the mc psmscr_psl[3:0] before reloading the new value into the counter. t cpsmc (mcpsmscr_psl[3:0]) -1 system clock cycles table g-24. mpwmsm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max pwmsm output resolution t pwmr ? 1 2.0 2 pwm output pulse 3 t pwmo 2.0 ? mpwmi input pin to mpwmscr_pin status set t pin 12 cpsm enable to output set 4 t pwmp (mpwmperr - mpwmpulr + 1) * (256 - mpwmscr_cp) * mcpsmscr_psl + 1 mpwmsm enable to output set (min) 5 t pwme (mpwmperr - mpwmpulr) * (256 - mpwmscr_cp) * mcpsmscr_psl + 3 + (255 - mpwmscr_cp) * mcpsmscr_psl 6 bit (pren) miob vs_pclk t cpsmc prescaler enable note 1: f sys is the internal system clock for the imb3 bus. note 2: the numbers associated with the f sys ticks refer to the imb3 internal state. note 3: vs_pclk is the mios prescaler clock which is di stributed around the mios to counter modules such as the mmcsm and mpwmsm. f sys 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-61 figure g-47. mpwmsm minimum out put pulse example timing diagram note f sys is the internal system clock for the imb3 bus. figure g-48. mcpsm enable to mpwmo ou tput pin rising edge timing diagram mpwmsm enable to output set (max) 5 t pwme t pwme (min) + mcpsmscr_psl - 1 6 interrupt flag to output pin reset (period start) 7 t flgp (256 - mpwmscr_cp) * mcpsmscr_psl - 1 6 1 minimum output resolution depends on mpwmsm and mcpsm prescaler settings. 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mpwmscr_cp[7:0] =0xff. 3 excluding the case where the output is always ?0?. 4 with mpwmsm enabled before enabling the mcpsm. please also see note 1 on the mcpsm timing information. 5 the exact timing from mpwmsm enable to the pin being se t depends on the timing of the register write and the mcpsm vs_pclk. 6 when mcpsmscr_psl = 0x0000, this gives a prescale va lue of 16 and it is 16 which should be used in these calculations. when mcpsmscr_psl = 0x0001, the cpsm is inactive. 7 the interrupt is set before the output pin is reset (signifying the start of a new period). table g-24. mpwmsm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max f sys mpwmo output pin min t pwmo f sys bit (pren) miob vs_pclk t pwmp prescaler enable 341 mpwmo output pin 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-62 freescale semiconductor figure g-49. mpwmsm enable to mpwmo ou tput pin rising edge timing diagram figure g-50. mpwmsm interrupt flag to mpwmo output pin falling edge timing diagram g.21.2 mmcsm timing characteristics table g-25. mmcsm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max mmcsm input pin period t pper 4? mmcsm pin low time t plo 2? mmcsm pin high time t phi 2? clock pin to counter bus increment. t pccb 12 load pin to new counter bus value t plcb 12 clock pin to pinc delay t pinc 12 load pin to pinl delay t pinl 12 counter bus resolution t cbr ? 1 2 2 counter bus overflow reload to interrupt flag t cbflg 1 mcpsm enable to counter bus increment. t mcmp (256 - mmcsmscr_cp) * mcpsmscr_psl + 2 bit t pwme mpwmscr enable 341 mpwmo output pin f sys t flgp mpsmo pin output a mpwmsm interrupt flag f sys 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-63 figure g-51. mmcsm minimum input pin (e ither load or clock) timing diagram note f sys is the internal system clock for the imb3 bus. figure g-52. mmcsm clock pin to count er bus increment timing diagram mmcsm enable to counter bus increment (min) 3 t mcme 4 + mcpsmscr_psl* (255 - mmcsmscr_cp) 3 mmcsm enable to counter bus increment (max) 3 t mcme 4 + mcpsmscr_psl * (255 - mmcsmscr_cp) + (mcpsmscr_psl - 1) 3 1 minimum output resolution depends on mmcsm and mcpsm prescaler settings. 2 maximum resolution is obtained by setting cpsm psl[3:0] =0x2 and mmcsmscr_cp[7:0] =0xff. 3 the exact timing from mmcsm enable to the pin being se t depends on the timing of the mmcsmscr register write and the mcpsm vs_pclk. the mmcsm enable is taken to mean the mmcsmscr_cls[1:0] being written to 2?b11. table g-25. mmcsm timing characteristics (continued) note: all delays are in syst em clock periods. characteristic symbol min max f sys mmcsm pin t phi min t plo min t pper min f sys mmcsm clock pin t pccb counter bus[15:0] a a+1 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-64 freescale semiconductor figure g-53. mmcsm load pin to counter bus reload timing diagram figure g-54. mmcsm counter bus reload to interrupt flag setting timing diagram figure g-55. mmcsm prescaler clock select to counter bus increment timing diagram g.21.3 mdasm timing characteristics table g-26. mdasm timing characteristics note: all delays are in syst em clock periods. characteristics symbol min max input modes: (ipw m, ipm, ic, dis) mdasm input pin period t pper 4? mdasm pin low time t plo 2? f sys mmcsm load pin t plcb counter bus[15:0] a b f sys mmcsm interrupt flag t cbflg counter bus[15:0] ffff 5afe fffe a mmcsmml[15:0] 5afe a f sys mmcsmscr_cls[1:0] t mcme counter bus[15:0] a a+1 34 2 11 00 11 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-65 figure g-56. mdasm minimum input pin timing diagram note f sys is the internal system clock for the imb3 bus. mdasm pin high time t phi 2? input capture resolution t capr ?2 input pin to counter bus capture delay t pcap 13 1 input pin to interrupt flag delay t pflg 23 input pin to pin delay t pin 12 counter bus resolution t cbr ?2 2 output modes: (oc, opwm) output pulse width 3 t pulw 2? compare resolution 3 t comr ?2 2 counter bus to pin change t cbp 3 counter bus to interrupt flag set. t cbflg 3 1 if the counter bus capt ure occurs when the counter bus is changing then the capture is delayed one cycle. in situations where the counter bus is stab le when the input c apture occurs the t pcap has a maximum delay of two cycles (the one-cycle uncertainty is due to the synchronizer). 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mdasmscr_cp[7:0] =0xff. 3 maximum output resolution and pulse width depends on counter (e.g., mmcsm) and mcpsm prescaler settings. table g-26. mdasm timing characteristics (continued) note: all delays are in syst em clock periods. characteristics symbol min max f sys mdai input pin t phi min t plo min t pper min 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-66 freescale semiconductor figure g-57. mdasm input pin to c ounter bus capture timing diagram figure g-58. mdasm input pin to md asm interrupt flag timing diagram figure g-59. mdasm minimum outp ut pulse width timing diagram figure g-60. counter bus to mdasm output pin change timing diagram f sys mdai input pin t pcap counter bus[15:0] a mdasmar[15:0] xxxx a f sys mdai input pin t pflg mdasm interrupt flag f sys mdao output pin t pulw min f sys mdao output pin t cbp counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-67 figure g-61. counter bus to mdasm interrupt flag setting timing diagram g.22 mpiosm timing characteristics figure g-62. mpiosm input pin to mp iosm_dr (data register) timing diagram table g-27. mpiosm timing characteristics note: all delays are in syst em clock periods. characteristic symbol min max input mode mpiosm input pin period t pper ? 1 1 the minimum input pin period, pin low and pin hi gh times depend on the rate at which the mpiosm_dr register is polled. ? mpiosm pin low time t plo ? 1 ? mpiosm pin high time t phi ? 1 ? input pin to mpiosm_dr delay t pdr 01 output mode output pulse width 2 2 the minimum output pulse width depends on how quick ly the cpu updates the value inside the miopsm_dr register. t pulw ? 2 ? f sys mdasm interrupt flag t cbflg counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe f sys mpiosm input pins t pdr mpiosm_dr ffa5 005a ffa5 005a 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-68 freescale semiconductor note f sys is the internal system clock for the imb3 bus. g.23 pin summary table g-28. mpc561/mpc563 signal names and pin names signal name pin name ball assignment usiu addr/sgpioa[8:31] addr_sgpioa8 af9 addr_sgpioa9 af8 addr_sgpioa10 ac6 addr_sgpioa11 y4 addr_sgpioa12 y3 addr_sgpioa13 ad7 addr_sgpioa14 ae7 addr_sgpioa15 af7 addr_sgpioa16 ad8 addr_sgpioa17 ae8 addr_sgpioa18 ac7 addr_sgpioa19 ad9 addr_sgpioa20 ac8 addr_sgpioa21 ad10 addr_sgpioa22 af10 addr_sgpioa23 ac9 addr_sgpioa24 ad11 addr_sgpioa25 ad12 addr_sgpioa26 ac11 addr_sgpioa27 af11 addr_sgpioa28 ae11 addr_sgpioa29 ae12 addr_sgpioa30 ae10 addr_sgpioa31 ae9 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-69 data/sgpiod[0:31] data_sgpiod0 ad13 data_sgpiod1 ac12 data_sgpiod2 af14 data_sgpiod3 af13 data_sgpiod4 af15 data_sgpiod5 ac13 data_sgpiod6 af16 data_sgpiod7 ac14 data_sgpiod8 af17 data_sgpiod9 ac16 data_sgpiod10 af18 data_sgpiod11 ac17 data_sgpiod12 ac18 data_sgpiod13 ad18 data_sgpiod14 ac20 data_sgpiod15 ad19 data_sgpiod16 ad20 data_sgpiod17 ae20 data_sgpiod18 af20 data_sgpiod19 ae19 data_sgpiod20 af19 data_sgpiod21 ae18 data_sgpiod22 ad17 data_sgpiod23 ae17 data_sgpiod24 ad16 data_sgpiod25 ae16 data_sgpiod26 ad15 data_sgpiod27 ae15 data_sgpiod28 ad14 data_sgpiod29 ae14 data_sgpiod30 ae13 data_sgpiod31 af12 irq 0/sgpioc0/mdo4 irq0_b_sgpioc0_mdo4 p3 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-70 freescale semiconductor irq 1/rsv /sgpioc1 irq1_b_rsv_b_sgpioc1 p4 irq 2/cr /sgpioc2/mts 1 irq2_b_cr_b_sgpioc2_mts_b p2 irq 3/kr /retry /sgpioc irq3_b_kr_b_retry_b_sgpioc3 n1 irq 4/at2/sgpioc4 irq4_b_at2_sgpioc4 p1 irq 5/sgpioc5/modck1 irq5_b_sgpioc5_modck1 ad21 irq [6:7]/modck[2:3] irq6_b_modck2 ae21 irq7_b_modck3 y24 pull_sel (input only) pull_sel r26 tsiz[0:1] tsiz0 v4 tsiz1 w1 rd/wr rd_wr _b v1 burst burst y1 bdip bdip_b w4 ts ts_b w2 ta t a _ b w 3 tea tea_b v3 rstconf /texp rstconf_b_texp y25 oe oe_b v2 bi /sts bi_b_sts_b y2 cs [0:3] cs0_b u1 cs1_b u2 cs2_b u3 cs3_b u4 we[ 0:3]/be [0:3]/at[0:3] we0_b_we0_b_a0 t1 we0_b_be1_b_at1 t2 we0_b_be2_b_at2 t3 we0_b_be3_b_at3 t4 poreset /trst poreset_b_trst_b w25 hreset hreset_b w23 sreset sreset_b w24 sgpioc6/frz/ptr sgpioc6_frz_ptr_b n4 sgpioc7/irqout /lwp0 sgpioc7_irqout_b_lwp0 r1 bg /vf0/lwp1 bg_b_vf0_lwp1 r3 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-71 br /vf1/iwp2 br_b_vf1_iwp2 r4 bb /vf2/iwp3 bb_b_vf2_iwp3 r2 iwp[0:1]/vfls[0:1] iwp0_vfls0 n2 iwp1_vfls1 n3 tms/evti tms_evti_b m2 tdi/dsdi/mdi0 tdi_dsdi_mdi0 m1 tck/dsck/mcki tck_dsck_mcki l2 tdo/dsdo/mdo0 tdo_dsdo_mdo0 m4 jcomp/rsti jcomp_rsti_b l1 xtal xtal ad26 extal extal ac26 xfc xfc aa26 clkout clkout u23 extclk extclk v24 engclk/buclk engclk_buclk v26 qsmcm pcs0/ss /qgpio0 pcs0_ss_b_qgpio0 n25 pcs[1:3]/qgpio[1:3] pcs1_qgpio1 n24 pcs2_qgpio2 n23 pcs3_qgpio3 p26 miso /qgpio4 miso_b_qgpio4 p25 mosi /qgpio5 mosi_b_qgpio5 p24 sck/qgpio6 sck_qgpio6 p23 txd1/qgpo1 txd1_qgpo1 r25 txd2/qgpo2/c_cntx0 txd2_qgpo2_c_cntx0 r24 rxd1/qgpi1 rxd1_qgpi1 r23 rxd2/qgpi2/c_cnrx0 rxd2_qgpi2_c_cnrx0 t26 mios14 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-72 freescale semiconductor mda[11:15] mda11 c20 mda12 d20 mda13 a21 mda14 b21 mda15 c21 mda[27:31] mda27 d21 mda28 a22 mda29 b22 mda30 f24 mda31 f25 mpwm[0:1]/mdi[1:2] mpwm0_mdi1 f26 mpwm1_mdo2 g23 mpwm2/ppm_tx1 mpwm2_ppm_tx1 g26 mpwm3/ppm_rx1 mpwm3_ppm_rx1 g25 mpwm16 mpwm16 g24 mpwm17/mdo3 mpwm17_mdo3 h23 mpwm[18:19]/mdo[6:7] mpwm18_mdo6 h24 mpwm19_mdo7 h25 vf0/mpio32b0/mdo1 vf0_mpio32b0_mdo1 l23 vf1/mpio32b1/mcko vf1_mpio32b1_mcko l24 vf2/mpio32b2/msei vf2_mpio32b2_msei_b m24 vfls0/mpio32b3/mseo vfls0_mpio32b3_mseo_b m25 vfls1/mpio32b4 vfls1_mpio32b4 m26 mpio32b5/mdo5 mpio32b5_mdo5 h26 mpio32b6/mpwm4/mdo6 mpio32b6_mpwm4_mdo6 j23 mpio32b7/mpwm5 mpio32b7_mpwm5 j24 mpio32b[8:9]/mpwm[20:21] mpio32b8_mpwm20 j25 mpio32b9_mpwm21 j26 mpio32b10/ppm_tsync mpio32b10_ppm_tsync k25 mpio32b11/c_cnrx0 mpio32b11_c_cnrx0 k24 mpio32b12/c_cntx0 mpio32b12_c_cntx0 k23 mpio32b13/ppm_tclk mpio32b13_ppm_tclk k26 mpio32b14/ppm_rx0 mpio32b14_ppm_rx0 l26 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-73 mpio32b15/ppm_tx0 mpio32b15_ppm_tx0 l25 tpu_a/tpu_b a_tpuch[0:15] a_tpuch0 f3 a_tpuch1 c5 a_tpuch2 b5 a_tpuch3 a5 a_tpuch4 c6 a_tpuch5 d6 a_tpuch6 b6 a_tpuch7 a6 a_tpuch8 c7 a_tpuch9 d7 a_tpuch10 b7 a_tpuch11 a7 a_tpuch12 c8 a_tpuch13 d8 a_tpuch14 b8 a_tpuch15 a8 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-74 freescale semiconductor b_tpuch[0:15] b_tpuch0 k1 b_tpuch1 k2 b_tpuch2 k3 b_tpuch3 k4 b_tpuch4 j1 b_tpuch5 j2 b_tpuch6 j3 b_tpuch7 j4 b_tpuch8 h1 b_tpuch9 h2 b_tpuch10 h3 b_tpuch11 h4 b_tpuch12 g1 b_tpuch13 g2 b_tpuch14 g3 b_tpuch15 g4 a_t2clk/pcs5 a_ t2clk_pcs5 f2 b_t2clk/pcs4 b_ t2clk_pcs4 f1 qadc64e_a/qadc64e_b etrig[1:2]/pcs[6:7] etrig1_pcs6 b20 etrig2_pcs7 a20 a_an0/anw/pqb0 a_an0_anw_pqb0 c11 a_an1/anx/pqb1 a_an1_anx_pqb1 d11 a_an2/any/pqb2 a_an2_any_pqb2 b11 a_an3/anz/pqb3 a_an3_anz_pqb3 a11 a_an[48:51]/pqb[4:7] a_an48_pqb4 c12 a_an49_pqb5 d12 a_an50_pqb6 b12 a_an51_pqb7 a12 a_an[52:54]/ma[0:2]/pqa [0:2] a_an52_ma0_pqa0 c13 a_an53_ma1_pqa1 d13 a_an54_ma2_pqa2 b13 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-75 a_an[55:59]/pqa[3:7] a_an55_pqa3 a13 a_an56_pqa4 a14 a_an57_pqa5 d14 a_an58_pqa6 b14 a_an59_pqa7 c14 b_an0/anw/pqb0 b_an0_anw_pqb0 a15 b_an1/anx/pqb1 b_an1_anx_pqb1 b15 b_an2/any/pqb2 b_an2_any_pqb2 c15 b_an3/anz/pqb3 b_an3_anz_pqb3 d15 b_an[48:51]/pqb[4:7] b_an48_pqb4 a16 b_an49_pqb5 b16 b_an50_pqb6 c16 b_an51_pqb7 d16 b_an[52:54]/ma[0:2]/pqa [0:2] b_an52_ma0_pqa0 a17 b_an53_ma1_pqa1 b17 b_an54_ma2_pqa2 c17 b_an[55:59]/pqa[3:7] b_an55_pqa3 d17 b_an56_pqa4 a18 b_an57_pqa5 b18 b_an58_pqa6 c18 b_an59_pqa7 d18 toucan_a/toucan_b/toucan_c a_cntx0 a_cntx0 m23 b_cntx0 b_cntx0 l4 a_cnrx0 a_cnrx0 n26 b_cnrx0 b_cnrx0 l3 uc3f b0epee 2 boepee t24 epee 2 epee t23 vflash 2 vflash u26 vddf 2 vddf u25 vssf 2 vssf u24 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-76 freescale semiconductor global power supplies nvddl nvddl ac10 ac15 ac19 ac4 ad3 ae2 af1 c9 d9 y23 vdd vdd a1 a25 ac22 ad23 ae24 af25 b2 b24 c23 c3 d22 d4 v23 vddh vddh af21 af5 c19 c22 d19 e1 f23 t25 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-77 vss vss a19, a2, a23, a24, a26, a3, a4, aa1, aa2, aa23, aa24, aa25, aa3 , ab1, ab2, ab24, ab25, ab4, ac1, ac21, ac23, ac25, ac3, ac5, ad2, ad22, ad24, ad4, ad5, ae1, ae22, ae23, ae25, ae3, ae4, ae5, af2, af22, af23, af24, af26 , af3, af4, af6, b1, b19, b23, b25, b3, b4 , c1, c2, c24, c26, c4, d1, d2, d23, d25, d26, d3, d5, e2, e24, e25, e26, e3, e4, l11, l12, l13, l14, l15, l16, m11, m1 2, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, v25 kapwr kapwr w26 iramstby iramstby m3 qvddl qvddl aa4 ab23 ab3 ac2 ac24 ad1 ad25 ad6 ae26 ae6 b26 c25 d24 e23 f4 usiu power supplies vddsyn vddsyn y26 vsssyn vsssyn ab26 qadc64e power supplies vrh vrh c10 vrl vrl a10 table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-78 freescale semiconductor g.23.1 package diagrams the package for the mpc561/mpc563 is the 388 pbga (27 x 27 mm, 1.0 mm ball pitch). this package has 352 balls in the perimeter rows and 36 ground balls in the center isla nd for a total of 388 balls. the case outline drawing is 1164-01, as shown in figure g-63 . altref altref b10 vdda vdda d10 vssa vssa a9 b9 1 this pin also included the mdo5 function on the k27s mask set off the mpc561. 2 mpc563 only, no connection on mpc561. table g-28. mpc561/mpc563 signal names and pin names (continued) signal name pin name ball assignment 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-79 1 note: top down view figure g-63. mpc561/mpc563 package footprint (1 of 2) 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-80 freescale semiconductor figure g-64. mpc561/mpc563 package footprint (2 of 2) 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-81 g.23.1.1 mpc561/mpc563 ball map the ball diagram of the mpc561/mpc563 is shown in figure g-65 . figure g-65. mpc561/mpc563 ball map 1 2 3 4 5 6 7 8 9 10 11121314 15 16 17 18 19 20 21 22 23 24 25 26 a vdd vss vss vss a_tpuch3 a_tpuch7 a_tpuch 11 a_tpuch15 vssa vrl a_an3_a nz_pqb3 a_an51_p qb7 a_an55_ pqa3 a_an56_p qa4 b_an0_an w_pqb0 b_an48_ pqb4 b_an52_m a0_pqa0 b_an56_p qa4 vss etrig2_ pcs7 mda13 mda28 vss vss vdd vss a b vss vdd vss vss a_tpuch2 a_tpuch6 a_tpuch 10 a_tpuch14 vssa altref a_an2_a ny_pqb2 a_an50_p qb6 a_an54_ ma2_pq a2 a_an58_p qa6 b_an1_an x_pqb1 b_an49_ pqb5 b_an53_m a1_pqa1 b_an57_p qa5 vss etrig1_ pcs6 mda14 mda29 vss vdd vss qvddl b c vss vss vdd vss a_tpuch1 a_tpuch4 a_tpuch 8 a_tpuch12 nvddl vrh a_an0_a nw_pqb 0 a_an48_p qb4 a_an52_ ma0_pq a0 a_an59_p qa7 b_an2_an y_pqb2 b_an50_ pqb6 b_an54_m a2_pqa2 b_an58_p qa6 vddh mda11 mda15 vddh vdd vss qvddl vss c d vss vss vss vdd vss a_tpuch5 a_tpuch 9 a_tpuch13 nvddl vdda a_an1_a nx_pqb1 a_an49_p qb5 a_an53_ ma1_pq a1 a_an57_p qa5 b_an3_an z_pqb3 b_an51_ pqb7 b_an55_p qa3 b_an59_p qa7 vddh mda12 mda27 vdd vss qvddl vss vss d e vddh vss vss vss qvddl vss vss vss e f b_t2clk_p cs4 a_t2clk_ pcs5 a_tpuch 0 qvddl vddh mda30 mda31 mpwm0_md i1 f g b_tpuch12 b_tpuch1 3 b_tpuch 14 b_tpuch1 5 mpwm1_md o2 mpwm16 mpwm3_pp m_rx1 mpwm2_pp m_tx1 g h b_tpuch8 b_tpuch9 b_tpuch 10 b_tpuch1 1 mpwm17_m do3 mpwm18_md o6 mpwm19_m do7 mpio32b5_ mdo5 h j b_tpuch4 b_tpuch5 b_tpuch 6 b_tpuch7 mpio32b6_ mpwm4_md o6 mpio32b7_mp wm5 mpio32b8_ mpwm20 mpio32b9_ mpwm21 j k b_tpuch0 b_tpuch1 b_tpuch 2 b_tpuch3 mpio32b12_ c_cntx0 mpio32b11_c _cnrx0 mpio32b10_ ppm_tsync mpio32b13_ ppm_tclk k l jcomp_rs ti_b tck_dsck _mcki b_cnrx0 b_cntx0 vss vss vss vss vss vss vf0_mpio32 b0_mdo1 vf1_mpio32b 1_mcko mpio32b15_ ppm_tx0 mpio32b14_ ppm_rx0 l m tdi_dsdi_ mdi0 tms_evti _b iramstby tdo_dsd o_mdo0 vss vss vss vss vss vss a_cntx0 vf2_mpio32b 2_msei_b vfls0_mpio 32b3_mseo _b vfls1_mpio 32b4 m n irq3_b_kr _b_retry _b_sgpio c3 iwp0_vfl s0 iwp1_vfl s1 sgpioc6_ frz_ptr_ b vss vss vss vss vss vss pcs2_qgpi o2 pcs1_qgpio1 pcs0_ss_b_ qgpio0 a_cnrx0 n p irq4_b_at 2_sgpioc4 irq2_b_c r_b_sgpi oc2_mdo 5_mts irq0_b_s gpioc0_ mdo4 irq1_b_r sv_b_sg pioc1 vss vss vss vss vss vss sck_qgpio 6 mosi_qgpio5 miso_qgpi o4 pcs3_qgpi o3 p r sgpioc7_i rqout_b_ lwp0 bb_b_vf2 _iwp3 bg_b_vf 0_lwp1 br_b_vf1 _iwp2 vss vss vss vss vss vss rxd1_qgpi 1 txd2_qgpo2 _c_cntx0 txd1_qgpo 1 pull-sel r t we_b_at0 we_b_at1 we_b_at 2 we_b_at 3 vss vss vss vss vss vss epee boepee vddh rxd2_qgpi 2_c_cnrx0 t u cs0_b cs1_b cs2_b cs3_b clkout vssf vddf vflash u v rd_wr_b oe_b tea_b tsiz0 vdd extclk vss engclk_bu clk v w tsiz1 ts_b ta_b bdip_b hreset_b sreset_b poreset_b _trst_b kapwr w y burst_b bi_b_sts_ b addr_sg pioa12 addr_sg pioa11 nvddl irq7_b_modc k3 rstconf_b _texp vddsyn y aa vss vss vss qvddl vss vss vss xfc aa ab vss vss qvddl vss qvddl vss vss vsssyn ab ac vss qvddl vss nvddl vss addr_sgp ioa10 addr_sg pioa18 addr_sgpi oa20 addr_sg pioa23 nvddl addr_s gpioa26 data_sg piod1 data_sg piod5 data_sg piod7 nvddl data_sg piod9 data_sgp iod11 data_sg piod12 nvddl data_s gpiod14 vss vdd vss qvddl vss extal ac ad qvddl vss nvddl vss vss qvddl addr_sg pioa13 addr_sgpi oa16 addr_sg pioa19 addr_sgp ioa21 addr_s gpioa24 addr_sg pioa25 data_sg piod0 data_sg piod28 data_sgp iod26 data_sg piod24 data_sgp iod22 data_sg piod13 data_sgpi od15 data_s gpiod16 irq5_b_s gpioc5_m odck1 vss vdd vss qvddl xtal ad ae vss nvddl vss vss vss qvddl addr_sg pioa14 addr_sgpi oa17 addr_sg pioa31 addr_sgp ioa30 addr_s gpioa28 addr_sg pioa29 data_sg piod30 data_sg piod29 data_sgp iod27 data_sg piod25 data_sgp iod23 data_sg piod21 data_sgpi od19 data_s gpiod17 irq6_b_m odck2 vss vss vdd vss qvddl ae af nvddl vss vss vss vddh vss addr_sg pioa15 addr_sgpi oa9 addr_sg pioa8 addr_sgp ioa22 addr_s gpioa27 data_sg piod31 data_sg piod3 data_sg piod2 data_sgp iod4 data_sg piod6 data_sgp iod8 data_sg piod10 data_sgpi od20 data_s gpiod18 vddh vss vss vss vdd vss af 1 2 3 4 5 6 7 8 9 10 11121314 15 16 17 18 19 20 21 22 23 24 25 26 ball map (as viewed from top, through the package and silicon) note: the flash balls are only available on the mp c563 and mpc564. these are no connects on the mpc561 and mpc562. flash supplies and inputs are lo cated on the following balls: t23, t24, u24, u25. u26. 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-82 freescale semiconductor figure g-66. mpc561/mpc563 ball map (black and white, page 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a vdd vss vss vss a_tpuch3 a_tpuch7 a_tpuch 11 a_tpuch15 vssa vrl a_an3_a nz_pqb3 a_an51_p qb7 a_an55_ pqa3 a_an56_p qa4 b vss vdd vss vss a_tpuch2 a_tpuch6 a_tpuch 10 a_tpuch14 vssa altref a_an2_a ny_pqb2 a_an50_p qb6 a_an54_ ma2_pq a2 a_an58_p qa6 c vss vss vdd vss a_tpuch1 a_tpuch4 a_tpuch 8 a_tpuch12 nvddl vrh a_an0_a nw_pqb 0 a_an48_p qb4 a_an52_ ma0_pq a0 a_an59_p qa7 d vss vss vss vdd vss a_tpuch5 a_tpuch 9 a_tpuch13 nvddl vdda a_an1_a nx_pqb1 a_an49_p qb5 a_an53_ ma1_pq a1 a_an57_p qa5 e vddh vss vss vss f b_t2clk_p cs4 a_t2clk_ pcs5 a_tpuch 0 qvddl g b_tpuch12 b_tpuch1 3 b_tpuch 14 b_tpuch1 5 h b_tpuch8 b_tpuch9 b_tpuch 10 b_tpuch1 1 j b_tpuch4 b_tpuch5 b_tpuch 6 b_tpuch7 k b_tpuch0 b_tpuch1 b_tpuch 2 b_tpuch3 l jcomp_rs ti_b tck_dsck _mcki b_cnrx0 b_cntx0 m tdi_dsdi_ mdi0 tms_evti _b iramstby tdo_dsd o_mdo0 n irq3_b_kr _b_retry iwp0_vfl iwp1_vfl sgpioc6_ frz_ptr_ vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-83 figure g-67. mpc561/mpc563 ball map (black and white, page 2) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss p irq4_b_at 2_sgpioc4 irq2_b_c r_b_sgpi oc2_mdo 5_mts irq0_b_s gpioc0_ mdo4 irq1_b_r sv_b_sg pioc1 r sgpioc7_i rqout_b_ lwp0 bb_b_vf2 _iwp3 bg_b_vf 0_lwp1 br_b_vf1 _iwp2 t we_b_at0 we_b_at1 we_b_at 2 we_b_at 3 u cs0_b cs1_b cs2_b cs3_b v rd_wr_b oe_b tea_b tsiz0 w tsiz1 ts_b ta_b bdip_b y burst_b bi_b_sts_ b addr_sg pioa12 addr_sg pioa11 aa vss vss vss qvddl ab vss vss qvddl vss ac vss qvddl vss nvddl vss addr_sgp ioa10 addr_sg pioa18 addr_sgpi oa20 addr_sg pioa23 nvddl addr_s gpioa26 data_sg piod1 data_sg piod5 ad qvddl vss nvddl vss vss qvddl addr_sg pioa13 addr_sgpi oa16 addr_sg pioa19 addr_sgp ioa21 addr_s gpioa24 addr_sg pioa25 data_sg piod0 ae vss nvddl vss vss vss qvddl addr_sg pioa14 addr_sgpi oa17 addr_sg pioa31 addr_sgp ioa30 addr_s gpioa28 addr_sg pioa29 data_sg piod30 af nvddl vss vss vss vddh vss addr_sg pioa15 addr_sgpi oa9 addr_sg pioa8 addr_sgp ioa22 addr_s gpioa27 data_sg piod31 data_sg piod3 12345678910111213 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-84 freescale semiconductor figure g-68. mpc561/mpc563 ball map (black and white, page 3) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss 14 15 16 17 18 19 20 21 22 23 24 25 26 a_an56_p qa4 b_an0_an w_pqb0 b_an48_ pqb4 b_an52_m a0_pqa0 b_an56_p qa4 vss etrig2_ pcs7 mda13 mda28 vss vss vdd vss a a_an58_p qa6 b_an1_an x_pqb1 b_an49_ pqb5 b_an53_m a1_pqa1 b_an57_p qa5 vss etrig1_ pcs6 mda14 mda29 vss vdd vss qvddl b a_an59_p qa7 b_an2_an y_pqb2 b_an50_ pqb6 b_an54_m a2_pqa2 b_an58_p qa6 vddh mda11 mda15 vddh vdd vss qvddl vss c a_an57_p qa5 b_an3_an z_pqb3 b_an51_ pqb7 b_an55_p qa3 b_an59_p qa7 vddh mda12 mda27 vdd vss qvddl vss vss d qvddl vss vss vss e vddh mda30 mda31 mpwm0_md i1 f mpwm1_md o2 mpwm16 mpwm3_pp m_rx1 mpwm2_pp m_tx1 g mpwm17_m do3 mpwm18_md o6 mpwm19_m do7 mpio32b5_ mdo5 h mpio32b6_ mpwm4_md o6 mpio32b7_mp wm5 mpio32b8_ mpwm20 mpio32b9_ mpwm21 j mpio32b12_ c_cntx0 mpio32b11_c _cnrx0 mpio32b10_ ppm_tsync mpio32b13_ ppm_tclk k vf0_mpio32 b0_mdo1 vf1_mpio32b 1_mcko mpio32b15_ ppm_tx0 mpio32b14_ ppm_rx0 l a_cntx0 vf2_mpio32b 2_msei_b vfls0_mpio 32b3_mseo _b vfls1_mpio 32b4 m pcs2_qgpi o2 pcs1_qgpio1 pcs0_ss_b_ qgpio0 a_cnrx0 n 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor g-85 figure g-69. mpc561/mpc563 ball map (black and white, page 4) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss sck_qgpio 6 mosi_qgpio5 miso_qgpi o4 pcs3_qgpi o3 p rxd1_qgpi 1 txd2_qgpo2 _c_cntx0 txd1_qgpo 1 pull_sel r epee 1 boepee 1 vddh rxd2_qgpi 2_c_cnrx0 t clkout vssf 1 vddf 1 vflash 1 u vdd extclk vss engclk_bu clk v hreset_b sreset_b poreset_b _trst_b kapwr w nvddl irq7_b_modc k3 rstconf_b _texp vddsyn y vss vss vss xfc aa qvddl vss vss vsssyn ab data_sg piod7 nvddl data_sg piod9 data_sgp iod11 data_sg piod12 nvddl data_s gpiod14 vss vdd vss qvddl vss extal ac data_sg piod28 data_sgp iod26 data_sg piod24 data_sgp iod22 data_sg piod13 data_sgpi od15 data_s gpiod16 irq5_b_s gpioc5_m odck1 vss vdd vss qvddl xtal ad data_sg piod29 data_sgp iod27 data_sg piod25 data_sgp iod23 data_sg piod21 data_sgpi od19 data_s gpiod17 irq6_b_m odck2 vss vss vdd vss qvddl ae data_sg piod2 data_sgp iod4 data_sg piod6 data_sgp iod8 data_sg piod10 data_sgpi od20 data_s gpiod18 vddh vss vss vss vdd vss af 14 15 16 17 18 19 20 21 22 23 24 25 26 66-mhz electrical characteristics mpc561/mpc563 reference manual, rev. 1.2 g-86 freescale semiconductor mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor regindex-1 a associated registers 10-4 b bar (breakpoint address register) 23-53 bbcmcr (bbc module configuration register) 4-19 br0 - br3 (emory controller base registers 0 -3) 10-32 breakpoint counter b value and control register (countb) 23-46 c calram_otr (calram ownership trace register) 22-17 , 22-18 canctrl0 (control register 0) 16-27 canctrl1 (control register 1) 16-28 canctrl2 (control register 2) 16-30 cfsr0 (tpu3 channel function select register 0) 19-16 cfsr1 (tpu3 channel function select register 1) 19-16 cfsr2 (tpu3 channel function select register 2) 19-16 cfsr3 (tpu3 channel function select register 3) 19-16 cier (tpu3 channel interrupt enable register) 19-15 cisr (tpu3 channel interrupt status register) 19-19 cmpa-cmpd (comparator a-d value registers) 23-41 cmpe-cmpf (comparator e-f value registers) 23-46 cmpg-cmph (comparator g-h value registers) 23-47 colir (change of lock interrupt register) 8-36 counta (breakpoint counter a value and control regis- ter) 23-45 countb (breakpoint counter b value and control regis- ter) 23-46 cpr0 (tpu3 channel priority register 0) 19-18 cpr1 (tpu3 channel priority register 1) 19-18 cram_rbax (calram region base address register) 22-15 , 22-16 crammcr (calram module configuration register) 22-13 cramovl (calram overlay configuration register) 22-17 d ddrqa (qadc64e port a data direction registers) 13-14 , 14-14 ddrqs (portqs data direction register) 15-14 dec (decrementer register) 6-40 der (debug enable register) 23-43 dmbr (dual mapping base register) 10-36 dpdr (development port data register) 23-53 dptram module configuration register (dptmcr) 20-3 ram base address register (rambar) 20-4 dscr (tpu3 development support control register) 19-12 dssr (tpu3 development support status register) 19-14 dual mapping option register 10-37 e ecr (exception cause register) 23-41 , 23-42 eibadr (external interrupt relocation table base address register) 4-25 emcr (external master control register) 6-29 g general-purpose i/o registers 6-46 gpdi (general-purpose data in register) 18-19 gpdo (general-purpose data out register) 18-18 h hsqr0 (tpu3 host sequence register 0) 19-17 hsqr1 (tpu3 host sequence register 1) 19-17 hssr0 (tpu3 host service request register 0) 19-17 hssr1 (tpu3 host service request register 1) 19-17 i ictrl (i-bus support control register) 23-51 , a-16 imask (interrupt mask register) 16-35 internal memory map register 6-28 k keep alive power registers lock mechanism 8-25 l l2u global region attribute register (l2u_gra) 11-16 module configuration register (l2u_mcr) 11-13 region attribute registers (l2u_rax) 11-15 region base address registers (l2u_rbax) 11-14 l2u_gra (l2u global region attribute register) 11-16 l2u_mcr (l2u module configuration register) 11-14 l2u_rax (l2u region x attribute register) 11-15 l2u_rbax (l2u region x base address register) 11-14 lctrl1 (l-bus support control register 1) 23-47 lctrl1 (l-bus support control register 2) 23-48 lctrl2 (l-bus support control register 2) 23-48 m mbism interrupt registers 17-69 mcpsmcr (mcpsm status/control register) 17-18 mdasmscr (mdasm status/control register) 17-43 mi_gra (global regionattribute register) 4-23 register index mpc561/mpc563 reference manual, rev. 1.2 regindex-2 freescale semiconductor mi_ra 1 - 3 (region base address registers (1 - 3)) 4-22 mi_rba 0 - 3 (region base address registers (0 - 3)) 4-21 mios bus interface (mbism) registers 17-13 mios1 interrupt level register 0 (mioslvl0) (mios1lvl0) 17-69 interrupt level register 1 (mioslvl1) (mios1lvl0) 17-70 module and version number register (mios1vnr) 17-14 mios14er0 interrupt enable register 17-66 mios14er1 interrupt enable register 17-68 mios14mcr (mios14 module configuration register) 17-15 mios14rpr0 request pending register 17-66 mios14rpr1 request pending register 17-68 mios14sr0 (interrupt status register) 17-66 mios14sr0 interrupt status register 17-65 , 24-8 mios14sr1 (interrupt status register) 17-67 , 17-68 mios14sr1 interrupt status register 17-67 mios14tpcr (test and pin control register) 17-13 , 17-14 mios1lvl0 (mios1 interrupt level register 0) 17-69 mios1lvl1 (mios1 interrupt level 1 register) 17-70 miscnt (misc counter) 20-6 , 21-5 , 21-9 misrh (multiple input signature register high) 20-5 misrl (multiple input signature register low) 20-6 mmcsmcnt (mmcsm up-counter register) 17-23 mmcsmmml (mmcsm modulus latch register) 17-24 mmcsmscr (mmcsm status/control register) 17-24 mpiosmddr (mpiosm data direction register) 17-63 mpiosmdr (mpiosm data register) 17-62 mpwmcntr (mpwmsm counter register) 17-58 mpwmperr (mpwmsm period register) 17-57 mpwmpulr (mpwmsm pulse width register) 17-57 mpwmscr (mpwmsm status/control register) 17-58 mstat (memory controller status registers) 10-32 o or0 - or3 (memory controller option registers 0-3) 10-34 p pdmcr (pads module configuration register) 2-22 pdmcr2 (pads module c onfiguration register) 2-23 piscr (periodic interrupt status and control register) 6-44 pitc (periodic interrupt timer count register) 6-45 pitr (periodic interrupt timer register) 6-45 plprcr (pll, low-power, an d reset-control register) 8-33 port data direction registers 13-14 , 14-13 port data registers 13-13 , 14-12 portqs (port qs data register) 15-12 ppmmcr (module configuration register) 18-10 ppmpcr (ppm control register) 18-12 pqspar (portqs pin assignment register) 15-13 presdiv (prescaler divide register) 16-29 q qacr0 (qadc64e control register 0) 13-14 , 14-14 qacr1 (qadc64e control register 1) 13-15 , 13-16 , 14-16 qacr2 (qadc64e control register 2) 13-17 , 14-18 qadcint (qadc64e interrupt register) 13-12 , 14-11 qadcmcr (module configuration register) 13-8 , 14-8 qasr (status register 0) 14-22 qasr (status registers) 13-20 qsci1cr (qsci1 control register) 15-60 qsci1sr (qsci1 status register) 15-61 qsmcm configuration register (qmcmmcr) 15-8 interrupt level register s (qdsci_il, qspi_il) 15-9 port qs data register (portqs) 15-11 portqs data direction register (ddrqs) 15-13 portqs pin assignment register (pqspar) 15-12 qsci1 control register (qsci1cr) 15-60 qsci1 status register (qsci1sr) 15-61 qspi command ram (crx) 15-23 qspi control register 0 (spcr0) 15-17 qspi control register 1 (spcr1) 15-19 qspi control register 2 (spcr2) 15-20 qspi control register 3 (spcr3) 15-20 qspi registers 15-16 qspi status register (spsr) 15-21 queued sci1 status and control registers 15-59 sci control register 0 (sccxr0) 15-46 sci control register 1 (sccxr1) 15-47 sci data register (scxdr) 15-50 sci registers 15-45 sci status register (scxsr) 15-48 test register (qtest) 15-9 qsmcmmcr (qsmcm module configuration register) 15-8 qspi_il (qspi interrupt level register) 15-10 r rcpu additional implementation-specific registers 3-27 condition register (cr) 3-16 condition register cr0 field definition 3-17 condition register cr1 field definition 3-17 condition register crn fiel d - compare instruction 3-17 count register (ctr) 3-19 dae/source instruction se rvice register (dsisr) 3-22 data address register (dar) 3-23 decrementer register (dec) 3-23 eie, eid, and nri speci al-purpose registers 3-25 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor regindex-3 floating-point exception cause register (fpecr) 3-26 floating-point registers (fprs) 3-12 floating-point status and control register (fpscr) 3-13 general special-purpose registers (sprg0-sprg3) 3-24 general-purpose registers (gprs) 3-12 implementation-specific special-purpose registers 3-25 integer exception register (xer) 3-18 link register (lr) 3-19 machine state register (msr) 3-20 machine status save/restore register 0 (srr0) 3-23 machine status save/restore register 1 (srr1) 3-23 oea register set 3-20 processor version register (pvr) 3-25 uisa register set 3-12 vea register set - time base 3-20 readi development control register 24-10 , 24-11 readi device id register 24-9 readi did 24-9 readi dta 1 and dta 2 (readi data trace attributes 1 and 2 registers) 24-17 readi rwa (readi read/write access register) 24-13 readi uba (readi user base accress register) 24-12 readi udi (readi upload/download information regis- ter) 24-15 region attribute register (0 - 3) 4-22 register diagrams calrlam_otr (calram ownership trace regis- ter) 22-18 canctrl0 (control register 0) 16-27 canctrl1 (control register 1) 16-28 canctrl2 (control register 2) 16-30 cfsr0 (tpu3 channel function select register 0) 19-16 cfsr1 (tpu3 channel function select register 1) 19-16 cfsr2 (tpu3 channel function select register 2) 19-16 cfsr3 (tpu3 channel function select register 3) 19-16 cier (tpu3 channel interrupt enable register) 19-15 cisr (tpu3 channel interrupt status register) 19-19 cmpg-cmph (comparator g-h value registers) 23-47 counta (breakpoint coun ter a value and control register) 23-45 cpr0 (tpu3 channel priority register 0) 19-18 cpr1 (tpu3 channel priority register 1) 19-18 cram_rbax (calram region base address regis- ter) 22-16 crammcr (calram module configuration regis- ter) 22-13 cramovl (calram overlay configuration regis- ter) 22-17 ddrqa (qadc64e port a data direction registers) 13-14 , 14-14 ddrqs (portqs data direction register) 15-14 der (debug enable register) 23-43 dscr (tpu3 development support control register) 19-12 dssr (tpu3 development support status register) 19-14 ecr (exception cause register) 23-42 eibadr (external interrupt relocation table base ad- dress register) 4-25 hsqr0 (tpu3 host sequence register 0) 19-17 hsqr1 (tpu3 host sequence register 1) 19-17 hssr0 (tpu3 host service request register 0) 19-17 hssr1 (tpu3 host service request register 1) 19-17 imask (interrupt mask register) 16-35 l2u_gra (l2u global region attribute register) 11-16 l2u_mcr (l2u module configuration register) 11-14 l2u_rax (l2u region x attribute register) 11-15 l2u_rbax (l2u region x base address register) 11-14 lctrl2 (l-bus support control register 2) 23-48 mios14sr0 (interrupt status register) 17-66 mios14sr1 (interrupt status register) 17-67 , 17-68 mios1lvl0 (mios1 interrupt level register 0) 17-69 mios1lvl1 (mios1 interrupt level 1 register) 17-70 miscnt (misc counter) 20-6 , 21-5 , 21-9 misrh (multiple input signature register high) 20-5 misrl (multiple input signature register low) 20-6 portqs (port qs data register) 15-12 pqspar (portqs pin assignment register) 15-13 presdiv (prescaler divide register) 16-29 qacr1 (qadc64e control register 1) 13-16 , 14-16 qadcmcr (module configuration register) 13-8 qsci1cr (qsci1 control register) 15-60 qsci1sr (qsci1 status register) 15-61 qsmcmmcr (qsmcm module configuration regis- ter) 15-8 qspi_il (qspi interrupt level register) 15-10 readi dta 1 and dta 2 (readi data trace at- tributes 1 and 2 registers) 24-17 region attribute register (0 - 3) 4-22 sccxr0 (qsmcm sci control register 0) 15-46 mpc561/mpc563 reference manual, rev. 1.2 regindex-4 freescale semiconductor sccxr1 (qsmcm sci control register 1) 15-47 scdr (qsmcm sci data register) 15-51 scxsr (qsmcm scix status register) 15-49 spcr0 (qspi control register 0) 15-17 spcr1 (qspi control register 1) 15-19 spcr2 (qspi control register 2) 15-20 spcr3 (qspi control register) 15-21 sprg0-sprg3 (general sp ecial-purpose registers 0-3) 3-24 spsr (qspi status register) 15-21 srr0 (machine status save/restore register 0) 3-23 tbref1 (time base reference register 1) 6-41 ticr (tpu3 interrupt configuration register) 19-14 tpumcr (tpu3 module configuration register) 19-11 tpumcr2 (tpu3 module configuration register 2) 19-19 tpumcr3 (tpu3 module configuration register 3) 19-21 , 19-22 uc3fcfig (hard reset configuration word) 21-16 uc3fctl (uc3f eeprom high voltage control reg- ister 21-11 uipend (uimb pending interrupt reqiuest register) 12-9 umcr (uimb module configuration register) 12-7 xer (integer exception register) 3-18 registers associated registers 10-4 bar (breakpoint address register) 23-53 bbcmcr (bbc module confi guration register) 4-19 br0 - br3 (memory controller base registers 0-3) 10-32 breakpoint counter b value and control register (countb) 23-46 calrlam_otr (calram ownership trace regis- ter) 22-17 cmpa-cmpd (comparator a-d value registers ) 23-41 cmpe-cmpf (comparator e-f value registers) 23-46 cmpg-cmph (comparator g-h value registers) 23-47 colir (change of lock register) 8-36 counta (breakpoint coun ter a value and control register) 23-45 countb (breakpoint coun ter b value and control register) 23-46 cram_rbax (calram region base address regis- ter) 22-15 crammcr (calram module configuration regis- ter) 22-13 cramovl (calram overlay configuration regis- ter) 22-17 dec (decrementer register) 6-40 der (debug enable register) 23-43 dmbr (dual mapping base register) 10-36 dpdr (development port data register) 23-53 dptram module configuration register (dptmcr) 20-3 ram base address register (rambar) 20-4 dual mapping option register 10-37 ecr (exception cause register) 23-41 eibadr (external interrupt relocation table base ad- dress register) 4-25 emcr (external master control register) 6-29 general-purpose i/o registers 6-46 gpdi (general-purpose data in register) 18-19 gpdo (general-purpose data out register) 18-18 ictrl (i-bus support control register) 23-51 , a-16 internal memory map register 6-28 keep alive power registers lock mechanism 8-25 l2u global region attribute register (l2u_gra) 11-16 module configuration register (l2u_mcr) 11-13 region attribute registers (l2u_rax) 11-15 region base address registers (l2u_rbax) 11-14 lctrl1 (l-bus support control register 1) 23-47 lctrl1 (l-bus support control register 2) 23-48 mbism interrupt registers 17-69 mcpsmscr (mcpsm status/control register) 17-18 mdasmscr (mdasm status/control register) 17-43 mi_gra (global region attribute register) 4-23 mi_ra 1 - 3 (region base address registers (1 - 3)) 4-22 mi_rba 0 - 3 (region base address registers (0 - 3)) 4-21 mios bus interface (mbism) registers 17-13 mios1 interrupt level register 0 (mioslvl0) (mios1lvl1) 17-69 interrupt level register 1 (mioslvl1) (mios1lvl0) 17-70 module and version number register (mios1vnr) 17-14 mios14er0 interrupt enable register 17-66 mios14er1interrupt enable register 17-68 mios14mcr (mios14 module configuration regis- ter) 17-15 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor regindex-5 mios14rpr0 request pending register 17-66 mios14rpr1 request pending register 17-68 mios14sr0 interrupt status register 17-65 , 24-8 mios14sr1interrupt status register 17-67 mios14tpcr (test and pin control register) 17-13 , 17-14 miscnt (misc counter) 20-6 mmcsmcnt (mmcsm up-counter register) 17-23 mmcsmmml (mmcsm modulus latch register) 17-24 mmcsmscr (mmcsmstatus/control register) 17-24 mpiosmddr (mpiosm data direction register) 17-63 mpiosmdr (mpiosm data register) 17-62 mpwmcntr (mpwmsm counter register) 17-58 mpwmperr (mpwmsm period register) 17-57 mpwmpulr (mpwmsm pulse width register) 17-57 mpwmscr (mpwmsm status/control register) 17-58 mstat (memory co ntroller status registers) 10-32 or0 - or3 (memory controller option registers 0-3) 10-34 pdmcr (pads module configuration register) 2-22 pdmcr2 (pads module c onfiguration register) 2-23 piscr (periodic interrupt st atus and control register) 6-44 pitc (periodic interrupt timer count register) 6-45 pitr (periodic interrupt timer register) 6-45 plprcr (pll, low-power, an d reset-control register) 8-33 port data direction registers 13-14 , 14-13 port data registers 13-13 , 14-12 ppmmcr (module confguration register) 18-10 ppmpcr (ppm control register) 18-12 qacr0 (qadc64e control register 0) 13-14 , 14-14 qacr1 (qadc64e control register 1) 13-15 , 14-16 qacr2 (qadc64e control register 2) 13-17 , 14-18 qadcint (qadc64e interrupt register) 13-12 , 14-11 qadcmcr (module configuration register) 14-8 qasr (status register 0) 14-22 qasr (status registers) 13-20 qsmcm configuration register (qmcmmcr) 15-8 interrupt level register s (qdsci_il, qspi_il) 15-9 port qs data register (portqs) 15-11 portqs data direction register (ddrqs) 15-13 portqs pin assignment register (pqspar) 15-12 qsci1 control register (qsci1cr) 15-60 qsci1 status register (qsci1sr) 15-61 qspi command ram (crx) 15-23 qspi control register 0 (spcr0) 15-17 qspi control register 1 (spcr1) 15-19 qspi control register 2 (spcr2) 15-20 qspi control register 3 (spcr3) 15-20 qspi registers 15-16 qspi status register (spsr) 15-21 queued sci1 status and control registers 15-59 sci control register 0 (sccxr0) 15-46 sci control register 1 (sccxr1) 15-47 sci data register (scxdr) 15-50 sci registers 15-45 sci status register (scxsr) 15-48 test register (qtest) 15-9 rcpu additional implementation-specific registers 3-27 condition register (cr) 3-16 condition register cr0 field definition 3-17 condition register cr1 field definition 3-17 condition register crn fiel d - compare instruction 3-17 count register (ctr) 3-19 dae/source instruction se rvice register (dsisr) 3-22 data address register (dar) 3-23 decrementer register (dec) 3-23 eie, eid, and nri special-purpose registers 3-25 floating-point exception cause register (fpecr) 3-26 floating-point registers (fprs) 3-12 floating-point status and control register (fpscr) 3-13 general special-purpose registers (sprg0-sprg3) 3-24 general-purpose registers (gprs) 3-12 implementation-specific sp ecial-purpose registers 3-25 integer exception register (xer) 3-18 link register (lr) 3-19 machine state register (msr) 3-20 machine status save/res tore register 0 (srr0) 3-23 machine status save/res tore register 1 (srr1) 3-23 mpc561/mpc563 reference manual, rev. 1.2 regindex-6 freescale semiconductor oea register set 3-20 processor version register (pvr) 3-25 uisa register set 3-12 vea register set - time base 3-20 readi development control register 24-10 , 24-11 readi did 24-9 readi dta 1 and dta 2 (readi data trace at- tributes 1 and 2 registers) 24-17 readi rwa (readi read/write access register) 24-13 readi uba (readi user base address register) 24-12 readi udi (readi upload/ download information register) 24-15 rsr (reset status register) 7-5 rtc (real-time clock register) 6-43 rtcal (real-time clock alarm register) 6-44 rtcsc (real-time clock stat us and control register) 6-42 rx_config_1 (rx configuration register 1) 18-16 rx_config_2 (rx configuration register 2) 18-16 rx_data register 18-17 rx_shifter register 18-18 rxectr (receive error counter) 16-36 scale_tclk_reg (scal e tclk register) 18-24 sccr (system clock control register) 8-29 sgpio control register (sgpiocr) 6-48 data register 1 (sgpiodt1) 6-46 data register 2 (sgpiodt2) 6-47 short_ch_reg (short channels register) 18-22 short_reg (short register) 18-19 simask (siu interrupt mask register) 6-33 simask2 (siu interrupt mask register 2) 6-34 simask3 (siu interrupt mask register 3) 6-35 sipend (siu interrupt pending register) 6-32 sipend2 (siu interrupt pending register 2) 6-32 sipend3 (siu interrupt pending register 3) 6-33 siu interrupt edge level register (siel) 6-35 interrupt mask register (simask) 6-33 interrupt registers 6-31 interrupt vector register (sivec) 6-35 siu interrupt in-s ervice register 6-37 siumcr (siu module configuration register) 6-25 swsr (software service register) 6-38 sypcr (system protection control register) 6-37 system configuration an d protection registers 6-24 system configur ation registers 6-24 system protection registers 6-37 system timer registers 6-40 tbref0 (time base reference registers) 6-41 tbscr (time base control and status register) 6-42 tesr (transfer error status register) 6-39 timer (free running timer register) 16-31 toucan canctrl0 (control register 0) 16-27 canctrl1 (control register 1) 16-28 canctrl2 (control register 2) 16-30 canicr (interrupt configuration register) 16-27 canmcr (module configuration register) 16-25 estat (error and status register) 16-33 iflag (interrupt flag register) 16-36 imask (interrupt mask register) 16-35 presdiv (prescaler divide register) 16-29 receive buffer 14 mask registers 16-32 receive buffer 15 mask registers 16-33 receive mask registers 16-7 rxgmskhi (receive glob al mask registers) 16-31 test configuration register 16-27 tpu3 channel function select registers (cfsrx) 19-15 channel interrupt enab le register (cier) 19-15 channel interrupt status register (cisr) 19-19 channel priority registers (cprx) 19-18 development support control register (dscr) 19-12 development support status register (dssr) 19-13 host sequence registers (hsqrx) 19-16 host service request registers (hssrx) 19-17 interrupt configuration register (ticr) 19-14 module configuration register (tpumcr) 19-11 module configuration register 2 (tpumcr2) 19-19 module configuration register 3 (tpumcr3) 19-21 service grant latch register (sglr) 19-22 tx_config_1 (tx confi guration register 1) 18-15 tx_config_2 (tx confi guration register 2) 18-15 tx_data register 18-18 uc3fcfig (hard reset configuration word) 21-16 uc3fctl (uc3f eeprom high voltage control reg- ister 21-11 uimb module configuration register (umcr) 12-7 pending interrupt reque st register (uipend) 12-8 test control register (utstcreg) 12-8 vsrmsr (vddsrm sensor register) 8-37 rsr (reset status register) 7-5 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor regindex-7 rtc (real-time clock register) 6-43 rtcal (real-time cloc k alarm register) 6-44 rtcsc (real-time clock stat us and control register) 6-42 rx data register 18-17 rx shifter register 18-18 rx_config_1 (rx configuration register 1) 18-16 rx_config_2 (rx configuration register 2) 18-16 rxectr (receive error counter) 16-36 s scale_tclk_reg (scal e tclk register) 18-24 sccr (system clock control register) 8-29 sccxr0 (qsmcm sci control register 0) 15-46 sccxr1 (qsmcm sci control register 1) 15-47 scdr (qsmcm sci data register) 15-51 scxsr (qsmcm scix status register) 15-49 sgpio control register (sgpiocr) 6-48 data register 1 (sgpiodt1) 6-46 data register 2 (sgpiodt2) 6-47 short_ch_reg (short channels register) 18-22 short_reg (short register) 18-19 simask (siu interrupt mask register) 6-33 simask2 (siu interrupt mask register 2) 6-34 simask3 (siu interrupt mask register 3) 6-35 sipend (siu interrupt pending register) 6-32 sipend2 (siu interrup t pending register 2) 6-32 sipend3 (siu interrup t pending register 3) 6-33 siu interrupt edge level register (siel) 6-35 interrupt mask register (simask) 6-33 interrupt registers 6-31 interrupt vector register (sivec) 6-35 siu interrupt in-s ervice register 6-37 siumcr (siu module configuration register) 6-25 spcr0 (qspi control register 0) 15-17 spcr1 (qspi control register 1) 15-19 spcr2 (qspi control register 2) 15-20 spcr3 (qspi control register) 15-21 sprg0-sprg3 (general speci al-purpose registers 0-3) 3-24 spsr (qspi status register) 15-21 srr0 (machine status save/restore register 0) 3-23 swsr (software service register) 6-38 sypcr (system protection control register) 6-37 system configuration an d protection registers 6-24 system configuration registers 6-24 system protection registers 6-37 system timer registers 6-40 t tbref0 (ime base reference registers) 6-41 tbref1 (time base reference register 1) 6-41 tbscr (time base control and status register) 6-42 tesr (transfer error status register) 6-39 ticr (tpu3 interrupt configuration register) 19-14 timer (free running timer register) 16-31 toucan canctrl0 (control register 0) 16-27 canctrl1 (control register 1) 16-28 canctrl2 (control register 2) 16-30 canicr (interrupt configuration register) 16-27 canmcr (module configuration register) 16-25 estat (error and status register) 16-33 iflag (interrupt flag register) 16-36 imask (interrupt mask register) 16-35 presdiv (prescaler divide register) 16-29 receive buffer 14 mask registers 16-32 receive buffer 15 mask registers 16-33 receive mask registers 16-7 rxgmskhi (receive global mask registers) 16-31 test configuration register 16-27 tpu3 channel function select registers (cfsrx) 19-15 channel interrupt enable register (cier) 19-15 channel interrupt status register (cisr) 19-19 channel priority registers (cprx) 19-18 development support control register (dscr) 19-12 development support status register (dssr) 19-13 host sequence registers (hsqrx) 19-16 host service request registers (hssrx) 19-17 interrupt configuration register (ticr) 19-14 module configuration register (tpumcr) 19-11 module configuration register 2 (tpumcr2) 19-19 module configuration register 3 (tpumcr3) 19-21 service grant latch register (sglr) 19-22 tpumcr (tpu3 module configuration register) 19-11 tpumcr2 (tpu3 module configuration register 2) 19-19 tpumcr3 (tpu3 module configuration register 3) 19-21 , 19-22 tx data register 18-18 tx_config_1 (tx confi guration register 1) 18-15 tx_config_2 (tx confi guration register 2) 18-15 u uc3fcfig (hard reset configuration word) 21-16 uc3fctl (uc3f eeprom high voltage control register 21-11 uimb module configuration register (umcr) 12-7 pending interrupt request register (uipend) 12-8 test control register (utstcreg) 12-8 uipend (uimb pending interrupt reqiuest register) 12-9 umcr (uimb module configuration register) 12-7 v vsrmsr (vddsrm mpc561/mpc563 reference manual, rev. 1.2 regindex-8 freescale semiconductor sensor register) 8-37 x xer (integer exce ption register) 3-18 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-1 a accesses clock requirements 13-52 , 14-51 ackerr 16-34 acknowledge error (ackerr) 16-34 addr[8:31] 9-4 , 9-37 address -mark wakeup 15-59 address bus 9-37 address space 13-11 address type (at[0:3]), 9-38 ale 23-42 alee 23-44 alignment exception 3-49 alu?bfu 3-5 an 13-7 , 14-6 analog front-end multiplexer 13-36 , 14-37 input considerations 13-73 , 14-71 pins 13-71 , 14-70 power pins 13-67 , 14-66 reference pins 13-71 , 14-70 section contents 13-2 , 14-2 submodule block diagram 13-34 , 14-36 supply filtering and grounding 13-69 , 14-67 pins 13-67 , 14-66 to digital converter operation 13-34 , 14-36 arbitration, 9-32 at[0:3] 9-4 atomic 9-32 atomic operation reservation of data 11-7 atomic update primitives, 3-43 b bar 3-60 , 23-53 base id mask bits 16-32 , 16-33 baud clock 15-52 bb 9-7 bbcmcr 4-19 bdip, 9-5 be bit 3-21 beginning of queue 2 (bq2) 13-19 , 14-20 bg 9-7 bi 9-7 , 9-40 binary divider 13-47 , 14-48 -weighted capacitors 13-36 , 14-37 bit stuff error (stufferr) 16-34 biterr 16-34 bits 15-18 bits per transfer enable (bitse) 15-24 field (bits) 15-18 bitse 15-24 , 15-39 bit-time 15-51 biu 13-2 , 13-51 , 14-2 , 14-51 biusm biutest ? biusm test configuration register 17-13 selecting the time base bus 17-13 bkpt (tpu asserted) 19-14 blc 19-12 block diagram calram 22-2 dptram 20-2 jtag test logic 25-3 l2u 11-2 memory controller 10-2 mios 17-1 mpc561/mpc563 1-2 readi 24-3 readi signal interface 24-22 toucan 16-1 uc3f eeprom 21-1 uimb 12-2 usiu 6-3 block diagrams analog subsystem 13-34 bbc module 4-2 clock 8-2 decram interfaces 4-13 mpc561/mpc563 signals 2-2 rcpu 3-1 usiu 5-2 boffint 16-35 boundary conditions 13-40 , 14-41 boundary scan register 25-4 index mpc561/mpc563 reference manual, rev. 1.2 index-2 freescale semiconductor bpu 3-4 , 3-5 bq2 13-19 , 13-40 , 14-20 , 14-41 br 9-7 branch prediction 3-5 processing unit 3-5 trace enable 3-21 branch latch control (blc) 19-12 branch processing unit 3-4 branch target buffer 4-14 break frame 15-52 breakpoint asserted flag (bkpt) 19-14 flag (pcbk) 19-14 breakpoint counter a value and control register 23-45 breakpoint counter b value and control register 23-46 breakpoints 23-9 brknomsk 23-50 brx registers 10-32 btb 4-14 burst 9-4 , 9-37 burst indicator (burst), 9-37 burst inhibit (bi), 9-40 burst read cycle (illustration), 9-21 burst transfer, 9-17 burst write cycle (i llustration), 9-26 bus monitor 6-17 off interrupt (boffint) 16-35 bus busy (bb), 9-34 bus exception control cycles, 9-45 bus grant (bg), 9-33 bus interface bus control signals, 9-2 bus operation address transfer phase related signals, 9-37 arbitration phase, 9-32 basic transfer protocol, 9-8 burst mechanism, 9-18 burst transfer, 9-17 bus exception control cycles, 9-45 single beat transfer single beat read flow, 9-9 single beat write flow, 9-9 , 9-11 single beat transfer, 9-9 storage reservation, 9-42 termination signals, 9-40 bus operations, 9-8 bus transfer signals, 9-1 features, 9-1 signal descriptions, 9-3 bus interface unit (biu) 13-2 , 14-2 components 13-51 , 14-51 bus request (br), 9-33 bus signals (illustration), 9-3 busy 16-16 receive message buffer code 16-5 byp 13-30 , 13-35 , 14-31 bypass mode 13-35 bytes field 3-19 c ca bit 3-19 cache control instructions, 3-43 calram clps 22-8 , 22-9 , 22-10 operation modes 22-4 privileges 22-5 can2.0b system 16-3 canctrl0 16-27 canctrl1 16-28 canctrl2 16-30 canicr 16-27 carry 3-19 ccl 19-13 ccw 13-2 , 13-27 , 14-2 , 14-28 censorship states 21-30 c f 13-75 , 14-73 cf1 13-21 , 14-22 cf2 13-22 , 14-23 cfsr 19-15 cgbmsk 23-48 ch 19-15 , 19-18 , 19-19 chan 13-31 , 14-32 channel 19-16 channel assignments multiplexed 13-32 nonmultiplexed 13-31 conditions latch (ccl) 19-13 interrupt enable /disable field (ch) 19-15 request level (cirl) 19-15 status (ch) 19-19 invalid 13-31 number (chan) 13-31 , 14-32 orthogonality 19-4 priority registers 19-18 register breakpoint flag (chbk) 19-14 reserved 13-31 charge sharing 13-76 , 14-73 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-3 chbk 19-14 chbmsk 23-48 check stop state 23-26 checkstop 7-3 checkstop enable 3-47 chip-select global 10-27 chstp bit 23-42 chstpe 23-43 chstpe bit 3-47 cie1 13-16 , 14-17 cie2 13-18 , 14-19 cier 19-15 , 19-19 cirl 19-15 cisr 19-8 , 19-19 class, instruction, 3-40 clkout 8-13 clkout to ta, bi assertion (when driven by the memory controller) f-21 , f-22 , g-21 clkout, 9-8 clks 19-12 clock block diagram 13-48 , 14-49 frequency 13-48 generation 13-47 , 14-48 phase (cpha) 15-18 polarity (cpol) 15-18 requirements 13-52 , 14-51 clocks general system 8-10 clps 22-9 clps bit 22-8 , 22-9 , 22-10 cmpa?cmpd 23-41 cmpe?cmpf 23-46 cmpg?cmph 23-47 cnrx/tx pins 16-2 cntc 23-45 cntv 23-45 code message buffer field 16-4 code decompression features a-1 modes of a-14 coherency 13-45 , 13-52 , 14-46 , 14-51 coherency 19-4 data coherency during reset 7-4 colir 8-36 comm d-17 command ram 15-23 command word pointer (cwp) 13-24 , 13-27 , 14-25 , 14-28 comparator 13-37 , 14-38 comparator a?d value registers 23-41 comparator e?f value registers 23-46 comparator g?h value registers 23-47 compare instructions 3-17 compare size 23-48 compare type 23-47 , 23-51 , a-17 completed queue pointer (cptqp) 15-22 compressed address generation direct branches a-4 exceptions a-6 indirect branches a-6 compression readi a-16 compression, code algorithm a-2 features of a-1 implementation of a-11 compression, environment initialization of a-13 condition register 3-16 , 3-17 configuration soft reset 7-13 configuration word hard reset (rcw) 7-11 cont 15-24 contention, 9-37 continue (cont) 15-24 continuous transfer mode 15-16 control registers 0 (qacr0) 13-7 , 14-7 1 (qacr1) 13-7 , 14-7 2 (qacr2) 13-7 , 14-7 qadc64e control register 1 (qacr1) 13-15 , 14-16 qadc64e control register 2 (qacr2) 13-17 , 14-18 controlling termination of a bu s cycle for a bus error, 9-45 conversion command word table (ccw) 13-2 , 13-27 , 13-37 , 14-2 , 14-28 , 14-38 cycle times 13-35 , 14-36 stages 13-29 , 14-30 conversion queue operation 14-29 count register 3-19 counta 23-45 , 23-51 countb 23-46 cpha 15-18 , 15-35 cpol 15-18 , 15-35 cpr 19-18 cptqp 15-22 , 15-25 cpu wait states 13-52 , 14-51 cr 3-5 , 3-16 , 3-19 , 9-5 and compare instructions 3-17 mpc561/mpc563 reference manual, rev. 1.2 index-4 freescale semiconductor cr0 field 3-17 cr1 field 3-17 cram_otr register 22-18 cram_ovlcr register 22-17 cram_rbax register 22-16 crammcr register 22-13 crcerr 16-34 crwe 23-47 crwf 23-47 csg 23-48 csh 23-48 cta 23-51 , a-17 ctb 23-51 , a-17 ctc 23-51 , a-17 ctd 23-51 , a-17 cte 23-47 ctf 23-47 ctg 23-47 cth 23-47 ctr 3-5 cwp 13-24 , 13-27 , 14-25 , 14-28 cyclic redundancy check error (crcerr) 16-34 d dac 13-2 , 14-2 dae/source instruction service register 3-22 dar 3-23 , 3-48 , 3-59 dar, 3-48 , 3-59 data frame 15-52 data [0:31] 9-6 data address register 3-23 data memory protection unit 11-1 data reservation 11-7 data storage interrupt, 3-48 dc 24-10 dccr 4-25 dccr0-15 a-19 ddrqs 15-10 , 15-34 , 15-39 debug enable register 23-53 debug mode 23-21 dec 3-23 , 6-18 , 6-40 dece 23-42 decee 23-44 decompression features a-1 modes of a-14 decrementer register 3-23 decrementer 6-18 decrementer exception 3-53 deep-sleep 6-23 delay after transfer (dt) 15-24 , 15-36 before sck (dsckl) 15-19 der 23-43 , 23-53 development port trap enable selection 23-52 , a-17 development port 23-28 development support debug mode 23-21 instruction support 23-14 port registers 23-30 program trace 23-4 protection features 23-40 registers 23-39 system interface 23-19 watchpoints 23-9 did 24-9 digital control section contents 13-2 , ??? 13-34 , 13-37 ???, 14-2 , ??? 14-35 , 14-38 ??? input/output port (pqa) 13-66 , 14-65 to analog converter (dac) 13-2 , 13-36 , 14-2 , 14-37 dio d-46 disable tpu2 pins field (dtpu) 19-20 disabled mode 13-41 , 14-42 discrete input/output (dio) d-46 div2 19-19 div8 clock 19-7 divide by two control field (div2) 19-19 diw0en 23-52 , a-17 diw1en 23-52 , a-17 diw2en 23-52 , a-17 diw3en 23-52 , a-17 dlw0en 23-50 dlw1en 23-50 dmbr register 10-36 dmor register 10-37 dmpu 11-1 double -buffered 15-54 , 15-57 doze 6-23 dpi 23-43 dptmcr 20-3 dptram 20-4 dptram operation 20-6 dsck 15-24 dsckl 15-19 dscr 19-12 dsisr 3-22 , 3-48 , 3-50 , 3-59 dssr 19-13 dt 15-24 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-5 dta1 24-17 dta2 24-17 dtl 15-19 dtpu 19-20 e ea 3-34 ebrk 23-43 ecr 23-41 ee bit 3-21 , 3-25 eeprom mapping 10-24 effective address 3-34 eibadr 4-25 eid 3-25 eie 3-25 ele bit 3-21 emcr 6-29 empty receive message buffer code 16-5 emu 19-4 , 19-11 emulation control (emu) 19-11 support 19-4 encoded one of three channel priority levels (ch) 19-18 time function for each ch annel (ch annel) 19-16 type of host service (ch) 19-18 ending queue pointer (endqp) 15-20 end-of- frame (eof) 16-17 end-of-queue condition 13-29 , 14-30 endqp 15-20 , 15-25 engclk 8-14 entry table bank select field (etbank) 19-20 eof 16-17 eoq 13-40 , 14-41 ep bit 3-21 , 3-22 errint 16-35 error conditions 15-57 interrupt (errint) 16-35 resulting from leakage 13-75 , 14-73 error counters 16-10 estat 16-33 etbank 19-20 etrig 13-67 , 13-71 , 14-66 , 14-69 event timing 19-3 exception cause register 23-41 exception prefix 3-21 , 3-22 exception table 4-7 exceptions 3-34 alignment 3-49 classes 3-35 decrementer 3-53 external interrupt 3-48 little endian mode 3-21 ordered 3-35 precise 3-36 program 3-51 system call 3-54 unordered 3-35 vector table 3-36 exceptions compressed address generation a-6 data storage 3-48 execution units 3-4 extended message format 16-1 frames 16-4 external interrupt disable 3-25 enable 3-25 leakage 13-76 , 14-73 trigger continuous-scan mode 13-46 , 14-47 trigger pins 13-67 , 14-66 trigger single-scan mode 13-43 , 14-44 external interface uc3f 21-4 external device arbitration phase 9-32 priority of 9-35 usiu address decoding 6-6 external interrupt 3-48 enable 3-21 , 3-25 external interrupt enhanced 4-10 external master memory controller 10-28 external master control register (emcr) 6-29 externally multiplexed mode (mux) 13-15 exti 23-42 extie 23-44 f fast quadrature decode tpu function (fqd) d-35 fault confinement state (fcs) 16-11 , 16-34 fcs 16-11 , 16-34 fe 15-50 , 15-57 fe bits 3-21 , 3-22 features biu 4-2 mpc561/mpc563 reference manual, rev. 1.2 index-6 freescale semiconductor bus interface, 9-1 fetch serialized 23-1 fex bit 3-14 fi 3-15 final sample time 13-35 , 14-36 floating-point available 3-21 enabled exception summary 3-14 exception mode 3-21 , 3-22 exception summary 3-14 fraction inexact 3-15 fraction rounded 3-15 inexact exception 3-14 enable 3-15 invalid operation exception enable 3-15 for *0 3-14 for / 3-14 for - 3-14 for 0/0 3-14 for invalid compare 3-15 for snan 3-14 summary 3-14 invalid operation exception for invalid integer convert 3-15 invalid operation exception for invalid square root 3-15 invalid operation exception for software request 3-15 overflow exception 3-14 enable 3-15 registers 3-12 result flags 3-15 rounding control 3-16 status and control register 3-13 underflow exception 3-14 unit 3-5 zero divide exception 3-14 , 3-15 formerr 16-34 fp bit 3-21 fpecr 3-26 fprf 3-15 fprs 3-12 fpsck 19-20 fpscr 3-13 fpu 3-5 fpuve 23-42 fpuvee 23-44 f qclk 13-47 , 14-48 fqd d-35 fqm d-10 fr 3-15 frame size 15-58 frames overload 16-17 remote 16-17 framing error (fe) flag 15-50 , 15-57 freez ack 16-18 freeze assertion response (frz) qsm 15-6 tpu 19-13 freeze enable (frz) 13-8 , 14-8 mode 13-9 freeze (internal signal) 13-10 , 13-30 , 14-9 , 14-31 freeze operation 6-23 frequency measurement (fqm) d-10 parameters d-12 frz 13-8 , 14-8 , 16-13 , 19-13 , 23-29 frzack 16-13 full receive message buffer code 16-5 function library for tpu 19-4 fx bit 3-14 g general purpose chip -select machine 10-3 general sprs 3-24 general-purpose registers (gprs) 3-12 global registers 13-7 gpcm 10-3 h hall effect decode (halld) d-20 halld d-20 halt 15-21 , 16-13 halt acknowledge flag (halta) 15-22 qspi (halt) 15-21 halta 15-22 halta and modf interrupt enable (hmie) 15-42 halta/modf interrupt enable (hmie) bit 15-21 hang on t4 (hot4) 19-12 hard reset 7-2 hard reset configuration word (rcw) 7-11 hmie 15-21 hot4 19-12 hreset 7-2 hsqr 19-16 hssr 19-17 i ibrk 23-43 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-7 i-bus watchpoint programming 23-51 , a-17 icdu features a-1 ictrl a-16 id extended (ide) field 16-6 high field 16-6 low field 16-6 ide 16-6 identifier (id) 16-1 bit field for stan dard format 16-6 idle 15-49 , 15-58 , 16-34 idle can status (idle) 16-34 frame 15-52 -line detect type (ilt) 15-47 detected (idle) 15-49 , 15-58 detection process 15-58 interrupt enable (ilie) 15-48 , 15-58 type (ilt) bit 15-58 iflag 16-36 ignore first match 23-52 , a-18 iifm 23-52 , a-18 ilbs 12-4 ilie 15-48 , 15-58 illegal and reserved instructions, 3-40 ilsci 15-9 , 15-10 ilt 15-47 , 15-58 imask 16-35 imb 13-47 , 14-48 imb clock 12-2 immr 6-28 implementation dependent software emulation interrupt, 3-56 implementation specific data tlb error interrupt, 3-58 implementation specific debug interrupt, 3-59 implementation specific instruction tlb error interrupt, 3-57 imul?idiv 3-5 information processing time (ipt) 16-10 initial sample time 13-35 , 14-36 input sample time (ist) 13-31 , 13-49 , 14-32 instruction pipeline 3-38 sequencer 3-3 set summary 3-28 timing 3-37 instruction fetch show cycle control 23-1 instruction storage interrupt, 3-48 instruction support 23-14 instructions cache control, 3-43 storage control, 3-45 instructions, partially executed, 3-60 integer exception register 3-18 integer unit 3-5 interchannel communication 19-4 intermission 16-17 internal bus arbiter 9-35 interrupt register (qadcint) 13-7 , 13-12 , 14-11 interrupt external 3-48 interrupt controller enhanced 6-8 interrupt level byte select 12-4 interrupt level of sci (ilsci) 15-9 , 15-10 interrupts toucan 16-20 tpu 19-5 interrupts mios 17-63 uimb 12-3 interrupts, 3-45 inter-transfer delay 15-15 interval timer single-scan mode 13-44 , 14-45 invalid and preferred instructions, 3-40 invalid channel number 13-31 ipt 16-10 iramstby 8-23 , 22-5 irq 19-5 isctl 23-1 ist 13-31 , 13-49 , 14-32 iu 3-5 iw 23-51 , a-17 iwpn 23-30 iwpnand vflsn 23-30 j jtag instruction register 25-30 pin diagram 25-1 reset 7-3 k kapwr 8-22 registers 8-26 keep alive power 8-24 keep-alive power 22-5 kr/retry, 9-5 mpc561/mpc563 reference manual, rev. 1.2 index-8 freescale semiconductor l l2u 11-1 modes of operation 11-3 l2u module configuration register (l2u_mcr) 11-13 l2u_gra 11-16 l2u_mcr 11-13 l2u_rax 11-15 l2u_rbax 11-14 lbrk 23-43 lbuf 16-29 l-bus support control register 1 23-47 control register 2 23-48 l-bus to u-bus interface unit 11-1 lctrl1 23-47 lctrl2 23-48 le bit 3-22 least significant bit (lsb) 13-36 , 14-38 length of delay after transfer (dtl) 15-19 link register 3-19 little endian mode 3-22 ljsrr 13-33 , 14-35 ljurr 13-33 , 14-35 load/store unit 3-4 , 3-6 lock /release/busy mechanism 16-16 loop mode (loops) 15-47 loopq 15-21 loops 15-47 low power stop 6-23 low power stop (lpstop) qsm 15-6 lowest buffer transmitted first (lbuf) 16-29 low-power stop mode enable (stop) tpu 19-11 lr 3-5 , 3-19 lsb 13-36 , 14-38 lsu 3-4 , 3-6 lw0en 23-49 lw0ia 23-49 lw0iadc 23-49 lw0la 23-49 lw0ladc 23-49 lw0ld 23-49 lw0lddc 23-49 lw1en 23-49 lw1ia 23-49 lw1iadc 23-49 lw1la 23-50 lw1ladc 23-50 lw1ld 23-50 lw1lddc 23-50 m m15-47 , 15-52 ma 13-14 machine check enable 3-21 state register 3-20 status save/restore register 0 3-23 status save/restore register 1 3-23 machine check enable 3-47 machine check exception enable 3-47 mapping dual 10-26 eeprom 10-24 mask examples for normal/extended messages 16-8 registers (rx) 16-7 master /slave mode select (mstr) 15-18 master external arbitration phase 9-32 mbism 17-13 mc 24-11 mce 23-42 mcee 23-43 mcie bit 3-47 mcpsm 17-16 mcpsmscr 17-18 mcpwm d-22 , d-30 mdasm submodule 17-70 mdasmar 17-41 mdasmbr 17-42 mdasmscr 17-44 mdasmscrd 17-43 me bit 3-21 , 3-47 memory controller registers 10-31 memory map 1-11 tpu 19-1 message buffer address map 16-24 code for rx/tx buffers 16-5 deactivation 16-14 structure 16-4 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-9 format error (formerr) 16-34 message can bus transmission 16-13 messaging readi 24-4 , 24-22 mi_gra 4-23 mi_ra [0:3] 4-22 mi_rba[0:3] 4-21 mios14 16-bit parallel port i/o submodule (mpiosm) 17-60 bus interface submodule (mbism) 17-13 counter prescaler submodule (mcpsm) 17-16 double action submodule (mdasm) 17-26 , 17-70 interrupt request submodule (mirsm) 17-64 interrupts 17-63 modulus counter submodule (mmcsm) 17-19 pulse width modulation submodule (mpwmsm) 17-46 mios14er0 17-66 mios14er1 17-68 mios14lvl0 17-69 mios14lvl1 17-70 mios14mcr 17-15 mios14rpr0 17-67 mios14rpr1 17-68 mios14sr0 17-66 mios14sr1 17-67 mios14tpcr 17-14 mios14vect 17-14 mios14vnr 17-14 misc 20-8 miscnt 20-6 miso 15-34 , 15-39 misrh 20-5 misrl 20-5 mmcsm 17-19 mmcsmcnt 17-23 mmcsmml 17-24 mmcsmscr 17-24 mmcsmscrd 17-24 mode fault flag (modf) 15-22 , 15-27 select (m) 15-47 mode fault flag (modf) 15-42 modes stop 14-8 modes bbc operation 4-4 calram operation 22-4 censorship modes of uc3f 21-31 clock frequency for each 8-17 code decompression a-14 debug operation of bbc 4-7 decram standby operation 4-14 disabled 13-41 , 14-42 dptram operation 20-6 external master 6-4 freeze 13-9 interrupt controller e nhanced operation 6-11 interrupt controller regular operation 6-10 jtag 25-3 l2u operation 11-3 limp support 8-14 low power 8-16 low-power 6-23 mios14 mdasm operation 17-3 , 17-29 mpc561/563 development support signals 2-29 readi 24-3 reserved 13-41 , 14-42 scan. see scan modes stop 13-9 toucan 16-17 modf 15-22 , 15-27 , 15-42 module configuration register (qadc64e) 13-8 module configuration register (qadcmcr) 14-8 modulus counter 15-52 mosi 15-34 , 15-39 most significant bit (msb) 13-36 , 14-38 mpc561/mpc563 block diagram 1-2 differences from mpc555 1-9 memory map 1-11 optional features 1-9 vflsn and mpio32b 23-30 mpiosm 17-60 mpiosmddr 17-63 mpiosmdr 17-62 mpwmcntr 17-58 mpwmperr 17-57 mpwmpulr 17-58 mpwmscr 17-58 mq1 13-16 , 14-17 mq2 13-18 , 14-19 msb 13-36 , 14-38 msr 3-20 , 3-46 , 3-48 , 3-49 , 3-50 , 3-52 , 3-53 , 3-54 , 3-55 , 3-56 , 3-57 , 3-59 , 3-60 mstat registers 10-32 mstr 15-18 multichannel pulse-width modulation (mcpwm) d-22 , d-30 parameters slave channel a mpc561/mpc563 reference manual, rev. 1.2 index-10 freescale semiconductor non-inverted center aligned mode d-48 slave edge-aligned mode d-23 multimaster operation 15-27 multiphase motor commutation (comm) d-17 multiple end-of-queue 13-40 , 14-41 multiple input signature calculator (misc) 20-8 multiplexed analog inputs 13-7 , 14-6 multiplexing signals 2-20 mux 13-15 n vflsn and mpio32b 23-30 negative stress 13-76 , 14-74 new queue pointer value (newqp) 15-20 new input capture/transistion counter (nitc) d-15 parameters d-15 newqp 15-20 , 15-25 nf 15-50 , 15-57 ni bit 3-16 nitc d-15 noise error flag (nf) 15-50 errors 15-57 flag (nf) 15-57 non-ieee floating-point operation 3-16 nonoptional instructions, 3-40 non-recoverable interrupt 3-25 not active receive message buffer code 16-5 not ready (notrdy) 16-21 notrdy 16-18 , 16-21 nri 3-25 o oc d-42 oe bit 3-15 op0 9-30 op1 9-30 op2 9-30 op3 9-30 open drain drivers 14-66 operand placement (effects), 3-43 operand representation (illustration), 9-30 operating environment architecture (book 3) branch processor, 3-44 exceptions, 3-45 fixed-point processor special purpose registers, 3-44 fixed-point processor, 3-44 optional facilities and instructions, 3-61 storage control instructions, 3-45 timer facilities, 3-61 operating environment architecture (oea) 3-44 optional instructions, 3-40 or 15-50 or registers 10-34 ordered exceptions 3-35 otr 24-8 output compare (oc) d-42 ov (overflow) bit 3-18 overload frames 16-17 overrun receive message buffer code 16-5 overrun error (or) 15-50 ox bit 3-14 p p 13-30 , 14-31 parameter ram 19-3 , 19-23 parity (pf) flag 15-57 checking 15-53 enable (pe) 15-47 error (pf) bit 15-50 errors 15-57 type (pt) 15-47 type (pt) bit 15-53 pause (p) 13-30 , 13-38 , 14-31 , 14-39 pcbk 19-14 pcs 15-24 to sck delay (dsck) 15-24 pcs0/ss 15-39 pcs3-pcs0/ss 15-42 pdmcr 2-22 pdmcr2 2-23 pe 15-47 performance l-bus 11-10 period /pulse-width accumulator (ppwa) d-38 periodic interrupt timer 6-20 periodic/interval timer 13-51 , 14-50 continuous-scan mode 13-47 , 14-48 peripheral chip-selects (pcs) 15-24 , 15-37 peripheral chip-select 3-0/slave select (pcs3-pcso/ss )15-42 pf 15-50 , 15-57 pf1 13-22 , 14-23 pf2 13-23 , 14-24 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-11 phase buffer segment 1/2 (pseg1/2) bit field 16-30 phase-lock loop, 9-8 pie1 13-16 , 14-17 pie2 13-18 , 14-19 piscr 6-44 pit 6-20 pitc 6-45 pitr 6-45 pll 8-3 loss of lock 7-2 pll, 9-8 plprcr 8-33 pointer 15-16 poreset 7-1 port a data register (portqa) 13-13 b data register (portqb) 13-13 port size device interfaces (illustration), 9-31 port width definition 9-1 portqa 13-13 portqb 13-13 portqs 15-11 positive stress 13-76 , 14-74 power on reset 7-1 ppwa d-38 pqa 13-66 , 14-65 pqspar 15-10 , 15-34 , 15-39 pr bit 3-7 , 3-21 pre 23-42 precise exceptions 3-36 pree 23-44 prescaler 13-48 clock (psck) 19-12 high time (psh) 13-15 low time (psl) 13-15 clock high time (psh) 13-48 , 14-15 control for tcr1 19-5 for tcr2 19-7 divide factor field 16-30 register (presdiv) 16-8 , 16-29 presdiv (bit field) 16-30 presdiv (register) 16-8 , 16-10 , 16-29 priority calram overlay regions 22-11 channel service 19-4 privilege level 3-7 , 3-21 processor version register 3-25 program 3-51 exception 3-51 programmable channel service priority 19-4 transfer length 15-15 programmable time accumulator (pta) d-3 parameters d-3 , d-40 , d-51 propagation segment time (propseg) 16-29 propseg 16-13 , 16-29 psck 19-12 pseg1 16-30 pseg2 16-10 , 16-13 , 16-30 psegs1 16-13 psh 13-15 , 13-48 , 14-15 psl 13-15 pt 15-47 , 15-53 pta d-3 ptr, 9-4 , 9-38 pulse-width modulation (pwm) d-44 parameters d-44 pvr 3-25 pwm d-44 q qacr0 13-7 , 13-15 , 14-7 qacr1 13-7 , 13-15 , 14-7 , 14-16 qacr2 13-7 , 13-17 , 13-18 , 14-7 , 14-18 qadc64e conversion queue operation 14-29 qadc64e module configuration register (qadcmcr) 13-7 qadcint 13-7 , 13-12 , 14-11 qadcmcr 13-7 , 13-8 , 14-8 qadctest 13-7 qadmcr 13-8 qasr 13-8 , 13-20 , 14-7 , 14-22 qclk 13-47 , 14-48 frequency 13-47 , 14-48 qddr 15-13 , 15-42 qilr 15-9 qom d-5 qpar 15-12 qpdr 15-11 , 15-42 qs 13-24 , 14-25 qsci1 registers qsci1cr 15-59 qsci1sr 15-59 qsm global registers 15-6 pin function 15-11 qspi 15-14 operating modes 15-27 operation 15-25 ram 15-22 registers mpc561/mpc563 reference manual, rev. 1.2 index-12 freescale semiconductor pin control registers 15-10 port qs data direction register (ddrqs) 15-10 data register (portqs) 15-11 qsci control register 1 (qsci1cr) 15-59 status register 1 (qsci1sr) 15-59 qspi control register 0 (spcr0) 15-17 control register 1 (spcr1) 15-19 control register 2 (spcr2) 15-20 control register 3 (spcr3) 15-20 status register (spsr) 15-20 sci control register 0 (sccr0) 15-46 control register 1 (sccr1) 15-47 data register (scdr) 15-50 status register (scsr) 15-48 sci 15-42 operation 15-51 pins 15-51 registers 15-45 qsm data direction register (qddr) 15-13 , 15-42 qsm interrupt level register (qilr) 15-9 qsm pin assignment register (qpar) 15-12 qsm port data register (qpdr) 15-11 , 15-42 qsmcmmcr bit settings 15-9 qspi 15-14 block diagram 15-15 enable (spe) 15-19 finished flag (spif) 15-22 initialization operation 15-28 loop mode (loopq) 15-21 master operation flow 15-29 operating modes 15-27 master mode 15-27 , 15-34 wraparound mode 15-38 slave mode 15-27 , 15-39 operation 15-25 peripheral chip-selects 15-37 ram 15-22 , 15-23 command ram 15-23 receive ram 15-23 transmit ram 15-23 qspi enable (spe) 15-42 qspi status register (spsr) 15-42 queue 13-37 , 14-38 1 completion flag (cf1) 13-21 , 14-22 1 completion interrupt enable (cie1) 13-16 , 14-17 1 operating mode (mq1) 13-16 , 14-17 1 pause flag (pf1) 13-22 , 14-23 1 pause interrupt enable (pie1) 13-16 , 14-17 1 single-scan enable bit (sse1) 13-16 , 14-17 1 trigger overrun (tor1) 13-23 , 14-24 2 completion flag (cf2) 13-22 , 14-23 2 completion software interrupt enable (cie2) 13-18 , 14-19 2 operating mode (mq2) 13-18 , 14-19 2 pause flag (pf2) 13-23 , 14-24 2 pause software interr upt enable (pie2) 13-18 , 14-19 2 single-scan enable bit (sse2) 13-18 , 14-19 2 trigger overrun (tor2) 13-24 , 14-25 pointers completed queue pointer (cptqp) 15-25 end queue pointer (endqp) 15-25 new queue pointer (newqp) 15-25 priority 13-38 , 14-39 priority schemes 13-54 , 13-63 , 14-53 , 14-62 status (qs) 13-24 , 14-25 queue sci 15-59 queued serial peripheral interface (qspi) 15-14 queued output match tpu function (qom) d-5 r raf 15-49 rambar 20-4 rcw 7-11 rd/wr 9-4 , 9-37 rdrf 15-49 , 15-57 re 15-46 , 15-48 , 15-57 re bit 3-22 , 3-25 read cycle, data bus requirements, 9-31 read/write (rd/wr), 9-37 readi compressed code mode guidelines 24-20 , a-16 compression a-16 features 24-1 public messages 24-5 register map 24-8 signals 24-21 vendor-defined messages 24-5 real-time clock 6-19 receive data register full (rdrf) 15-49 error status flag (rxwarn) 16-34 ram 15-23 time sample clock (rt) 15-53 , 15-57 receive buffer message code 16-5 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-13 receiver active (raf) 15-49 data register (rdrf) flag 15-57 enable (re) 15-48 , 15-57 interrupt enable (rie) 15-48 wakeup (rwu) 15-48 , 15-59 receiver enable (re) 15-46 reception of transm itted frames 16-14 recoverable exception 3-22 , 3-25 register diagrams mpwmperr mpwmsm period register 18-10 , 18-12 , 18-16 , 18-17 , 18-18 , 18-19 registers bbcmcr bbc module confi guration register 4-19 breakpoint address register (bar) 23-53 breakpoint counter a value and control register (counta) 23-45 breakpoint counter b value and control register (countb) 23-46 calram_otr calram ownership trace register 22-18 change of lock interrupt register (colir) 8-36 cmpa?cmpd 23-41 cmpe?cmpf 23-46 comparator g-h value registers (cmpg?cmph) 23-47 condition register (cr) 3-16 conversion command word table (ccw) 13-30 , 14-31 count register (ctr) 3-19 cram_rbax calram region base address register 22-16 crammcr calram module configuration register 22-13 cramovl calram overlay configuration register 22-17 dae/source instruction service register (dsisr) 3-22 data address register (dar) 3-23 dccr0-dccr15 decompressor class configuration registers a-19 debug enable register (der) 23-43 decompressor class configuration 4-25 decrementer register (dec) 6-40 development port data register (der) 23-53 documenter register (dec) 3-23 dptram base address register (rambar) 20-4 dptram module configuration register (dptmcr) 20-3 dptram test register (dpttcr) 20-4 dual-mapping base register (dmbr) 10-36 dual-mapping option register (dmor) 10-37 eibadr external interrupt relocation table base address register 4-25 exception cause register (ecr) 23-41 external master contro l register (emcr) 6-29 floating point (fprs) 3-12 floating point exception cause register (fpecr) 3-26 floating point status and control register (fpscr) 3-13 general purpose registers (gprs) 3-12 general sprs 3-24 hard reset configuration word register (uc3fcfig) 21-16 i-bus support control register (counta) 23-51 i-bus support control register (ictrl) a-16 implementation specific sprs 3-25 integer exception register (xer) 3-18 internal memory map register (immr) 6-28 interrupt (qadcint) 13-12 , 14-11 interrupt in-service registers (sisr2 and sisr3) 6-37 iramstby control register (vsrmcr) 8-37 l2u global region attribute registers (l2u_gra) 11-16 l2u module configuration register (l2u_mcr) 11-13 l2u region attribute registers (l2u_rax) 11-15 l2u region base address registers (l2u_rbax) 11-14 l-bus support control register 1 (lctrl1) 23-47 l-bus support control register 2 (lctrl2) 23-48 left justified, unsigned result format (ljurr) 13-33 , 14-35 link register (lr) 3-19 machine state (msr) 3-20 machine status save/restore register 0 (srr0) 3-23 machine status save/restore register 1 (srr1) 3-23 mbism interrupt registers 17-69 mbism registers, list of 17-13 mcpsm register organization 17-17 , 17-62 mcpsmscr mcpsm status/control register 17-18 mdasm status/control re gister (duplicated) (mdasmscrd) 17-43 mdasm status/control register (mdasmscr) 17-44 mdasmar mdasm data a register 17-41 mdasmbr mdasm data b register 17-42 memory controller base registers (br0-br3) 10-32 memory controller option registers (or0-or3) 10-34 memory controller status registers (mstat) 10-32 mi_gra global region atribute register 4-23 mi_ra [0:3] region attribute register 4-22 mi_rba[0:3] region base address register 4-21 mios14er0 interrupt enable register 17-66 mios14er1 interrupt enable register 17-68 mios14lvl0 interrupt level register 0 17-69 mios14lvl1 interrupt level register 1 17-70 mios14mcr module configuration register 17-15 mios14rpr0 interrupt request pending register 0 17-67 mios14rpr1 interrupt request pending register 1 17-68 mpc561/mpc563 reference manual, rev. 1.2 index-14 freescale semiconductor mios14sr0 interrupt status register 17-66 mios14sr1 interrupt status register 17-67 mios14tpcr test and signal control register 17-14 mios14tvect vector register 17-14 mios14vnr module and version number register 17-14 misc counter register (miscnt) 20-6 misr high register 20-5 misr low register 20-5 mmcsm registers 17-22 mmcsmcnt mmcsm up-counter register 17-23 mmcsmml mmcsm modulus latch register 17-24 mmcsmscr mmcsm status/control register 17-24 mmscm status/control register duplicated (mmcsmscrd) 17-24 module configuration (qadc64e) 13-8 mpiosmddr mpiosm data direction register 17-63 mpiosmdr mpiosm data register 17-62 mpwmcntr mpwmsm counter register 17-58 mpwmperr mpwmsm period register 17-57 mpwmpulr mpwmsm pulse width register 17-58 mpwmscr mpwmsm status/control register 17-58 pads module configuration register (pdmcr) 2-22 pads module configuration register 2 (pdmcr2) 2-23 pending interrupt request register (uipend) 12-8 periodic interrupt status and control register (piscr) 6-44 periodic interrupt timer count register (pitc) 6-45 periodic interrupt timer register (pitr) 6-45 pll, low power, and reset control register (plprcr) 8-33 port a data register (portqa) 13-13 port b data register (portqb) 13-13 processor version register (pvr) 3-25 qacr0 control register 13-15 , 14-14 qadc64e control register 1 (qacr1) 13-15 , 14-16 qadc64e control register 2 (qacr2) 13-17 , 13-18 , 14-18 qadc64e module configuration (qadcmcr) 14-8 qadc64e portqa port a data register 14-13 qadc64e portqa port a data register 13-13 readi data trace attribute 1 register (dta1) 24-17 readi data trace attribute 2 register (dta2) 24-17 readi development control register (dc) 24-10 readi device id register (did) 24-9 readi mode control register (mc) 24-11 readi ownership trace register (otr) 24-8 readi read/write access register (rwa) 24-13 readi upload/download information register (udi) 24-15 readi user base address register (uba) 24-12 real-time clock alarm register (rtcal) 6-44 real-time clock register (rtc) 6-43 real-time clock status and co ntrol register (rtcsc) 6-42 receive mask 16-7 reset status register (rsr) 7-5 sgpio control register (sgpiocr) 6-48 sgpio data register 1 (sgpiodt1) 6-46 sgpio data register 2 (sgpiodt2) 6-47 siu interrupt edge level register (siel) 6-35 siu interrupt mask registers (simask) 6-33 siu interrupt vector register (sivec) 6-35 siu module configuration register (siumcr) 6-25 software service register (swsr) 6-38 special purpose 3-44 added registers, 3-44 unsupported registers, 3-44 status (qasr) 13-20 , 14-22 status (qasr0) 13-21 , 14-22 status (qasr1) 13-27 , 14-28 system clock and reset control register (sccr) 8-30 system protection control register (sypcr) 6-37 time base control and status register (tbscr) 6-42 time base reference registers (tbref0 and tbref1) 6-41 time base spr (tb) 3-23 time base spr (tbspr) 6-40 toucan control register (canctrl0) 16-27 toucan control register 0 (canctrl0) 16-27 toucan control register 1 (canctrl1) 16-28 toucan control register 2 (canctrl2) 16-30 toucan error and status register (estat) 16-33 toucan error counters 16-36 toucan free running timer (timer) 16-31 toucan interrupt configuration register (canicr) 16-27 toucan interrupt flag register (iflag) 16-36 toucan interrupt mask register (imask) 16-35 toucan module configuration register (canmcr) 16-25 toucan prescaler divide register (presdiv) 16-29 toucan receive buffer 14 mask registers 16-32 toucan receive buffer 15 mask registers 16-33 toucan receive global mask registers 16-31 tpu channel interrupt enable register (cier) 19-15 tpu channel interrupt status register (cisr) 19-19 tpu channel priority register (cpr) 19-18 tpu development support control register (dscr) 19-12 tpu function select register (cfsr) 19-15 tpu host sequence re gister (hsqr) 19-16 tpu host service reques t register (hsrr) 19-17 tpu interrupt configuration register (ticr) 19-14 tpu module configuration register (tpumcr) 19-11 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-15 tpu module configuration register 2 (tpumcr2) 19-19 tpu module configuration register 3 (tpumcr3) 19-21 tpu support status register (dssr) 19-13 transfer error status register (tesr) 6-39 uc3f configuration register (uc3fmcr) 21-5 uc3f extended configuration register (uc3fmcre) 21-8 uc3f high voltage control register (uc3fctl) 21-11 uimb 12-6 uimb module configuration register (umcr) 12-7 usiu special purpose registers 5-6 remote frames 16-17 transmission request (rtr) 16-5 transmission reques t field (rtr) 16-6 reservation of data 11-7 reservation protocol for a multi-level (local) bus, 9-43 reserved channel number 13-31 mode 13-41 , 14-42 reset bbc behavior 4-6 configuration 7-7 soft reset configuration 7-13 sources of 7-3 status register 7-5 resistor-divider chain 13-36 , 14-37 resolution time 13-35 , 14-36 result word table 13-2 , 13-32 , 13-37 , 14-2 , 14-34 , 14-38 resynchronization jump width (rjw) bit field 16-30 retry, 9-45 r f 13-75 , 14-73 rie 15-48 rjurr 13-33 , 14-35 rjw 16-13 , 16-30 rn field 3-16 rsr 7-5 rsv, 9-38 rt 15-57 rtc 6-19 rtc register 6-43 rtcal 6-44 rtcsc 6-42 rtr 16-5 , 16-17 rtr field 16-6 rwa 24-13 rwu 15-48 , 15-59 rx14mskhi 16-32 rx14msklo 16-32 rx15mskhi 16-33 rx15msklo 16-33 rxectr 16-36 rxgmskhi 16-31 rxgmsklo 16-31 rxwarn 16-34 s s0 15-9 samp 16-29 sample amplifier bypass (byp) 13-30 , 14-31 sampling mode (samp) 16-29 sar 13-37 , 14-38 sbk 15-48 , 15-54 scan modes continuous-scan modes external trigger 13-46 , 14-47 periodic timer continuous-scan mode 13-47 , 14-48 software initiated 13-45 , 14-46 single-scan modes external trigger 13-43 , 14-44 interval timer 13-44 , 14-45 software initiated 13-42 , 14-43 scbr 15-46 sccr 8-30 sccr0 15-46 sccr1 15-47 scdr 15-50 sci 15-34 , 15-42 baud clock 15-52 rate (scbr) 15-46 equation 15-46 idle-line detection 15-58 internal loop 15-59 operation 15-51 parity checking 15-53 pins 15-51 queue 15-59 receiver block diagram 15-44 operation 15-57 wakeup 15-58 registers 15-45 sccr0 15-46 sccr1 15-46 sci baud rates 15-53 sci submodule 15-13 scsr 15-45 transmitter block diagram 15-43 operation 15-54 sci control register 0 (sccr0) 15-46 mpc561/mpc563 reference manual, rev. 1.2 index-16 freescale semiconductor sci control register 1 (sccr1) 15-46 sci status register (scsr) 15-45 sck 15-12 , 15-34 , 15-39 actual delay before sck (equation) 15-36 baud rate (equation) 15-35 s-clock 16-8 scsr 15-48 se bit 3-21 see 23-42 send break (sbk) 15-48 , 15-54 sequencer, instruction 3-3 serial clock baud rate (spbr) 15-18 communication interface (sci) 15-42 formats 15-52 mode (m) bit 15-52 shifter 15-54 serial clock (sck) 15-12 serialization fetch 23-1 service request breakpoint flag (srbk) 19-14 sglr 19-22 sgpiocr 6-48 sgpiodt1 6-46 sgpiodt2 6-47 shadow row erasing 21-28 programming 21-24 select read 21-21 uc3f 21-15 show cycles l-bus 11-9 siel 6-35 signals internal clock 8-7 mpc561/563 signals 2-3 multiplexing 2-20 simask 6-33 simask2 6-34 simask3 6-35 simplified mnemonics 3-33 single-step trace enable 3-21 sipend 6-32 sipend2 6-32 sipend3 6-33 sisr2 6-37 sisr3 6-37 siu interrupt pending registers (sipend) 6-32 siu signals, 9-4 siumcr 6-25 sivec 6-35 siw0en 23-52 , a-17 siw1en 23-52 , a-17 siw2en 23-52 , a-17 siw3en 23-52 , a-17 slave select (ss) 15-42 slave select signal (ss) 15-39 sleep 6-23 slw0en 23-50 slw1en 23-50 snooping l2u 11-9 snooping external bus activity, 3-43 so bit 3-18 sof 16-10 soft reset 7-2 soft reset control field (soft_rst) 19-20 soft_rst 19-20 softrst 16-12 software initiated continuous-scan mode 13-45 , 14-46 single-scan mode 13-42 , 14-43 software trap enable selection 23-52 , a-17 software watchdog timer 6-21 spbr 15-18 spcr0 15-17 spcr1 15-19 spcr2 15-20 spcr3 15-20 spe 15-19 , 15-42 special purpose registers 5-6 bbc 4-17 implementation-specific 3-25 special purpose registers, general 3-24 spi finished interrupt enable (spifie) 15-20 spif 15-22 spifie 15-20 sprg0?sprg3 3-24 sprgs 3-24 sprs 5-6 bbc 4-17 general 3-24 spsr 15-20 , 15-42 spwm d-48 sram supervisor space only 15-9 srbk 19-14 sreset 7-2 srr field 16-6 srr0 3-23 , 3-45 , 3-47 , 3-55 , 3-56 , 3-57 , 3-59 , 3-60 srr1 3-23 , 3-45 , 3-47 , 3-49 , 3-50 , 3-52 , 3-53 , 3-54 , 3-55 , 3-56 , 3-57 , 3-59 , 3-60 mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-17 ss 15-42 ss 15-39 sse1 13-16 , 14-17 sse2 13-18 , 14-19 standard message format 16-1 frames 16-4 standby operation 22-5 star-point ground system 13-70 , 14-68 start bit (beginning of data frame) 15-51 -of-frame (sof) symbol 16-10 state machine 13-47 , 14-48 , 15-57 status register (qasr) 13-8 , 13-20 , 14-7 , 14-22 stf 19-11 stop 13-8 , 13-9 , 14-8 , 16-18 , 19-11 stop clocks to tcrs (clks) 19-12 enable (stop) 13-8 , 14-8 enable (stop) bit qsm 15-6 toucan 16-18 tpu 19-11 flag (stf) 19-11 mode 13-9 , 14-8 sci end of data frame bit 15-51 storage control instructions, 3-45 storage reservation, 9-42 stress conditions 13-76 , 14-74 stufferr 16-34 subqueue 13-38 , 14-39 substitute remote request field (srr) 16-6 successive approximatio n register (sar) 13-37 , 14-38 summary overflow 3-18 supervisor /unrestricted data space (supv) 13-9 , 14-8 /unrestricted data space (supv) tpu 19-11 supervisor mode and sram 15-9 supv 13-9 , 13-11 , 14-8 , 14-10 susg 23-48 sush 23-48 swsr 6-38 swt 6-21 synchronized pulse-width modulation (spwm) d-48 sypcr 6-37 syse 23-42 sysee 23-44 system call exception 3-54 system clock output, 9-8 system reset exception 3-45 system reset interrupt, 3-45 t t1 13-54 , 14-53 t2 13-54 , 14-53 t2cfilter 19-20 t2cg 19-7 , 19-11 t2clk pin filter control (t2cfilter) 19-20 t2csl 19-12 ta 9-6 , 9-40 table stepper motor (tsm) d-7 tap controller 25-4 tb 6-19 tb register 3-23 , 6-40 tbref registers 6-41 tbrs1, tbrs0 - bits in biumcr 17-13 tbscr 6-42 tbspr 6-40 tc 15-49 , 15-54 tcie 15-47 , 15-55 tcnmcr 16-25 tcode 24-4 tcr1p 19-11 tcr2 clock/gate control (t2cg) 19-11 tdre 15-49 te 15-46 , 15-48 tea 9-6 , 9-40 termination signals, 9-40 tesr 6-39 test register (dpttcr) 20-4 test register (qadctest) 13-7 ticr 19-14 , 19-21 tie 15-47 , 15-55 time quanta clock 16-8 stamp 16-4 , 16-12 time base (tb) 6-19 time base bus selecting 17-13 time base register (tb) 3-23 timebase register 3-44 timer 16-31 timer count register 1 prescaler control (tcr1p) 19-11 synchronize mode (tsync) 16-29 timing, instruction 3-37 tool-mapped registers 24-9 tor 13-55 , 14-54 tor1 13-23 , 14-24 tor2 13-24 , 14-25 toucan mpc561/mpc563 reference manual, rev. 1.2 index-18 freescale semiconductor address map 16-21 bit timing configuration 16-8 , 16-10 external pins 16-2 initialization sequence 16-12 interrupts 16-20 message buffer address map 16-24 operation 16-3 receive process 16-14 registers control register 0 (canctrl0) 16-27 control register 1 (ctrl1) 16-8 control register 1(canctrl1) 16-28 control register 2 (canctrl2) 16-30 control register 2 (ctrl2) 16-8 error and status register (estat) 16-33 free running timer register (timer) 16-31 interrupt configuration register (canicr) 16-27 flag register (iflag) 16-36 mask register (imask) 16-35 module configuration register (tcnmcr) 16-25 receive buffer 14 mask registers (rx14mskhi/lo) 16-32 buffer 15 mask registers (rx15mskhi/lo) 16-33 global mask registers (rxgmsklo/hi 16-31 rx/tx error counter registers (rxectr/txectr) 16-36 test configuration register (cantcr) 16-27 special operating modes 16-17 auto power save mode 16-19 debug mode 16-17 low-power stop mode 16-18 transmit process 16-13 toucan features 16-1 tpu address map 19-8 components 19-2 freeze flag (tpuf) 19-14 function library 19-4 host interface 19-2 interrupts 19-5 microengine 19-2 operation 19-3 coherency 19-4 emulation support 19-4 event timing 19-3 interchannel communication 19-4 programmable channel service priority 19-4 parameter ram 19-2 , 19-23 address map 19-23 registers channel function select registers (cfsr) 19-15 interrupt enable register (cier) 19-5 , 19-15 status register (cisr) 19-5 , 19-19 priority registers (cpr) 19-18 development support control register (dscr) 19-12 support status register (dssr) 19-13 host sequence registers (hsqr) 19-16 service request registers (hssr) 19-17 module configuration register (tpumcr) 19-11 service grant latch register (sglr) 19-22 tpu interrupt configuration register (ticr) 19-14 , 19-21 scheduler 19-2 time bases 19-2 timer channels 19-2 tpu reference manual 19-3 , 19-17 tpu2 module configuration register 2 (tpumcr2) 19-19 tpu3 emulation mode operation 20-7 tpuf 19-14 tpumcr 19-11 tpumcr2 19-19 tr 23-42 trace indicators 23-4 trace interrupt, 3-54 transaction (bus), 9-8 transfer length options 15-37 time 13-35 , 14-36 transfer acknowledge (ta), 9-40 transfer code 24-4 transfer error acknowledge (tea), 9-40 transfer size (tsiz), 9-38 transfer start (ts) 9-37 transfers alignment and packaging 9-29 burst-inhibited 9-18 termination signals 9-40 transmission complete (tc) flag 15-54 interrupt enable (tcie) 15-55 transmit /receive status (tx/rx) 16-34 bit error (biterr) 16-34 complete mpc561/mpc563 reference manual, rev. 1.2 freescale semiconductor index-19 bit (tc) 15-49 interrupt enable (tcie) 15-47 data register empty (tdre) flag 15-49 error status flag (txwarn) 16-34 interrupt enable (tie) 15-47 , 15-55 pin configuration control (txmode) 16-28 ram 15-23 transmitter enable (te) 15-46 transmitter enable (te) 15-48 , 15-54 tre 23-44 trigger event 13-28 , 13-54 , 14-29 , 14-53 overrun error (tor) 13-55 , 14-54 ts signal 9-5 , 9-37 tsiz[0:1] 9-4 , 9-38 tsiz0 9-1 tsiz1 9-1 tsm d-7 t sr 13-9 , 14-8 tsync 16-29 tx/rx 16-34 txectr 16-36 txmode 16-28 txwarn 16-34 u uart d-12 uba 24-12 uc3f 512-kbyte array 21-19 array addressing 21-15 censorship states 21-30 features 21-3 high voltage operations 21-21 operation 21-19 program sequencing 21-22 registers 21-5 shadow row 21-15 signals 21-4 uc3fcfig register 21-16 uc3fctl register 21-11 uc3fmcr register 21-5 uc3fmcre register 21-8 udi 24-15 uimb interface features 12-1 uimb module configuration register 12-7 uipend register 12-8 umcr register 12-7 universal asynchronous receiver/transmitter (uart) d-12 parameters receiver parameters d-13 transmitter parameters d-12 unordered exceptions 3-35 user instruction set architecture book 1 instruction fetching, 3-40 user instruction set architecture (book 1) branch instructions, 3-40 branch processor, 3-40 computation modes, 3-39 exceptions, 3-40 fixed point-processor, 3-41 floating point processor, 3-41 instruction classes, 3-40 load/store processor, 3-42 reserved fields, 3-39 user-mapped registers readi 24-8 using the tpu function library and tpu emulation mode 19-5 ux bit 3-14 v v cf 13-75 , 14-73 v dda 13-67 , 13-71 , 14-66 , 14-70 vddsyn 8-22 ve bit 3-15 vector table, exception 3-36 vector table, exceptions 3-36 vflsn 23-30 vfn 23-2 v ih 13-66 , 14-65 v il 13-66 , 14-65 virtual environment architecture (book 2) operand placement effects, 3-43 storage control instructions, 3-43 timebase register 3-44 virtual environment ar chitecture (vea) 3-43 vo l t a g e inputs 13-66 , 14-65 reference pins 13-71 , 14-69 v rh 13-31 , 13-32 , 13-36 , 13-71 , 13-75 , 14-34 , 14-37 , 14-69 , 14-70 , 14-73 v rl 13-31 , 13-36 , 13-71 , 13-75 , 14-37 , 14-69 , 14-70 , 14-73 v src 13-75 , 14-73 vsrmcr 8-37 vss 8-23 v ssa 13-67 , 13-71 , 14-66 , 14-70 vsssyn 8-22 vx bit 3-14 mpc561/mpc563 reference manual, rev. 1.2 index-20 freescale semiconductor vxcvi 3-15 vxidi 3-14 vximz bit 3-14 vxisi 3-14 vxsnan 3-14 vxsoft 3-15 vxsqrt 3-15 vxvc bit 3-15 vxzdz bit 3-14 w wake 15-47 , 15-59 wake interrupt (wakeint) 16-35 wakeint 16-18 , 16-35 wakemsk 16-18 wakeup address mark (wake) 15-47 , 15-59 watchpoint counters 23-19 watchpoints and breakpoints 23-9 wired-or mode for qspi pins (womq) 15-18 for sci pins (woms) 15-47 , 15-54 womq 15-18 woms 15-47 , 15-54 wrap enable (wren) 15-20 to (wrto) 15-20 wraparound mode 15-16 master 15-38 wren 15-20 write cycle data bus contents, 9-32 wrto 15-20 x xe bit 3-15 xer 3-18 xx bit 3-14 z ze 3-15 zx bit 3-14 |
Price & Availability of MPC563MZP66
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |